Summary and Expected Results for the Digital Hardware Lab
Summary of the Lab and Expected Results
The students begin with a prelab, where the layouts of the two chips (called circuit A and circuit
B) are compared. This exercise demonstrates both proper and improper layout for these signals
and allows the students to make an educated guess at to which chip will demonstrate clock skew
and which chip will demonstrate rail bounce.
There are two parts to the hardware lab. The first part tests clock skew in both circuits. The end of
the clock wire is taken off-chip through an analog buffer. The students measure this output with
and oscope and compare the clock output with the clock input. Clock skew is evident in the clock
skew circuit, as shown in Figure 1(a). The students measure the rise and fall time of the clock output compared to the clock input. Using the same board, the same measurement is obtained for rail
bounce circuit, where very little clock skew is observed, as shown in Figure 1(b).
clkin
clkin
clkout
output voltage
output voltage
clkout
time
(a)
time
(b)
Figure 1: Clock output (solid line) compared to clock input (dashed line) showing clock skew.
Part (a) shows the clock skew due to the serpentine layout and part (b) shows the clock skew
due to the H-tree distribution.
.
output voltage
clkin
clkout
time
Figure 2: Clock output (solid line) compared to clock input (dashed line) showing the effects of
clock skew when the frequency of the clock has been increased so that the RC delay is a
significant portion of the clock period.
The next experiment of the clock skew lab asks the students to increase the clock frequency and
observe the output of the clock line. The RC delay is a significant portion of the clock period and
as a result, the clock signal does not reach Vdd or ground, as shown in Figure 2. The students are
asked to think about the effects of this effect on the circuit operation.
This final experiment in the clock skew lab measures the effects of clock skew on the outputs of
the flip-flops. Students using a multichannel digital probe measure the clock input, the common
flip-flop input, and the output of 6 flip-flops. The students change the input to the flip-flops from
a 1 to a zero (or vice versa). The flip-flop outputs change on the falling edge of the clock. The students measure the delay between the clock signal and when the flip-flops latch the data. As shown
in Figure 3(a), flip-flops further down the clock line take longer to latch the data in the clock skew
chip. For the rail bounce chip, the effect of the clock skew on the latching of the data is diminished, as shown in Figure 3(b). By increasing the frequency of the clock input, the students can
observe some signal outputs changing on the next clock, resulting in a set-up time violation (this
experiment is not in the current version of the lab due to time constraints for the lab).
clkin
clkindig
in
Out0
(a)
Out1
Out2
Out3
Out4
time
clkin
clkindig
in
Out0
(b)
Out1
Out2
Out3
Out4
time
Figure 3: Effects of clock skew on flip-flop outputs. Part (a) is the data for the clock skew chip.
Out4 is further down the clock line than Out0, demonstrating more delay. Part (b) is the data for
the rail bounce chip. Effects of clock skew is less evident.
The next portion of the digital lab demonstrates power/ground bounce. The end of the Vdd wire is
taken off-chip through an analog buffer. The students measure this output with and oscope to
observe the effects of rail bounce. As shown in Figure 4(a), the Power bounce is evident for the
rail bounce circuit every time the clock changes (because there is an inverter in every cell that
switch at the same time) and worsened when the input is switched (because the input is common
to all cells and therefore switches at the same time). The students are asked to interpret the results
considering the layout of the flip-flop cell. The clock skew chip demonstrates less rail bounce, as
shown in Figure 4(b).
Vdd
input
changed
clkin
output voltage
output voltage
Vdd
clkin
time
time
(a)
(b)
Figure 4: Power rail output (solid line) compared to clock input (dashed line) showing power
bounce at each clock change. Part (a) shows the rail bounce for the rail bounce circuit. Part
(b) shows the rail bounce for the clock skew circuit.
One final experiment that may be performed in the rail bounce portion of the lab is to reduce the
value of Vdd. This experiment is not included in the current version of the lab due to time constraints on the time for the students to complete the lab. However, the results of such an experiment are shown in Figure 5. By decreasing Vdd from 5V to 3.3V, the rail bounce is decreased.
With a lower rail voltage, less current is drawn when the inverters change state, which results in a
lower rail voltage. This experiment would be a good demonstration of the effect of supply voltage
on circuit power
Vdd
output voltage
output voltage
Vdd
clkin
clkin
time
time
(a)
(b)
Figure 5: Effect of power supply voltage on rail bounce. Part (a) shows the rail bounce when
Vdd=5V. Part (b) shows the rail bounce when Vdd=3.3V.