Termination of High-Speed Converter
Clock Distribution Devices
C3
By Jerome Patoux
When using clock distribution devices1 or fanout buffers to clock
ADCs and DACs, two main sources of signal degradation—
printed-circuit board (PCB) trace implementation and output
termination—need to be dealt with.
C3
Clock Traces and Signal Swing
PCB traces behave like low-pass filters, attenuating clock signals
as they travel along the trace and increasing pulse-edge distortion
with trace length. Higher frequency clock signals are subject to
increased attenuation, distortion, and noise, but to improve jitter,
which is worst at low slew rates (Figure 1), clock edges with a
high slew rate are typically used. To correctly implement a quality
clock, use high-swing clock signals and short clock PCB traces;
place the device to be clocked as close to the clock-distribution
device as possible.
300
RMS JITTER (fS)
250
200
150
100
50
0
0
1
2
3
4
5
6
7
500ps/DIV
Figure 2. ADCLK954 clock buffer output
waveforms with 3.3-V supply.
Output Termination
Clock-signal attenuation can cause increased jitter, so it is
important to terminate the driver outputs to avoid signal reflection
and to maximize power transfer over a relatively large bandwidth.
Indeed, ref lections may cause undershoot and overshoot,
severely degrading the signal and the overall clock performance
or, in extreme cases, possibly damaging the receiver or driver.
Reflections, caused by impedance mismatches, occur when the
traces are not properly terminated. They are more significant
for high-speed signals with fast rise- and fall times due to the
high-pass nature of the reflection coefficient. The reflected pulse
is superimposed on the main clock signal, thus degrading the
clock pulse. It also affects the edges of the clock signal by adding
a time-delay uncertainty to the rising and falling edges, as shown
in Figure 3.
VREF
Figure 1. ADCLK925 rms jitter vs. input slew rate.
Two such clock-distribution devices are the ADCLK9542 clock
fanout buffer and the ADCLK9143 ultrafast clock buffer. The
ADCLK954 comprises 12 output drivers that can drive 800-mV
full-swing ECL (emitter-coupled logic) or LVPECL (low-voltage
positive ECL) signals into 50-Ω loads for a total differential output
swing of 1.6 V, as shown in Figure 2. It operates at toggle rates to
4.8 GHz. The ADCLK914 can drive 1.9-V high-voltage differential
signals (HVDS) into 50-Ω loads for a total differential output
swing of 3.8 V. The ADCLK914 features a 7.5-GHz toggle rate.
When driving a DAC, the clock-distribution device should be
placed as close as possible to the DAC’s clock input so that the
required high slew rate, high amplitude clock signals do not
cause routing difficulties, generate EMI, or become degraded by
dielectric and other losses. Note that the characteristic impedance
(Z 0) of the trace will vary with trace dimension (length, width,
and depth); the driver’s output impedance must be matched to
this characteristic impedance.
References
1
w w w.analog.com /en /clock-and-timing /clockgeneration-and-distr ibution /products/index.html.
2
w w w.analog.com /en /clock-and-timing /clockgeneration-and-distr ibution /adclk954/products/
product.html.
w w w.analog.com /en /clock-and-timing /clockgeneration-and-distr ibution /adclk914/products/
product.html.
Analog Dialogue 44-01 Back Burner, January (2010)
100mV/DIV
8
INPUT SLEW RATE (V/ns)
3
C4
Δt
Δt
Figure 3. Jitter impact of reflected signal due to
improper termination.
The magnitude of the echo due to the improper termination varies
with time, so ∆t will also vary with time. The termination time
constant also affects the shape and width of the echo pulse. For
these reasons, this additional reflection-induced jitter shape, which
looks Gaussian, adds to the classical jitter. To avoid the adverse
effects of this jitter and clock quality reduction, use proper signal
termination, as summarized in Table 1. Z 0 is the impedance of
the line; ZOUT is the output impedance of the driver; and ZIN is the
input impedance of the receiver. Only CMOS and PECL/LVPECL
circuits are shown.
Author
Jerome Patoux [jerome.patoux@analog.com]
is a product marketing engineer for ADI’s Clock and
Signal Synthesis Group in Greensboro, NC. In 2002,
he graduated from ESIGETEL, Avon, France, with a
master’s degree in electronics and telecommunications
engineering. He also has a master’s degree in
international project management from the University of Quebec
in Hull-Gatineau, Canada, and ISMANS, Le Mans, France. Prior
to joining ADI in 2005, Jerome worked as a radio engineer for SFR
Group and as a department manager for SNCF.
www.analog.com/analogdialogue
1
Table 1. Clock Terminations
Method
Description
Strength
Weakness
Comments
Series
Termination
CMOS
Low power solution
(no sink current to
ground).
Rise/fall time
impacted by
circuit R and C,
increasing jitter.
CMOS drivers.
R
Z0
BUFFER ZOUT
ADC ZIN
In practice, resistance (R) is omitted at
the buffer output as it is hard to match the
impedance due to its dynamic behavior
over frequency.
Pull-Down
Resistor
CMOS
Easy to calculate R
(Z 0 – ZOUT).
Only useful with
low-frequency
signals.
Very simple (R = Z 0)
High power
consumption.
Not suitable for highfrequency clock signals.
Suitable for lowfrequency clock signals
and very short traces.
Not recommended.
Z0
R
BUFFER ZOUT
ADC ZIN
LVPECL
Simple, 3-resistor
solution.
Z0
Z0
BUFFER ZOUT
R
R
Place termination
resistors as close as
possible to the PECL
receiver.
Slightly better in
terms of power
saving, while saving a
component compared
to 4-resistor
termination.
ADC ZIN
R
AC
Termination
Recommended.
CMOS
C should be small
to avoid high power
consumption, but not
too small to allow sink
current.
No dc power
consumption.
Z0
R
BUFFER ZOUT
ADC ZIN
C
LVPECL
VCC
R
R
R
R
Z0
BUFFER ZOUT
Resistor
Bridge
Z0
R
R
CMOS
AC-coupling
allows bias voltage
adjustment. Avoids
power flow between
the two sides of the
circuit.
AC-coupling is
AC-coupling capacitors
only recommended should be low ESR, low
for balanced
capacitance.
signals (50% duty
cycle clock).
Reasonable trade-off
on power.
Uses two parts
for single-ended
clocks.
ADC ZIN
VCC
R
Z0
R
BUFFER ZOUT
ADC ZIN
LVPECL
Uses four external
Widely used termination
parts for differential for 3.3-V LVPECL
output logic.
drivers.
VCC
R
R
R
R
Z0
VCC – 2V
BUFFER ZOUT
2
Z0
ADC ZIN
Analog Dialogue 44-01 Back Burner, January (2010)