GaAs, pHEMT, MMIC, Medium Power
Amplifier, 24 GHz to 35 GHz
HMC1131
GND
NIC
5
NIC
6
14
NIC
13
NIC
12
NIC
11
VGG2
10
9
NIC
NIC
NIC
8
HMC1131
7
Point-to-point radios
Point-to-multipoint radios
VSAT and SATCOM
1.5kΩ
1.5kΩ
VGG1
APPLICATIONS
NIC
15
19
4
VDD4
RFOUT
GND
VDD3
16
20
GND
3
VDD2
GND
RFIN
21
NIC
17
22
18
2
VDD1
1
NIC
NIC
23
FUNCTIONAL BLOCK DIAGRAM
High saturated output power (PSAT): 25 dBm
High output third-order intercept (IP3): 35 dBm
High gain: 22 dB (24 GHz to 27 GHz)
High output power for 1 dB compression (P1dB): 24 dBm
DC supply: 5 V at 225 mA
Compact 24-lead, 4 mm × 4 mm LCC package
24
FEATURES
PACKAGE
BASE
13105-001
Data Sheet
Figure 1.
GENERAL DESCRIPTION
The HMC1131 is a gallium arsenide (GaAs), pseudomorphic
high electron mobility transfer (pHEMT), monolithic microwave
integrated circuit (MMIC), driver amplifier that operates from
24 GHz to 35 GHz. The HMC1131 provides 22 dB of gain at the
24 GHz to 27 GHz range, 35 dBm output IP3, and 24 dBm of
output power at 1 dB gain compression, while requiring 225 mA
Rev. A
from a 5 V supply. The HMC1131 is capable of supplying 25 dBm
of saturated output power and is housed in a compact, 4 mm ×
4 mm ceramic leadless chip carrier (24-lead LCC). The HMC1131
is an ideal driver amplifier for a wide range of applications,
including point-to-point radios, from 24 GHz to 35 GHz.
Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
HMC1131
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1 ESD Caution...................................................................................4 Applications ....................................................................................... 1 Pin Configuration and Function Descriptions..............................5 Functional Block Diagram .............................................................. 1 Interface Schematics .....................................................................6 General Description ......................................................................... 1 Typical Performance Characteristics ..............................................7 Revision History ............................................................................... 2 Applications Information .............................................................. 11 Electrical Specifications ................................................................... 3 Evaluation PCB ........................................................................... 12 24 GHz to 27 GHz Frequency Range ......................................... 3 Typical Application Circuit ........................................................... 13 27 GHz to 35 GHz Frequency Range ......................................... 3 Outline Dimensions ....................................................................... 14 Absolute Maximum Ratings............................................................ 4 Ordering Guide .......................................................................... 14 REVISION HISTORY
9/15—Rev. 0 to Rev. A
Changes to Features Section and General Description Section........ 1
Change to Gain Parameter, Table 1 ................................................ 3
7/15—Revision 0: Initial Version
Rev. A | Page 2 of 14
Data Sheet
HMC1131
ELECTRICAL SPECIFICATIONS
24 GHz TO 27 GHz FREQUENCY RANGE
TA = 25°C, VDD1 = VDD2 = VDD3 = VDD4 = 5 V, IDD = 225 mA, unless otherwise stated. Adjust VGG1 and VGG2 between −2 V to 0 V to
achieve IDD = 225 mA typical.
Table 1.
Parameter
FREQUENCY RANGE
GAIN
Gain Variation Over Temperature
RETURN LOSS
Input
Output
OUTPUT
Output Power for 1 dB Compression
Saturated Output Power
Output Third-Order Intercept 1
SUPPLY CURRENT
Total Supply Current
Total Supply Current vs. VDD 2
1
2
Symbol
P1dB
PSAT
IP3
Min
24
18
20
IDD
Typ
Max
27
22
0.031
Unit
GHz
dB
dB/°C
8
7
dB
dB
23
27
34
dBm
dBm
dBm
225
4
5
mA
V
V
Measurement taken at POUT/tone = 10 dBm.
The amplifier operates over the full voltage ranges shown. VGG1 and VGG2 are adjusted to achieve IDD = 225 mA at 5 V.
27 GHz TO 35 GHz FREQUENCY RANGE
TA = 25°C, VDD1 = VDD2 = VDD3 = VDD4 = 5 V, IDD = 225 mA, unless otherwise stated. Adjust VGG1 and VGG2 between −2 V to 0 V to
achieve IDD = 225 mA typical.
Table 2.
Parameter
FREQUENCY RANGE
GAIN
Gain Variation Over Temperature
RETURN LOSS
Input
Output
OUTPUT
Output Power for 1 dB Compression
Saturated Output Power
Output Third-Order Intercept 1
SUPPLY CURRENT
Total Supply Current
Total Supply Current vs. VDD 2
1
2
Symbol
P1dB
PSAT
IP3
Min
27
18
21
IDD
Measurement taken at POUT/tone = 10 dBm.
The amplifier operates over the full voltage ranges shown. VGG1 and VGG2 are adjusted to achieve IDD = 225 mA at 5 V.
Rev. A | Page 3 of 14
Typ
Max
35
20
0.031
Unit
GHz
dB
dB/°C
8
7
dB
dB
24
25
35
dBm
dBm
dBm
225
4
5
mA
V
V
HMC1131
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 3.
Parameter
Drain Bias Voltage (VDD)
RF Input Power (RFIN)
Channel Temperature
Continuous Power Dissipation (PDISS),
TA = 85°C (Derate 22 mW/°C)
Thermal Resistance, RTH (Junction to
Ground Paddle)
Operating Temperature
Storage Temperature
ESD Sensitivity, Human Body Model (HBM)
Maximum Peak Reflow Temperature
Rating
5.5 V
12 dBm
175°C
1.97 W
45.5°C/W
−40°C to +85°C
−65°C to +150°C
Class 0,
passed 150 V
260°C
ESD CAUTION
Rev. A | Page 4 of 14
Data Sheet
HMC1131
VDD1
VDD2
VDD3
VDD4
NIC
23
22
21
20
19
GND
14
NIC
NIC
6
13
NIC
12
15
5
NIC
4
NIC
11
GND
10
RFOUT
TOP VIEW
(Not to Scale)
NIC
16
VGG2
HMC1131
9
3
8
GND
RFIN
NIC
NIC
17
VGG1
18
2
7
1
NIC
NIC
GND
NOTES
1. NIC = NOT INTERNALLY CONNECTED.
2. THE EXPOSED PAD MUST BE CONNECTED
TO RF/DC GROUND.
13105-100
NIC
24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1, 5 to 7, 9, 10, 12 to 14,
18, 19, 24
2, 4, 15, 17
3
8
Mnemonic
NIC
GND
RFIN
VGG1
11
VGG2
16
20 to 23
RFOUT
VDD4 to VDD1
EPAD
Description
Not Internally Connected. However, all data was measured with these pins connected to RF/dc
ground externally.
Ground. These pins must be connected to RF/dc ground.
RF Input. This pin is ac-coupled and matched to 50 Ω.
Gate Bias Pin for the First and Second Stages. External bypass capacitors of 100 pF, 10 nF, and 4.7 μF
are required for this pin.
Gate Bias Pin for the Third and Fourth Stages. External bypass capacitors of 100 pF, 10 nF, and 4.7 μF
are required for this pin.
RF Output. This pin is ac-coupled and matched to 50 Ω.
Drain Bias Voltage Pins. External bypass capacitors of 100 pF, 10 nF, and 4.7 μF are required for
these pins.
Exposed Pad. The exposed pad must be connected to RF/dc ground.
Rev. A | Page 5 of 14
HMC1131
Data Sheet
INTERFACE SCHEMATICS
13105-025
1.5kΩ
13105-028
RFOUT
RFIN
1.5kΩ
Figure 3. RFIN Interface Schematic
Figure 6. RFOUT Interface Schematic
VDD1, VDD2,
VDD3, VDD4
13105-029
13105-026
GND
Figure 4. GND Interface Schematic
13105-027
VGG1, VGG2
Figure 7. VDD1 to VDD4 Interface Schematic
Figure 5. VGG1/VGG2 Interface Schematic
Rev. A | Page 6 of 14
Data Sheet
HMC1131
TYPICAL PERFORMANCE CHARACTERISTICS
30
30
28
20
24
10
GAIN (dB)
RESPONSE (dB)
26
0
22
20
18
–10
16
25
27
29
31
33
35
37
FREQUENCY (GHz)
12
24
13105-002
–30
23
–5
OUTPUT RETURN LOSS (dB)
–5
–10
–15
–20
–25
26
27
28
29
30
31
32
33
34
35
36
FREQUENCY (GHz)
Figure 9. Input Return Loss vs. Frequency at Various Temperatures
28
29
30
31
32
33
34
35
36
–10
–15
–20
–25
–35
24
TA = +85°C
TA = +25°C
TA = –40°C
25
26
27
28
29
30
31
32
33
34
35
36
FREQUENCY (GHz)
Figure 12. Output Return Loss vs. Frequency at Various Temperatures
30
28
28
26
26
24
24
P1dB (dBm)
30
22
20
18
22
20
18
16
TA = +85°C
TA = +25°C
TA = –40°C
14
12
24
25
26
27
28
29
30
31
32
33
34
35
FREQUENCY (GHz)
14
36
Figure 10. P1dB vs. Frequency at Various Temperatures
12
24
4V
5V
25
26
27
28
29
30
31
32
33
34
35
FREQUENCY (GHz)
Figure 13. P1dB vs. Frequency at Various Supply Voltages
Rev. A | Page 7 of 14
36
13105-007
16
13105-004
P1dB (dBm)
27
–30
TA = +85°C
TA = +25°C
TA = –40°C
13105-003
INPUT RETURN LOSS (dB)
0
25
26
Figure 11. Gain vs. Frequency at Various Temperatures
0
–30
25
FREQUENCY (GHz)
Figure 8. Response (Broadband Gain and Return Loss) vs. Frequency
–35
24
TA = +85°C
TA = +25°C
TA = –40°C
14
13105-005
S11
S21
S22
13105-006
–20
Data Sheet
30
30
28
28
26
26
24
24
PSAT (dBm)
22
20
18
20
18
16
TA = +85°C
TA = +25°C
TA = –40°C
25
26
27
28
29
30
31
32
33
34
35
36
FREQUENCY (GHz)
28
28
26
26
24
24
PSAT (dBm)
30
22
20
18
27
28
29
30
31
32
33
34
35
36
22
20
18
16
16
175mA
200mA
225mA
250mA
25
26
27
28
29
30
31
32
33
34
35
175mA
200mA
225mA
250mA
14
36
FREQUENCY (GHz)
12
24
13105-009
14
25
26
27
28
29
30
31
32
33
34
38
36
36
34
34
OUTPUT IP3 (dBm)
40
38
32
30
28
26
24
32
30
28
26
24
TA = +85°C
TA = +25°C
TA = –40°C
26
27
28
29
30
31
32
33
34
35
175mA
200mA
225mA
250mA
22
36
FREQUENCY (GHz)
13105-010
25
36
Figure 18. PSAT vs. Frequency at Various Supply Currents
40
22
35
FREQUENCY (GHz)
Figure 15. P1dB vs. Frequency at Various Supply Currents
OUTPUT IP3 (dBm)
26
Figure 17. PSAT vs. Frequency at Various Supply Voltages
30
20
24
25
FREQUENCY (GHz)
Figure 14. PSAT vs. Frequency at Various Temperatures
12
24
4V
5V
12
24
13105-012
12
24
14
13105-008
14
13105-011
16
P1dB (dBm)
22
Figure 16. Output IP3 vs. Frequency at Various Temperatures,
POUT/Tone = 10 dBm
20
24
25
26
27
28
29
30
31
32
33
34
35
36
FREQUENCY (GHz)
Figure 19. Output IP3 vs. Frequency at Various Supply Currents,
POUT/Tone = 10 dBm
Rev. A | Page 8 of 14
13105-013
PSAT (dBm)
HMC1131
Data Sheet
HMC1131
40
70
28GHz
30GHz
32GHz
34GHz
38
60
34
OUTPUT IM3 (dBc)
32
30
28
26
50
40
24
30
22
27
28
29
30
31
32
33
34
35
36
FREQUENCY (GHz)
20
14
12
16
Figure 23. Output Third-Order Intermodulation (IM3) vs.
POUT/Tone at VDD = 4 V
30
400
60
25
370
20
340
15
310
10
280
POUT (dBm), GAIN (dB), PAE (%)
70
50
40
30
28GHz
30GHz
32GHz
34GHz
20
4
6
8
10
12
14
16
POUT/TONE (dBm)
0
–15 –13 –11
26
26
GAIN (dB), P1dB (dBm), PSAT (dBm)
27
25
24
23
22
21
225
250
IDD (mA)
13105-016
PSAT
GAIN
P1dB
200
–7
–5
–3
–1
1
3
7
5
220
9
Figure 24. Power Compression at 30.5 GHz
(PAE Is Power Added Efficiency)
27
19
175
–9
250
INPUT POWER (dBm)
Figure 21. Output Third-Order Intermodulation (IM3) vs.
POUT/Tone at VDD = 5 V
20
POUT
PAE
GAIN
IDD
5
13105-015
OUTPUT IM3 (dBc)
10
8
POUT/TONE (dBm)
Figure 20. Output IP3 vs. Frequency for Various Supply Voltages,
POUT/Tone = 10 dBm
GAIN (dB), P1dB (dBm), PSAT (dBm)
6
4
13105-018
26
IDD (mA)
25
13105-017
4V
5V
13105-014
20
24
Figure 22. Gain, P1dB, and PSAT vs. Supply Current (IDD) at 30.5 GHz
25
24
23
22
21
PSAT
GAIN
P1dB
20
19
4.0
4.2
4.4
4.6
4.8
5.0
VDD (V)
Figure 25. Gain, P1dB, and PSAT vs. Supply Voltage (VDD) at 30.5 GHz
Rev. A | Page 9 of 14
13105-019
OUTPUT IP3 (dBm)
36
HMC1131
Data Sheet
0
40
35
OUTPUT IP3 (dBm)
30
–20
–30
–40
20
15
TA = +85°C
TA = +25°C
TA = –40°C
25
26
27
28
29
30
31
32
33
34
35
10dBm
12dBm
14dBm
5
36
FREQUENCY (GHz)
0
170
Figure 26. Reverse Isolation vs. Frequency at Various Temperatures
175
180
185
190
195
200
205
210
215
220
225
IDD (mA)
13105-023
–60
24
Figure 29. Output IP3 vs. IDD over POUT/Tone at 30 GHz,
VDD = 5 V, IDD = 225 mA, IDD2 = Fixed, and IDD1 Varied from 0 mA to 50 mA
25
25
20
20
15
15
GAIN (dB)
INPUT IP3 (dBm)
25
10
–50
13105-020
REVERSE ISOLATION (dB)
–10
10
5
10
5
175
180
185
190
195
200
205
210
215
220
225
IDD (mA)
0
170
13105-021
0
170
Figure 27. Input IP3 vs. IDD over POUT/Tone at 30 GHz,
VDD = 5 V, IDD = 225 mA, IDD2 = Fixed, and IDD1 Varied from 0 mA to 50 mA
27GHz
28GHz
30GHz
32GHz
33GHz
34GHz
1.4
1.2
1.0
0.8
0.6
–12
–9
–6
–3
–0
3
6
9
INPUT POWER (dBm)
185
190
195
200
205
210
215
220
225
Figure 30. Gain vs. IDD over POUT/Tone = 14 dBm at 30 GHz,
VDD = 5 V, IDD = 225 mA, IDD2 = Fixed, and IDD1 Varied from 0 mA to50 mA
13105-022
POWER DISSIPATION (W)
1.6
180
IDD (mA)
2.0
1.8
175
13105-024
10dBm
12dBm
14dBm
Figure 28. Power Dissipation (PDISS) at 85°C vs. Input Power for
Various Frequencies
Rev. A | Page 10 of 14
Data Sheet
HMC1131
APPLICATIONS INFORMATION
The following is the recommended bias sequence during
power-down:
The HMC1131 is a GaAs, pHEMT, MMIC, medium power
amplifier consisting of four gain stages in series. VGG1 is the gate
bias pin for the first and second stages, while VGG2 is the gate
bias pin for the third and fourth stages. A simplified block
diagram is shown in Figure 31.
1.
2.
All measurements for this device were taken using the evaluation
printed circuit board (PCB) in its default configuration. Unless
otherwise noted, the VGG1, VGG2, and VDD1 to VDD4 pins were
tied together during measurement, respectively.
3.
4.
The VDDx = 5 V and IDD = 225 mA bias conditions are the operating
points recommended to optimize the overall performance.
Unless otherwise noted, the data shown was taken using the
recommended bias conditions. Operation of the HMC1131 at
different bias conditions may result in performance that differs
from that shown in Figure 27 and Figure 30. Biasing the
HMC1131 for higher drain current typically results in higher
P1dB, OIP3, and gain but at the expense of increased power
consumption.
The following is the recommended bias sequence during
power-up:
5.
Connect to ground.
Set VGG1 and VGG2 to −2 V.
Set VDD1 through VDD4 to 5 V.
Increase VGG1 and VGG2 to achieve a quiescent
IDD = 225 mA.
Apply the RF signal.
VDD1
IDD1A
VDD3
VDD2
IDD1B
VDD4
IDD2A
IDD2B
RFOUT
RFIN
IDD1 = IDD1A + IDD1B
IDD2 = IDD2A + IDD2B
VGG1
VGG2
Figure 31. Simplified Block Diagram
Rev. A | Page 11 of 14
13105-032
1.
2.
3.
4.
Turn the RF signal off.
Decrease VGG1 and VGG2 to −2 V to achieve a quiescent
IDD = 0 mA (approximately).
Decrease VDD1 through VDD4 to 0 V.
Increase VGG1 and VGG2 to 0 V.
HMC1131
Data Sheet
EVALUATION PCB
exposed paddle must be connected directly to the ground plane
similar to what is shown in Figure 32. Use a sufficient number
of via holes to connect the top and bottom ground planes.
Generate the evaluation PCB used in this application with
proper RF circuit design techniques. Signal lines at the RF port
must have 50 Ω impedance, and the package ground leads and
THRU CAL
VD2
VD3
TP3
+
C17
C15
+
+
C16
C18
C11
C10
C3
C1
C2
C4
C8
+
C9
TP2
TP1
VD4
TP4
VD1
U1
C12
C6
C7
C5
C13
C14
+
RFOUT
C20
TP5
VG2
600-00145-00-1
+
+
C21
C19
TP6 TP7
VCTRL
VG1
13105-031
RFIN
Figure 32. 600-00145-00-1 Evaluation PCB
Bill of Materials
Table 5. Evaluation Board (EV1HMC1131LC4) Bill of Materials
Item
J1, J2
TP1 to TP7
C1 to C6
C8 to C13
C15 to C20
U1
PCB
1
Description
PCB mount, K connector
DC pin
100 pF capacitors, 0402 package
10000 pF capacitors, 0402 package
2.2 µF capacitors, 0402 package
HMC1131LC4
600-00145-00-1 evaluation board, Rogers 4350 or Arlon 25FR circuit board material
Blank cells in the manufacturer column left blank intentionally for they are user selectable.
Rev. A | Page 12 of 14
Manufacturer 1
Analog Devices, Inc.
600-00145-00-1, Analog Devices, Inc.
Data Sheet
HMC1131
TYPICAL APPLICATION CIRCUIT
C16 +
4.7µF
+ C17
4.7µF
C10
0.01µF
C3
100pF
C4
100pF
C11
0.01µF
C18 +
4.7µF
1
18
NIC
2
17
GND
3
16
15
VDD4
RFOUT
RFOUT
GND
NIC
13
NIC
12
14
VGG2
VGG1
C20
+ 4.7µF
C13
0.01µF
C6
100pF
C5
100pF
Figure 33. Typical Application Circuit
Rev. A | Page 13 of 14
C12
0.01µF
C19
4.7µF +
13105-030
NIC
NIC
VGG1
11
HMC1131
10
6
NIC
VGG2
NIC
9
5
1.5kΩ
NIC
4
NIC
7
GND
1.5kΩ
VDD3
19
20
21
22
NIC
VDD1
23
NIC
GND
RFIN
RFIN
NIC
C9
0.01µF
VDD4
C2
100pF
VDD3
C1
100pF
VDD2
C8
0.01µF
24
VDD1
+ C15
4.7µF
8
VDD2
HMC1131
Data Sheet
OUTLINE DIMENSIONS
PIN 1
INDICATOR
4.13
4.00 SQ
3.87
0.36
0.30
0.24
PIN 1
(0.32 × 0.32)
19
24
1
18
0.50
BSC
EXPOSED
PAD
2.50 SQ
13
6
7
12
TOP VIEW
BOTTOM VIEW
SIDE VIEW
3.10 BSC
1.02 MAX
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
PKG-000000
SEATING
PLANE
04-03-2015-A
2.50 REF
Figure 34. 24-Terminal Ceramic Leadless Chip Carrier [LCC]
(HE-24-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
HMC1131LC4
Temperature Range
−40°C to +85°C
MSL Rating2
MSL3
Lead Finish
Gold over Nickel
Package Description
24-Terminal LCC
Package Option
HE-24-1
HMC1131LC4TR
−40°C to +85°C
MSL3
Gold over Nickel
24-Terminal LCC
HE-24-1
EV1HMC1131LC4
1
2
3
Evaluation Board
The HMC1131LC4 and the HMC1131LC4TR are RoHS Compliant.
See the Absolute Maximum Ratings section.
XXXX is the 4-digit lot number.
©2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13105-0-9/15(A)
Rev. A | Page 14 of 14
Branding3
H1131
XXXX
H1131
XXXX