Evaluation Board Documentation
ADE7763 Energy Metering IC
EVAL-ADE7763EB
The evaluation board was designed so that the ADE7763 can be
evaluated in the end application, i.e., watt-hour meter. Using the
appropriate transducers on the current channel, e.g., di/dt
sensor, CT, and shunt, the evaluation board can be connected to
a test bench or high voltage (240 V rms) test circuit. An onboard resistor divider network provides the attenuation for the
line voltage. This data sheet also describes how the current
transducers should be connected for the best performance. The
ADE7763 has a built-in digital integrator that allows for simple
interfacing with any di/dt sensor (such as the Rogowski coil).
FEATURES
Evaluation board is designed to be used together with
accompanying software to implement a fully functional
energy meter (watt-hour meter)
Easy connection of various external transducers via screw
terminals
Easy modification of signal conditioning components using
PCB sockets
LED indicators on logic outputs CF, ZX, SAG, and IRQ
Optically isolated data output connection to PC parallel port
Optically isolated frequency output (CF) to BNC
External reference option available for on-chip reference
evaluation
The evaluation board (watt-hour meter) is configured and
calibrated via the parallel port of a PC. The data interface
between the evaluation board and the PC is fully isolated.
Windows® based software is provided with the evaluation board
so it can be configured quickly as an energy meter.
GENERAL DESCRIPTION
The ADE7763 is a high accuracy electrical power measurement
IC with a serial interface and pulse output. The ADE7763
incorporates two second-order Σ-Δ ADCs, reference circuitry,
temperature sensor, and all the signal processing required to
perform active and apparent energy measurement.
The evaluation board also functions as a standalone evaluation
system, which can be incorporated easily into an existing system
via a 25-way D-Sub connector.
The evaluation board requires two external 5 V power supplies
(one is required for isolation purposes) and the appropriate
current transducer.
This data sheet describes the ADE7763 evaluation kit’s
hardware and software functionality. The ADE7763 evaluation
board, together with the ADE7763 data sheet and the EVALADE7763EB data sheet, provides a complete evaluation
platform for the ADE7763.
FUNCTIONAL BLOCK DIAGRAM
AGND
V1P
DVDD DGND +5V
AVDD
FILTER
NETWORK
V1N
V–
DOUT
SCLK
DIN
CS
74HC08
ADE7763
AGND
V+
CONNECTOR
TO PC
PARALLEL
PORT
RESET
74HC08
V2N
V2P
FILTER
NETWORK
AND
ATTENUATION
EXTERNAL 2.5V
AD780
REFERENCE
BNC
EXTERNAL
CLOCK IN
OPTICALLY
COUPLED
FREQUENCY
OUTPUT
CF
ZX
SAG
IRQ
04729-0-001
PROTOTYPE
AREA
BNC
CF
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
EVAL-ADE7763EB
TABLE OF CONTENTS
Analog Inputs (SK1 and SK2) ......................................................... 3
Online Help................................................................................. 10
Current Sense Inputs (SK2) ........................................................ 3
Measuring CT Phase Errors Using the ADE7763.................. 11
Using a di/dt Sensor as the Current Transducer ...................... 3
Using Phase Calibration to Correct Small (<0.5°) External
Phase Errors ................................................................................ 11
Using a CT as the Current Transducer ...................................... 4
Using a Shunt Resistor as the Current Transducer .................. 4
Voltage Sense Inputs .................................................................... 5
Jumper Settings ................................................................................. 6
Setting Up the ADE7763 Evaluation Board .................................. 7
Evaluation Software.......................................................................... 8
Installing the ADE7763 Software ............................................... 8
Removing the ADE7763 Evaluation Software .......................... 8
Main Menu .................................................................................... 8
Calibrating the Meter................................................................... 9
Menu Selections............................................................................ 9
Correcting Large External Phase Errors ................................. 11
Evaluation Board Bill of Materials ............................................... 12
Evaluation Board Schematic (Rev. D and Rev. E) ...................... 13
PCB Layout—Component Placement (Rev. D).......................... 14
PCB Layout—Component Side (Rev. D)..................................... 15
PCB Layout—Solder Side (Rev. D) .............................................. 16
PCB Layout—Component Placement (Rev. E) .......................... 17
PCB Layout—Component Side (Rev. E) ..................................... 18
PCB Layout—Solder Side (Rev. E) ............................................... 19
Ordering Guide .......................................................................... 20
Waveform Sampling Routine.................................................... 10
REVISION HISTORY
4/04—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
EVAL-ADE7763EB
ANALOG INPUTS (SK1 AND SK2)
Voltage and current signals are connected at the screw terminals
SK1 and SK2, respectively. All analog input signals are filtered
using the on-board antialiasing filters before being presented to
the analog inputs of the ADE7763. The default component
values, which are shipped with the evaluation board, are the
recommended values for the ADE7763. Users can easily change
these components if they are familiar with selecting the
component values for the analog input filters. Interested users
are encouraged to refer to the ADE7763 data sheet for a more
comprehensive description of the antialiasing filters and their
function.
USING A DI/DT SENSOR AS THE CURRENT
TRANSDUCER
Figure 3 shows how a di/dt sensor can be used as a current
transducer in a signal-phase, 2-wire distribution system. A di/dt
sensor is typically made from an air-core coil. Because of the
mutual inductance between the coil and the phase wire, a
voltage signal is output from the coil, which is proportional to
the time differentiation of the current (di/dt).
PHASE
WIRE
JP15
JP1
100Ω
1kΩ
33nF
C50
JP3
TP1
CURRENT SENSE INPUTS (SK2)
JP2
SK2 is a 3-way connection block that allows the ADE7763 to be
connected to a current transducer. Figure 2 shows the connector
SK2 and the filtering network provided on the evaluation board.
R50
100Ω
JP2
SK2 2
JP4
JP25
C11
1kΩ
33nF
C50
JP3
R42
R51
100Ω
1kΩ
33nF
C51
C21
TP1
TP2
V1N
33nF
ADE7763
SK2 3
C21
1kΩ
33nF
C51
33nF
FULL-SCALE
DIFFERENTIAL INPUT = 62.5mV
AT GAIN = +8
Figure 3. di/dt Sensor Connection to Current Channel
The di/dt sensor outputs a voltage by mutual inductance. When
using a di/dt sensor as the current sensor, Jumpers JP15/JP25
and JP1/JP3 should be left open. Both sets of filters are
necessary to provide the antialiasing filters (see Figure 3).
In theory, air-core di/dt sensors have an associated phase shift
of +90° at all input frequencies. This phase shift is compensated
by the −90° phase shift of the integrator. Additional phase
error, from external component mismatch, for example,
can be corrected by writing to the phase calibration register
(PHCAL[7:0]) in the ADE7763. The software supplied with the
ADE7763 evaluation board allows users to adjust the phase
calibration register. See the Evaluation Software section for
more information.
V1P
33nF
SH1B
04729-0-002
SK2 1
JP1
R41
V1N
JP4
di/dt
CURRENT
SENSOR
The RC networks are the antialiasing filters required by the onchip ADCs. The default corner frequency for these low-pass
filters (LPF) is selected as 4.8 kHz (1 kΩ and 33nF). These filters
can easily be adjusted by replacing the components on the
evaluation board.
JP15
TP2
100Ω
ADE7763
The RC networks R41/C11 and R42/C21 provide attenuation
of high frequency noise and equalize the 20 dB/dec gain at high
frequency when the di/dt sensor is used as the current
transducer (see the Using a di/dt Sensor as the Current
Transducer section). These RC networks are easily disabled by
placing JP15 and JP25 and removing C11 and C21 (socketed).
SH1A
V1P
33nF
04729-0-003
The resistors SH1A and SH1B are by default not populated.
They should be used as burden resistors when a CT is used as
the current transducer (see the Using a CT as the Current
Transducer section).
JP25
C11
For this example, notice that the maximum analog input range
on Channel 1 is set to 62.5 mV, and the gain for Channel 1 has
been set to 8. The maximum analog input range and gain are set
via the gain register (GAIN). See the ADE7763 data sheet. The
evaluation software allows users to configure the channel range
and gain. The maximum peak differential signal on Channel 1 is
0.5 V (at Gain = +1).
Figure 2. Current Channel on the ADE7763 Evaluation Board
Rev. 0 | Page 3 of 20
EVAL-ADE7763EB
USING A SHUNT RESISTOR AS THE CURRENT
TRANSDUCER
Figure 4 shows how a CT can be used as a current transducer in
a signal-phase, 3-wire distribution system. This is how electrical
energy is distributed to residential users in the United States.
Phase A and Phase B are nominally 180° out of phase. The
vector addition of the two currents is easily achieved by using
two primary turns of opposite polarity on the CT.
PHASE B
IMAX = 80A
CT
1:1800
SH1A
2.8Ω
JP15
JP1
TP1
JP2
100Ω
1kΩ
JP25
JP3
100Ω
1kΩ
C50
33nF
V1P
355mV
RMS
TP2
V1N
C51
33nF
PHASE A
ADE7763
SH1B
2.8Ω
FULL-SCALE
DIFFERENTIAL INPUT = 250mV
AT GAIN = +2
Figure 4. CT Connection to Current Channel
The CT secondary current is converted to a voltage by using a
burden resistance across the secondary winding outputs. Care
should be taken when using a CT as the current transducer. If
the secondary is left open, i.e., no burden is connected, a large
voltage could be present at the secondary outputs. This can
cause an electrical shock hazard and potentially damage
electronic components.
04729-0-004
JP4
Figure 5 shows how a shunt resistor can be used to perform the
current-to-voltage conversion required for the ADE7763. A
shunt is a cost-effective way to perform the current-to-voltage
conversion in a 2-wire, single-phase application. No isolation is
required in a 2-wire application, and the shunt has advantages
over the CT arrangement. For example, a shunt does not suffer
from dc saturation problems, and the phase response of the
shunt is linear over a very wide dynamic range. Although the
shunt is predominately resistive, it does have parasitic reactive
elements (inductance) that can become significant, even at
50 Hz/60 Hz. This means that there can be a small phase shift
associated with the shunt. Once it is understood, the phase shift
is easily compensated for with the filter network R41/C11 and
R42/C21 (see Application Note AN-559 for more details).
The shunt used in this example is a 200 µΩ Manganin® type.
The resistance of the shunt should be as low as possible in order
to avoid excessive power dissipation in the shunt. Figure 5
shows how the shunt can be connected to the evaluation board.
Two sense wires should be soldered to the shunt as shown at the
copper/Manganin junctions. These sense wires should be
formed into a twisted pair to reduce the loop area that reduces
antenna effects. A connection for the common-mode voltage
can be made at the connection point for the current-carrying
conductor (see Figure 5).
TWISTED-PAIR
CONNECTION
The antialiasing filters should be enabled by opening Jumpers
JP1/JP3 (see Figure 4).
Most CTs have an associated phase shift of between 0.1° and 1°
at 50 Hz/60 Hz. This phase shift or phase error can lead to
significant energy measurement errors, especially at low power
factors. However, this phase error can be corrected by writing to
the phase calibration register (PHCAL[7:0]) in the ADE7763.
The software supplied with the ADE7763 evaluation board
allows users to adjust the phase calibration register. See the
Evaluation Software section for more information.
JP15
200µΩ
When using a CT as the current sensor, the phase compensation
network for a shunt application should be disabled. This is
achieved by closing Jumpers JP15/JP25 and removing C11/C21.
JP1
TP1
100Ω
JP2
JP25
C11
1kΩ
33nF
C50
JP3
33nF
V1P
16mV
RMS
TP2
V1N
100Ω
80A
JP4
C21
1kΩ
33nF
C51
33nF
ADE7763
BVM-D-R0002-5.0
For this example, notice that the maximum analog input range
on Channel 1 is set to 250 mV, and the gain for Channel 1 has
be set to 2. The maximum analog input range and gain are set
via the gain register (GAIN). See the ADE7763 data sheet. The
evaluation software allows users to configure the channel range
and gain.
Rev. 0 | Page 4 of 20
FULL-SCALE
DIFFERENTIAL INPUT = 31.25mV
AT GAIN = +16
Figure 5. Shunt Connection to Current Channel
04729-0-005
USING A CT AS THE CURRENT TRANSDUCER
EVAL-ADE7763EB
Note that the analog input V2N is connected to AGND via the
antialiasing filter R57/C54 using JP10. Also, Jumper JP9 should
be left open.
VOLTAGE SENSE INPUTS
The voltage input connections on the ADE7763 evaluation
board can be directly connected to the line voltage source.
The line voltage is attenuated using a simple resistor divider
network before it is presented to the ADE7763. Because of the
relatively large signal on this channel and the small dynamic
range requirement, the voltage channel can be configured in a
single-ended configuration. Figure 6 shows a typical connection
for the line voltage.
The voltage attenuation network is made up of R53, R54, and
R56. The maximum signal level permissible at V2P is 0.5 V
peak. Although the ADE7763 analog inputs can withstand ±6 V
without risk of permanent damage, the signal range should not
exceed ±0.5 V with respect to AGND for specified operation.
The attenuation network can be easily modified by the user to
accommodate any input signal levels. However, the value of R56
(1 kΩ) should not be altered as the phase response of Channel 2
should match the phase response of Channel 1 (see Application
Note AN-559).
PHASE
JP9
TP5
R57
SK1 1
V2N
1kΩ
JP10
C54
33nF
JP7
JP8
255kΩ
255kΩ
ATTENUATION
NETWORK
100V RMS TO 180V RMS
JP51 TP4
R54
V2P
R56
1kΩ
C53
33nF
200mV RMS
TO
300mV RMS
ADE7763
NEUTRAL
04729-0-006
R53
SK1 2
Figure 6. Voltage Channel on the ADE7763 Evaluation Board
Rev. 0 | Page 5 of 20
EVAL-ADE7763EB
JUMPER SETTINGS
Table 1.
JP14
Option
Closed
Open
Closed
Closed
Open
Closed
A
B
A
B
Closed
Closed
Closed
Open
Closed
Closed
A
B
Closed
Open
Closed
JP15
Closed
JP19
JP20
JP21
JP25
A
B
Closed
Closed
Closed
JP51
Closed
JP2
JP3
JP4
JP5
JP6
JP7
JP8
JP9
JP10
JP11
JP12
JP13
Description
This shorts out R50. The effect is to disable the antialiasing filter on the analog input V1P. Default open.
Enable the antialiasing filter on V1P.
This connects the analog input V1P to ground. Default open.
This shorts out R51. The effect is to disable the antialiasing filter on the analog input V1N. Default open.
Enable the antialiasing filter on V1N.
This connects the analog input V1N to ground. Default open.
This connects the buffered logic output IRQ to the LED1.
This connects the buffered logic output IRQ to Pin 10 on the D-Sub connector via an optical isolator.
This connects the buffered logic output SAG to the LED2.
This connects the buffered logic output SAG to Pin 11 on the D-Sub connector via an optical isolator.
This shorts the attenuation network on Channel 2. Default open.
This connects the analog input V2P to ground. Default open.
This shorts out R57. The effect is to disable the antialiaing filter on the analog input V2N. Default open.
Enable the antialiasing filter on V2N.
This connects the analog input V2N to ground. Default open.
This connects the analog and digital ground planes of the PCB. Default closed.
This connects the buffered logic output CF to the LED4.
This connects the buffered logic output CF to the BNC2 connector via an optical isolator.
This connects an external reference 2.5 V (AD780) to the ADE7763.
This enables the ADE7763 on-chip reference.
This connects the optical isolator ground to the evaluation board ground (DGND). If full isolation between the
evaluation board and PC is required, this jumper should be left open.
This shorts out R41. The effect is to disable the first-state antialiasing filter (for di/dt sensors or for shunts) on the
analog input V1P. Default open.
This connects the buffered logic output ZX to the LED3.
This connects the buffered logic output ZX to Pin 12 on the D-Sub connector via an optical isolator.
This connects the AVDD and DVDD supply for the evaluation board together. Default closed.
This connects the DVDD and 5 V (buffers) supply for the evaluation board together. Default closed.
This shorts out R42. The effect is to disable the first-state antialiasing filter (for di/dt sensors or shunt) on the analog
input V1N. Default open.
This shorts out/disconnects analog input V2P from the ADE7763. Default closed.
ADE7753/6/9 - Eval Rev D
JP20
JP21
JP14
JP2
JP4
JP15
JP1
JP25
JP3
ADE7763
JP9
JP51
JP10
JP7
JP8
AB
JP13
JP11
JP5
JP6
JP19
JP12
AB
04729-0-007
Jumper
JP1
Figure 7. ADE7763 Evaluation Board Jumper Positions
Rev. 0 | Page 6 of 20
EVAL-ADE7763EB
SETTING UP THE ADE7763 EVALUATION BOARD
Figure 8 shows a typical setup for the ADE7763 evaluation
board. In this example, a kWh meter for a 2-wire, single-phase
distribution system is shown. For a more detailed description
on how to use a di/dt as a current transducer, see the Current
Sense Inputs (SK2) section. The line voltage is connected
directly to the evaluation board, as shown in Figure 8. Note
JP7 should be left open to ensure that the attenuation network is
not bypassed, and also note the use of two power supplies. The
second power supply is used to power the optical isolation. With
JP14 left open, there is no electrical connection between the
high voltage test circuit and the PC. The power supplies should
have floating voltage outputs.
The evaluation board is connected to the PC parallel port using
the cable supplied. The cable length should not exceed 6 feet
(2 meters) or the serial communication between the PC and the
evaluation board may become unpredictable and error prone.
When the evaluation board has been powered up and is
connected to the PC, the supplied software can be launched.
The software automatically starts in energy meter mode. The
next section describes how the ADE7763 evaluation software
can be installed and removed.
–
5.000 V
+
+
NEUTRAL
PHASE
DGND
DVDD
JP2
JP1
R41
R50
100Ω
1kΩ
33nF
C50
JP3
JP25
C11
R42
R51
100Ω
1kΩ
33nF
C51
JP4
V+
C21
V1P
33nF
V1N
33nF
AGND
JP9
SK1
R57
V2N
1kΩ
JP10
C54
33nF
JP7
JP8
V–
SK5
JP15
SK2
+5V
SK4
di/dt CURRENT SENSOR
110V
–
R53
R54
255kΩ
255kΩ
JP1 = OPEN
JP2 = OPEN
JP3 = OPEN
JP4 = OPEN
JP5 = B
JP6 = B
JP7 = OPEN
JP8 = OPEN
JP9 = OPEN
JP10 = CLOSED
JP11 = CLOSED
JP12 = B
JP13 = OPEN
JP14 = OPEN
JP15 = OPEN
JP19 = B
JP20 = CLOSED
JP21 = CLOSED
JP25 = OPEN
TO PC
PARALLEL
PORT
BNC2
215mV RMS
FREQUENCY COUNTER
V2P
R56
1kΩ
1.0666 Hz
C53
33nF
LOAD
Figure 8. Typical Setup for the ADE7763 Evaluation Board
Rev. 0 | Page 7 of 20
04729-0-008
5.000 V
EVAL-ADE7763EB
EVALUATION SOFTWARE
The ADE7763 evaluation board is supported by Windows based
software that allows users to access all the functionality of the
ADE7763. The software is designed to communicate with the
ADE7763 evaluation board via the parallel port of the PC.
INSTALLING THE ADE7763 SOFTWARE
The ADE7763 software is supplied on a CD. The minimum
requirements for the PC are Pentium® II 233 MHz processor,
32 MB RAM, 10 MB free HD space, and at least one PS/2 or
ECP parallel port. To install the software place the CD in the
drive and double-click setup.exe. This launches the setup
program, which automatically installs all the software
components, including the uninstall program, and creates the
required directories. When the setup program has finished
installing the ADE7763eval program, users are prompted to
install National Instruments’ run-time engine. This software
was developed using National Instruments’ LabVIEW™
software, and the run-time engine is required to run the
ADE7763eval program. GIVEIO software is required to run the
program on all systems. Users are prompted to install this
software as well, and they should follow the on-screen
instructions to complete the installation. Users need to reboot
their computers to complete the installation. To launch the
software, select Start—>Programs—>ADE7763 menu and click
ADE7763eval.
REMOVING THE ADE7763 EVALUATION
SOFTWARE
The ADE7763Eval program, National Instruments’ run-time
engine, and GIVEIO are easily removed by using the Add
or Remove Programs feature in the Control Panel. Select
Start—>Control Panel—>Add or Remove Programs and click
the program to remove it.
Figure 9. Removing the ADE7763 Evaluation Software
MAIN MENU
When the software is launched, the program automatically
displays the main menu shown in Figure 10. To stop the
ADE7763eval software, select Exit from the menu. Each of the 9
selections in the menu starts a new window that accesses the
registers and displays information from the ADE7763. By
pressing the Exit button in the new window, users are brought
back to the main menu. Register values are not reset by the
program when a new window opens or closes. The register
addresses and functionality can be found in the ADE7763
data sheet.
Using the ADE7763eval software, the evaluation board can be
used as a fully functional energy meter. When the appropriate
line voltage, test current, frequency, and meter constant are set
up, users can use the calibration routine to remove any errors
associated with the transducers. The CF output can be used
with a standard frequency counter to check the accuracy. The
measured CF output frequency should be adjusted to match the
theoretical CF frequency of the evaluation software.
Note that the calibration routine does not automatically remove
the phase mismatch errors associated with the current and
voltage transducer. These must be removed by using the
ADE7763 PHCAL register. This is explained in the Measuring
CT Phase Errors Using the ADE7763 section. The calibration
routine is launched by selecting Calibration from the menu.
Rev. 0 | Page 8 of 20
EVAL-ADE7763EB
Ensure that the analog input signal levels have been matched to
the transducer output signal levels, as previously described.
Figure 10. Main Menu
Figure 11. Calibration Window
Note also that the input signal range and gain must be set for
the PGAs on Channel 1 and Channel 2. This ensures that the
output signal range from the transducers is matched to the
analog inputs. For example, by selecting a gain of 1 for the PGA
in Channel 2, the peak differential input signal is set to 500 mV.
In the meter example shown in Figure 8, the line voltage is
attenuated to approximately 215 mV rms or 304 mV peak.
Similarly, as an example for Channel 1, assuming a maximum
current of 120 A, the maximum differential output signal
from the di/dt sensor is 30 mV rms or 42 mV peak (the value
depends on the sensor used). To allow for surge current, the
full-scale differential input signal level is set to 62 mV by
setting the gain to 2 if the ADC input range is set to 0.125 V
(see Table I in the ADE7763 data sheet). Access to the PGAs is
allowed in the active energy and apparent energy windows that
can be opened from the menu.
MENU SELECTIONS
The menu selections include the following: Interrupt Registers,
Active Energy, Apparent Energy, Offsets, Power Quality
Information, Line Accumulation, Calibration, and Temperature.
The mask and status interrupt registers described in the
ADE7763 data sheet are accessible from the Interrupt Registers
window. In the Active Energy and Apparent Energy windows,
users can view the datapath, configure or reset the part by
writing to the necessary registers, and read the active or
apparent energy registers.
In addition, Waveform Sampling is available from any of these
selections. Figure 12 shows the Active Energy window.
CALIBRATING THE METER
In order to calibrate the energy meter, the line voltage, test
current, line frequency, and meter constant must be entered, as
shown in Figure 11. In this example, the line voltage is 220 V, the
test current is 5 A, the frequency is 50 Hz, and the required
meter constant is 3,200 imp/kWh. The menu lists the option for
calibrating active or apparent energy. Once the parameters are
entered, the voltage and current circuits are energized, and the
energy is selected, click the Calibrate button. The software then
executes the calibration routine and automatically starts to
register energy.
Calibration can be done by changing the CFDEN, CFNUM, and
WGAIN (or VAGAIN) registers, which is explained in the
ADE7763 data sheet. The measured CF output frequency is
then adjusted to match the theoretical CF frequency of the
evaluation software. To write to CFNUM, CFDEN, and WGAIN
for manual calibration, click Adjust Values. Calibration should
be run before this is done to calculate the target frequency.
Figure 12. Active Energy Window
Channel 1, Channel 2, active power, and rms offset registers are
accessible via the Offsets selection from the menu. The user
may modify and view rms, peak, and SAG registers from the
Power Quality window. Additionally, the relevant mask and
status registers are presented in this window.
Rev. 0 | Page 9 of 20
EVAL-ADE7763EB
The Line Accumulation window allows one to view line
accumulation active energy and line accumulation apparent
energy. To begin line accumulation, press the Start Read button.
The number of line cycles can be changed in this window at any
time.
When using this feature with sine wave signals, the user should
be aware that if the samples represent a noninteger number of
periods of the selected signal, then the rms and mean values are
biased. To correct this, the number of samples should be chosen
to give an integer number of signal cycles as follows:
WAVEFORM SAMPLING ROUTINE
No. of Samples =
In this mode, the evaluation software programs the ADE7763
for waveform sampling with an updated rate of 3.5 kSPS
(CLKIN/1024). The user can define the number of samples
needed and select the signal waveform to transfer. The options
are Channel 1, Channel 2, or multiplier waveforms. Three
parameters are processed when the waveform is displayed: rms
value, mean value, and standard deviation. For comparison, the
voltage and current rms registers are shown in the waveform
sampling window (Figure 13). The waveform sampling routine
can be accessed from the Active Energy, Apparent Energy, or
Power Quality windows by pressing the Waveform Sampling
button. Figure 13 shows the Waveform Sampling Window.
No. of Signal Cycles × ADE7763 CLKIN Frequency
1024 × Signal Frequency
ONLINE HELP
The ADE7763 evaluation software also comes with an online
help feature. Select Help —> Show Help on the menu (see
Figure 14). A Help Window opens. For a description of a
particular option, e.g., button or text box, move the cursor over
the item. The Help window displays a description of the item.
Figure 14. Online Help Function
Figure 13. Waveform Sampling Window
Rev. 0 | Page 10 of 20
EVAL-ADE7763EB
MEASURING CT PHASE ERRORS USING THE
ADE7763
USING PHASE CALIBRATION TO CORRECT SMALL
(<0.5°) EXTERNAL PHASE ERRORS
The ADE7763 can measure the phase error associated with the
current sensor during calibration. The ADE7763 has negligible
internal phase error (PHCAL = 00 hex), and the error due to
external components is small (<0.5°). The procedure is based on
a 2-point measurement, at PF = 1 and PF = 0.5 (lag). The PF is
set up using the test bench source, and this source must be very
accurate. The ADE7763 should be configured for energy
measurement mode.
From the previous example, it is seen that the CT introduced a
phase lead in Channel 1 of 0.091°. Therefore, instead of a 60°
phase difference between Channel 1 and Channel 2, it is
actually 59.89°. In order to bring the phase difference back to
60°, the phase compensation circuit in Channel 2 is used to
introduce an extra lead of 0.091°. This is achieved by reducing
the amount of time delay in Channel 2.
An energy measurement is first made with PF = 1
(Measurement A). A second energy measurement should be
made at PF = 0.5 (Measurement B). The frequency output CF
can be used for this measurement. Using the following formula,
the phase error is easily calculated:
⎛ B − A2 ⎞
⎟
Phase Error (°) = tan −1 ⎜
⎜A × 3⎟
⎠
⎝ 2
For example, using the frequency output CF to measure power,
a frequency of 3.66621 Hz is recorded for PF = 1. The PF is then
set to 0.5 lag and a measurement of 1.83817 Hz is obtained.
Using the formula above, the phase error on Channel 1 is
calculated as:
⎛ 1.83817 − 3.6662 1 2 ⎞
⎟ = 0.091°
Phase Error (°) = tan −1 ⎜
⎜ 3.6662 1 × 3 ⎟
2
⎠
⎝
The formula also gives the correct sign for the phase error. In
this example, the phase error is calculated as 0.091° at the input
to Channel 1 of the ADE7763. This means that the current
sensor has introduced a phase lead of 0.091°. Therefore, the
phase difference at the input to Channel 1 is now 59.89° lag
instead of 60° lag. Determining whether the error is a lead
or lag can also be figured intuitively from the frequency output.
Figure 15 shows how the output frequency varies with phase
(cos {Φ}). Because the Output Frequency B (1.83817 Hz) at the
PF = 0.5 lag setting in the example is actually greater than A/2
(1.833105 Hz), the phase error between Channel 1 and Channel 2
is actually less than 60°. This means there is additional lead in
Channel 1 due to the CT.
CF (Hz)
The maximum time delay adjustment in Channel 2 is −97.86 µs
to +39.96 µs with a CLKIN of 3.579545 MHz. The PHCAL
register is a signed twos complement 6-bit register. Therefore,
each LSB is equivalent to 2.22 µs. The default value of this
register is 0x0D and is equivalent to 0.00°. In this example, the
line frequency is 50 Hz. This means each LSB is equivalent to
360° × 2.22 µs × 50 Hz = 0.040°. To introduce a lead of 0.091°,
the delay in Channel 2 must be reduced. This is achieved by
writing 0xB or +0.08° to the PHCAL register. The PHCAL
register can be written to by entering the value in the active
energy window.
CORRECTING LARGE EXTERNAL PHASE ERRORS
In this example, the phase correction range at 50 Hz is
approximately −1.76° to +0.7°. However, it is best to use the
PHCAL register only for small phase corrections, i.e., <0.5°.
If larger corrections are required, the larger part of the
correction can be made using an external passive component.
For example, the resistors in the antialiasing filter can be
modified to shift the corner frequency of the filter to introduce
more or less lag. The lag through the antialiasing filters with
1 kΩ and 33 nF is 0.56° at 50 Hz. Fine adjustment can be made
with the PHCAL register. Note that typically CT phase shift
does not vary significantly from part to part. If a CT phase shift
is 1°, then the part-to-part variation should only be about ±0.1°.
Therefore, the bulk of the phase shift (1°) can be canceled with
fixed component values at design. The remaining small
adjustments can be made in production using the PHCAL
register.
FREQUENCY B > A/2
PHASE DIFFERENCE < 60° LAG
PF = 1
PF > 0.5
PF = 0.5
PF < 0.5
PF = 0
360°
PHASE LAG
04729-0-015
60°
Figure 15. CF Frequency vs. Phase (PF)
Rev. 0 | Page 11 of 20
EVAL-ADE7763EB
EVALUATION BOARD BILL OF MATERIALS
Table 2.
Designator
R3, R5, R6, R13,
R22, R30, R31,
R33, R34, R37
R2, R7 to R10,
R39, R40
R1, R14 to R27, R36
R50 to R52, R57
Value
100 Ω, 5%, ¼ Ω
Description
Resistor, No Special Requirements.
10 kΩ, 5%, ¼ Ω
Resistor, No Special Requirements.
820 Ω, 5%, ¼ Ω
1 kΩ, 0.1%, ¼ Ω
Resistor, No Special Requirements.
±5 ppm/°C Resistor, Good Tolerance, Used as Part of the Analog Filter Network. These
resistors are not soldered but are plugged into the PCB pin sockets for easy modification by
the customer. Low drift Vishay Dale Part No.CMF551001BT-2.
±5 ppm/°C Resistor, Good Tolerance. Vishay Dale Part No. CMF554993FT-1.
±5 ppm/°C Resistor, Good Tolerance. Low drift Vishay Dale Part No. CMF551000BT-2.
Not Populated, Pin Socket to Be Used with External 50 Ω Clock Source.
R53, R54
R41, R42
R11
R4
C5, C7, C24, C28, C30
C14, C15
C6, C8, C23, C25, C27,
C29, C31 to C36
C16
C11, C21, C50,
C51, C53, C54
499 kΩ, 0.1%, ¼ Ω
100 Ω, 0.1%, ¼ Ω
51 Ω, 1%, ¼ Ω
0 Ω, 10%,¼ Ω
10 µF, 10 V dc
22 pF, Ceramic
100 nF, 50 V
U1
U2, U3
U4
U5, U7 to U9
U6
LED1 to LED4
XTAL
ADE7763ARS
74HC08
AD780
HCPL2232
HCPL2211
LED
3.579545 MHz
SK1, SK3, SK5
Screw Terminal
SK2, SK4
Screw Terminal
BNC1, BNC2
P1
TP4 to TP14
JP1 to JP4, JP7 to
JP11,JP13 to JP15,
JP20, JP21, JP25, JP51
JP5, JP6, JP12, JP19
Pin Sockets
BNC Connector
D-Sub 25-Way Male
Test Point Loop
2-Pin Header
Pin Sockets
Discretes
220 pF
33 nF, 10%, 50 V
2-Pin Header × 2
DIL
Power Supply Decoupling Capacitors, 20%, AVX-Kyocera, Farnell Part No. 643-579.
Gate Oscillator Load Capacitors, Farnell Part No. 108-927.
Power Supply Decoupling Capacitors, 10%, X7R type, AVX-Kyocera,
Farnell Part No. 108-950.
AVX-Kyocera, Farnell Part No. 108-946.
X7R Capacitor, Part of the Filter Network. These resistors are not soldered but are plugged
into the PCB mount sockets for easy modification by the customer. The SR15 series
AVX-Kyocera, Farnell Part No. 108-948.
Supplied by Analog Devices, Inc.
Quad CMOS AND Gates.
2.5 V Reference, Supplied by Analog Devices, Inc.
HP Optical Isolator, Newark Part No. 06F5434.
HP Optical Isolator, Newark Part No. 06F5428.
Low Current, Red, Farnell Part No. 637-087.
Quartz Crystal, HC-49 (US), ECS Part No. ECS-35-17-4.
Digi-Key Part No. X079-ND.
15 A, 2.5 mm Cable Screw Terminal Sockets. Farnell Part No. 151-785, Length 10 mm,
Pitch 5 mm, Pin Diameter 1 mm.
15 A, 2.5 mm Cable Screw Terminal Sockets. Farnell Part No. 151-786, Length 15 mm,
Pitch 5 mm, Pin Diameter 1 mm.
Straight Square, 1.3 mm Holes, 10.2 mm × 10.2 mm Farnell Part No. 149-453.
AMP 747238-4 Right Angle D-Sub 8 mm PCB Mount, Digi-Key Part No. 747238-4.
Test Point Loop, Compnt Corp. TP-104-01-XX.
2-Pin, 0.025 Sq., 0.01 Ctrs, Compnt Corp., CSS-02-02.
2-Pin, 0.025 Sq., 0.01 Ctrs, Compnt Corp., CSS-02-02.
Sockets for U1 to U9, 0.022” to 0.025” Pin Diameter, ADI Stock 12-18-33.
Advance KSS100-85TG.
R11, R41, R42, R50 to R54, R57, C11, C21, C50 to C54. ADI Stock 12-18-41.
Rev. 0 | Page 12 of 20
Rev. 0 | Page 13 of 20
Figure 16. Evaluation Board Schematic
C8
100nF
1
04729-0-016
2
1
AVDD
2
2
1
1
2
3
1
2
1
2
3
JP8
TBLK02
SK1
TBLK03
SK2
TBLK02
SK3
TBLK03
SK4
C28
10µF
2
1
R53 2
JP7
JP11
+ C7
10µF
499kΩ
1 R54 2
499kΩ
1
1
2
2
2
2
JP4
JP2
+
+
+
1
2
3
4
2
1
1
1
1
2
JP25
100Ω
1
1
8
7
6
5
C53
33nF
1kΩ
R572
JP9
100Ω
2
2
1 R42 2
1
JP15
1 R41 2
1
2
+5V
AVDD
JP21
AD780N
U4
JP10
TP13
DGND
C26
10µF
SH1A
2
1
C30
1 10µF
2
2
1
SH1B
1
2
1
TP14
AGND
C25
100nF
C29
100nF
C27
100nF
1
JP51
C54
33nF
2
1
2
TP4
V2P
TP5
V2N
TP2
V1N
2
2
1
GND 7
7408
U3
VCC 14
JP13
2
2
1
2
1
AVDD
C33
0.1µF
C6
1
2
3
4
5
6
7
8
9
10
GND 7
7408
U2
VCC 14
U1
3
C34
2 0.1µF
1
1
20
19
18
17
16
15
14
13
12
11
0.1µF
1
C35
2
1
100Ω
R33 2
100Ω
R34 2
1
TP9
CF
TP8
VX
TP7
SAG
TP6
IRQ
TP12
CSB
TP11
SCLK
TP10
DOUT2
7408 2
U3
+ C5
10µF
ADE7763
TP3
DIN2
2 100nF
1
+5V
V1P
V1N
V2N
V2P
C51
33nF
C50
33nF
C32
0.1µF
JP20
TP1
V1P
1
R56 1.0kΩ/1%
1
2
1 R51 2
JP3
1kΩ
C21
33nF
1
2
1 R50 2
JP1
1kΩ
C11
33nF
1
C31
0.1µF
DVDD
R9 2
220pF
1
10kΩ
1 R7 2
10kΩ
1 R10 2
10kΩ
10kΩ
1 R40 2
1 R8 2
C16
2
10kΩ
10kΩ
1 R392
5
4
2
1
10
9
13
12
2
R4 2
GND
VO2
6
7408
U2
7408
U2
8
11
DVDD
7408
U2
2
U3
12
R6 2
JP6
JP19
1
JP12
820Ω
R24 2
3
1
820Ω
1 R212
3
1
820Ω
1 R18 2
3
1
820Ω
1 R19 2
3
1
JP5
4
2
4
2
4
2
4
2
100Ω
1
7408 13
U3
7408 10
9
U3
7408
R15 2
50Ω
R16 2
2
1
R17 2
1
LN21RPHL
2
820Ω
LED4
1
LN21RPHL
2
820Ω
LED3
1 R20 2
2
+5V
LN21RPHL
1
820Ω
LED2
1
1
+5V
LN21RPHL
820Ω
LED1
1
1
R112
R30 2
100Ω
1
100Ω
6
DIN
2 P1
4
3
2
1
4
3
2
1
5
6
7
8
3
2
6
GND
VO2
HCPL2232
U9
VO1
VCC
5
6
7
8
GND 5
VO2
HCPL2232
U7
7
VCC 8
VO1
+5V
0.1µF
1
C36
2
R1 2
820Ω
1
BNC1
EXT_CLK
RESETBIN
3 P1
1 R31 2
4
5
10kΩ
C15
3
R25
820Ω
1
820Ω
1 R36 2
1 R2 2
2 22pF
1
8
11
4
3
2
1
DVDD
7408
U2
HCPL2232
U5
VO1
VCC
XTAL
1
1
5
6
7
8
C14
22pF
1
2
1
+5V
GND
VO2
4
3
2
1
5
7
2
VPLUS
VMINUS
+C24
10µF
R3 2
R5
2
100Ω
1
100Ω
1
100Ω
1 R13 2
100Ω
1 R22 2
0.1µF
1 C23
HCPL2232
U8
VO1
VCC
U6 GND
HCPL2211
VO
VCC 8
VPLUS
VMINUS
1
1
1
R37 2
1
BNC2
DOUT
13 P1
CFOUT
15 P1
VXOUT
12 P1
SAGOUT
11 P1
IRQOUT
10 P1
24 P1
25 P1
22 P1
23 P1
20 P1
21 P1
18 P1
19 P1
CSBIN
4 P1
SCLKIN
5 P1
TBLK02
SK5
VMINUS
2
1
2
JP14
820Ω
R27 2
820Ω
R26 2
100Ω
EVAL-ADE7763EB
EVALUATION BOARD SCHEMATIC (REV. D AND REV. E)
EVAL-ADE7763EB
PCB LAYOUT—COMPONENT PLACEMENT (REV. D)
Figure 17. PCB Layout—Component Placement
Rev. 0 | Page 14 of 20
EVAL-ADE7763EB
PCB LAYOUT—COMPONENT SIDE (REV. D)
Figure 18. PCB Layout—Component Side
Rev. 0 | Page 15 of 20
EVAL-ADE7763EB
PCB LAYOUT—SOLDER SIDE (REV. D)
Figure 19. PCB Layout—Solder Side
Rev. 0 | Page 16 of 20
EVAL-ADE7763EB
PCB LAYOUT—COMPONENT PLACEMENT (REV. E)
Figure 20. PCB Layout—Component Placement
Rev. 0 | Page 17 of 20
EVAL-ADE7763EB
PCB LAYOUT—COMPONENT SIDE (REV. E)
Figure 21. PCB Layout—Component Side
Rev. 0 | Page 18 of 20
EVAL-ADE7763EB
PCB LAYOUT—SOLDER SIDE (REV. E)
Figure 22. PCB Layout—Solder Side
Rev. 0 | Page 19 of 20
EVAL-ADE7763EB
ORDERING GUIDE
Model
EVAL-ADE7763EB
Description
Evaluation Board
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04729–0–4/04(0)
Rev. 0 | Page 20 of 20