AN-1333
APPLICATION NOTE
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
Architecting a Direct, 3-Phase Energy Meter with Shunts
Using the ADE7932/ADE7933/ADE7978
by Petre Minciunescu and Dave Smith
INTRODUCTION
METER CASE
ARCHITECTING A DIRECT, 3-PHASE METER USING
THE ADE7932/ADE7933/ADE7978
1
2
3
4
5
6
7
8
9
10
11
12
PHASE A
PHASE A
PHASE B
PHASE B
PHASE C
PHASE C
NEUTRAL
NEUTRAL
Figure 1 shows how a direct, 3-phase energy meter using the
ADE7932/ADE7933/ADE7978 isolated metering chipset is
connected in a 3-phase, 4-wire system. Phase A connects to
Terminal 1 and Terminal 3 of the meter, Phase B connects to
Terminal 4 and Terminal 6 of the meter, Phase C connects to
Terminal 7 and Terminal 9 of the meter, and the neutral line
connects to Terminal 10 and Terminal 12 of the meter.
Figure 1. 3-Phase, 4-Wire, Direct Meter Connections
Rev. 0 | Page 1 of 13
12666-001
The ADE7932/ADE7933/ADE7978 isolated metering chipset
targets the polyphase energy metering applications using shunt
current sensors. This application note expands on the Applications
Information section of the ADE7932/ADE7933/ADE7978 data
sheet. It provides in-depth explanations of how to use the chipset
when developing a direct, 3-phase meter with shunts.
AN-1333
Application Note
Note that the typical voltage terminals, Terminal 2, Terminal 5,
and Terminal 8, of the meter are not used when the meter is
based on the chipset. The reference terminals of the shunts
(GND_A, GND_B, and GND_C) that are directly connected to
the phase lines become the reference points for the voltage
sensing resistor dividers.
Figure 2 presents how a meter that uses the chipset is architected.
Three shunts are connected to the meter terminals where the
3-phase, 4-wire connections are made. Every ADE7932/ADE7933
device manages one phase through some interface circuitry. The
reference terminal of the shunt becomes the ground of the isolated
side of the ADE7932/ADE7933. The GND_A reference terminal
is the ground of the Phase A ADE7932/ADE7933 isolated side,
the GND_B reference terminal is the ground of the Phase B
ADE7932/ADE7933 isolated side, and the GND_C reference
terminal is the ground of the Phase C ADE7932/ADE7933 isolated
side. The resistor dividers, R1_x and R2_x, where x = A, B, and C,
sense the voltage between the A, B, and C phase lines and the
neutral line. The current channel analog-to-digital converter
(ADC) of every ADE7932/ADE7933 measures the voltages
across the shunts, while the V1 voltage channel ADC measures
the voltages across the R1_x resistors.
The interface circuitry between the shunts, the voltage dividers, and
the ADE7932/ADE7933 devices is discussed in the Interfacing the
ADE7932/ADE7933 with the Shunt and the Resistor Divider
section.
The ADE7978 manages the ADE7932/ADE7933 through a bit
stream interface. The microcontroller (MCU) manages the
ADE7978 using either the serial port interface (SPI) or I2C
communication. If I2C communication is used, the MCU can
also use the high speed data capture (HSDC) port for meters
that must analyze the currents and voltages beyond what the
ADE7978 offers. The HSDC port is a master SPI port that the
ADE7978 uses to send out various instantaneous metering
quantities.
For the meter presented in Figure 2, the neutral line current is
not monitored. Figure 3 presents the architecture of a direct,
3-phase meter in which the neutral current is monitored. The
only difference is an additional ADE7932 (Phase N) that senses
only the neutral line current using a shunt. The voltage channel
of this chip is not used.
The neutral line determines the ground of the microcontroller
(GND_MCU) that manages the chipset, which is the same ground
of the ADE7978 and of the primary side of the ADE7932/ADE7933.
The MCU uses the SPI or the I2C interface to communicate
with the ADE7978, which also means that the power supply of
the meter must provide a supply voltage to the microcontroller
and to the chipset that has GND_MCU on the neutral line.
METER CASE
METER BOARD
METER CASE
MCU
METER BOARD
SPI OR I2C, HSDC
MCU
GND_MCU
ADE7978
PHASE A
ADE7932/
ADE7933
PHASE B
ADE7932/
ADE7933
PHASE C
ADE7932/
ADE7933
PHASE N
ADE7932
INTERFACE
CIRCUTRY
INTERFACE
CIRCUTRY
INTERFACE
CIRCUTRY
INTERFACE
CIRCUTRY
GND_MCU
ADE7978
BIT STREAM INTERFACE
PHASE A
ADE7932/
ADE7933
PHASE B
ADE7932/
ADE7933
PHASE C
ADE7932/
ADE7933
ISOLATION
BARRIER
GND_ A
SHUNT
SHUNT
SHUNT
R1_A R2_A
2
SHUNT
3
4
5
1
SHUNT
6
7
8
9
10
11
12
PHASE A
PHASE A
PHASE B
PHASE B
PHASE C
PHASE C
NEUTRAL
NEUTRAL
2
3
4
5
6
7
8
9
10
11
12
PHASE A
PHASE A
PHASE B
PHASE B
PHASE C
PHASE C
NEUTRAL
NEUTRAL
12666-003
SHUNT
1
SHUNT
GND_MCU
R1_C R2_C
R1_B R2_B
Figure 3. Shunt-Based, Direct, 3-Phase Meter Architecture with Monitored
Neutral Line
12666-002
GND_A
GND_N
R1_A R2_A
INTERFACE
CIRCUTRY
GND_C
GND_B
ISOLATION
BARRIER
R1_C R2_C
GND_C
R1_B R2_B
GND_B
INTERFACE
CIRCUTRY
GND_MCU
BIT STREAM INTERFACE
SPI OR I2C, HSDC
INTERFACE
CIRCUTRY
GND_MCU
Figure 2. Shunt-Based, Direct, 3-Phase Meter Architecture
Rev. 0 | Page 2 of 13
Application Note
AN-1333
The MCU, the ADE7978, and the primary side of the ADE7932/
ADE7933 have a GND_MCU isolated ground from the neutral
line. This architecture means the power supply of the meter must
provide a supply voltage to the MCU and to the chipset that is
isolated from the neutral line.
This full-scale voltage is sufficient to monitor 230 V, 3-phase
systems. The capacitor, C (33 nF), parallel to R2_x, creates the
antialiasing filter in the V1P pin path. Between the ground
point, AGND_ADC, derived from the ground terminal,
GND_x, of the shunt (see Figure 4), and the VM pin of the
ADE7932/ADE7933 (see Figure 5), there is an identical
antialiasing filter, R/C (1 kΩ/33 nF). Note that the antialiasing
filters in both current paths and voltage paths are the same, which
ensures that the delays introduced in the phase current and
voltage measurements are similar.
INTERFACING THE ADE7932/ADE7933 WITH THE
SHUNT AND THE RESISTOR DIVIDER
All of the ADE7932/ADE7933 devices that monitor the phase
lines have the same interface circuitry. The interface circuitry is
composed of two paths: one that interfaces the ADE7932/ADE7933
with the shunt (see Figure 4) and one that interfaces the ADE7932/
ADE7933 with the voltage divider (see Figure 5).
The E ferrite beads (150 Ω at 100 MHz) are placed in the shunt
and voltage divider connections to filter the high frequency
noise that may be induced into the wires during electrical fast
transient (EFT) tests.
A shunt senses the Phase A, Phase B, Phase C, or Phase N current
(see Figure 4). The antialiasing filter, R/C (1 kΩ/33 nF), between
the IP pin and the IM pin, and the shunt terminals have a corner at
4.8 kHz (1/(2 × π × 103 × 33 × 10−9)). The AGND_ADC ground
point where the filter capacitors are biased is connected to the
GND_A reference terminal, the GND_B reference terminal, the
GND_C reference terminal, or the GND_N reference terminal
of the shunts.
As the meter architectures considered in Figure 2 and Figure 3 do
not present any additional voltages to measure besides the phase to
neutral voltages, Figure 5 does not present the circuitry required to
interface the V2P pin of the ADE7933. However, if additional
voltages must be monitored, the V2P pin circuitry is identical to the
V1P pin circuitry. The V2P pin functionality is available only on
the ADE7933. The V2P pin functionality is not available on the
ADE7932.
The Phase A, Phase B, or Phase C to neutral voltages are sensed
by the voltage dividers, R1_x and R2_x, where x = A, B, or C (see
Figure 5). Resistor R1_x is composed of three 330 kΩ resistors and
R2_x is 1 kΩ. This resistor divider ensures a full-scale voltage
equal to the following:
3 × 330 kΩ + 1 kΩ
1 kΩ
= 350.37 V
PHASE A, PHASE B,
PHASE C, OR PHASE N
ADE7932/ADE7933
E
FROM ONE OF METER
TERMINAL 1,
TERMINAL 4,
TERMINAL 7,
OR TERMINAL 10
R
150Ω
IM
1kΩ
C
33nF
E
AGND_ADC
GND_A,
GND_B, 150Ω
GND_C,
OR GND_N
E
TO ONE OF METER
TERMINAL 3,
TERMINAL 6,
TERMINAL 9,
OR TERMINAL 12
C
33nF
R
150Ω
IP
12666-004
2
×
1kΩ
Figure 4. Interfacing the ADE7932/ADE7933 with a Shunt
E
R1_A, R1_B, OR R1_C
METER TERMINAL 10
150Ω
330kΩ 330kΩ 330kΩ
R2_A, R2_B, OR R2_C
1kΩ
PHASE A, PHASE B, OR PHASE C
ADE7932/ADE7933
V1P
C
33nF
AGND_ADC
AGND_ADC
R
1kΩ
VM
C
33nF
Figure 5. Interfacing the ADE7932/ADE7933 with a Voltage Divider
Rev. 0 | Page 3 of 13
12666-005
0. 5
AN-1333
Application Note
PROVIDING CLOCK SIGNAL TO ADE7978
See the ADE7932/ADE7933/ADE7978 data sheet for details on
providing a clock to the ADE7978.
COMMUNICATING WITH THE ADE7978
The ADE7978 has an SPI interface multiplexed with an I2C
interface. The ADE7932/ADE7933/ADE7978 data sheet provides
extensive details on the protocol used to read to and write from
the device registers.
In the following, a system perspective of the MCU managing
the ADE7978 in a 3-phase energy meter is proposed. Both I2C
and SPI communications are analyzed. I2C functions at the
maximum serial clock frequency of 400 kHz, while the SPI
functions at the maximum serial clock frequency of 2.5 MHz.
The ADE7978 has 90 configuration registers: 63 that are sent to
the ADE7978 in 32-bit format, 15 registers that are 16 bits wide,
and 12 registers that are 8 bits wide.
At maximum serial clock frequency, the time it takes to write all
90 configuration registers into the ADE7978 at power up or after a
reset is different for I2C and SPI usage.
If I2C is used, it is
63 × 36 + 15 × 18 + 12 × 9 + 90 × (1 + 9 + 18 + 1)
400 × 103
= 13.14 ms
If SPI is used, it is
63 × 32 + 15 × 16 + 12 × 8 + 90 × (8 + 16 )
2.5 × 106
= 1.8048 ms
The configuration registers must be read back to ensure that
they have been captured correctly by the ADE7978. At maximum
serial clock frequency, the time to read back all 90 registers is
different for I2C and SPI usage.
If I2C is used, it is
63 × 36 + 15 × 18 + 12 × 9 + 90 × (1 + 9 + 18 + 1 + 9 + 1)
400 × 103
= 15.39 ms
If SPI is used, it is
63 × 32 + 15 × 16 + 12 × 8 + 90 × (8 + 16 )
2.5 × 106
= 1.8048 ms
Note that these timings do not consider the inefficiencies of the
MCU in servicing the I2C and SPI ports without any delay.
These are the shortest timings users can achieve when writing
and reading all the configuration registers of the ADE7978.
The ADE7978 provides data out at a frequency of 8 kHz. Many
output registers, such as the energy registers (the AWATTHR register,
for example), do not need to be read so frequently.
If I2C is used, the HSDC port is available. Enable the HSDC
port to get the instantaneous values of various phase voltages,
currents, and powers if advanced metrology functionality, not
provided by the ADE7978, is required.
If SPI is used, the HSDC port is not available. Use the SPI burst
read functionality to access all the instantaneous phase voltages
and currents contained from Address 0xE50C to Address 0xE512.
The time to read them is
8 + 16 + 7 × 32
2.5 × 106
= 99.2 µs
This timing is the minimum access time possible because the
programming inefficiencies of the MCU raise it. Because these
registers are updated every 8 kHz, the margin to accommodate
them is
1
− 99.2 µs = 28.8 µs
8 kHz
LAYOUT GUIDELINES
Figure 6 presents the schematic of the metrology section of a
direct, 3-phase meter using four ADE7933 devices. It is the
schematic of the ADE7978 evaluation board. The second
voltage channel, V2P, is shown with a voltage divider to provide
the most comprehensive layout example possible.
A 4-layer printed circuit board (PCB) is required when using
the chipset. The devices pass Class B CISPR22/EN-55022
standard specification with a sufficient margin only with a
4-layer PCB (see the Radiated Emission Tests Results section for
details on these results). The top and bottom layers are identical
to a 2-layer PCB design, and the inner layers create a stitching
capacitor. The presence of the stitching capacitor is essential to
reducing the emissions generated by the ADE7932/ADE7933
dc-to-dc converters and meet the standard requirements.
Figure 7 presents the structure of the 4-layer PCB. The top layer
contains the components. Layer 2 creates one plate of the stitching
capacitor using the GNDISO isolated ground plane of the ADE7932/
ADE7933. Layer 3 creates the other plate of the stitching capacitor
using the GND_MCU primary ground plane of the ADE7932/
ADE7933 devices. Note that the PCB thickness between the
plates is 0.5 mm. The standard IEC 62052-31 requires a minimum
thickness of 0.4 mm when the lines to neutral voltages are below
300 V, but a 0.5 mm thickness allows any PCB production variation.
Do not invert Layer 2 with Layer 3 (that is, set the GND_MCU plane
on Layer 2 and the GNDISO plane on Layer 3) because the
GND_MCU plane creates a parasitic capacitance with the shunt
related PCB traces on the top layer. This parasitic capacitance creates
a voltage that adds to the voltage across the shunt and is proportional
and in phase with the voltage between the GNDISO plane and the
GND_MCU plane. The added voltage affects the accuracy of the
metrology measurements. By setting the GNDISO plane on Layer 2
and the GND_MCU plane on Layer 3, the GNDISO planes shield
the GND_MCU plane and remove the coupling to the PCB traces
of the IP pin and the IM pin of the shunt on the top layer .
Figure 8, Figure 9, Figure 10, and Figure 11 present the recommended 4-layer layout of the Figure 6 metrology section. It is the
layout implemented in the ADE7978 evaluation board.
Rev. 0 | Page 4 of 13
Application Note
AN-1333
TO ONE OF
METER TERMINAL 3,
TERMINAL 6,
TERMINAL 9,
OR TERMINAL 12
10µF
150Ω
FERRITE
150Ω
FERRITE
1kΩ
150Ω
FERRITE
4
1kΩ
IP
19
3.3V
20
100nF
10µF
GND_MCU
3.3V
33nF
1kΩ
10kΩ
EMI_CTRL
V1P
ADE7933A
5
AGND_ADC
3
DATA
VM
V2/TEMP
SYNC
V2P
RESET_EN
33nF
XTAL1
AGND_ADC
AGND_ADC
GND
33nF
AGND_ADC
330kΩ 330kΩ 330kΩ
VDD
GNDISO
6 IM
330kΩ 330kΩ
1kΩ
VDDISO
AGND_ADC
33nF
1kΩ
330kΩ
2
7
33nF
150Ω
FERRITE
FROM METER
TERMINAL 10 150Ω
FERRITE
AUXILIARY VOLTAGE
TERMINAL
100nF
8
4.7µF
100nF
10
4.7µF
100nF
9
1
2
3
4
5
SAME AS IN
ADE7933A
6
7
8
9
10
1
2
3
4
5
SAME AS IN
ADE7933A
6
7
8
9
10
1
2
3
4
5
SAME AS IN
ADE7933A
6
7
8
9
10
XTAL2
LDO
GNDISO
GND
18
ADE7978
15
28
17
27
12
5
16
3
13
4
14
11
GNDISO
SYNC
V2P
XTAL2
V1P
RESET_EN
V2/TEMP
VM
ADE7933B VDD
IM
IP
XTAL1
DATA
LDO
REF
GND
GNDISO
GND
VDDISO
EMI_CTRL
GNDISO
SYNC
V2P
DATA
V1P
RESET_EN
VM
V2/TEMP
IM
ADE7933C VDD
IP
XTAL1
LDO
XTAL2
REF
GND
GNDISO
GND
IRQ1
EMI_CTRL
RESET_EN
3.3V
1µF
RESET
20pF
12
10kΩ
18
12
14
10kΩ
3.3V
GND_MCU
GND_MCU
80.6Ω
16
17
1
19
VT_B
13
SAME AS IN
ADE7933 A
13
15
CF1
2
10kΩ
DATA_B
GND_MCU
11
20
CF2
3.3V
18
10kΩ
10µF
3.3V
100nF
12
GND_MCU
15
21
20
7
14
SAME AS CF1
VDD
GND
DATA_C
16
17
6
19
VT_C
SAME AS IN
ADE7933A
13
14
3.3V
11
4.7µF
20
100nF
22
23
LDO
DGND
GND_MCU
CF3/HSCLK
18
SCLK/SCL
10kΩ
12
SYNC
14
XTAL2
V2P
16
RESET_EN
V1P
17
VM
V2/TEMP
19
IM
ADE7933N VDD
13
XTAL1
IP
15
DATA
LDO
11
GND
REF
20
GND
GNDISO
GNDISO
MISO/HSD
GND_MCU
MOSI/SDA
8
ZX/DREADY
15
16
17
18
19
26
TO MCU
TO MCU
TO MCU
TO MCU
TO MCU
TO MCU
VT_N
SAME AS IN
ADE7933A
9
GND_MCU
Figure 6. Direct, 3-Phase Meter Schematic of Metrology Section
Rev. 0 | Page 5 of 13
TO MCU
CLKOUT
SS/HSA
VDDISO
TO MCU
11
SYNC
16.384MHz
20pF
EMI_CTRL
VT_A
25
XTALIN
24
XTALOUT
REF
VDDISO
IRQ0 10
DATA_A
DATA_N
12666-007
1
FROM ONE OF
METER TERMINAL 1,
TERMINAL 4,
TERMINAL 7,
OR TERMINAL 10
AN-1333
Application Note
PRIMARY SIDE GROUND
PLANE ON TOP LAYER
ADE7933
62mils ±10%=
1.574mm NOMINAL
20mils = 0.508mm MIN
C23
50mils = 1.27mm
8mm
ISOLATED SIDE GROUND
PLANE ON LAYER TWO
PRIMARY SIDE GROUND
PLANE ON LAYER THREE
PRIMARY SIDE GROUND
PLANE ON BOTTOM LAYER
12666-006
ISOLATED SIDE GROUND
PLANE ON TOP LAYER
12666-008
Figure 7. 4-Layer Structure with Stitching Capacitor
Figure 8. Top Layer Layout of the Direct, 3-Phase Meter Metrology Section
Rev. 0 | Page 6 of 13
AN-1333
12666-009
Application Note
12666-010
Figure 9. Layer 2 Layout of the Direct, 3-Phase Meter Metrology Section
Figure 10. Layer 3 Layout of the Direct, 3-Phase Meter Metrology Section
Rev. 0 | Page 7 of 13
Application Note
12666-011
AN-1333
Figure 11. Bottom Layer Layout of the Direct, 3-Phase Meter Metrology Section
Rev. 0 | Page 8 of 13
Application Note
AN-1333
ADE7932/ADE7933 Decoupling Capacitors Layout
Guidelines
•
•
•
Place the 100 nF capacitors closest to the chip.
Make the connections between the capacitors and the
VDD pin, the VDDISO pin, the LDO pin, and the REF pin as
short as possible.
Make the connections between the capacitors and the
GND pin, the GNDISO pin, the LDO pin, and the REF pin as
short as possible.
12666-014
Follow these recommendations for the decoupling capacitors
between the VDD pin and the GND pin (10 µF and 100 nF), the
VDDISO pin and the GNDISO pin (10 µF and 100 nF), the LDO pin
and the GNDISO pin (4.7 µF and 100 nF), and between the REF pin
and the GNDISO pin (4.7 µF and 100 nF) of the ADE7932/
ADE7933:
Figure 14. Layout of Capacitors Between the LDO Pin and the GNDISO Pin
12666-015
This setup improves the electromagnetic compatibility (EMC)
immunity of the chips and lowers the emissions generated by the
ADE7932/ADE7933 dc-to-dc converters.
Figure 12, Figure 13, Figure 14, and Figure 15 present the various
layouts of these capacitors.
Figure 15. Layout of Capacitors Between the REF Pin and the GNDISO Pin
12666-012
ADE7932/ADE7933 Isolated Ground Layout Guidelines
12666-013
Figure 12. Layout of Capacitors Between the VDD Pin and the GND Pin
The ADE7932/ADE7933 have two GNDISO isolated ground pins.
The GNDISO pins are connected through ferrites to the reference
terminal of the shunt and determine the isolated ground plane on
the top layer of the PCB. The connections between the GNDISO pins
and the isolated ground plane must be very short. To have the
lowest inductance possible, the vias that connect the isolated
ground plane from the top layer to the stitching capacitor plate on
Layer 2 must be close to the GNDISO pins (see Figure 16). Limit
the number of vias to the minimum because they take area from
the stitching capacitor plates and therefore reduce its capacitance.
12666-016
Figure 13. Layout of Capacitors Between the VDDISO Pin and the GNDISO Pin
Figure 16. Layout of GNDISO Connections to Isolated Ground Plane and
Related Vias
Rev. 0 | Page 9 of 13
AN-1333
Application Note
The minimum stitching capacitor area that is recommended to
pass Class B CISPR22/EN-55022 standard specification is
825 mm2, giving a capacitor value of 63 pF (see the Radiated
Emission Tests Results section for more details).
C = ε0 × εr ×
A
d
where:
ε0 is the vacuum permittivity and equals 8.854 × 10−12 F/m.
εr is the relative permittivity of the PCB FR4 material and equals 4.3.
A is the area of the capacitor plates and equals 825 mm2.
d is the distance between the plates and equals 0.5 mm.
12666-017
Plates on Layer 2 and Layer 3 create the stitching capacitor.
Figure 17 shows the layout of one plate created underneath Phase A
of the ADE7932/ADE7933. The vias that are circled in red connect
the Layer 2 plate to the GNDISO plane from the top layer. Figure 18
shows the layout of the GND_MCU plane in Layer 3. This plane
creates the plate of four stitching capacitors, one for each ADE7932/
ADE7933. The vias circled in red are the GNDISO vias. More than
1 mm of space is between these vias and the GND_MCU plate,
which complies with the IEC 62052-31 standard that requires
0.4 mm minimum distance between adjacent conductors when the
line to neutral voltages are below 300 V.
Figure 17. Section of Layer 2, Creating Stitching Capacitor GNDISO Plate
1.27mm
1.27mm
12666-018
1.59mm
Figure 18. Section of Layer 3, Creating Stitching Capacitor GNDMCU Plate
Rev. 0 | Page 10 of 13
Application Note
AN-1333
7.62mm
7.62mm
12666-019
7.62mm
12666-020
Figure 19. Section of Layer 2 Showing All Four Stitching Capacitors
Figure 20. ADE7978 Placed Symmetrically to Phase A and Phase C of the ADE7933 and Close to Phase B of the ADE7933
Increasing the area of the plates leads to a larger capacitor value,
which yields a bigger margin in passing the Class B CISPR22/
EN-55022 standard. In the ADE7978 evaluation board, there is
7.62 mm of space between the GNDISO plates of various ADE7933
devices on Layer 2, even though the IEC 62052-31 standard
requires 0.4 mm minimum distance between adjacent conductors
when the line to neutral voltages are below 300 V (see Figure 19).
The capacitor value is 84 pF for an area of the plates equal to
1100 mm2.
ADE7978 Crystal and Load Capacitors Layout Guidelines
Place the load capacitors of the crystal closest to the ADE7978 to
improve the EMC immunity of the chip, whereas the crystal can be
placed in close proximity (see Figure 21). The distance between the
crystal and the load capacitors is not as critical as the distance
between the capacitors and the XTALIN pin and the
XTALOUT pin.
Place the ADE7978 symmetrically relative to Phase A and Phase C
of the ADE7932/ADE7933 devices and close to Phase B of the
ADE7932/ADE7933 (see Figure 20). Phase N of the ADE7933
can be placed somewhat farther from the ADE7978 because
Phase A, Phase B, and Phase C of the ADE7932/ADE7933 devices
provide data upon which the meter executes the billing, and the
integrity of these signals must be as high as possible. Shield the
traces of the connections between the ADE7978 and the ADE7932/
ADE7933 devices. Ensure that the GND_MCU ground plane
around ADE7978 is solid to avoid corruption of the bit stream
communication during EMC tests.
Rev. 0 | Page 11 of 13
12666-021
ADE7978 Placement on Board Guidelines
Figure 21. Layout of the ADE7978 Crystal
AN-1333
Application Note
•
•
•
•
Place the 100 nF capacitors closest to the chip.
Connect the capacitors to the VDD pin and the LDO pin
with traces as short as possible.
Connect the capacitors to the GND pin and the DGND pin
with traces as short as possible.
Make a solid ground plane (GND_MCU of the meter)
around the ADE7978.
This setup improves the EMC immunity of the ADE7978 (see
Figure 22).
ADE7978 Exposed Pad Guidelines
The ADE7978 package has a 3.3 mm × 3.3 mm exposed pad
underneath the package. Create a similar pad on the PCB under
the exposed pad and solder the exposed pad to it to confer
mechanical strength to the package. Then, connect the pads to
the GND pin and the DGND pin, as shown in Figure 22.
With a stitching capacitor of 84 pF (1,100 mm2 plates), a minimum
11 dBµV/m quasi peak margin to Class B CISPR22/EN-55022
limits was obtained for frequencies between 30 MHz and 1 GHz
(see Figure 23). For frequencies between 1 GHz and 2 GHz, a
minimum 10 dBµV/m average results margin to Class B CISPR22/
EN-55022 limits was obtained (see Figure 24).
100
90
TRACE3: MEASURED AVERAGE
TRACE2: MEASURED QUASI PEAK
TRACE1: MEASURED PEAK
80
70
60
50
40
CISPR22 CLASS B AT 10m QP
30
20
10
0
30M
100M
1G
FREQUENCY (Hz)
12666-023
Follow these recommendations for the decoupling capacitors
between the VDD pin and the GND pin of the ADE7978 (10 µF
and 100 nF), and between the LDO pin and the DGND pin (4.7 µF
and 100 nF):
Measurements of the radiated emissions were executed for
frequencies between 30 MHz and 1 GHz and between 1 GHz
and 2 GHz.
LEVEL (dBµV/m)
ADE7978 Decoupling Capacitors Layout Guidelines
Figure 23. Anechoic Chamber Emissions from ADE7978 Evaluation Board,
84 pF Stitching Capacitor (Quasi Peak Points in Blue, 30 MHz to 1 GHz)
100
90
80
LEVEL (dBm/µV)
70
CISPR 22 CLASS B AT 3M PEAK
60
50
CISPR 22 CLASS B AT 3M AVERAGE
40
30
20
12666-022
TRACE3: MEASURED AVERAGE
TRACE1: MEASURED PEAK
0
1G
Figure 22. Layout of the ADE7978 Decoupling Capacitors and Exposed Pad
RADIATED EMISSION TESTS RESULTS
FREQUENCY (Hz)
2G
12666-024
10
Figure 24. Anechoic Chamber Emissions from ADE7978 Evaluation Board,
84 pF Stitching Capacitor (Average Points in Green, 1 GHz to 2 GHz)
The ADE7978 evaluation board was tested for compliance with
the Class B CISPR22/EN-55022 standard. The board was placed
in a 3-phase meter case and was powered from a battery. A 5 m,
3-phase cable, without termination, was mounted on the meter
and then placed under the floor in the anechoic chamber. Note
that the ADE7978 evaluation board contains four ADE7933
isolated ADCs.
Rev. 0 | Page 12 of 13
Application Note
AN-1333
90
80
70
CISPR 22 CLASS B AT 3M PEAK
60
50
CISPR 22 CLASS B AT 3M AVERAGE
40
30
20
10
TRACE3: MEASURED AVERAGE
TRACE1: MEASURED PEAK
0
1G
100
TRACE3: MEASURED AVERAGE
90 TRACE2: MEASURED QUASI PEAK
TRACE1: MEASURED PEAK
Figure 26. Anechoic Chamber Emissions from ADE7978 Evaluation Board,
63 pF Stitching Capacitor (Average Points in Green, 1 GHz to 2 GHz)
80
CONCLUSIONS
LEVEL (dBµV/m)
70
This application note has shown how to develop a direct, 3-phase
meter with shunts using the ADE7932/ADE7933/ADE7978
isolated metering chipset. It provided recommendations on the
schematic and layout to pass the Class B CISPR22/EN-55022
radiated emissions specification by a margin of at least 10 dBμV/m.
It showed how much bandwidth an MCU has to reserve for
managing the I2C, SPI, or HSDC communications with the
ADE7978.
60
50
40
30
2G
FREQUENCY (Hz)
12666-026
PCB designs that have stitching capacitors smaller than 63 pF
(that is, with the area of the plates smaller than 825 mm2) are
not recommended. For example, with a stitching capacitor of
42 pF (an area of the plates of 550 mm2), an ADE7978 evaluation
board was over the Class B CISPR22/EN-55022 limit by
4 dBμV/m at 380 MHz.
100
LEVEL (dBm/µV)
An ADE7978 evaluation board with a stitching capacitor of 63 pF
(825 mm2) was used to test the radiated emissions when the
stitching capacitor is smaller than 84 pF. The ADE7978 evaluation
board passed Class B CISPR22/EN-55022 specification by a
9 dBμV/m quasi peak margin for frequencies between 30 MHz
and 1 GHz (see Figure 25) and a 7 dBμV/m average results margin
for frequencies between 1 GHz and 2 GHz (see Figure 26).
CISPR22 CLASS B AT 10m QP
20
0
30M
100M
FREQUENCY (Hz)
1G
12666-025
10
Figure 25. Anechoic Chamber Emissions from ADE7978 Evaluation Board,
63 pF Stitching Capacitor (Quasi Peak Points in Blue, 30 MHz to 1 GHz)
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
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registered trademarks are the property of their respective owners.
AN12666-0-11/14(0)
Rev. 0 | Page 13 of 13