AN-636
APPLICATION NOTE
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
ADN2819 Evaluation Board
by Kevin Buckley
INTRODUCTION
This application note describes the use of the ADN2819
evaluation board. The ADN2819 is a multirate clock recovery,
data-retiming device based on a multiloop PLL architecture.
The ADN2819 can recover clock and data at SONET OC-3,
OC-12, OC-48, and Gigabit Ethernet data rates as well as 15/14
Forward Error Correction (FEC) for these rates by using a
single reference clock or external crystal oscillator.
The ADN2819 evaluation board is fabricated using standard
FR-4 materials. All high speed signal traces are matched to
within 1 mil length and maintain a 50 Ω characteristic
impedance to preserve signal integrity. The ADN2819
evaluation board is also used for the ADN2811.
03563-001
QUICK START GUIDE FOR OC-48, NORMAL
OPERATING MODE
1. Apply a 3.3 V supply to the AVCC and GND vector pins.
2. Connect PIN/NIN to a pattern generator that can supply a
differential input of greater than 10 mV to the ADN2819.
Use cables of matching length.
3. Connect CLKOUTP/CLKOUTN, DATAOUTP/
DATAOUTN to measurement equipment using cables of
matching length.
4. All switches, S1 through S9, should be in the 0 position. 1
This sets the part up in OC-48, normal operating mode,
using the on-board 19.44 MHz crystal as the reference
clock.
5. Apply a single-ended or differential 2.488 Gbps NRZ data
stream to the ADN2819 inputs. The recovered 2.488 GHz
clock and retimed data is present at the CLKOUTP/
CLKOUTN and DATAOUTP/DATAOUTN outputs,
respectively.
1
For a 0, the red switch should be in the right-most position, as shown in
Figure 1. For the ADN2819 evaluation boards that are populated with 3-pin
jumpers instead of the slide switches, the jumper should be placed on the
left-most two pins for a 0.
Figure 1. ADN2819 Evaluation Board (Actual Size)
POWER SUPPLY
The ADN2819 evaluation board requires a single 3.3 V nominal
supply for basic operation. This supply is brought on-board
through vector pins AVCC and GND at the top center of the
board. The evaluation board is shipped configured for a single
supply through Jumpers JP1 through JP4, which are populated
with ferrite beads. If these ferrite beads are removed, separate
3.3 V supplies must be applied to vector pins DVCC and
DRVCC. This allows the user to keep the analog supply, digital
supply, and output driver supply separate, although it is not
required.
DATA RATE SELECTION
The input data rate of the ADN2819 is selected by SEL0, SEL1,
SEL2, Switches S2 through S4 (see Table 1). The ADN2819 can
be programmed to acquire OC-3 (155.52 Mbps), OC-3 FEC
(166.6 Mbps), OC-12 (622.08 Mbps), OC-12 FEC (666.5 Mbps),
OC-48 (2.488 Gbps), OC-48 FEC (2.665 Gbps), Gigabit
Ethernet (1.25 Gbps), and Gigabit Ethernet FEC (1.339 Gbps).
Rev. A | Page 1 of 8
AN-636
LOOP FILTER CAPACITOR
Table 1. Data Rate Selection
SEL2
0
0
0
0
1
1
1
1
SEL1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
Rate
OC-48
GbE
OC-12
OC-3
OC-48 × 15/14
GbE × 15/14
OC-12 × 15/14
OC-3 × 15/14
Frequency
2.48832 GHz
1.25 GHz
622 MHz
155.5 MHz
2.666 GHz
1.339 GHz
666.5 MHz
166.6 MHz
REFERENCE CLOCK
The ADN2819 has an on-chip crystal oscillator that is used with
a 19.44 MHz external crystal resonator in series resonant mode.
When the REFSEL pin is set to 0, the crystal oscillator is used to
supply the reference frequency. If an external clock oscillator or
other external reference clock is used, the REFSEL pin is set to 1
and an external reference clock is brought in either differentially
or single ended on the REFCLKP/REFCLKN pins. When
configured to use an external reference clock, the ADN2819
XTAL oscillator is disabled by populating R1 and R2 with 1 kΩ
pull-up resistors.
The ADN2819 can accept any of the following reference clock
frequencies: 19.44 MHz, 38.88 MHz, or 77.76 MHz at
LVTTL/LVCMOS/LVPECL/LVDS levels or 155.52 MHz at
LVPECL/LVDS levels via the REFCLKN/REFCLKP inputs. The
reference clock frequency is selected independent of data rate.
Only a single reference clock rate needs to be selected for the
ADN2819 to operate over all data rates. Setting REFSEL Switch
S1 to 1 disconnects the on-board 19.44 MHz crystal oscillator
and selects the external reference clock inputs, REFCLKN/
REFCLKP on SMA Connectors J5 and J6. REFCLKN/
REFCLKP accept any differential signal with a peak-to-peak
differential voltage level of greater than 100 mV (for example,
LVPECL or LVDS) or a single-ended LVTTL or LVCMOS input.
The REFCLK inputs are high impedance. However, on the
evaluation board, there is a 100 Ω resistor, R3, placed across
REFCLKP and REFCLKN to provide a differential 100 Ω
termination in case the REFCLK inputs are being driven by a
100 Ω differential source impedance. If this 100 Ω termination
is not required, (for example, the reference clock is being driven
single ended by a clock oscillator), R3 should be removed. The
external reference clock frequency is selected by REFSEL0,
REFSEL1 Switches S5 through S6 (see Table 2).
The loop filter capacitor, CF, is connected between CF1 (Pin 21)
and CF2 (Pin 25). The recommended capacitor parameters are
shown in Table 3. The ADN2819 evaluation board uses a low
leakage 4.7 μF X7R capacitor.
Table 3. Recommended Capacitor Specifications
Parameter
Capacitance (−40°C to +85°C)
Leakage (−40°C to +85°C)
Rating
PIN/NIN INPUTS
The PIN/NIN inputs are brought onto the ADN2819 evaluation
board through SMA Connectors J1 and J2. Capacitors C3, C4
provide ac coupling to the on-chip 50 Ω termination resistors.
When ac coupling the inputs and outputs of the ADN2819, care
must be taken when choosing the ac coupling capacitor values.
The time constant formed with the 50 Ω resistors in the signal
path must be considered. In addition, when a large number of
consecutive identical digits (CIDs) are applied, the capacitor
voltage can droop, causing pattern dependent jitter. The
designers of the ADN2819 have done a thorough investigation
at the OC-3 and OC-48 data rates. Assuming that 1000 CIDs
must be tolerated, a minimum capacitor of 1.6 μF to PIN/NIN
and 0.1 μF on DATAOUTP/DATAOUTN should be used. The
ADN2819 evaluation board is shipped with 1.8 μF X7R
capacitors in the C1, C2 positions to optimize performance at
the OC-3 data rate.
CLOCK/DATA OUTPUTS
CLKOUTP and CLKOUTN are brought out through 0.1 μF ac
coupling capacitors to SMA Connectors J7 and J8, respectively.
DATAOUTP and DATAOUTN are brought out through 0.1 μF
ac coupling capacitors to SMA Connectors J9 and J10, respectively.
SLICEP/SLICEN
SLICE allows the ADN2819’s input quantizer decision level to
be adjusted to accommodate amplified spontaneous emission
(ASE) in fiber amplifier applications. The slicing level can be
adjusted by up to ±100 mV by applying a differential input
voltage of up to ±800 mV to SLICEP/SLICEN. The SLICEP and
SLICEN inputs are brought onto the ADN2819 evaluation
board through SMA Connectors J11 and J12, respectively.
When not being used, the SLICEN/SLICEP inputs should be
tied to VCC using the jumpers.
Table 2. Reference Frequency Selection
REFSEL1
0
0
1
1
REFSEL0
0
1
0
1
Value
4.7 μF
<80 nA
6.3 V
Applied Reference Frequency (MHz)
19.44
38.88
77.76
155.52
Rev. A | Page 2 of 8
AN-636
LOSS OF LOCK (LOL)
BYPASS MODE
The ADN2819 lock detector monitors the frequency difference
between the VCO and the reference clock. The LOL signal is
deasserted when the VCO is within 500 ppm of the center
frequency. If the frequency error between the input data rate
and the selected data rate drifts by more than 0.1% (1000 ppm),
the LOL output is asserted. LED CR2 provides a visual indication
of LOL status; it turns on when the part has lost lock.
Asserting the BYPASS input through the BYPASS Switch S8
connects the output of the quantizer directly to the data output
buffers, bypassing the clock recovery circuit. This only affects
the data output circuitry. The clock output remains connected
to the clock recovery circuit and continues to output a valid
clock if the input data rate is valid.
The LOL output is LVTTL compatible and shows the lock status
of the frequency detector loop. Loss-of-lock output is brought
out to a test point labeled LOL.
SIGNAL DETECT OUTPUT (SDOUT)
SDOUT/LOS uses peak detection circuitry to determine if the
input data to the quantizer is above the threshold set by
THRADJ Resistor R30. The SDOUT output is LVTTL
compatible. LED CR1 provides a visual indication of SDOUT
status; it turns on when a loss-of-signal condition is detected.
SDOUT is also brought out to a test point labeled SDOUT.
SQUELCH
LOOPEN MODE
Asserting the loop enable input through the LOOPEN
Switch S9 connects the test data inputs TDINN and TDINP
through the input multiplexer to the clock recovery circuit. This
function can be used for testing the clock recovery functionality
as well as configuring the ADN2819 for use with an external
limiting amplifier/quantizer.
Table 4. ADN2819 Test Modes
LOOPEN
0
0
1
PYPASS
0
1
0
Function
Normal operation
BYPASS mode
LOOPEN mode
When the SQUELCH input, Pin 39, is driven to a TTL high,
both the clock and data outputs are set to a zero state. Switch S7
is provided to drive the SQUELCH pin high or low. If the
SQUELCH function is not required, the SQUELCH pin should
be driven low.
TEST MODES
Test Data Inputs, TDINN/TDINP
The test data inputs, TDINN and TDINP, facilitate the use of an
external quantizer/limiting amplifier bypassing the ADN2819’s
input quantizer to provide direct input to the clock recovery
circuit. Test data inputs TDINN and TDINP are brought onto
the ADN2819 evaluation board through SMA Connectors J3
and J4, respectively.
03563-002
Test modes are enabled using LOOPEN (Pin 48) and BYPASS
(Pin 44). These are LVTTL-/CMOS-compatible logic inputs.
Switches S8 and S9 are used to set BYPASS and LOOPEN,
respectively.
Figure 2. Silkscreen Layer
Table 4 shows how to set the test modes.
Rev. A | Page 3 of 8
Figure 3. Top Layer
03563-005
03563-003
AN-636
03563-004
03563-006
Figure 5. Ground Plane
Figure 4. Bottom Layer
Figure 6. Power Plane
Rev. A | Page 4 of 8
Figure 7. Evaluation Board
Rev. A | Page 5 of 8
C16
0.1µF
03563-007
NIN
PIN
TDINN
TDINP
J12
J11
J2
J1
J4
J3
TP6
TP5
C17
1nF
C19
1nF
C21
1nF
DUT DECOUPLNG
C14
0.1µF
DRVCC
DVCC
C29
0.1µF
C5
1µF
C24
10µF
C23
10µF
DVCC
TP9
C11
0.1µF
TP10
C13
1.8µF
C12
1.8µF
C3
0.1µF
C4
0.1µF
C20
1nF
C28
1nF
C6
0.1µF
R30
20kΩ
C22
0.1µF
C26
0.1µF
C25
0.1µF
JP2
1
REFCLK_P
REFCLK_N
J6
J5
C7
0.1µF
C8
0.1µF
DVCC
R1
1kΩ
R2
1kΩ
C18
0.1µF
2
JP3 JP4
0
0
1
1
2
TP3
TP4
40
C9
0Ω
4.7µF
C27
R16
R17
82.5Ω 82.5Ω
R18
R19
82.5Ω 82.5Ω
0.1µF
C2
0Ω
R11
0.1µF
C1
R10
0Ω
0.1µF
R13
100Ω
R9
R14
100Ω
2
3
3
2
3
2
3
2
3
2
2
3
3
2
3
2
DVCC
C10
R12
100Ω
S6
S5
DAVCC
1
1
S4
S3
S2
S1
S7
S8
2
3
0.1µF
R15
100Ω
R29
1.05kΩ
R28
1.05kΩ
1
1
R27
1.05kΩ
1
R26
1.05kΩ
1
R25
1.05kΩ
R24
1.05kΩ
1
1
1
S9
0Ω
DATAOUTP 38
DATAOUTN 37
R23
1.05kΩ
R22
1.05kΩ
R21
1.05kΩ
R20
1.05kΩ
R8
13 REFCLKN
14 REFCLKP
48
44
39
42
15
32
31
30
24
23
41
AVCC
DRVCC
LOOPEN
BYPASS
SQUELCH
VEE
4 VREF
REFSEL
5 PIN
ADN2819 SEL0
6 NIN
SEL1
SEL2
7 SLICEP
A1
REFSEL0
8 SLICEN
REFSEL1
12 X02
CLKOUTP
11 X01
CLKOUTN
21 CF1
45
10
1
17
18
AVCC
VCCPD
SDOUT
LOL
THRADJ
TDINP
TDINN
CR2
RED
R3
100Ω
R6
R7
1kΩ 1kΩ
TP12 TP11
TP7 TP8
LOL SDOUT CR2
RED
1
2
Y1
19.44M
JP1
2
DVCC
TP1 TP13 C15
10µF
VCC1
VCC2
VCC3
VEE1
VEE2
VEE3
VEE4
VEE5
VEE6
VEE7
+
VEE1
VEE2
CF2
VEE4
VEE5
TP2
PAD
DVCC
DVRCC
DVRCC
DVCC
AVCC
AVCC
AVCC
20
35
36
47
2
26
28
VCC4
VCC1
VCC2
VCC3
+
16
19
22
33
34
43
46
3
9
25
27
29
AVCC
J10
J9
J8
J7
DATAOUTN
DATAOUTP
CLKOUTN
CLKOUTP
AN-636
AN-636
NOTES
Rev. A | Page 6 of 8
AN-636
NOTES
Rev. A | Page 7 of 8
AN-636
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
AN03563-0-2/06(A)
Rev. A | Page 8 of 8