Quad-Channel, 12-Bit, Serial Input, 4 mA to 20 mA
and Voltage Output DAC with Dynamic Power Control
AD5735
Data Sheet
On-chip dynamic power control minimizes package power
dissipation in current mode. This reduced power dissipation
is achieved by regulating the voltage on the output driver from
7.4 V to 29.5 V using a dc-to-dc boost converter optimized for
minimum on-chip power dissipation.
FEATURES
12-bit resolution and monotonicity
Dynamic power control for thermal management
Current and voltage output pins connectable to a single
terminal
Current output ranges: 0 mA to 20 mA, 4 mA to 20 mA,
and 0 mA to 24 mA
±0.1% total unadjusted error (TUE) maximum
Voltage output ranges (with 20% overrange): 0 V to 5 V,
0 V to 10 V, ±5 V, and ±10 V
±0.09% total unadjusted error (TUE) maximum
User-programmable offset and gain
On-chip diagnostics
On-chip reference: ±10 ppm/°C maximum
−40°C to +105°C temperature range
The AD5735 uses a versatile 3-wire serial interface that operates
at clock rates of up to 30 MHz and is compatible with standard
SPI, QSPI™, MICROWIRE®, DSP, and microcontroller interface
standards. The serial interface also features optional CRC-8 packet
error checking, as well as a watchdog timer that monitors activity
on the interface.
PRODUCT HIGHLIGHTS
1.
2.
3.
APPLICATIONS
Dynamic power control for thermal management.
12-bit performance.
Quad channel.
COMPANION PRODUCTS
Process control
Actuator control
PLCs
Product Family: AD5755, AD5755-1, AD5757, AD5737
External References: ADR445, ADR02
Digital Isolators: ADuM1410, ADuM1411
Power: ADP2302, ADP2303
Additional companion products on the AD5735 product page
GENERAL DESCRIPTION
The AD5735 is a quad-channel voltage and current output DAC
that operates with a power supply range from −26.4 V to +33 V.
FUNCTIONAL BLOCK DIAGRAM
AVCC
5.0V
AVSS
–15V
AGND
AVDD
+15V
SWx
DVDD
VBOOST_x
7.4V TO 29.5V
DGND
LDAC
DC-TO-DC
CONVERTER
SCLK
SDIN
SYNC
SDO
CLEAR
DIGITAL
INTERFACE
IOUT_x
+
FAULT
ALERT
GAIN REG A
OFFSET REG A
AD1
AD0
DAC A
CURRENT AND
VOLTAGE
OUTPUT RANGE
SCALING
RSET_x
+VSENSE_x
VOUT_x
–VSENSE_x
DAC CHANNEL A
REFOUT
REFERENCE
REFIN
DAC CHANNEL B
DAC CHANNEL C
DAC CHANNEL D
09961-100
AD5735
NOTES
1. x = A, B, C, OR D.
Figure 1.
Rev. D
Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2011–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD5735
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1 Control Registers ........................................................................ 35 Applications ....................................................................................... 1 Readback Operation .................................................................. 38 General Description ......................................................................... 1 Device Features ............................................................................... 41 Product Highlights ........................................................................... 1 Fault Output ................................................................................ 41 Companion Products ....................................................................... 1 Voltage Output Short-Circuit Protection ................................ 41 Functional Block Diagram .............................................................. 1 Digital Offset and Gain Control ............................................... 41 Revision History ............................................................................... 3 Status Readback During a Write .............................................. 41 Detailed Functional Block Diagram .............................................. 4 Asynchronous Clear................................................................... 42 Specifications..................................................................................... 5 Packet Error Checking ............................................................... 42 AC Performance Characteristics ................................................ 8 Watchdog Timer ......................................................................... 42 Timing Characteristics ................................................................ 9 Alert Output ................................................................................ 42 Absolute Maximum Ratings.......................................................... 12 Internal Reference ...................................................................... 42 Thermal Resistance .................................................................... 12 External Current Setting Resistor ............................................ 42 ESD Caution ................................................................................ 12 Digital Slew Rate Control .......................................................... 43 Pin Configuration and Function Descriptions ........................... 13 Dynamic Power Control............................................................ 43 Typical Performance Characteristics ........................................... 16 DC-to-DC Converters ............................................................... 44 Voltage Outputs .......................................................................... 16 AICC Supply Requirements—Static .......................................... 45 Current Outputs ......................................................................... 20 AICC Supply Requirements—Slewing ...................................... 45 DC-to-DC Converter ................................................................. 24 Applications Information .............................................................. 47 Reference ..................................................................................... 25 Voltage and Current Output Pins on the Same Terminal ..... 47 General ......................................................................................... 26 Current Output Mode with Internal RSET ................................ 47 Terminology .................................................................................... 27 Precision Voltage Reference Selection ..................................... 47 Theory of Operation ...................................................................... 29 Driving Inductive Loads ............................................................ 48 DAC Architecture ....................................................................... 29 Transient Voltage Protection .................................................... 48 Power-On State of the AD5735 ................................................ 30 Microprocessor Interfacing ....................................................... 48 Serial Interface ............................................................................ 30 Layout Guidelines....................................................................... 48 Transfer Function ....................................................................... 30 Galvanically Isolated Interface ................................................. 49 Registers ........................................................................................... 31 Outline Dimensions ....................................................................... 50 Enabling the Output................................................................... 32 Ordering Guide .......................................................................... 50 Reprogramming the Output Range ......................................... 32 Data Registers ............................................................................. 33 Rev. D | Page 2 of 52
AVCC
5.0V
AVSS
–15V
DVDD
DGND
LDAC
CLEAR
SCLK
SDIN
SYNC
SDO
AGND
SWA
VBOOST_A
POWER-ON
RESET
DC-TO-DC
CONVERTER
DYNAMIC
POWER
CONTROL
INPUT
SHIFT
REGISTER
AND
CONTROL
FAULT
STATUS
REGISTER
ALERT
AVDD
+15V
12
DAC
DATA
REG A
+
DAC
INPUT
REG A
12
7.4V TO 29.5V VSEN1
R2
VSEN2
R3
DAC A
GAIN REG A
OFFSET REG A
IOUT_A
RSET_A
R1
WATCHDOG
TIMER
(SPI ACTIVITY)
30kΩ
REFOUT
REFIN
VOUT
RANGE
SCALING
VREF
REFERENCE
BUFFERS
+VSENSE_A
VOUT_A
DAC CHANNEL A
–VSENSE_A
AD1
AD0
AD5735
RSET_B, RSET_C, RSET_D
DAC CHANNEL D
±V SENSE_B, ±VSENSE_C, ±VSENSE_D
VOUT_B, VOUT_C, VOUT_D
SWB, SWC, SWD
VBOOST_B, VBOOST_C, VBOOST_D
09961-001
IOUT_B, IOUT_C, IOUT_D
DAC CHANNEL B
DAC CHANNEL C
AD5735
Data Sheet
Timing Diagrams
t1
SCLK
1
2
24
t3
t6
t2
t4
t5
SYNC
t8
t7
SDIN
t19
MSB
LSB
t10
t10
t9
LDAC
t17
t12
t11
VOUT_x
LDAC = 0
t12
t16
VOUT_x
t13
CLEAR
t14
VOUT_x
09961-002
t18
RESET
Figure 3. Serial Interface Timing Diagram
SCLK
1
1
24
24
t6
SYNC
MSB
LSB
MSB
LSB
INPUT WORD SPECIFIES
REGISTER TO BE READ
NOP CONDITION
MSB
SDO
LSB
UNDEFINED
t15
SELECTED REGISTER DATA
CLOCKED OUT1
1IF
FIRST SCLK IS NEGATIVE EDGE WITHIN SYNC FRAME OF NOP CONDITION, 7 DONT CARE BITS + 16 DATA BITS CLOCKED OUT (TOTAL 23 BITS).
IF FIRST SCLK IS POSITIVE EDGE WITHIN SYNC FRAME OF NOP CONDITION, 8 DONT CARE BITS + 16 DATA BITS CLOCKED OUT (TOTAL 24 BITS).
SEE THE READBACK OPERATION SECTION FOR FURTHER INFORMATION.
Figure 4. Readback Timing Diagram (Packet Error Checking Disabled)
Rev. D | Page 10 of 52
09961-003
SDIN
Data Sheet
SCLK
AD5735
1
24
1
32
24
32
t62
SYNC
MSB
SDIN
LSB
CRC7
INPUT WORD SPECIFIES
REGISTER TO BE READ
CRC0
MSB
LSB
CRC7
NOP
CONDITION
8-BIT CRC
CRC0
8-BIT CRC
MSB
SDO
LSB
8-BIT CRC
t15
UNDEFINED
SELECTED REGISTER DATA
CLOCKED OUT1
FIRST SCLK IS NEGATIVE EDGE WITHIN SYNC FRAME OF NOP CONDITION, 7 DONT CARE BITS + 16 DATA BITS CLOCKED OUT + 8 CRC BITS (TOTAL 31 BITS).
IF FIRST SCLK IS POSITIVE EDGE WITHIN SYNC FRAME OF NOP CONDITION, 8 DONT CARE BITS + 16 DATA BITS CLOCKED OUT + 8 CRC BITS (TOTAL 32 BITS).
2 AVOID SCLK ACTIVITY DURING t AS IT MAY RESULT IN A PEC ERROR ON READBACK.
6
SEE THE READBACK OPERATION AND PACKET ERROR CHECKING SECTIONS FOR FURTHER INFORMATION.
09961-105
1IF
Figure 5. Readback Timing Diagram (Packet Error Checking Enabled)
LSB
1
MSB
24
2
SCLK
SDO
R/W
DUT_
AD1
DUT_
AD0
SDO DISABLED
X
X
X
D15
D14
D1
D0
SDO_
ENAB
STATUS
STATUS
STATUS
STATUS
Figure 6. Status Readback During Write, Timing Diagram
200µA
TO OUTPUT
PIN
IOL
VOH (MIN) OR
VOL (MAX)
CL
50pF
200µA
IOH
Figure 7. Load Circuit for SDO Timing Diagrams
Rev. D | Page 11 of 52
09961-005
SDIN
09961-004
SYNC
RSET_C
RSET_D
REFOUT
REFIN
COMPLV_D
–VSENSE_D
+VSENSE_D
COMPDCDC_D
VBOOST_D
VOUT_D
IOUT_D
AVSS
COMPLV_C
–VSENSE_C
+VSENSE_C
VOUT_C
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
PIN 1
INDICATOR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AD5735
TOP VIEW
(Not to Scale)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
COMPDCDC_C
IOUT_C
VBOOST_C
AVCC
SWC
GNDSWC
GNDSWD
SWD
AVSS
SWA
GNDSWA
GNDSWB
SWB
AGND
VBOOST_B
IOUT_B
NOTES
1.THE EXPOSED PADDLE SHOULD BE CONNECTED TO THE POTENTIAL OF THE
AVSS PIN, OR, ALTERNATIVELY, IT CAN BE LEFT ELECTRICALLY UNCONNECTED.
IT IS RECOMMENDED THAT THE PADDLE BE THERMALLY CONNECTED TO A
COPPER PLANE FOR ENHANCED THERMAL PERFORMANCE.
09961-006
POC
RESET
AVDD
COMPLV_A
–VSENSE_A
+VSENSE_A
COMPDCDC_A
VBOOST_A
VOUT_A
IOUT_A
AVSS
COMPLV_B
–VSENSE_B
+VSENSE_B
VOUT_B
COMPDCDC_B
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
RSET_B
RSET_A
REFGND
REFGND
AD0
AD1
SYNC
SCLK
SDIN
SDO
DVDD
DGND
LDAC
CLEAR
ALERT
FAULT
0.008
0.008
AVDD = +15V
AVSS = –15V
TA = 25°C
0.006
0.004
0.004
INL ERROR (%FSR)
0.002
0
–0.002
±12V RANGE
2000
3000
4000
CODE
–0.008
–40
09961-208
–0.006
1000
–0.002
–20
0
20
40
60
80
100
TEMPERATURE (°C)
1.0
1.0
AVDD = +15V
AVSS = –15V
TA = 25°C
0.8
0.8
0.6
0.6
0.4
0.4
DNL ERROR (LSB)
DNL ERROR (LSB)
AVDD = +15V
AVSS = –15V
OUTPUT UNLOADED
–0.006
±10V RANGE
WITH DC-TO-DC CONVERTER
0
0
+5V RANGE MAX INL
±10V RANGE MAX INL
±12V RANGE MAX INL
+5V RANGE MIN INL
±10V RANGE MIN INL
±12V RANGE MIN INL
–0.004
±10V RANGE
–0.004
0.002
09961-211
INL ERROR (%FSR)
0.006
0.2
0
–0.2
±10V RANGE
–0.4
AVDD = +15V
AVSS = –15V
ALL RANGES
MAX DNL
0.2
0
MIN DNL
–0.2
–0.4
±12V RANGE
–0.6
–0.6
±10V RANGE
WITH DC-TO-DC CONVERTER
–0.8
0
1000
2000
3000
4000
CODE
–1.0
–40
09961-209
–1.0
0
20
40
60
80
100
60
80
100
TEMPERATURE (°C)
0.02
0.06
0
–0.01
–0.02
±10V RANGE
–0.03
±12V RANGE
±10V RANGE
WITH DC-TO-DC CONVERTER
–0.04
0
1000
2000
CODE
3000
4000
0.05
+5V RANGE
±10V RANGE
±12V RANGE
0.04
0.03
AV DD = +15V
AV SS = –15V
OUTPUT UNLOADED
0.02
0.01
0
–0.01
–40
–20
0
20
40
TEMPERATURE (°C)
09961-129
0.01
TOTAL UNADJUSTED ERROR (%FSR)
AVDD = +15V
AVSS = –15V
TA = 25°C
09961–210
TOTAL UNADJUSTED ERROR (%FSR)
–20
09961-212
–0.8
0.09
0.06
0.08
0.07
+5V RANGE
±10V RANGE
±12V RANGE
0.04
GAIN ERROR (%FSR)
FULL-SCALE ERROR (%FSR)
0.05
0.03
AV DD = +15V
AV SS = –15V
OUTPUT UNLOADED
0.02
0.01
0.06
+5V RANGE
±10V RANGE
±12V RANGE
AV DD = +15V
AV SS = –15V
OUTPUT UNLOADED
0.05
0.04
0.03
0.02
0.01
0
0
–20
0
20
40
60
80
100
TEMPERATURE (°C)
–0.02
–40
09961-132
–0.01
–40
–20
0
20
40
60
80
100
60
80
100
TEMPERATURE (°C)
0.015
09961-135
–0.01
0.006
0.010
0.005
+5V RANGE
±10V RANGE
±12V RANGE
–0.005
–0.010
–0.015
AV DD = +15V
AV SS = –15V
OUTPUT UNLOADED
–0.020
–0.025
–0.030
+5V RANGE
0.004
0.003
+6V RANGE
0.002
0.001
AV DD = +15V
AV SS = –15V
OUTPUT UNLOADED
–0.035
–20
0
20
40
60
80
100
TEMPERATURE (°C)
0
–40
09961-133
–0.040
–40
0
20
40
TEMPERATURE (°C)
0.010
0.006
MAX INL
±10V RANGE
0.005
0.004
0
–0.010
–0.015
INL ERROR (%FSR)
–0.005
AV DD = +15V
AV SS = –15V
OUTPUT UNLOADED
–0.020
–0.025
±12V RANGE
0.002
0V TO 5V RANGE
TA = 25°C
AVSS = –26.4V FOR AVDD > +26.4V
AVSS = –10.8V FOR AVDD < +10.8V
0
–0.002
–0.030
–0.035
–0.004
MIN INL
–0.045
–40
–20
0
20
40
TEMPERATURE (°C)
60
80
100
–0.006
5
10
15
20
SUPPLY (V)
25
30
09961-219
–0.040
09961-134
BIPOLAR ZERO ERROR (%FSR)
–20
09961-136
0
ZERO-SCALE ERROR (%FSR)
OFFSET ERROR (%FSR)
0.005
1.0
12
AV DD = +15V
AV SS = –15V
±10V RANGE
TA = 25°C
OUTPUT UNLOADED
0.8
ALL RANGES
TA = 25°C
AVSS = –26.4V FOR AVDD > +26.4V
AVSS = –10.8V FOR AVDD < +10.8V
0.4
0.2
OUTPUT VOLTAGE (V)
DNL ERROR (LSB)
0.6
8
MAX DNL
0
MIN DNL
–0.2
–0.4
–0.6
4
0
–4
–8
5
10
15
20
SUPPLY (V)
25
–12
–5
09961-220
–1.0
30
10
15
12
0V TO 5V RANGE
TA = 25°C
AV SS = –26.4V FOR AV DD > +26.4V
AV SS = –10.8V FOR AV DD < +10.8V
0.015
0.010
AV DD = +15V
AV SS = –15V
±10V RANGE
TA = 25°C
OUTPUT UNLOADED
8
OUTPUT VOLTAGE (V)
0.005
MAX TUE
0
–0.005
MIN TUE
–0.010
4
0
–4
–0.015
–8
5
10
15
20
25
–12
–5
09961-035
–0.025
30
SUPPLY (V)
10
15
15
AV DD = +15V
AV SS = –15V
±10V RANGE
TA = 25°C
0x7FFF TO 0x8000
0x8000 TO 0x7FFF
8mA LIMIT, CODE = 0xFFFF
16mA LIMIT, CODE = 0xFFFF
10
0.0010
VOLTAGE (mV)
5
0.0005
0
–0.0005
–0.0010
–12
–8
–4
0
4
8
OUTPUT CURRENT (mA)
12
16
–5
–15
20
09961-036
–16
0
–10
AV DD = +15V
AV SS = –15V
±10V RANGE
TA = 25°C
–0.0015
–0.0020
–20
5
TIME (µs)
0.0020
0.0015
0
09961-038
–0.020
THE EXTERNAL RESISTOR IS A
VISHAY S102C, 0.6ppm RESISTOR
–20
0
1
2
3
TIME (µs)
4
5
09961-039
TOTAL UNADJUSTED ERROR (%FSR)
5
TIME (µs)
0.020
OUTPUT VOLTAGE DELTA (V)
0
09961-037
–0.8
15
60
AV DD = +15V
AV SS = –15V
±10V RANGE
TA = 25°C
OUTPUT UNLOADED
10
40
20
0
0
–5
–20
–40
–60
POC = 1
POC = 0
–80
AV DD = +15V
AV SS = –15V
±10V RANGE
TA = 25°C
INT_ENABLE = 1
–100
–10
–120
0
1
2
3
4
5
6
7
8
9
10
TIME (s)
300
AV DD = +15V
AV SS = –15V
–140
09961-040
–15
0
6
8
10
0
±10V RANGE OUTPUT UNLOADED
TA = 25°C
–20
VOUT_X PSRR (dB)
100
0
–100
–200
AV DD = +15V
VBOOST = +15V
AV SS = –15V
TA = 25°C
–40
–60
–80
–300
0
1
2
3
4
5
6
7
8
9
10
TIME (µs)
09961-041
–100
25
20
15
10
5
0
–5
–10
–15
–25
0
25
50
75
TIME (µs)
100
125
09961-043
AV DD = +15V
AV SS = –15V
TA = 25°C
–20
–120
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
09961-045
VOLTAGE (µV)
4
TIME (µs)
200
VOLTAGE (mV)
2
09961-044
VOLTAGE (mV)
VOLTAGE (µV)
5
0.008
0.008
4mA TO 20mA, INTERNAL RSET, WITH DC-TO-DC CONVERTER
4mA TO 20mA, EXTERNAL RSET, WITH DC-TO-DC CONVERTER
4mA TO 20mA, INTERNAL RSET
4mA TO 20mA, EXTERNAL RSET
0.006
0.006
INL ERROR (%FSR)
0.002
0
–0.002
0.002
0
–0.002
4mA TO 20mA RANGE MAX INL
0mA TO 24mA RANGE MAX INL
0mA TO 20mA RANGE MAX INL
4mA TO 20mA RANGE MIN INL
0mA TO 24mA RANGE MIN INL
0mA TO 20mA RANGE MIN INL
AVDD = +15V
AVSS = –15V/0V
–0.004
AVDD = +15V
AVSS = –15V
TA = 25°C
–0.006
–0.006
0
1000
2000
3000
4000
CODE
–0.008
–40
09961-231
–0.004
–20
0
20
40
60
80
100
TEMPERATURE (°C)
09961-234
INL ERROR (%FSR)
0.004
0.004
0.008
1.0
4mA TO 20mA, INTERNAL RSET, WITH DC-TO-DC CONVERTER
4mA TO 20mA, EXTERNAL RSET, WITH DC-TO-DC CONVERTER
4mA TO 20mA, INTERNAL RSET
4mA TO 20mA, EXTERNAL RSET
0.8
0.6
0.006
INL ERROR (%FSR)
DNL ERROR (LSB)
0.004
0.4
0.2
0
–0.2
–0.4
0.002
0
–0.002
4mA TO 20mA RANGE MAX INL
0mA TO 24mA RANGE MAX INL
0mA TO 20mA RANGE MAX INL
4mA TO 20mA RANGE MIN INL
0mA TO 24mA RANGE MIN INL
0mA TO 20mA RANGE MIN INL
AVDD = +15V
AVSS = –15V/0V
–20
60
–0.004
AVDD = +15V
AVSS = –15V
TA = 25°C
–1.0
0
1000
2000
3000
4000
CODE
0.05
0.4
DNL ERROR (LSB)
0.6
0.02
AVDD = +15V
AVSS = –15V
TA = 25°C
–0.01
–0.02
0
1000
2000
CODE
3000
4000
100
MAX DNL
0
MIN DNL
–0.2
–0.4
–0.8
4mA TO 20mA, EXTERNAL RSET
4mA TO 20mA, EXTERNAL RSET, WITH DC-TO-DC CONVERTER
–0.04
80
0.2
–0.6
–0.03
40
0.8
0.03
0
20
1.0
0.04
0.01
0
TEMPERATURE (°C)
4mA TO 20mA, INTERNAL RSET
4mA TO 20mA, INTERNAL RSET, WITH DC-TO-DC CONVERTER
09961-233
TOTAL UNADJUSTED ERROR (%FSR)
0.06
–0.008
–40
09961-235
–0.006
09961-232
–0.8
–1.0
–40
AVDD = +15V
AVSS = –15V/0V
ALL RANGES
INTERNAL AND EXTERNAL RSET
–20
0
20
40
TEMPERATURE (°C)
60
80
100
09961-236
–0.6
0.008
0.025
MAX INL
0.006
0.015
0.005
0
–0.005
AV DD = +15V
AV SS = –15V
–0.010
0.004
INL ERROR (%FSR)
0.010
4mA TO 20mA RANGE
TA = 25°C
AVSS = –26.4V FOR AVDD > +26.4V
AVSS = –10.8V FOR AVDD < +10.8V
0.002
0
–0.002
–0.015
–20
0
60
20
40
TEMPERATURE (°C)
80
100
–0.006
MIN INL
5
10
15
20
25
30
25
30
SUPPLY (V)
0.020
0.008
0.015
0.006
09961-240
–0.025
–40
–0.004
4mA TO 20mA RANGE, INTERNAL RSET
4mA TO 20mA RANGE, EXTERNAL RSET
–0.020
09961-155
TOTAL UNADJUSTED ERROR (%FSR)
0.020
0.010
0
–0.005
AV DD = +15V
AV SS = –15V
–40
–20
0
60
20
40
TEMPERATURE (°C)
–0.004
80
100
–0.006
10
15
20
1.0
ALL RANGES
TA = 25°C
AVSS = –26.4V FOR AVDD > +26.4V
AVSS = –10.8V FOR AVDD < +10.8V
0.8
0
DNL ERROR (LSB)
0.6
–0.005
–0.010
–0.015
AV DD = +15V
AV SS = –15V
–0.020
–20
0
60
20
40
TEMPERATURE (°C)
0.4
MAX DNL
0.2
0
MIN DNL
–0.2
–0.4
–0.6
4mA TO 20mA RANGE, INTERNAL RSET
4mA TO 20mA RANGE, EXTERNAL RSET
80
–0.8
100
09961-159
GAIN ERROR (%FSR)
5
SUPPLY (V)
0.005
–0.025
–40
MIN INL
09961-241
–0.020
0
–0.002
4mA TO 20mA RANGE, INTERNAL RSET
4mA TO 20mA RANGE, EXTERNAL RSET
–0.015
4mA TO 20mA RANGE
TA = 25°C
AVSS = –26.4V FOR AVDD > +26.4V
AVSS = –10.8V FOR AVDD < +10.8V
0.002
–1.0
5
10
15
20
SUPPLY (V)
25
30
09961-242
–0.010
0.004
INL ERROR (%FSR)
0.005
09961-157
FULL-SCALE ERROR (%FSR)
MAX INL
4
MAX TUE
0
2
–0.005
0
–0.020
MIN TUE
–4
–6
–0.025
AV DD = +15V
AV SS = –15V
TA = 25°C
RLOAD = 300Ω
INT_ENABLE = 1
–8
–0.030
5
10
15
20
25
30
SUPPLY (V)
0.07
0.06
MAX TUE
0.05
0.04
4mA TO 20mA RANGE
TA = 25°C
AV SS = –26.4V FOR AV DD > +26.4V
AV SS = –10.8V FOR AV DD < +10.8V
0.03
0.02
0.01
0
MIN TUE
–0.01
10
15
20
25
09961-061
–0.02
5
–10
09961-060
–0.035
30
SUPPLY (V)
0
1
2
3
4
5
6
TIME (µs)
30
25
20
IOUT_x
VBOOST_x
15
10
0mA TO 24mA RANGE
1kΩ LOAD
fSW = 410kHz
INDUCTOR = 10µH (XAL4040-103)
AV CC = 5V
TA = 25°C
5
0
–0.50 –0.25
0
0.25
0.50
0.75
1.00 1.25
1.50 1.75 2.00
TIME (ms)
6
30
AV DD = +15V
AV SS = –15V
TA = 25°C
RLOAD = 300Ω
25
OUTPUT CURRENT (mA)
5
3
2
1
20
TA = –40°C
TA = +25°C
TA = +105°C
15
10
0mA TO 24mA RANGE
1kΩ LOAD
fSW = 410kHz
INDUCTOR = 10µH (XAL4040-103)
AV CC = 5V
5
0
0
5
10
TIME (µs)
15
20
09961-062
CURRENT (µA)
4
0
–0.25
0
0.25
0.50
0.75
1.00
TIME (ms)
1.25
1.50
1.75
09961-168
TOTAL UNADJUSTED ERROR (%FSR)
–2
09961-063
–0.015
09961-167
–0.010
CURRENT (µA)
4mA TO 20mA RANGE
TA = 25°C
AV SS = –26.4V FOR AV DD > +26.4V
AV SS = –10.8V FOR AV DD < +10.8V
OUTPUT CURRENT (mA) AND V BOOST_x VOLTAGE (V)
TOTAL UNADJUSTED ERROR (%FSR)
0.005
8
30
0mA TO 24mA RANGE
1kΩ LOAD
fSW = 410kHz
INDUCTOR = 10µH (XAL4040-103)
TA = 25°C
7
HEADROOM VOLTAGE (V)
20
AVCC = 4.5V
AVCC = 5.0V
AVCC = 5.5V
10
0mA TO 24mA RANGE
1kΩ LOAD
fSW = 410kHz
INDUCTOR = 10µH (XAL4040-103)
TA = 25°C
0
–0.25
0
0.25
0.50
0.75
1.00
1.25
1.50
1.75
TIME (ms)
10
5
4
3
2
1
0
0
6
IOUT_x PSRR (dB)
4
2
0
–2
–4
–6
AV CC = 5V
fSW = 410kHz
INDUCTOR = 10µH (XAL4040-103)
2
4
6
20
8
TIME (µs)
10
12
14
AV DD = +15V
VBOOST_x = +15V
AV SS = –15V
TA = 25°C
–40
–60
–80
–100
0mA TO 24mA RANGE
1kΩ LOAD
EXTERNA L RSET
TA = 25°C
09961-170
CURRENT (AC-COUPLED) (µA)
–20
0
15
0
8
–10
10
OUTPUT CURRENT (mA)
20mA OUTPUT
10mA OUTPUT
–8
5
09961-067
5
6
–120
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
09961-068
15
09961-169
OUTPUT CURRENT (mA)
25
100
100
AVCC = 4.5V
AVCC = 5.0V
AVCC = 5.5V
90
90
80
70
60
50
40
30
0mA TO 24mA RANGE
1kΩ LOAD
EXTERNAL RSET
fSW = 410kHz
INDUCTOR = 10µH (XAL4040-103)
TA = 25°C
10
0
0
0.005
0.010
0.015
0.025
0.020
OUTPUT CURRENT (A)
20mA
60
50
40
30
0mA TO 24mA RANGE
1kΩ LOAD
EXTERNAL RSET
AVCC = 5V
fSW = 410kHz
INDUCTOR = 10µH (XAL4040-103)
20
10
0
–40
09961-016
20
70
–20
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
100
09961-019
OUTPUT EFFICIENCY (%)
VBOOST EFFICIENCY (%)
80
0.6
90
20mA
SWITCH RESISTANCE (Ω)
0.5
70
60
50
40
0mA TO 24mA RANGE
1kΩ LOAD
EXTERNAL RSET
AVCC = 5V
fSW = 410kHz
INDUCTOR = 10µH (XAL4040-103)
20
10
0
–40
–20
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
AV CC = 4.5V
AV CC = 5.0V
AV CC = 5.5V
70
60
50
40
0mA TO 24mA RANGE
1kΩ LOAD
EXTERNAL RSET
fSW = 410kHz
INDUCTOR = 10µH (XAL4040-103)
TA = 25°C
20
10
0
0
0.005
0.010
0.015
OUTPUT CURRENT (A)
0.020
0.025
09961-018
OUTPUT EFFICIENCY (%)
80
30
0.3
0.2
0.1
100
90
0.4
0
–40
–20
0
20
40
TEMPERATURE (°C)
60
80
100
09961-123
30
09961-017
VBOOST EFFICIENCY (%)
80
5.0050
16
AV DD
REFOUT
TA = 25°C
12
8
6
4
2
0
5.0040
5.0035
5.0030
5.0025
5.0020
5.0015
5.0010
0.2
0.4
0.6
0.8
1.0
1.2
TIME (ms)
5.0000
–40
20
40
60
80
100
5.002
AV DD = 15V
TA = 25°C
REFERENCE OUTPUT VOLTAGE (V)
2
1
0
–1
–3
2
4
6
8
10
TIME (s)
09961-011
–2
0
0
TEMPERATURE (°C)
4
3
–20
AV DD = 15V
TA = 25°C
5.001
5.000
4.999
4.998
4.997
4.996
4.995
0
2
4
6
8
10
LOAD CURRENT (mA)
150
5.00000
REFERENCE OUTPUT VOLTAGE (V)
AV DD = 15V
TA = 25°C
100
50
0
–50
–100
–150
0
5
10
TIME (ms)
15
20
09961-012
VOLTAGE (µV)
09961-014
0
09961-010
–2
09961-163
5.0005
4.99995
TA = 25°C
4.99990
4.99985
4.99980
4.99975
4.99970
4.99965
4.99960
10
15
20
AV DD (V)
25
30
09961-015
VOLTAGE (V)
10
VOLTAGE (µV)
30 DEVICES SHOWN
AV DD = 15V
5.0045
REFERENCE OUTPUT VOLTAGE (V)
14
450
13.4
DVDD = 5V
TA = 25°C
400
13.3
350
FREQUENCY (MHz)
13.2
250
200
150
13.1
13.0
12.9
12.8
100
12.7
50
0
1
2
3
4
5
SDIN VOLTAGE (V)
12.6
–40
09961-007
0
DVDD = 5.5V
–20
0
20
40
60
80
09961-020
DICC (µA)
300
100
TEMPERATURE (°C)
10
14.4
8
14.2
6
AIDD
AISS
TA = 25°C
VOUT = 0V
OUTPUT UNLOADED
2
0
14.0
FREQUENCY (MHz)
CURRENT (mA)
4
–2
–4
13.8
13.6
13.4
–6
–8
13.2
–10
15
20
25
30
VOLTAGE (V)
8
7
5
4
3
2
AIDD
TA = 25°C
IOUT = 0mA
1
0
10
15
20
VOLTAGE (V)
25
30
09961-009
CURRENT (mA)
6
13.0
2.5
3.0
3.5
4.0
VOLTAGE (V)
4.5
5.0
5.5
09961-021
TA = 25°C
09961-008
–12
10
Data Sheet
AD5735
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
Relative accuracy, or integral nonlinearity (INL), is a measure
of the maximum deviation from the best fit line through the
DAC transfer function. INL is expressed in percent of full-scale
range (% FSR). Typical INL vs. code plots are shown in Figure 9
and Figure 32.
Differential Nonlinearity (DNL)
Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified DNL of ±1 LSB maximum ensures
monotonicity. The AD5735 is guaranteed monotonic by design.
Typical DNL vs. code plots are shown in Figure 10 and
Figure 33.
Monotonicity
A DAC is monotonic if the output either increases or remains
constant for increasing digital input code. The AD5735 is
monotonic over its full operating temperature range.
Negative Full-Scale Error or Zero-Scale Error
Negative full-scale error is the error in the DAC output voltage
when 0x0000 (straight binary coding) is loaded to the DAC
register.
Zero-Scale Temperature Coefficient (TC)
Zero-scale TC is a measure of the change in zero-scale error
with a change in temperature. Zero-scale TC is expressed in
ppm FSR/°C.
Bipolar Zero Error
Bipolar zero error is the deviation of the analog output from the
ideal half-scale output of 0 V when the DAC register is loaded
with 0x8000 (straight binary coding).
Bipolar Zero Temperature Coefficient (TC)
Bipolar zero TC is a measure of the change in the bipolar zero
error with a change in temperature. It is expressed in ppm
FSR/°C.
Offset Error
In voltage output mode, offset error is the deviation of the
analog output from the ideal quarter-scale output when the
DAC is configured for a bipolar output range and the DAC
register is loaded with 0x4000 (straight binary coding).
In current output mode, offset error is the deviation of the
analog output from the ideal zero-scale output when all DAC
registers are loaded with 0x0000.
Offset Error Drift or Offset TC
Offset error drift, or offset TC, is a measure of the change in
offset error with changes in temperature and is expressed in
ppm FSR/°C.
Gain Temperature Coefficient (TC)
Gain TC is a measure of the change in gain error with changes
in temperature and is expressed in ppm FSR/°C.
Full-Scale Error
Full-scale error is a measure of the output error when full-scale
code is loaded to the DAC register. Ideally, the output should be
full-scale − 1 LSB. Full-scale error is expressed in % FSR.
Full-Scale Temperature Coefficient (TC)
Full-scale TC is a measure of the change in full-scale error with
changes in temperature and is expressed in ppm FSR/°C.
Total Unadjusted Error (TUE)
Total unadjusted error (TUE) is a measure of the output error
that includes all the error measurements: INL error, offset error,
gain error, temperature, and time. TUE is expressed in % FSR.
DC Crosstalk
DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is measured
with a full-scale output change on one DAC while monitoring
another DAC, which is at midscale.
Current Loop Compliance Voltage
The current loop compliance voltage is the maximum voltage
at the IOUT_x pin for which the output current is equal to the
programmed value.
Voltage Reference Thermal Hysteresis
Voltage reference thermal hysteresis is the difference in output
voltage measured at +25°C compared to the output voltage
measured at +25°C after cycling the temperature from +25°C to
−40°C to +105°C and back to +25°C. The hysteresis is specified
in ppm.
Output Voltage Settling Time
Output voltage settling time is the amount of time it takes
for the output to settle to a specified level for a full-scale input
change. Plots of settling time are shown in Figure 24, Figure 49,
and Figure 50.
Slew Rate
The slew rate of a device is a limitation in the rate of change of
the output voltage. The output slewing speed of a voltage output
DAC is usually limited by the slew rate of the amplifier used at
its output. Slew rate is measured from 10% to 90% of the output
signal and is given in V/μs.
Power-On Glitch Energy
Power-on glitch energy is the impulse injected into the analog
output when the AD5735 is powered on. It is specified as the
area of the glitch in nV-sec (see Figure 29 and Figure 46).
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer function from the ideal,
expressed in % FSR.
Rev. D | Page 27 of 52
AD5735
Data Sheet
Digital-to-Analog Glitch Energy
Digital-to-analog glitch energy is the impulse injected into
the analog output when the input code in the DAC register
changes state but the output voltage remains constant. It is
normally specified as the area of the glitch in nV-sec and is
measured when the digital input code is changed by 1 LSB at
the major carry transition (~0x7FFF to 0x8000). See Figure 26.
Glitch Impulse Peak Amplitude
Glitch impulse peak amplitude is the peak amplitude of the
impulse injected into the analog output when the input code in
the DAC register changes state. It is specified as the amplitude
of the glitch in mV and is measured when the digital input code
is changed by 1 LSB at the major carry transition (~0x7FFF to
0x8000). See Figure 26.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC but is measured when the DAC output is not updated. It is
specified in nV-sec and measured with a full-scale code change
on the data bus.
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and a subsequent
output change of another DAC. DAC-to-DAC crosstalk includes
both digital and analog crosstalk. It is measured by loading one
DAC with a full-scale code change (all 0s to all 1s and vice versa)
with LDAC low while monitoring the output of another DAC.
The energy of the glitch is expressed in nV-sec.
Reference Temperature Coefficient (TC)
Reference TC is a measure of the change in the reference output
voltage with changes in temperature. It is expressed in ppm/°C.
Line Regulation
Line regulation is the change in the reference output voltage due
to a specified change in supply voltage. It is expressed in ppm/V.
Load Regulation
Load regulation is the change in the reference output voltage due
to a specified change in load current. It is expressed in ppm/mA.
DC-to-DC Converter Headroom
DC-to-DC converter headroom is the difference between the
voltage required at the current output and the voltage supplied
by the dc-to-dc converter (see Figure 52).
Output Efficiency
Output efficiency is defined as the ratio of the power delivered
to a channel’s load and the power delivered to the channel’s
dc-to-dc input. The VBOOST_x quiescent current is considered
part of the dc-to-dc converter’s losses.
I OUT 2  R LOAD
AVCC  AI CC
Efficiency at VBOOST_x
The efficiency at VBOOST_x is defined as the ratio of the power
delivered to a channel’s VBOOST_x supply and the power delivered
to the channel’s dc-to-dc input. The VBOOST_x quiescent current is
considered part of the dc-to-dc converter’s losses.
Power Supply Rejection Ratio (PSRR)
PSRR indicates how the output of the DAC is affected by changes
in the power supply voltage.
Rev. D | Page 28 of 52
I OUT  V BOOST _ x
AVCC  AI CC
VBOOST_x
R2
R3
T2
A2
T1
IOUT_x
A1
RSET
2R
2R
2R
2R
2R
2R
S0
S1
S7
E1
E2
E15
8-BIT R-2R LADDER
FOUR MSBs DECODED INTO
15 EQUAL SEGMENTS
09961-069
VOUT
2R


+VSENSE_X
RANGE
SCALING
VOUT_X
VOUT_X SHORT FAULT
–VSENSE_X
09961-070
12-BIT
DAC
09961-071
12-BIT
DAC


OUTPUT
AMPLIFIERS
VREFIN
LDAC
12-BIT
DAC
VOUT_x
DAC
REGISTER
DAC INPUT
REGISTER
OFFSET
AND GAIN
CALIBRATION
SCLK
SYNC
SDIN
INTERFACE
LOGIC
SDO
09961-072
DAC DATA
REGISTER
AD5735
Data Sheet
ENABLING THE OUTPUT
REPROGRAMMING THE OUTPUT RANGE
To correctly write to and set up the part from a power-on
condition, use the following sequence:
When changing the range of an output, the same sequence
described in the Enabling the Output section should be used.
It is recommended that the range be set to 0 V (zero scale or
midscale) before the output is disabled. Because the dc-to-dc
switching frequency, maximum output voltage, and phase have
already been selected, there is no need to reprogram these values.
Figure 75 provides a flowchart of this sequence.
3.
4.
5.
Perform a hardware or software reset after initial power-on.
Configure the dc-to-dc converter supply block. Set the
dc-to-dc switching frequency, the maximum output voltage
allowed, and the dc-to-dc converter phase between channels.
Configure the DAC control register on a per-channel basis.
Select the output range, and enable the dc-to-dc converter
block (DC_DC bit). Other control bits can also be configured. Set the INT_ENABLE bit, but do not set the OUTEN
(output enable) bit.
Write the required code to the DAC data register. This step
implements a full internal DAC calibration. For reduced
output glitch, allow at least 200 μs before performing Step 5.
Write to the DAC control register again to enable the
output (set the OUTEN bit).
Figure 74 provides a flowchart of this sequence.
CHANNEL OUTPUT IS ENABLED.
STEP 1: WRITE TO CHANNEL’S DAC DATA
REGISTER. SET THE OUTPUT
TO 0V (ZERO OR MIDSCALE).
STEP 2: WRITE TO DAC CONTROL REGISTER.
DISABLE THE OUTPUT (OUTEN = 0) AND
SET THE NEW OUTPUT RANGE. KEEP THE
DC_DC BIT AND THE INT_ENABLE BIT SET.
STEP 3: WRITE VALUE TO THE DAC DATA REGISTER.
POWER ON.
STEP 4: WRITE TO DAC CONTROL REGISTER.
RELOAD SEQUENCE AS IN STEP 2.
SET THE OUTEN BIT TO ENABLE THE
OUTPUT.
STEP 1: PERFORM A SOFTWARE/HARDWARE RESET.
09961-074
1.
2.
Figure 75. Programming Sequence to Change the Output Range
STEP 2: WRITE TO DC-TO-DC CONTROL REGISTER TO
SET DC-TO-DC CLOCK FREQUENCY, PHASE,
AND MAXIMUM VOLTAGE.
STEP 3: WRITE TO DAC CONTROL REGISTER. SELECT
THE DAC CHANNEL AND OUTPUT RANGE.
SET THE DC_DC BIT AND OTHER CONTROL
BITS AS REQUIRED. SET THE INT_ENABLE BIT
BUT DO NOT SET THE OUTEN BIT.
STEP 5: WRITE TO DAC CONTROL REGISTER. RELOAD
SEQUENCE AS IN STEP 3. SET THE OUTEN
BIT TO ENABLE THE OUTPUT.
09961-073
STEP 4: WRITE TO ONE OR MORE DAC DATA REGISTERS.
ALLOW AT LEAST 200µs BETWEEN STEP 3
AND STEP 5 FOR REDUCED OUTPUT GLITCH.
Figure 74. Programming Sequence to Correctly Enable the Output
Rev. D | Page 32 of 52





DAC DATA
REGISTER
DAC
INPUT
REGISTER
DAC
OFFSET (C)
REGISTER
09961-075
GAIN (M)
REGISTER




UPDATE ON SYNC HIGH
SYNC
SCLK
MSB
D23
SDIN
LSB
D0
24-BIT DATA
24-BIT DATA TRANSFER—NO ERROR CHECKING
UPDATE ON SYNC HIGH
ONLY IF ERROR CHECK PASSED
SYNC
SCLK
SDIN
FAULT
LSB
D8
24-BIT DATA
D7
D0
8-BIT CRC
FAULT PIN GOES LOW
IF ERROR CHECK FAILS
32-BIT DATA TRANSFER WITH ERROR CHECKING
09961-180
MSB
D31





CDCDC
4.7µF
SWx
RFILTER
10Ω
VBOOST_x
CFILTER
0.1µF
29.6
VMAX
DC-DCx BIT
29.5
0mA TO 24mA RANGE, 24mA OUTPUT
OUTPUT UNLOADED
29.4
29.3
29.2
29.1
DC-DC MaxV BITS = 29.5V
DC-DCx BIT = 1
29.0
fSW = 410kHz
28.9
TA = 25°C
28.8
28.7
DC-DCx BIT = 0
28.6
0
0.5
1.0
1.5
2.0
2.5
TIME (ms)
3.0
3.5
4.0
09961-183
DDCDC
10µH
VBOOST_x VOLTAGE (V)
CIN
≥10µF
LDCDC
09961-077
AV CC





25
AICC CURRENT (A)
0.6
0mA TO 24mA RANGE
1kΩ LOAD
fSW = 410kHz
INDUCTOR = 10µH (XAL4040-103)
TA = 25°C
0.5
0.4
20
15
0.3
10
0.2
AICC
IOUT
VBOOST
0.1
5
0
0
0
0.5
1.0
1.5
TIME (ms)
2.0
2.5
09961-184
30
0.7
IOUT_x CURRENT (mA)/ VBOOST_x VOLTAGE (V)
0.8
0.8
AICC CURRENT (A)
0.6
28
24
AICC
IOUT
VBOOST
0.5
20
0.4
16
0.3
12
0.2
8
0.1
4
0
0
24
0.5
20
0.4
16
0.3
12
8
0.2
AICC
IOUT
VBOOST
0.1
4
0
0
0.5
1.0
1.5
TIME (ms)
2.0
0.8
0mA TO 24mA RANGE
500Ω LOAD
fSW = 410kHz
INDUCTOR = 10µH (XAL4040-103)
TA = 25°C
0.6
28
24
0.5
20
0.4
16
0.3
12
0.2
8
0.1
4
0
0
0.5
1.0
1.5
TIME (ms)
2.0
0
2.5
IOUT_x CURRENT (mA)/V BOOST_x VOLTAGE (V)
32
AICC
IOUT
VBOOST
0.7
AICC CURRENT (A)
0
2.5
09961-186
AICC CURRENT (A)
0.6
28
IOUT_x CURRENT (mA)/ VBOOST_x VOLTAGE (V)
0.7
0
32
0mA TO 24mA RANGE
1kΩ LOAD
fSW = 410kHz
INDUCTOR = 10µH (XAL4040-103)
TA = 25°C
09961-185
0.8
1
2
3
TIME (ms)
4
5
6
09961-187
0.7
IOUT_x CURRENT (mA)/ VBOOST_x VOLTAGE (V)
32
0mA TO 24mA RANGE
1kΩ LOAD
fSW = 410kHz
INDUCTOR = 10µH (XAL4040-103)
TA = 25°C
AD5735
10Ω
SYNC
SPORT_TSCLK
SCLK
SPORT_DT0
SDIN
CFILTER
0.1µF
ADSP-BF527
VBOOST_x
AD5735
IOUT_x
AGND
GPIO0
D1
RP
D2
AVSS
RLOAD
LDAC
09961-080
CDCDC
4.7µF
RFILTER
09961-079
(FROM
DC-TO-DC
CONVERTER)
SPORT_TFS



i



ADuM1411
SERIAL CLOCK
OUT
VIA
SERIAL DATA
OUT
VIB
SYNC OUT
CONTROL OUT
VIC
VID
ENCODE
DECODE
ENCODE
DECODE
ENCODE
DECODE
ENCODE
DECODE
VOA
VOB
VOC
VOD
TO SCLK
TO SDIN
TO SYNC
TO LDAC
09961-081
MICROCONTROLLER
AD5735
Data Sheet
OUTLINE DIMENSIONS
9.10
9.00 SQ
8.90
0.60 MAX
0.60
MAX
64
49
1
PIN 1
INDICATOR
48
PIN 1
INDICATOR
8.85
8.75 SQ
8.65
0.50
BSC
0.50
0.40
0.30
33
32
0.05 MAX
0.02 NOM
0.30
0.23
0.18
0.25 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
06-13-2012-C
SEATING
PLANE
16
7.50 REF
0.80 MAX
0.65 TYP
12° MAX
17
BOTTOM VIEW
TOP VIEW
1.00
0.85
0.80
7.25
7.10 SQ
6.95
EXPOSED
PAD
Figure 87. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm × 9 mm Body, Very Thin Quad
(CP-64-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD5735ACPZ
AD5735ACPZ-REEL7
1
Resolution (Bits)
12
12
Temperature Range
−40°C to +105°C
−40°C to +105°C
Z = RoHS Compliant Part.
Rev. D | Page 50 of 52
Package Description
64-Lead LFCSP_VQ
64-Lead LFCSP_VQ
Package Option
CP-64-3
CP-64-3