Quad-Channel, 12-Bit, Serial Input, 4 mA to 20 mA Output
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Quad-Channel, 12-Bit, Serial Input, 4 mA to 20 mA Output DAC with Dynamic Power Control and HART Connectivity AD5737 Data Sheet Each channel has a corresponding CHART pin so that HART signals can be coupled onto the current output of the AD5737. FEATURES 12-bit resolution and monotonicity Dynamic power control for thermal management or external PMOS mode Current output ranges: 0 mA to 20 mA, 4 mA to 20 mA, and 0 mA to 24 mA ±0.1% total unadjusted error (TUE) maximum User-programmable offset and gain On-chip diagnostics On-chip reference: ±10 ppm/°C maximum −40°C to +105°C temperature range The AD5737 uses a versatile 3-wire serial interface that operates at clock rates of up to 30 MHz and is compatible with standard SPI, QSPI™, MICROWIRE®, DSP, and microcontroller interface standards. The serial interface also features optional CRC-8 packet error checking, as well as a watchdog timer that monitors activity on the interface. PRODUCT HIGHLIGHTS 1. 2. 3. 4. APPLICATIONS Process control Actuator control PLCs HART network connectivity Dynamic power control for thermal management. 12-bit performance. Quad channel. HART compliant. COMPANION PRODUCTS Product Family: AD5755, AD5755-1, AD5757, AD5735 HART Modem: AD5700, AD5700-1 External References: ADR445, ADR02 Digital Isolators: ADuM1410, ADuM1411 Power: ADP2302, ADP2303 Additional companion products on the AD5737 product page GENERAL DESCRIPTION The AD5737 is a quad-channel current output DAC that operates with a power supply range from 10.8 V to 33 V. On-chip dynamic power control minimizes package power dissipation by regulating the voltage on the output driver from 7.4 V to 29.5 V using a dc-to-dc boost converter optimized for minimum on-chip power dissipation. FUNCTIONAL BLOCK DIAGRAM AV CC 5.0V AGND AV DD +15V SWx DVDD VBOOST_x 7.4V TO 29.5V DGND LDAC DC-TO-DC CONVERTER SCLK SDIN SYNC SDO CLEAR DIGITAL INTERFACE IOUT_x + FAULT ALERT GAIN REG A OFFSET REG A AD1 RSET_x DAC A CURRENT OUTPUT RANGE SCALING CHARTx AD0 DAC CHANNE L A REFERENCE REFIN DAC CHANNEL B DAC CHANNEL C AD5737 DAC CHANNEL D 10067-101 REFOUT NOTES 1. x = A, B, C, OR D. Figure 1. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2011–2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD5737 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Readback Operation .................................................................. 31 Applications ....................................................................................... 1 Device Features ............................................................................... 34 General Description ......................................................................... 1 Fault Output ................................................................................ 34 Product Highlights ........................................................................... 1 Digital Offset and Gain Control ............................................... 34 Companion Products ....................................................................... 1 Status Readback During a Write .............................................. 34 Functional Block Diagram .............................................................. 1 Asynchronous Clear................................................................... 34 Revision History ............................................................................... 3 Packet Error Checking ............................................................... 35 Detailed Functional Block Diagram .............................................. 4 Watchdog Timer ......................................................................... 35 Specifications..................................................................................... 5 Alert Output ................................................................................ 35 AC Performance Characteristics ................................................ 7 Internal Reference ...................................................................... 35 Timing Characteristics ................................................................ 7 External Current Setting Resistor ............................................ 35 Absolute Maximum Ratings .......................................................... 10 HART Connectivity ................................................................... 36 Thermal Resistance .................................................................... 10 Digital Slew Rate Control .......................................................... 36 ESD Caution ................................................................................ 10 Dynamic Power Control............................................................ 37 Pin Configuration and Function Descriptions ........................... 11 DC-to-DC Converters ............................................................... 37 Typical Performance Characteristics ........................................... 14 AICC Supply Requirements—Static .......................................... 38 Current Outputs ......................................................................... 14 AICC Supply Requirements—Slewing ...................................... 39 DC-to-DC Converter ................................................................. 18 External PMOS Mode ................................................................ 40 Reference ..................................................................................... 19 Applications Information .............................................................. 41 General ......................................................................................... 20 Current Output Mode with Internal RSET ................................ 41 Terminology .................................................................................... 21 Precision Voltage Reference Selection ..................................... 41 Theory of Operation ...................................................................... 22 Driving Inductive Loads............................................................ 41 DAC Architecture ....................................................................... 22 Transient Voltage Protection .................................................... 42 Power-On State of the AD5737 ................................................ 22 Microprocessor Interfacing ....................................................... 42 Serial Interface ............................................................................ 22 Layout Guidelines....................................................................... 42 Transfer Function ....................................................................... 23 Galvanically Isolated Interface ................................................. 43 Registers ........................................................................................... 24 Industrial HART Capable Analog Output Application ........ 44 Enabling the Output ................................................................... 25 Outline Dimensions ....................................................................... 45 Reprogramming the Output Range ......................................... 25 Ordering Guide .......................................................................... 45 Data Registers ............................................................................. 26 Control Registers ........................................................................ 28 Rev. E | Page 2 of 45 Data Sheet AD5737 REVISION HISTORY 9/14—Rev. D to Rev. E 5/12—Rev. A to Rev. B Changes to Table 3 ............................................................................ 7 Changes to Software Register and Status Register Descriptions .....................................................................................24 Changes to Software Register Section, Table 24, and Table 25 ... 30 Changes to Status Register Section and Table 34 ........................33 Changes to Packet Error Checking Section .................................35 Changes to Companion Products Section ..................................... 1 Change to Table 5 ............................................................................ 12 Added Industrial HART Capable Analog Output Application Section and Figure 65, Renumbered Sequentially ...................... 42 Updated Outline Dimensions........................................................ 43 6/14—Rev. C to Rev. D Change to Accuracy, External RSET Parameter in Table 1 ............ 4 Changes to Power-On State of the AD5737 Section .................. 21 Changes to Readback Operation Section and Readback Example Section .............................................................................. 30 Change to Thermal Hysteresis Parameter, Table 1 ....................... 6 Changes to Table 3 ............................................................................ 7 Changes to Figure 5 and Added Figure 6; Renumbered Sequentially ........................................................................................ 9 Changes to Table 5 ..........................................................................10 Changes to Figure 33, Figure 34, Figure 35, and Figure 36 .......18 Changes to Terminology Section ..................................................21 Changes to Table 8 and Table 9 .....................................................24 Changes to Software Register Section, Table 24, and Table 25 .......30 Changes to Readback Operation Section and Table 34, Added Table 30 and Table 31; Renumbered Sequentially ......................31 Changes to Status Readback During a Write Section .................34 Changes to Packet Error Checking Section .................................35 Changes to Table 36 ........................................................................37 Changes to Figure 62 ......................................................................40 11/11—Rev. 0 to Rev. A 7/11—Revision 0: Initial Version 11/12—Rev. B to Rev. C Changed Thermal Impedance from 20°C/W to 28°C/W ..........10 Changes to Pin 6 Description ........................................................11 Changes to DUT_AD1, DUT_AD0 Description, Table 11 .......26 Changes to Changes to Packet Error Checking Section and Internal Reference Section .............................................................34 Changes to Figure 56 ......................................................................36 Changes to Figure 62 ......................................................................41 Changes to Figure 65 ......................................................................43 Updated Outline Dimensions ........................................................44 Rev. E | Page 3 of 45 AD5737 Data Sheet DETAILED FUNCTIONAL BLOCK DIAGRAM AV CC 5.0V AGND DVDD DGND LDAC CLEAR SCLK SDIN SYNC SDO INPUT SHIFT REGISTER AND CONTROL VBOOST_A DC-TO-DC CONVERTER DYNAMIC POWER CONTROL STATUS REGISTER REFOUT SWA POWER-ON RESET FAULT ALERT AV DD +15V 12 DAC DATA REG A + DAC INPUT REG A 12 7.4V TO 29.5V VSEN1 R2 VSEN2 R3 DAC A GAIN REG A OFFSET REG A IOUT_A R1 WATCHDOG TIMER (SPI ACTIVITY) RSET_A CHARTA VREF DAC CHANNEL A AD1 AD0 REFERENCE BUFFERS AD5737 IOUT_B, IOUT_C, IOUT_D RSET_B, RSET_C, RSET_D DAC CHANNEL B DAC CHANNEL C CHARTB, CHARTC, CHARTD DAC CHANNEL D SWB, SWC, SWD Figure 2. Rev. E | Page 4 of 45 VBOOST_B, VBOOST_C, VBOOST_D 10067-001 REFIN Data Sheet AD5737 SPECIFICATIONS AVDD = VBOOST_x = 15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = GNDSWx = 0 V; REFIN = 5 V; RL = 300 Ω; all specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter1 CURRENT OUTPUT Output Current Ranges Resolution ACCURACY, EXTERNAL RSET Total Unadjusted Error (TUE) TUE Long-Term Stability Relative Accuracy (INL) Differential Nonlinearity (DNL) Offset Error Offset Error Drift2 Gain Error Gain TC2 Full-Scale Error Full-Scale TC2 DC Crosstalk ACCURACY, INTERNAL RSET Total Unadjusted Error (TUE)3, 4 TUE Long-Term Stability Relative Accuracy (INL) Differential Nonlinearity (DNL) Offset Error3, 4 Offset Error Drift2 Gain Error Gain TC2 Full-Scale Error3, 4 Full-Scale TC2 DC Crosstalk4 OUTPUT CHARACTERISTICS2 Current Loop Compliance Voltage Min Typ 0 0 4 12 Max Unit 24 20 20 mA mA mA Bits Assumes ideal resistor (see the External Current Setting Resistor section for more information) −0.1 −0.032 −1 −0.1 −0.1 −0.1 −0.14 −0.032 −1 −0.1 −0.12 −0.14 ±0.019 100 ±0.006 ±0.012 ±4 ±0.004 ±3 ±0.014 ±5 0.0005 ±0.022 180 ±0.006 ±0.017 ±6 ±0.004 ±9 ±0.02 ±14 −0.011 VBOOST_x − 2.4 +0.1 +0.032 +1 +0.1 +0.1 +0.1 +0.14 +0.032 +1 +0.1 +0.12 +0.14 VBOOST_x − 2.7 % FSR ppm FSR % FSR LSB % FSR ppm FSR/°C % FSR ppm FSR/°C % FSR ppm FSR/°C % FSR % FSR ppm FSR % FSR LSB % FSR ppm FSR/°C % FSR ppm FSR/°C % FSR ppm FSR/°C % FSR 90 140 Resistive Load 100 0.02 Drift after 1000 hours, TJ = 150°C Guaranteed monotonic External RSET Drift after 1000 hours, TJ = 150°C Guaranteed monotonic Internal RSET V Output Current Drift vs. Time DC Output Impedance DC PSRR REFERENCE INPUT/OUTPUT Reference Input2 Reference Input Voltage DC Input Impedance Reference Output Output Voltage Reference TC2 Test Conditions/Comments 1000 ppm FSR ppm FSR Ω 1 MΩ µA/V Drift after 1000 hours, ¾ scale output, TJ = 150°C External RSET Internal RSET The dc-to-dc converter has been characterized with a maximum load of 1 kΩ, chosen such that compliance is not exceeded; see Figure 31 and the DC-DC MaxV bits in Table 27 4.95 45 5 150 5.05 V MΩ For specified performance 4.995 −10 5 ±5 5.005 +10 V ppm/°C TA = 25°C Rev. E | Page 5 of 45 AD5737 Parameter1 Output Noise (0.1 Hz to 10 Hz)2 Noise Spectral Density2 Output Voltage Drift vs. Time2 Capacitive Load2 Load Current Short-Circuit Current Line Regulation2 Load Regulation2 Thermal Hysteresis2 DC-TO-DC CONVERTER Switch Switch On Resistance Switch Leakage Current Peak Current Limit Oscillator Oscillator Frequency Maximum Duty Cycle DIGITAL INPUTS2 Input High Voltage, VIH Input Low Voltage, VIL Input Current Pin Capacitance DIGITAL OUTPUTS2 SDO, ALERT Pins Output Low Voltage, VOL Output High Voltage, VOH High Impedance Leakage Current High Impedance Output Capacitance FAULT Pin Output Low Voltage, VOL Data Sheet Min Typ 7 100 180 1000 9 10 3 95 200 Max 0.425 10 0.8 11.5 13 14.5 0.8 +1 2.6 0.4 +1 2.5 AICC IBOOST5 Power Dissipation 7 9.2 155 V V µA pF V V µA 0.4 V V V 33 5.5 5.5 7.5 11 V V V mA mA 1 1 mA mA mW 3.6 9 2.7 4.5 At 10 kHz Drift after 1000 hours, TJ = 150°C See Figure 42 See Figure 43 See Figure 42 This oscillator is divided down to provide the dc-to-dc converter switching frequency At 410 kHz dc-to-dc switching frequency JEDEC compliant Per pin Per pin Sinking 200 µA Sourcing 200 µA pF 0.6 Output High Voltage, VOH POWER REQUIREMENTS AVDD DVDD AVCC AIDD DICC MHz % 2 DVDD − 0.5 −1 Test Conditions/Comments Ω nA A 89.6 −1 Unit µV p-p nV/√Hz ppm nF mA mA ppm/V ppm/mA ppm 10 kΩ pull-up resistor to DVDD At 2.5 mA 10 kΩ pull-up resistor to DVDD VIH = DVDD, VIL = DGND, internal oscillator running, over supplies Outputs unloaded, over supplies Per channel, 0 mA output AVDD = 15 V, DVDD = 5 V, dc-to-dc converter enabled, outputs disabled Temperature range: −40°C to +105°C; typical at +25°C. Guaranteed by design and characterization; not production tested. For current outputs with internal RSET, the offset, full-scale, and TUE measurements exclude dc crosstalk. The measurements are made with all four channels enabled and loaded with the same code. 4 See the Current Output Mode with Internal RSET section for more information about dc crosstalk. 5 Efficiency plots in Figure 33 through Figure 36 include the IBOOST quiescent current. 1 2 3 Rev. E | Page 6 of 45 Data Sheet AD5737 AC PERFORMANCE CHARACTERISTICS AVDD = VBOOST_x = 15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = GNDSWx = 0 V; REFIN = 5 V; RL = 300 Ω; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter1 DYNAMIC PERFORMANCE, CURRENT OUTPUT Output Current Settling Time Min Max 15 See Test Conditions/Comments Output Noise (0.1 Hz to 10 Hz Bandwidth) Output Noise Spectral Density 1 Typ Unit Test Conditions/Comments µs ms To 0.1% FSR, 0 mA to 24 mA range For settling times when using the dc-to-dc converter, see Figure 26, Figure 27, and Figure 28 12-bit LSB, 0 mA to 24 mA range 0.15 LSB p-p 0.5 nA/√Hz Measured at 10 kHz, midscale output, 0 mA to 24 mA range Guaranteed by design and characterization; not production tested. TIMING CHARACTERISTICS AVDD = VBOOST_x = 15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = GNDSWx = 0 V; REFIN = 5 V; RL = 300 Ω; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter1, 2, 3 t1 t2 t3 t4 t5 t6 t7 t8 t9 Limit at TMIN, TMAX 33 13 13 13 13 198 5 5 5 20 Unit ns min ns min ns min ns min ns min ns min µs min ns min ns min µs min t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 5 10 500 See Table 2 10 5 40 5 500 800 20 µs min ns min ns max µs max ns min µs max ns max µs min ns min ns min µs min 5 µs min 1 2 3 Description SCLK cycle time SCLK high time SCLK low time SYNC falling edge to SCLK falling edge setup time 24th/32nd SCLK falling edge to SYNC rising edge (see Figure 54) SYNC high time following a configuration write SYNC high time following a DAC update write Data setup time Data hold time SYNC rising edge to LDAC falling edge (applies to any channel with digital slew rate control enabled; single DAC updated) SYNC rising edge to LDAC falling edge (single DAC updated) LDAC pulse width low LDAC falling edge to DAC output response time DAC output settling time CLEAR high time CLEAR activation time SCLK rising edge to SDO valid SYNC rising edge to DAC output response time (LDAC = 0) (single DAC updated) LDAC falling edge to SYNC rising edge RESET pulse width SYNC rising edge to next SYNC low (falling edge (digital slew rate control enabled; single DAC updated) SYNC rising edge to next SYNC low (falling edge (digital slew rate control disabled; single DAC updated) Guaranteed by design and characterization; not production tested. All input signals are specified with tRISE = tFALL = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.2 V. See Figure 3, Figure 4, Figure 5, and Figure 7. Rev. E | Page 7 of 45 AD5737 Data Sheet Timing Diagrams t1 SCLK 1 2 24 t3 t6 t2 t4 t5 SYNC t8 t7 SDIN t19 LSB MSB t10 t10 t9 LDAC t17 t12 t11 IOUT_x LDAC = 0 t12 t16 IOUT_x t13 CLEAR t14 IOUT_x 10067-002 t18 RESET Figure 3. Serial Interface Timing Diagram SCLK 1 1 24 24 t6 SYNC MSB LSB MSB LSB INPUT WORD SPECIFIES REGISTER TO BE READ NOP CONDITION MSB SDO LSB UNDEFINED t15 SELECTED REGISTER DATA CLOCKED OUT1 1IF FIRST SCLK IS NEGATIVE EDGE WITHIN SYNC FRAME OF NOP CONDITION, 7 DONT CARE BITS + 16 DATA BITS CLOCKED OUT (TOTAL 23 BITS). IF FIRST SCLK IS POSITIVE EDGE WITHIN SYNC FRAME OF NOP CONDITION, 8 DONT CARE BITS + 16 DATA BITS CLOCKED OUT (TOTAL 24 BITS). SEE THE READBACK OPERATION SECTION FOR FURTHER INFORMATION. Figure 4. Readback Timing Diagram (Packet Error Checking Disabled) Rev. E | Page 8 of 45 10067-003 SDIN Data Sheet SCLK AD5737 1 24 1 32 24 32 t62 SYNC SDIN MSB LSB CRC7 INPUT WORD SPECIFIES REGISTER TO BE READ CRC0 MSB LSB CRC7 8-BIT CRC NOP CONDITION 8-BIT CRC CRC0 MSB SDO LSB 8-BIT CRC t15 UNDEFINED SELECTED REGISTER DATA CLOCKED OUT1 FIRST SCLK IS NEGATIVE EDGE WITHIN SYNC FRAME OF NOP CONDITION, 7 DONT CARE BITS + 16 DATA BITS CLOCKED OUT + 8 CRC BITS (TOTAL 31 BITS). IF FIRST SCLK IS POSITIVE EDGE WITHIN SYNC FRAME OF NOP CONDITION, 8 DONT CARE BITS + 16 DATA BITS CLOCKED OUT + 8 CRC BITS (TOTAL 32 BITS). 2 AVOID SCLK ACTIVITY DURING t AS IT MAY RESULT IN A PEC ERROR ON READBACK. 6 SEE THE READBACK OPERATION AND PACKET ERROR CHECKING SECTIONS FOR FURTHER INFORMATION. Figure 5. Readback Timing Diagram (Packet Error Checking Enabled) LSB 1 MSB 24 2 SCLK SDO R/W DUT_ AD1 DUT_ AD0 SDO DISABLED X X X D15 D14 D1 D0 SDO_ ENAB STATUS STATUS STATUS STATUS Figure 6. Status Readback During a Write 200µA TO OUTPUT PIN IOL VOH (MIN) OR VOL (MAX) CL 50pF 200µA IOH Figure 7. Load Circuit for SDO Timing Diagrams Rev. E | Page 9 of 45 10067-005 SDIN 10067-104 SYNC 10067-004 1IF AD5737 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up. Table 4. Parameter AVDD, VBOOST_x to AGND, DGND AVCC to AGND DVDD to DGND Digital Inputs to DGND Digital Outputs to DGND REFIN, REFOUT to AGND IOUT_x to AGND SWx to AGND AGND, GNDSWx to DGND Operating Temperature Range (TA) Industrial1 Storage Temperature Range Junction Temperature (TJ max) Power Dissipation Lead Temperature Soldering 1 Rating −0.3 V to +33 V −0.3 V to +7 V −0.3 V to +7 V −0.3 V to DVDD + 0.3 V or +7 V (whichever is less) −0.3 V to DVDD + 0.3 V or +7 V (whichever is less) −0.3 V to AVDD + 0.3 V or +7 V (whichever is less) AGND to VBOOST_x or 33 V if using the dc-to-dc converter −0.3 V to +33 V −0.3 V to +0.3 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE Junction-to-air thermal resistance (θJA) is specified for a JEDEC 4-layer test board. Table 5. Thermal Resistance Package Type 64-Lead LFCSP (CP-64-3) ESD CAUTION −40°C to +105°C −65°C to +150°C 125°C (TJ max − TA)/θJA JEDEC industry standard J-STD-020 Power dissipated on chip must be derated to keep the junction temperature below 125°C. Rev. E | Page 10 of 45 θJA 28 Unit °C/W Data Sheet AD5737 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RSET_C RSET_D REFOUT REFIN NC CHARTD IGATED COMPDCDC_D VBOOST_D NC IOUT_D AGND NC CHARTC NC IGATEC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AD5737 TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 COMPDCDC_C IOUT_C VBOOST_C AV CC SWC GNDSWC GNDSWD SWD AGND SWA GNDSWA GNDSWB SWB AGND VBOOST_B IOUT_B NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED PADDLE SHOULD BE CONNECTED TO AGND, OR, ALTERNATIVELY, IT CAN BE LEFT ELECTRICALLY UNCONNECTED. IT IS RECOMMENDED THAT THE PADDLE BE THERMALLY CONNECTED TO A COPPER PLANE FOR ENHANCED THERMAL PERFORMANCE. 10067-006 DGND RESET AV DD NC CHARTA IGATEA COMPDCDC_A VBOOST_A NC IOUT_A AGND NC CHARTB NC IGATEB COMPDCDC_B 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 RSET_B RSET_A REFGND REFGND AD0 AD1 SYNC SCLK SDIN SDO DVDD DGND LDAC CLEAR ALERT FAULT Figure 8. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1 Mnemonic RSET_B 2 RSET_A 3 4 5 6 REFGND REFGND AD0 AD1 7 SYNC 8 SCLK 9 10 11 12 13 SDIN SDO DVDD DGND LDAC Description An external, precision, low drift, 15 kΩ current setting resistor can be connected to this pin to improve the IOUT_B temperature drift performance. For more information, see the External Current Setting Resistor section. An external, precision, low drift, 15 kΩ current setting resistor can be connected to this pin to improve the IOUT_A temperature drift performance. For more information, see the External Current Setting Resistor section. Ground Reference Point for Internal Reference. Ground Reference Point for Internal Reference. Address Decode for the Device Under Test (DUT) on the Board. Address Decode for the DUT on the Board. It is not recommended to tie both AD1 and AD0 low when using PEC (see the Packet Error Checking section). Frame Synchronization Signal for the Serial Interface. Active low input. When SYNC is low, data is clocked into the input shift register on the falling edge of SCLK. Serial Clock Input. Data is clocked into the input shift register on the falling edge of SCLK. The serial interface operates at clock speeds of up to 30 MHz. Serial Data Input. Data must be valid on the falling edge of SCLK. Serial Data Output. Used to clock data from the serial register in readback mode (see Figure 4 and Figure 5). Digital Supply Pin. The voltage range is from 2.7 V to 5.5 V. Digital Ground. Load DAC. This active low input is used to update the DAC register and, consequently, the DAC outputs. When LDAC is tied permanently low, the addressed DAC data register is updated on the rising edge of SYNC. If LDAC is held high during the write cycle, the DAC input register is updated, but the DAC output is updated only on the falling edge of LDAC (see Figure 3). Using this mode, all analog outputs can be updated simultaneously. Do not leave the LDAC pin unconnected. Rev. E | Page 11 of 45 AD5737 Data Sheet Pin No. 14 Mnemonic CLEAR 15 ALERT 16 FAULT 17 18 19 20 21 22 DGND RESET AVDD NC CHARTA IGATEA 23 COMPDCDC_A 24 VBOOST_A 25 26 27 28 29 30 31 NC IOUT_A AGND NC CHARTB NC IGATEB 32 COMPDCDC_B 33 34 IOUT_B VBOOST_B 35 36 AGND SWB 37 38 39 GNDSWB GNDSWA SWA 40 41 AGND SWD 42 43 44 GNDSWD GNDSWC SWC 45 46 AVCC VBOOST_C 47 48 IOUT_C COMPDCDC_C Description Active High, Edge Sensitive Input. When this pin is asserted, the output current is set to the programmed clear code bit setting. Only channels enabled to be cleared are cleared. For more information, see the Asynchronous Clear section. When CLEAR is active, the DAC output register cannot be written to. Active High Output. This pin is asserted when there is no SPI activity on the interface pins for a preset time. For more information, see the Alert Output section. Active Low, Open-Drain Output. This pin is asserted low when any of the following conditions is detected: open circuit, PEC error, or an overtemperature condition (see the Fault Output section). Digital Ground. Hardware Reset, Active Low Input. Positive Analog Supply Pin. The voltage range is from 9 V to 33 V. No Connect. Do not connect to this pin. HART Input Connection for DAC Channel A. For more information, see the HART Connectivity section. Optional Connection for External Pass Transistor. Leave this pin unconnected when using the dc-to-dc converter. For more information, see the External PMOS Mode section. DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the feedback loop of the Channel A dc-to-dc converter. Alternatively, if using an external compensation resistor, place a resistor in series with a capacitor to ground from this pin. For more information, see the DC-to-DC Converter Compensation Capacitors section and the AICC Supply Requirements—Slewing section. Supply for Channel A Current Output Stage (see Figure 49). To use the dc-to-dc converter, connect this pin as shown in Figure 56. No Connect. Do not connect to this pin. Current Output Pin for DAC Channel A. Ground Reference Point for Analog Circuitry. This pin must be connected to 0 V. No Connect. Do not connect to this pin. HART Input Connection for DAC Channel B. For more information, see the HART Connectivity section. No Connect. Do not connect to this pin. Optional Connection for External Pass Transistor. Leave this pin unconnected when using the dc-to-dc converter. For more information, see the External PMOS Mode section. DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the feedback loop of the Channel B dc-to-dc converter. Alternatively, if using an external compensation resistor, place a resistor in series with a capacitor to ground from this pin. For more information, see the DC-to-DC Converter Compensation Capacitors section and the AICC Supply Requirements—Slewing section. Current Output Pin for DAC Channel B. Supply for Channel B Current Output Stage (see Figure 49). To use the dc-to-dc converter, connect this pin as shown in Figure 56. Ground Reference Point for Analog Circuitry. This pin must be connected to 0 V. Switching Output for Channel B DC-to-DC Circuitry. To use the dc-to-dc converter, connect this pin as shown in Figure 56. Ground Connection for DC-to-DC Switching Circuit. This pin must always be connected to ground. Ground Connection for DC-to-DC Switching Circuit. This pin must always be connected to ground. Switching Output for Channel A DC-to-DC Circuitry. To use the dc-to-dc converter, connect this pin as shown in Figure 56. Ground Reference Point for Analog Circuitry. This pin must be connected to 0 V. Switching Output for Channel D DC-to-DC Circuitry. To use the dc-to-dc converter, connect this pin as shown in Figure 56. Ground Connection for DC-to-DC Switching Circuit. This pin must always be connected to ground. Ground Connection for DC-to-DC Switching Circuit. This pin must always be connected to ground. Switching Output for Channel C DC-to-DC Circuitry. To use the dc-to-dc converter, connect this pin as shown in Figure 56. Supply for DC-to-DC Circuitry. The voltage range is from 4.5 V to 5.5 V. Supply for Channel C Current Output Stage (see Figure 49). To use the dc-to-dc converter, connect this pin as shown in Figure 56. Current Output Pin for DAC Channel C. DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the feedback loop of the Channel C dc-to-dc converter. Alternatively, if using an external compensation resistor, place a resistor in series with a capacitor to ground from this pin. For more information, see the DC-to-DC Converter Compensation Capacitors section and the AICC Supply Requirements—Slewing section. Rev. E | Page 12 of 45 Data Sheet Pin No. 49 Mnemonic IGATEC 50 51 52 53 54 55 56 NC CHARTC NC AGND IOUT_D NC VBOOST_D 57 COMPDCDC_D 58 IGATED 59 60 61 62 CHARTD NC REFIN REFOUT 63 RSET_D 64 RSET_C EPAD AD5737 Description Optional Connection for External Pass Transistor. Leave this pin unconnected when using the dc-to-dc converter. For more information, see the External PMOS Mode section. No Connect. Do not connect to this pin. HART Input Connection for DAC Channel C. For more information, see the HART Connectivity section. No Connect. Do not connect to this pin. Ground Reference Point for Analog Circuitry. This pin must be connected to 0 V. Current Output Pin for DAC Channel D. No Connect. Do not connect to this pin. Supply for Channel D Current Output Stage (see Figure 49). To use the dc-to-dc converter, connect this pin as shown in Figure 56. DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the feedback loop of the Channel D dc-to-dc converter. Alternatively, if using an external compensation resistor, place a resistor in series with a capacitor to ground from this pin. For more information, see the DC-to-DC Converter Compensation Capacitors section and the AICC Supply Requirements—Slewing section. Optional Connection for External Pass Transistor. Leave this pin unconnected when using the dc-to-dc converter. For more information, see the External PMOS Mode section. HART Input Connection for DAC Channel D. For more information, see the HART Connectivity section. No Connect. Do not connect to this pin. External Reference Voltage Input. Internal Reference Voltage Output. It is recommended that a 0.1 µF capacitor be placed between REFOUT and REFGND. REFOUT must be connected to REFIN to use the internal reference. An external, precision, low drift, 15 kΩ current setting resistor can be connected to this pin to improve the IOUT_D temperature drift performance. For more information, see the External Current Setting Resistor section. An external, precision, low drift, 15 kΩ current setting resistor can be connected to this pin to improve the IOUT_C temperature drift performance. For more information, see the External Current Setting Resistor section. Exposed Pad. The exposed paddle must be connected to AGND, or, alternatively, it can be left electrically unconnected. It is recommended that the paddle be thermally connected to a copper plane for enhanced thermal performance. Rev. E | Page 13 of 45 AD5737 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS CURRENT OUTPUTS 0.008 0.008 4mA TO 20mA, INTERNAL RSET, WITH DC-TO-DC CONVERTER 4mA TO 20mA, EXTERNAL RSET, WITH DC-TO-DC CONVERTER 4mA TO 20mA, INTERNAL RSET 4mA TO 20mA, EXTERNAL RSET 0.006 0.006 0.004 INL ERROR (%FSR) 0.002 0 –0.002 0.002 0 –0.002 4mA TO 20mA RANGE MAX INL 0mA TO 24mA RANGE MAX INL 0mA TO 20mA RANGE MAX INL 4mA TO 20mA RANGE MIN INL 0mA TO 24mA RANGE MIN INL 0mA TO 20mA RANGE MIN INL AVDD = 15V –0.004 AVDD = 15V TA = 25°C –0.006 –0.006 0 1000 2000 3000 4000 CODE –0.008 –40 10067-231 –0.004 –20 0 20 40 60 80 10067-234 INL ERROR (%FSR) 0.004 100 TEMPERATURE (°C) Figure 9. Integral Nonlinearity Error vs. DAC Code Figure 12. Integral Nonlinearity Error vs. Temperature, Internal RSET 0.008 1.0 4mA TO 20mA, INTERNAL RSET, WITH DC-TO-DC CONVERTER 4mA TO 20mA, EXTERNAL RSET, WITH DC-TO-DC CONVERTER 4mA TO 20mA, INTERNAL RSET 4mA TO 20mA, EXTERNAL RSET 0.8 0.6 0.006 INL ERROR (%FSR) 0.2 0 –0.2 –0.4 3000 4000 CODE –0.008 –40 DNL ERROR (LSB) 0.4 0.02 AVDD = 15V TA = 25°C 0 MIN DNL –0.6 –0.04 CODE AVDD = 15V ALL RANGES INTERNAL AND EXTERNAL RSET –0.8 4mA TO 20mA, EXTERNAL RSET 4mA TO 20mA, EXTERNAL RSET, WITH DC-TO-DC CONVERTER 3000 MAX DNL 0 –0.02 2000 100 –0.2 –0.4 1000 80 0.2 –0.01 4000 10067-233 TOTAL UNADJUSTED ERROR (%FSR) 0.03 0 60 0.8 0.6 –0.03 40 1.0 0.04 0.01 20 Figure 13. Integral Nonlinearity Error vs. Temperature, External RSET 4mA TO 20mA, INTERNAL RSET 4mA TO 20mA, INTERNAL RSET, WITH DC-TO-DC CONVERTER 0.05 0 TEMPERATURE (°C) Figure 10. Differential Nonlinearity Error vs. DAC Code 0.06 –20 10067-235 2000 10067-232 –1.0 1000 –0.002 AVDD = 15V –0.006 –0.8 0 0 4mA TO 20mA RANGE MAX INL 0mA TO 24mA RANGE MAX INL 0mA TO 20mA RANGE MAX INL 4mA TO 20mA RANGE MIN INL 0mA TO 24mA RANGE MIN INL 0mA TO 20mA RANGE MIN INL –0.004 AVDD = 15V TA = 25°C –0.6 0.002 Figure 11. Total Unadjusted Error vs. DAC Code –1.0 –40 –20 0 20 40 60 80 100 TEMPERATURE (°C) Figure 14. Differential Nonlinearity Error vs. Temperature Rev. E | Page 14 of 45 10067-236 DNL ERROR (LSB) 0.004 0.4 Data Sheet AD5737 0.025 0.008 MAX INL 0.006 0.015 0.005 0 –0.005 AV DD = 15V –0.010 0.004 INL ERROR (%FSR) 0.010 4mA TO 20mA RANGE TA = 25°C 0.002 0 –0.002 –0.015 –0.004 –0.025 –40 –20 0 60 20 40 TEMPERATURE (°C) 80 100 –0.006 MIN INL 5 10 15 20 25 30 SUPPLY (V) Figure 15. Total Unadjusted Error vs. Temperature 10067-240 4mA TO 20mA RANGE, INTERNAL R SET 4mA TO 20mA RANGE, EXTERNAL R SET –0.020 10067-155 TOTAL UNADJUSTED ERROR (%FSR) 0.020 Figure 18. Integral Nonlinearity Error vs. Supply, External RSET 0.020 0.008 MAX INL 0.006 0.010 0 –0.005 –0.004 –0.020 –20 0 60 20 40 TEMPERATURE (°C) 80 100 –0.006 10 15 20 25 30 Figure 19. Integral Nonlinearity Error vs. Supply, Internal RSET 0.005 1.0 ALL RANGES TA = 25°C 0.8 0 DNL ERROR (LSB) 0.6 –0.005 –0.010 –0.015 0.4 MAX DNL 0.2 0 MIN DNL –0.2 –0.4 AV DD = 15V –0.6 –0.020 4mA TO 20mA RANGE, INTERNAL R SET 4mA TO 20mA RANGE, EXTERNAL R SET –20 0 60 20 40 TEMPERATURE (°C) 80 –0.8 100 10067-159 GAIN ERROR (%FSR) 5 SUPPLY (V) Figure 16. Full-Scale Error vs. Temperature –0.025 –40 MIN INL Figure 17. Gain Error vs. Temperature –1.0 5 10 15 20 25 30 SUPPLY (V) Figure 20. Differential Nonlinearity Error vs. Supply Rev. E | Page 15 of 45 10067-242 –40 0 10067-241 4mA TO 20mA RANGE, INTERNAL R SET 4mA TO 20mA RANGE, EXTERNAL R SET –0.015 4mA TO 20mA RANGE TA = 25°C 0.002 –0.002 AV DD = 15V –0.010 0.004 INL ERROR (%FSR) 0.005 10067-157 FULL-SCALE ERROR (%FSR) 0.015 AD5737 Data Sheet 6 AV DD = 15V TA = 25°C RLOAD = 300Ω MAX TUE 0 5 –0.005 4 CURRENT (µA) 4mA TO 20mA RANGE TA = 25°C –0.010 –0.015 –0.020 3 2 MIN TUE –0.025 1 –0.035 5 10 15 20 25 30 SUPPLY (V) 0 0 5 Figure 21. Total Unadjusted Error vs. Supply, External RSET 20 4 0.06 MAX TUE 2 0.05 0 4mA TO 20mA RANGE TA = 25°C 0.02 0.01 –2 –4 –6 0 –8 –0.01 –0.02 5 10 15 20 25 30 SUPPLY (V) –10 0 0.002 0 –0.002 TA = 25°C EXTERNAL PMOS (NTLJS4149) 4mA TO 20mA RANGE RLOAD = 300Ω –0.006 –0.008 10 15 20 25 30 VBOOST_x SUPPLY (V) 10067-188 MIN TUE –0.010 OUTPUT CURRENT (mA) AND VBOOST_x VOLTAGE (V) MAX TUE –0.004 2 3 4 5 6 Figure 25. Current vs. Time on Output Enable 0.006 0.004 1 TIME (µs) Figure 22. Total Unadjusted Error vs. Supply, Internal RSET –0.012 AV DD = 15V TA = 25°C RLOAD = 300Ω INT_ENABLE = 1 MIN TUE Figure 23. Total Unadjusted Error vs. VBOOST_x Supply Using External PMOS Mode 30 25 20 IOUT_x VBOOST_x 15 10 0mA TO 24mA RANGE 1kΩ LOAD fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) AV CC = 5V TA = 25°C 5 0 –0.50 –0.25 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 TIME (ms) Figure 26. Output Current and VBOOST_x Settling Time with DC-to-DC Converter (See Figure 56) Rev. E | Page 16 of 45 10067-167 0.03 10067-063 CURRENT (µA) 0.04 10067-061 TOTAL UNADJUSTED ERROR (%FSR) 15 Figure 24. Current vs. Time on Power-Up 0.07 TOTAL UNADJUSTED ERROR (%FSR) 10 TIME (µs) 10067-062 –0.030 10067-060 TOTAL UNADJUSTED ERROR (%FSR) 0.005 Data Sheet AD5737 10 30 20mA OUTPUT 10mA OUTPUT 8 TA = –40°C TA = +25°C TA = +105°C 15 10 0mA TO 24mA RANGE 1kΩ LOAD fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) AV CC = 5V 5 0 0.25 0.75 0.50 1.00 1.25 1.50 4 2 0 –2 –4 –6 AV CC = 5V fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) –8 1.75 –10 TIME (ms) 0 2 4 6 0mA TO 24mA RANGE 1kΩ LOAD fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) TA = 25°C HEADROOM VOLTAGE (V) 25 20 AV CC = 4.5V AV CC = 5.0V AV CC = 5.5V 10 0mA TO 24mA RANGE 1kΩ LOAD fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) TA = 25°C 5 0 0.25 0.50 0.75 1.00 1.25 1.50 6 5 4 3 2 1 1.75 0 TIME (ms) 0 5 10 15 20 OUTPUT CURRENT (mA) Figure 28. Output Current Settling Time with DC-to-DC Converter over AVCC (See Figure 56) 10067-067 15 10067-169 OUTPUT CURRENT (mA) 14 8 7 Figure 31. DC-to-DC Converter Headroom vs. Output Current (See Figure 56) 25 0 IOUT (4mA TO 20mA STEP) –20 15 IOUT_x PSRR (dB) 20 TA = 25°C EXTERNAL PMOS (NTLJS4149) 4mA TO 20mA RANGE RLOAD = 300Ω VBOOST_x = 24V 10 AVDD = 15V VBOOST_x = 15V TA = 25°C –40 –60 –80 IOUT (20mA TO 4mA STEP) 5 –100 0 5 10 TIME (µs) 15 20 –120 10 10067-189 OUTPUT CURRENT (mA) 12 Figure 30. Output Current, AC-Coupled vs. Time with DC-to-DC Converter (See Figure 56) 30 0 –5 10 TIME (µs) Figure 27. Output Current Settling Time with DC-to-DC Converter over Temperature (See Figure 56) 0 –0.25 8 0mA TO 24mA RANGE 1kΩ LOAD EXTERNA L RSET TA = 25°C 100 1k 10k 100k FREQUENCY (Hz) Figure 29. Output Current Settling Time with External PMOS Transistor Rev. E | Page 17 of 45 Figure 32. IOUT_x PSRR vs. Frequency 1M 10M 10067-068 0 –0.25 6 10067-170 CURRENT (AC-COUPLED) (µA) 20 10067-168 OUTPUT CURRENT (mA) 25 AD5737 Data Sheet DC-TO-DC CONVERTER 100 100 AVCC = 4.5V AVCC = 5.0V AVCC = 5.5V 90 90 80 70 60 50 40 30 0mA TO 24mA RANGE 1kΩ LOAD EXTERNAL RSET fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) TA = 25°C 10 0 0 0.010 0.005 0.025 0.020 0.015 OUTPUT CURRENT (A) 20mA 60 50 40 30 0mA TO 24mA RANGE 1kΩ LOAD EXTERNAL RSET AVCC = 5V fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) 20 10 0 –40 10067-055 20 70 –20 20 0 40 60 80 100 120 140 TEMPERATURE (°C) Figure 33. Efficiency at VBOOST_x vs. Output Current (See Figure 56) Figure 36. Output Efficiency vs. Temperature (See Figure 56) 100 0.6 10067-258 OUTPUT EFFICIENCY (%) VBOOST EFFICIENCY (%) 80 90 SWITCH RESISTANCE (Ω) 70 60 50 40 0mA TO 24mA RANGE 1kΩ LOAD EXTERNAL RSET AVCC = 5V fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) 20 10 0 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) AVCC = 4.5V AVCC = 5.0V AVCC = 5.5V 70 60 50 40 0mA TO 24mA RANGE 1kΩ LOAD EXTERNAL RSET fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) TA = 25°C 10 0 0 0.005 0.010 0.015 0.020 0.025 OUTPUT CURRENT (A) 10067-257 OUTPUT EFFICIENCY (%) 80 20 0.2 0 –40 –20 0 20 40 60 80 TEMPERATURE (°C) Figure 37. Switch Resistance vs. Temperature 100 30 0.3 0.1 Figure 34. Efficiency at VBOOST_x vs. Temperature (See Figure 56) 90 0.4 Figure 35. Output Efficiency vs. Output Current (See Figure 56) Rev. E | Page 18 of 45 100 10067-123 30 10067-256 VBOOST EFFICIENCY (%) 0.5 20mA 80 Data Sheet AD5737 REFERENCE 5.0050 16 AV DD REFOUT TA = 25°C 12 8 6 4 2 0 5.0035 5.0030 5.0025 5.0020 5.0015 5.0010 0.2 0.4 0.6 0.8 1.0 1.2 TIME (ms) 5.0000 –40 10067-010 0 Figure 38. REFOUT Voltage Turn-On Transient –20 40 20 0 100 80 60 TEMPERATURE (°C) 10067-163 5.0005 –2 Figure 41. REFOUT Voltage vs. Temperature (When the AD5737 is soldered onto a PCB, the reference shifts due to thermal shock on the package. The average output voltage shift is −4 mV. Measurement of these parts after seven days shows that the outputs typically shift back 2 mV toward their initial values. This second shift is due to the relaxation of stress incurred during soldering.) 5.002 3 REFERENCE OUTPUT VOLTAGE (V) AV DD = 15V TA = 25°C 2 1 0 –1 –3 0 2 4 6 8 10 TIME (s) 5.000 4.999 4.998 4.997 4.996 4.995 10067-011 –2 AV DD = 15V TA = 25°C 5.001 0 2 4 6 8 10 LOAD CURRENT (mA) 10067-014 4 VOLTAGE (µV) 5.0040 Figure 42. REFOUT Voltage vs. Load Current Figure 39. REFOUT Output Noise (0.1 Hz to 10 Hz Bandwidth) 5.00000 150 REFERENCE OUTPUT VOLTAGE (V) AV DD = 15V TA = 25°C 100 50 0 –50 –150 0 5 10 15 TIME (ms) 20 10067-012 –100 4.99995 TA = 25°C 4.99990 4.99985 4.99980 4.99975 4.99970 4.99965 4.99960 10 15 20 25 AV DD (V) Figure 43. REFOUT Voltage vs. AVDD Figure 40. REFOUT Output Noise (100 kHz Bandwidth) Rev. E | Page 19 of 45 30 10067-015 VOLTAGE (V) 10 VOLTAGE (µV) 30 DEVICES SHOWN AV DD = 15V 5.0045 REFERENCE OUTPUT VOLTAGE (V) 14 AD5737 Data Sheet GENERAL 450 13.4 DVDD = 5V TA = 25°C 400 13.3 350 FREQUENCY (MHz) 13.2 250 200 150 13.0 12.9 12.8 12.7 50 0 1 2 3 4 5 SDIN VOLTAGE (V) 12.6 –40 10067-007 0 –20 0 20 40 60 80 100 TEMPERATURE (°C) Figure 44. DICC vs. Logic Input Voltage Figure 46. Internal Oscillator Frequency vs. Temperature 8 14.4 7 14.2 6 FREQUENCY (MHz) 14.0 5 4 3 13.8 13.6 13.4 2 AIDD TA = 25°C IOUT = 0mA 15 20 25 30 VOLTAGE (V) 13.2 TA = 25°C 10067-009 1 0 10 DVDD = 5.5V 10067-020 100 CURRENT (mA) 13.1 Figure 45. Supply Current (AIDD) vs. Supply Voltage (AVDD) 13.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VOLTAGE (V) Figure 47. Internal Oscillator Frequency vs. DVDD Supply Voltage Rev. E | Page 20 of 45 10067-021 DICC (µA) 300 Data Sheet AD5737 TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) Relative accuracy, or integral nonlinearity (INL), is a measure of the maximum deviation from the best fit line through the DAC transfer function. INL is expressed in percent of full-scale range (% FSR). A typical INL vs. code plot is shown in Figure 9. Differential Nonlinearity (DNL) Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified DNL of ±1 LSB maximum ensures monotonicity. The AD5737 is guaranteed monotonic by design. A typical DNL vs. code plot is shown in Figure 10. Monotonicity A DAC is monotonic if the output either increases or remains constant for increasing digital input code. The AD5737 is monotonic over its full operating temperature range. Offset Error Offset error is the deviation of the analog output from the ideal zero-scale output when all DAC registers are loaded with 0x0000. It is expressed in % FSR. Offset Error Drift or Offset TC Offset error drift, or offset TC, is a measure of the change in offset error with changes in temperature and is expressed in ppm FSR/°C. Current Loop Compliance Voltage The current loop compliance voltage is the maximum voltage at the IOUT_x pin for which the output current is equal to the programmed value. Voltage Reference Thermal Hysteresis Voltage reference thermal hysteresis is the difference in output voltage measured at +25°C compared to the output voltage measured at +25°C after cycling the temperature from +25°C to −40°C to +105°C and back to +25°C. The hysteresis is expressed in ppm. Power-On Glitch Energy Power-on glitch energy is the impulse injected into the analog output when the AD5737 is powered on. It is specified as the area of the glitch in nV-sec (see Figure 24). Power Supply Rejection Ratio (PSRR) PSRR indicates how the output of the DAC is affected by changes in the power supply voltage. Reference Temperature Coefficient (TC) Reference TC is a measure of the change in the reference output voltage with changes in temperature. It is expressed in ppm/°C. Line Regulation Line regulation is the change in the reference output voltage due to a specified change in supply voltage. It is expressed in ppm/V. Gain Error Gain error is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer function from the ideal, expressed in % FSR. Gain Temperature Coefficient (TC) Gain TC is a measure of the change in gain error with changes in temperature and is expressed in ppm FSR/°C. Full-Scale Error Full-scale error is a measure of the output error when full-scale code is loaded to the DAC register. Ideally, the output is fullscale − 1 LSB. Full-scale error is expressed in % FSR. Full-Scale Temperature Coefficient (TC) Full-scale TC is a measure of the change in full-scale error with changes in temperature and is expressed in ppm FSR/°C. Total Unadjusted Error (TUE) Total unadjusted error (TUE) is a measure of the output error that includes all the error measurements: INL error, offset error, gain error, temperature, and time. TUE is expressed in % FSR. DC Crosstalk DC crosstalk is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC while monitoring another DAC, which is at midscale. Load Regulation Load regulation is the change in the reference output voltage due to a specified change in load current. It is expressed in ppm/mA. DC-to-DC Converter Headroom DC-to-DC converter headroom is the difference between the voltage required at the current output and the voltage supplied by the dc-to-dc converter (see Figure 31). Output Efficiency Output efficiency is defined as the ratio of the power delivered to a channel’s load and the power delivered to the channel’s dc-to-dc input. The VBOOST_x quiescent current is considered part of the dc-to-dc converter’s losses. I OUT 2 × R LOAD AVCC × AI CC Efficiency at VBOOST_x The efficiency at VBOOST_x is defined as the ratio of the power delivered to a channel’s VBOOST_x supply and the power delivered to the channel’s dc-to-dc input. The VBOOST_x quiescent current is considered part of the dc-to-dc converter’s losses. Rev. E | Page 21 of 45 I OUT × V BOOST _ x AVCC × AI CC AD5737 Data Sheet THEORY OF OPERATION The AD5737 is a quad, precision digital-to-current loop converter designed to meet the requirements of industrial process control applications. It provides a high precision, fully integrated, low cost, single-chip solution for generating current loop outputs. The current ranges available are 0 mA to 20 mA, 4 mA to 20 mA, and 0 mA to 24 mA. The output configuration is user-selectable via the DAC control register. On-chip dynamic power control minimizes package power dissipation (see the Dynamic Power Control section). DAC ARCHITECTURE The DAC core architecture of the AD5737 consists of two matched DAC sections. A simplified circuit diagram is shown in Figure 48. The four MSBs of the 12-bit data-word are decoded to drive 15 switches, E1 to E15. Each switch connects one of 15 matched resistors either to ground or to the reference buffer output. The remaining eight bits of the data-word drive Switch S0 to Switch S7 of an 8-bit voltage mode R-2R ladder network. VOUT 2R 2R 2R 2R 2R 2R 2R S0 S1 S7 E1 E2 E15 POWER-ON STATE OF THE AD5737 When the AD5737 is first powered on, the IOUT_x pins are in tristate mode. After a device power-on or a device reset, it is recommended that the user wait at least 100 µs before writing to the device to allow time for internal calibrations to take place. SERIAL INTERFACE The AD5737 is controlled by a versatile 3-wire serial interface that operates at clock rates of up to 30 MHz and is compatible with SPI, QSPI, MICROWIRE, and DSP standards. Data coding is always straight binary. Input Shift Register The input shift register is 24 bits wide. Data is loaded into the device MSB first as a 24-bit word under the control of the serial clock input, SCLK. Data is clocked in on the falling edge of SCLK. If packet error checking (PEC) is enabled, an additional eight bits must be written to the AD5737, creating a 32-bit serial interface (see the Packet Error Checking section). The DAC outputs can be updated in one of two ways: individual DAC updating or simultaneous updating of all DACs. 8-BIT R-2R LADDER 10067-069 Individual DAC Updating FOUR MSBs DECODED INTO 15 EQUAL SEGMENTS Figure 48. DAC Ladder Structure The voltage output from the DAC core is converted to a current, which is then mirrored to the supply rail so that the application sees only a current source output (see Figure 49). The current outputs are supplied by VBOOST_x. VBOOST_x R2 R3 T2 To update an individual DAC, LDAC is held low while data is clocked into the DAC data register. The addressed DAC output is updated on the rising edge of SYNC. See Table 3 and Figure 3 for timing information. Simultaneous Updating of All DACs To update all DACs simultaneously, LDAC is held high while data is clocked into the DAC data register. After LDAC is taken high, only the first write to the DAC data register of each channel is valid; subsequent writes to the DAC data register are ignored, although these subsequent writes are returned if a readback is initiated. All DAC outputs are updated by taking LDAC low after SYNC is taken high. A2 OUTPUT AMPLIFIERS T1 IOUT_x A1 RSET VREFIN 10067-071 12-BIT DAC LDAC 12-BIT DAC IOUT_x DAC REGISTER Figure 49. Voltage-to-Current Conversion Circuitry DAC INPUT REGISTER Reference Buffers OFFSET AND GAIN CALIBRATION The AD5737 can operate with either an external or internal reference. The reference input requires a 5 V reference for specified performance. This input voltage is then buffered before it is applied to the DAC. SCLK SYNC SDIN INTERFACE LOGIC SDO 10067-072 DAC DATA REGISTER Figure 50. Simplified Serial Interface of the Input Loading Circuitry for One DAC Channel Rev. E | Page 22 of 45 Data Sheet AD5737 TRANSFER FUNCTION For the 4 mA to 20 mA range, For the 0 mA to 20 mA, 0 mA to 24 mA, and 4 mA to 20 mA current output ranges, the output current is expressed by the following equations: For the 0 mA to 20 mA range, 20 mA I OUT = N × D 2 16 mA I OUT = N × D + 4 mA 2 where: D is the decimal equivalent of the code loaded to the DAC. N is the bit resolution of the DAC. For the 0 mA to 24 mA range, 24 mA I OUT = N × D 2 Rev. E | Page 23 of 45 AD5737 Data Sheet REGISTERS Table 7, Table 8, and Table 9 provide an overview of the registers for the AD5737. Table 7. Data Registers for the AD5737 Register DAC Data Registers Gain Registers Offset Registers Clear Code Registers Description The four DAC data registers (one register per DAC channel) are used to write a DAC code to each DAC channel. The DAC data bits are D15 to D4. The four gain registers (one register per DAC channel) are used to program the gain trim on a per-channel basis. The gain data bits are D15 to D4. The four offset registers (one register per DAC channel) are used to program the offset trim on a per-channel basis. The offset data bits are D15 to D4. The four clear code registers (one register per DAC channel) are used to program the clear code on a perchannel basis. The clear code data bits are D15 to D4. Table 8. Control Registers for the AD5737 Register Main Control Register DAC Control Registers Software Register DC-to-DC Control Register Slew Rate Control Registers Description The main control register is used to configure functions for the entire part. These functions include the following: enabling status readback during a write; enabling the output on all four DAC channels simultaneously; power-on of the dc-to-dc converter on all four DAC channels simultaneously; and enabling and configuring the watchdog timer. For more information, see the Main Control Register section. The four DAC control registers (one register per DAC channel) are used to configure the following functions on a per-channel basis: output range (for example, 4 mA to 20 mA); selection of the internal current sense resistor or an external current sense resistor; enabling/disabling the use of a clear code; enabling/disabling the internal circuitry (dc-to-dc converter, DAC, and internal amplifiers); power-on/power-off of the dc-to-dc converter; and enabling/disabling the output channel. The software register is used to perform a reset, to toggle the user bit in the status register, and, as part of the watchdog timer feature, to verify correct data communication operation. The dc-to-dc control register is used to set the control parameters for the dc-to-dc converter: maximum output voltage, phase, and switching frequency. This register is also used to select the internal compensation resistor or an external compensation resistor for the dc-to-dc converter. The four slew rate control registers (one register per DAC channel) are used to program the slew rate of the DAC output. Table 9. Readback Register for the AD5737 Register Status Register Description The status register contains any fault information, as well as a user toggle bit. Rev. E | Page 24 of 45 Data Sheet AD5737 ENABLING THE OUTPUT REPROGRAMMING THE OUTPUT RANGE To correctly write to and set up the part from a power-on condition, use the following sequence: When changing the range of an output, use the same sequence described in the Enabling the Output section. Set the range to 0 V (zero scale or midscale) before the output is disabled. Because the dc-to-dc switching frequency, maximum output voltage, and phase are already selected, there is no need to reprogram these values. Figure 52 provides a flowchart of this sequence. 3. 4. 5. Perform a hardware or software reset after initial power-on. Configure the dc-to-dc converter supply block. Set the dc-to-dc switching frequency, the maximum output voltage allowed, and the dc-to-dc converter phase between channels. Configure the DAC control register on a per-channel basis. Select the output range, and enable the dc-to-dc converter block (DC_DC bit). Other control bits can also be configured. Set the INT_ENABLE bit, but do not set the OUTEN (output enable) bit. Write the required code to the DAC data register. This step implements a full internal DAC calibration. For reduced output glitch, allow at least 200 µs before performing Step 5. Write to the DAC control register again to enable the output (set the OUTEN bit). STEP 1: WRITE TO CHANNEL’S DAC DATA REGISTER. SET THE OUTPUT TO 0V (ZERO OR MIDSCALE). STEP 2: WRITE TO DAC CONTROL REGISTER. DISABLE THE OUTPUT (OUTEN = 0) AND SET THE NEW OUTPUT RANGE. KEEP THE DC_DC BIT AND THE INT_ENABLE BIT SET. STEP 3: WRITE VALUE TO THE DAC DATA REGISTER. Figure 51 provides a flowchart of this sequence. STEP 4: WRITE TO DAC CONTROL REGISTER. RELOAD SEQUENCE AS IN STEP 2. SET THE OUTEN BIT TO ENABLE THE OUTPUT. POWER ON. Figure 52. Programming Sequence to Change the Output Range STEP 1: PERFORM A SOFTWARE/HARDWARE RESET. STEP 2: WRITE TO DC-TO-DC CONTROL REGISTER TO SET DC-TO-DC CLOCK FREQUENCY, PHASE, AND MAXIMUM VOLTAGE. STEP 3: WRITE TO DAC CONTROL REGISTER. SELECT THE DAC CHANNEL AND OUTPUT RANGE. SET THE DC_DC BIT AND OTHER CONTROL BITS AS REQUIRED. SET THE INT_ENABLE BIT BUT DO NOT SET THE OUTEN BIT. 10067-073 STEP 4: WRITE TO ONE OR MORE DAC DATA REGISTERS. ALLOW AT LEAST 200µs BETWEEN STEP 3 AND STEP 5 FOR REDUCED OUTPUT GLITCH. STEP 5: WRITE TO DAC CONTROL REGISTER. RELOAD SEQUENCE AS IN STEP 3. SET THE OUTEN BIT TO ENABLE THE OUTPUT. CHANNEL OUTPUT IS ENABLED. 10067-074 1. 2. Figure 51. Programming Sequence to Correctly Enable the Output Rev. E | Page 25 of 45 AD5737 Data Sheet DATA REGISTERS DAC Data Register The input shift register is 24 bits wide. When PEC is enabled, the input shift register is 32 bits wide, with the last eight bits corresponding to the PEC code (see the Packet Error Checking section for more information about PEC). When writing to a data register, the format shown in Table 10 must be used. When writing to a DAC data register, Bit D15 to Bit D4 are the DAC data bits. Table 12 shows the register format, and Table 11 describes the functions of Bit D23 to Bit D16. Table 10. Input Shift Register for a Write Operation to a Data Register MSB D23 R/W D22 DUT_AD1 D21 DUT_AD0 D20 DREG2 D19 DREG1 D18 DREG0 D17 DAC_AD1 D16 DAC_AD0 LSB D15 to D0 Data Table 11. Descriptions of Data Register Bits[D23:D16] Bit Name R/W DUT_AD1, DUT_AD0 DREG2, DREG1, DREG0 DAC_AD1, DAC_AD0 Description This bit indicates whether the addressed register is written to or read from. 0 = write to the addressed register. 1 = read from the addressed register. Used in association with the external pins AD1 and AD0, these bits determine which AD5737 device is being addressed by the system controller. It is not recommended to tie both AD1 and AD0 low when using PEC (see the Packet Error Checking section). DUT_AD1 DUT_AD0 Part Addressed 0 0 Pin AD1 = 0, Pin AD0 = 0 0 1 Pin AD1 = 0, Pin AD0 = 1 1 0 Pin AD1 = 1, Pin AD0 = 0 1 1 Pin AD1 = 1, Pin AD0 = 1 These bits select the register to be written to. If a control register is selected (DREG[2:0] = 111), the CREG bits in the control register select the specific control register to be written to (see Table 19). DREG2 DREG1 DREG0 Function 0 0 0 Write to DAC data register (one DAC channel) 0 0 1 Reserved 0 1 0 Write to gain register (one DAC channel) 0 1 1 Write to gain registers (all DAC channels) 1 0 0 Write to offset register (one DAC channel) 1 0 1 Write to offset registers (all DAC channels) 1 1 0 Write to clear code register (one DAC channel) 1 1 1 Write to a control register These bits are used to specify the DAC channel. If a write to the part does not apply to a specific DAC channel, these bits are don’t care bits. DAC_AD1 DAC_AD0 DAC Channel 0 0 DAC A 0 1 DAC B 1 0 DAC C 1 1 DAC D Table 12. Programming the DAC Data Register D23 R/W 1 D22 DUT_AD1 D21 DUT_AD0 D20 0 D19 0 D18 0 X = don’t care. Rev. E | Page 26 of 45 D17 DAC_AD1 D16 DAC_AD0 D15 to D4 DAC data D3 to D0 X1 Data Sheet AD5737 Gain Register DREG[2:0] bits to 100 (see Table 15). To write the same offset code to all four DAC channels at the same time, set the DREG[2:0] bits to 101. The offset register coding is straight binary, as shown in Table 16. The default code in the offset register is 0x8000, which results in zero offset programmed to the output (for more information, see the Digital Offset and Gain Control section). The 12-bit gain register allows the user to adjust the gain of each channel in steps of 1 LSB. To write to the gain register of one DAC channel, set the DREG[2:0] bits to 010 (see Table 13). To write the same gain code to all four DAC channels at the same time, set the DREG[2:0] bits to 011. The gain register coding is straight binary, as shown in Table 14. The default code in the gain register is 0xFFFF. The maximum recommended gain trim is approximately 50% of the programmed range to maintain accuracy (for more information, see the Digital Offset and Gain Control section). Clear Code Register The 12-bit clear code register allows the user to set the clear value of each channel. To configure a channel to be cleared when the CLEAR pin is activated, set the CLR_EN bit in the DAC control register for that channel (see Table 23). To write to the clear code register, set the DREG[2:0] bits to 110 (see Table 17). The default clear code is 0x0000 (for more information, see the Asynchronous Clear section). Offset Register The 12-bit offset register allows the user to adjust the offset of each channel by −2048 LSB to +2047 LSB in steps of 1 LSB. To write to the offset register of one DAC channel, set the Table 13. Programming the Gain Register R/W 0 DUT_AD1 DUT_AD0 Device address DREG2 0 DREG1 1 DREG0 0 DAC_AD1 DAC_AD0 DAC channel address D15 to D4 Gain adjustment D3 to D0 1111 Table 14. Gain Register Bit Descriptions Gain Adjustment +4096 LSB +4095 LSB … 1 LSB 0 LSB G15 1 1 … 0 0 G14 1 1 … 0 0 G13 to G5 111111111 111111111 … 000000000 000000000 G4 1 0 … 1 0 G3 to G0 1111 1111 1111 1111 1111 Table 15. Programming the Offset Register R/W 0 DUT_AD1 DUT_AD0 Device address DREG2 1 DREG1 0 DREG0 0 DAC_AD1 DAC_AD0 DAC channel address D15 to D4 Offset adjustment D3 to D0 0000 Table 16. Offset Register Bit Descriptions Offset Adjustment +2047 LSB +2046 LSB … No Adjustment (Default) … −2047 LSB −2048 LSB OF15 1 1 … 1 … 0 0 OF14 1 1 … 0 … 0 0 OF13 1 1 … 0 … 0 0 OF12 to OF5 11111111 11111111 … 00000000 … 00000000 00000000 OF4 1 0 … 0 … 1 0 OF3 to OF0 0000 0000 0000 0000 0000 0000 0000 Table 17. Programming the Clear Code Register R/W 0 DUT_AD1 DUT_AD0 Device address DREG2 1 DREG1 1 DREG0 0 Rev. E | Page 27 of 45 DAC_AD1 DAC_AD0 DAC channel address D15 to D4 Clear code D3 to D0 0000 AD5737 Data Sheet CONTROL REGISTERS Main Control Register When writing to a control register, the format shown in Table 18 must be used. See Table 11 for information about the configuration of Bit D23 to Bit D16. The control registers are addressed by setting the DREG[2:0] bits (Bits[D20:D18] in the input shift register) to 111 and then setting the CREG[2:0] bits to select the specific control register (see Table 19). The main control register options are shown in Table 20 and Table 21. See the Device Features section for more information about the features controlled by the main control register. Table 18. Input Shift Register for a Write Operation to a Control Register MSB D23 R/W D22 DUT_AD1 D21 DUT_AD0 D20 1 D19 1 D18 1 D17 DAC_AD1 D16 DAC_AD0 D15 CREG2 D14 CREG1 D13 CREG0 LSB D12 to D0 Data Table 19. Control Register Addresses (CREG[2:0] Bits) CREG2 (D15) 0 0 0 0 1 CREG1 (D14) 0 0 1 1 0 CREG0 (D13) 0 1 0 1 0 Control Register Slew rate control register (one per channel) Main control register DAC control register (one per channel) DC-to-DC control register Software register Table 20. Programming the Main Control Register D15 0 1 D14 0 D13 1 D12 0 D11 STATREAD D10 EWD D9 WD1 D8 WD0 D7 X1 D6 X1 D5 D4 OUTEN_ALL DCDC_ALL D3 to D0 X1 X = don’t care. Table 21. Main Control Register Bit Descriptions Bit Name STATREAD EWD WD1, WD0 OUTEN_ALL DCDC_ALL Description Enable status readback during a write. See the Status Readback During a Write section. 0 = disable status readback (default). 1 = enable status readback. Enable the watchdog timer. See the Watchdog Timer section. 0 = disable the watchdog timer (default). 1 = enable the watchdog timer. Timeout select bits. Used to select the timeout period for the watchdog timer. WD1 WD0 Timeout Period (ms) 0 0 5 0 1 10 1 0 100 1 1 200 Setting this bit to 1 enables the output on all four DACs simultaneously. Do not use the OUTEN_ALL bit when using the OUTEN bit in the DAC control register. Setting this bit to 1 powers up the dc-to-dc converter on all four channels simultaneously. To power down the dc-to-dc converters, all channel outputs must first be disabled. Do not use the DCDC_ALL bit when using the DC_DC bit in the DAC control register. Rev. E | Page 28 of 45 Data Sheet AD5737 DAC Control Register The DAC control register is used to configure each DAC channel. The DAC control register options are shown in Table 22 and Table 23. Table 22. Programming the DAC Control Register D15 0 1 D14 1 D13 0 D12 X1 D11 X1 D10 X1 D9 X1 D8 D7 D6 INT_ENABLE CLR_EN OUTEN D5 RSET D4 DC_DC D3 X1 D2 R2 D1 R1 D0 R0 X = don’t care. Table 23. DAC Control Register Bit Descriptions Bit Name INT_ENABLE CLR_EN OUTEN RSET DC_DC R2, R1, R0 Description Powers up the dc-to-dc converter, DAC, and internal amplifiers for the selected channel. This bit applies to individual channels only; it does not enable the output. After setting this bit, it is recommended that a >200 µs delay be observed before enabling the output to reduce the output enable glitch. See Figure 25 for plots of this glitch. Per-channel clear enable bit. This bit specifies whether the selected channel is cleared when the CLEAR pin is activated. 0 = channel is not cleared when the part is cleared (default). 1 = channel is cleared when the part is cleared. Enables or disables the selected output channel. 0 = channel disabled (default). 1 = channel enabled. Selects the internal current sense resistor or an external current sense resistor for the selected DAC channel. 0 = external resistor selected (default). 1 = internal resistor selected. Powers up or powers down the dc-to-dc converter on the selected channel. All dc-to-dc converters can be powered up simultaneously using the DCDC_ALL bit in the main control register. To power down the dc-to-dc converter, the OUTEN and INT_ENABLE bits must also be set to 0. 0 = dc-to-dc converter is powered down (default). 1 = dc-to-dc converter is powered up. Selects the output range to be enabled. R2 R1 R0 Output Range Selected 0 0 0 Reserved 0 0 1 Reserved 0 1 0 Reserved 0 1 1 Reserved 1 0 0 4 mA to 20 mA current range 1 0 1 0 mA to 20 mA current range 1 1 0 0 mA to 24 mA current range Rev. E | Page 29 of 45 AD5737 Data Sheet Software Register The software register allows the user to perform a software reset of the part. This register is also used to set the user toggle bit, D11, in the status register and as part of the watchdog timer feature when that feature is enabled. Bit D12 in the software register can be used to ensure that communication has not been lost between the MCU and the AD5737 and that the datapath lines are working properly (that is, SDIN, SCLK, and SYNC). When the watchdog timer feature is enabled, the user must write 0x195 to Bits[D11:D0] of the software register within the timeout period. If this command is not received within the timeout period, the ALERT pin signals a fault condition. This command is only required when the watchdog timer feature is enabled. DC-to-DC Control Register The dc-to-dc control register allows the user to configure the dc-to-dc switching frequency and phase, as well as the maximum allowable dc-to-dc output voltage. The dc-to-dc control register options are shown in Table 26 and Table 27. Table 24. Programming the Software Register D15 1 D14 0 D13 0 D12 User program D11 to D0 Reset code/SPI code Table 25. Software Register Bit Descriptions Bit Name User Program Reset Code/SPI Code Description This bit is mapped to Bit D11 of the status register. When this bit is set to 1, Bit D11 of the status register is set to 1. When this bit is set to 0, Bit D11 of the status register is also set to 0. This feature can be used to ensure that the SPI pins are working correctly by writing a known bit value to this register and then reading back Bit D11 from the status register. Option Description Reset code Writing 0x555 to Bits[D11:D0] performs a software reset of the AD5737. SPI code If the watchdog timer feature is enabled, 0x195 must be written to the software register (Bits[D11:D0]) within the programmed timeout period (see Table 21). Table 26. Programming the DC-to-DC Control Register D15 0 1 D14 1 D13 1 D12 to D7 X1 D6 DC-DC comp D5 to D4 DC-DC phase D3 to D2 DC-DC freq D1 to D0 DC-DC MaxV X = don’t care. Table 27. DC-to-DC Control Register Bit Descriptions Bit Name DC-DC Comp DC-DC Phase DC-DC Freq DC-DC MaxV Description Selects the internal compensation resistor or an external compensation resistor for the dc-to-dc converter. See the DC-to-DC Converter Compensation Capacitors section and the AICC Supply Requirements—Slewing section. 0 = selects the internal 150 kΩ compensation resistor (default). 1 = bypasses the internal compensation resistor. When this bit is set to 1, an external compensation resistor must be used; this resistor is placed at the COMPDCDC_x pin in series with the 10 nF dc-to-dc compensation capacitor to ground. Typically, a resistor of ~50 kΩ is recommended. User-programmable dc-to-dc converter phase (between channels). 00 = all dc-to-dc converters clock on the same edge (default). 01 = Channel A and Channel B clock on the same edge; Channel C and Channel D clock on the opposite edge. 10 = Channel A and Channel C clock on the same edge; Channel B and Channel D clock on the opposite edge. 11 = Channel A, Channel B, Channel C, and Channel D clock 90° out of phase from each other. Switching frequency for the dc-to-dc converter; this frequency is divided down from the internal 13 MHz oscillator (see Figure 46 and Figure 47). 00 = 250 kHz ± 10%. 01 = 410 kHz ± 10% (default). 10 = 650 kHz ± 10%. Maximum allowed VBOOST_x voltage supplied by the dc-to-dc converter. 00 = 23 V + 1 V/−1.5 V (default). 01 = 24.5 V ± 1 V. 10 = 27 V ± 1 V. 11 = 29.5 V ± 1 V. Rev. E | Page 30 of 45 Data Sheet AD5737 Slew Rate Control Register SYNC frame of the NOP command (see Figure 4, Table 30, and Table 31). This register is used to program the slew rate control for the selected DAC channel. The slew rate control is enabled/disabled and programmed on a per-channel basis. See Table 28 and the Digital Slew Rate Control section for more information. If the first clock edge in the NOP command is positive, the data readback is 24 bits in length, consisting of 8 don’t care bits prior to the 16 data bits (see Table 30). READBACK OPERATION If the first clock edge in the NOP command is negative, the data readback is 23 bits in length, consistent of 7 don’t care bits prior to the 16 data bits (see Table 31). Readback mode is invoked by setting the R/W bit = 1 in the serial input register write. See Table 29 for the bits associated with a readback operation. The DUT_AD1 and DUT_AD0 bits, in association with Bits[RD4:RD0], select the register to be read (see Table 32). The remaining data bits in the write sequence are don’t care bits. In both cases, if PEC is enabled, there must be no activity on SCLK in between the read command and the NOP command, otherwise an incorrect PEC may be read back (see Figure 5). During the next SPI transfer, the data that appears on the SDO output contains the data from the previously addressed register (see Figure 4). This second SPI transfer must be either a request to read another register on a third data transfer or a no operation command. The no operation command for DUT Address 00 is 0x1CE000; for other DUT addresses, Bits[D22:D21] are set accordingly. Readback Example To read back the gain register of AD5737 Device 1, Channel A, implement the following sequence: 1. 2. The data readback is contained in the 16 LSBs. The MSBs consist of don’t care bits. The number of don’t care bits is dependent on the polarity of the first clock edge within the Write 0xA80000 to the input register to configure Device Address 1 for read mode with the gain register of Channel A selected. The data bits, D15 to D0, are don’t care bits. Execute another read command or a no operation command (0x3CE000). During this command, the data from the Channel A gain register is clocked out on the SDO line. Table 28. Programming the Slew Rate Control Register D15 0 1 D14 0 D13 0 D12 SREN D11 to D7 X1 D6 to D3 SR_CLOCK D2 to D0 SR_STEP X = don’t care. Table 29. Input Shift Register for a Read Operation MSB D23 R/W 1 D22 DUT_AD1 D21 DUT_AD0 D20 RD4 D19 RD3 D18 RD2 D17 RD1 D16 RD0 LSB D15 to D0 X1 X = don’t care. Table 30. Decoding Data Readback on SDO (First Clock Edge Within the SYNC Frame of the NOP Command is Positive) MSB D23 X1 1 LSB D22 X1 D21 X1 D20 X1 D19 X1 D18 X1 D17 X1 D16 X1 D15 to D0 Data Readback X = don’t care. Table 31. Decoding Data Readback on SDO (First Clock Edge Within the SYNC Frame of the NOP Command is Negative) MSB D22 X1 1 LSB D21 X1 D20 X1 D19 X1 D18 X1 X = don’t care. Rev. E | Page 31 of 45 D17 X1 D16 X1 D15 to D0 X1 AD5737 Data Sheet Table 32. Read Addresses (Bits[RD4:RD0]) RD4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 RD3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 RD2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 RD1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 RD0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Function Read DAC A data register Read DAC B data register Read DAC C data register Read DAC D data register Read DAC A control register Read DAC B control register Read DAC C control register Read DAC D control register Read DAC A gain register Read DAC B gain register Read DAC C gain register Read DAC D gain register Read DAC A offset register Read DAC B offset register Read DAC C offset register Read DAC D offset register Read DAC A clear code register Read DAC B clear code register Read DAC C clear code register Read DAC D clear code register Read DAC A slew rate control register Read DAC B slew rate control register Read DAC C slew rate control register Read DAC D slew rate control register Read status register Read main control register Read dc-to-dc control register Rev. E | Page 32 of 45 Data Sheet AD5737 Status Register register contents can be read back on the SDO pin during every write sequence. Alternatively, if the STATREAD bit is not set, the status register can be read using the normal readback operation (see the Readback Operation section). The status register is a read-only register. This register contains any fault information, as a well as a ramp active bit (Bit D9) and the status of the packet error checking feature (Bit D10). When the STATREAD bit in the main control register is set, the status Table 33. Decoding the Status Register MSB D15 D14 D13 D12 D11 D10 DC-DCD DC-DCC DC-DCB DC-DCA User PEC toggle error 1 D9 Ramp active D8 Over temp D7 X1 D6 X1 D5 X1 D4 X1 D3 IOUT_D fault D2 IOUT_C fault D1 IOUT_B fault LSB D0 IOUT_A fault X = don’t care. Table 34. Status Register Bit Descriptions Bit Name DC-DCD DC-DCC DC-DCB DC-DCA User Toggle PEC Error Ramp Active Over Temp IOUT_D Fault IOUT_C Fault IOUT_B Fault IOUT_A Fault Description This bit is set if the dc-to-dc converter on Channel D cannot maintain compliance, for example, if the dc-to-dc converter is reaching its VMAX voltage; in this case, the IOUT_D fault bit is also set. See the DC-to-DC Converter VMAX Functionality section for more information about the operation of this bit under this condition. This bit is set if the dc-to-dc converter on Channel C cannot maintain compliance, for example, if the dc-to-dc converter is reaching its VMAX voltage; in this case, the IOUT_C fault bit is also set. See the DC-to-DC Converter VMAX Functionality section for more information about the operation of this bit under this condition. This bit is set if the dc-to-dc converter on Channel B cannot maintain compliance, for example, if the dc-to-dc converter is reaching its VMAX voltage; in this case, the IOUT_B fault bit is also set. See the DC-to-DC Converter VMAX Functionality section for more information about the operation of this bit under this condition. This bit is set if the dc-to-dc converter on Channel A cannot maintain compliance, for example, if the dc-to-dc converter is reaching its VMAX voltage; in this case, the IOUT_A fault bit is also set. See the DC-to-DC Converter VMAX Functionality section for more information about the operation of this bit under this condition. User toggle bit. This bit is set or cleared via the software register and can be used to verify data communications, if needed. Denotes a PEC error on the last data-word received over the SPI interface. This bit is set while any output channel is slewing (digital slew rate control is enabled on at least one channel). This bit is set if the AD5737 core temperature exceeds approximately 150°C. This bit is set if a fault is detected on the IOUT_D pin. This bit is set if a fault is detected on the IOUT_C pin. This bit is set if a fault is detected on the IOUT_B pin. This bit is set if a fault is detected on the IOUT_A pin. Rev. E | Page 33 of 45 AD5737 Data Sheet DEVICE FEATURES FAULT OUTPUT The output data from the calibration is routed to the DAC input register. This data is then loaded to the DAC, as described in the Serial Interface section. Both the gain register and the offset register have 12 bits of resolution. The correct order to calibrate the gain and offset is to first calibrate the gain and then calibrate the offset. The AD5737 is equipped with a FAULT pin, an active low, open-drain output that allows several AD5737 devices to be connected together to one pull-up resistor for global fault detection. The FAULT pin is forced active by any one of the following fault conditions: • • • The voltage at IOUT_x attempts to rise above the compliance range due to an open-loop circuit or insufficient power supply voltage. The internal circuitry that develops the fault output avoids using a comparator with windowed limits because this requires an actual output error before the FAULT output becomes active. Instead, the signal is generated when the internal amplifier in the output stage has less than approximately 1 V of remaining drive capability. Thus, the FAULT output is activated slightly before the compliance limit is reached. An interface error is detected due to a PEC failure (see the Packet Error Checking section). The core temperature of the AD5737 exceeds approximately 150°C. The IOUT_x fault, PEC error, and over temp bits of the status register are used in conjunction with the FAULT output to inform the user which fault condition caused the FAULT output to be activated. Each DAC channel has a gain (M) register and an offset (C) register, which allow trimming out of the gain and offset errors of the entire signal chain. Data from the DAC data register is operated on by a digital multiplier and adder controlled by the contents of the gain and offset registers; the calibrated DAC data is then stored in the DAC input register (see Figure 53). DAC INPUT REGISTER DAC 10067-075 GAIN (M) REGISTER OFFSET (C) REGISTER Code DACRegister = D × ( M + 1) 212 + C − 211 (1) where: D is the code loaded to the DAC data register of the DAC channel. M is the code in the gain register (default code = 212 − 1). C is the code in the offset register (default code = 211). STATUS READBACK DURING A WRITE The AD5737 can be configured to read back the contents of the status register during every write sequence. This feature is enabled using the STATREAD bit in the main control register. When this feature is enabled, the user can continuously monitor the status register and act quickly in the case of a fault. When status readback during a write is enabled, the contents of the 16-bit status register (see Table 34) are output on the SDO pin, as shown in Figure 5. DIGITAL OFFSET AND GAIN CONTROL DAC DATA REGISTER The value (in decimal) that is written to the DAC input register can be calculated as follows: Figure 53. Digital Offset and Gain Control Although Figure 53 indicates a multiplier and adder for each channel, the device has only one multiplier and one adder, which are shared by all four channels. This design has implications for the update speed when several channels are updated at once (see Table 3). When data is written to the gain (M) or offset (C) register, the output is not automatically updated. Instead, the next write to the DAC channel uses the new gain and offset values to perform a new calibration and automatically updates the channel. When the AD5737 is powered up, the status readback during a write feature is disabled. When this feature is enabled, readback of registers other than the status register is not available. To read back any other register, clear the STATREAD bit before following the readback sequence (see the Readback Operation section). The STATREAD bit can be set high again after the register read. If multiple units on the same SDO bus have the STATREAD feature enabled, ensure that each unit is provided a unique physical address (AD1 and AD0) to prevent contention on the bus. If packet error checking is enabled, ignore the PEC values returned on a status readback during a write operation. See the Packet Error Checking section. ASYNCHRONOUS CLEAR CLEAR is an active high, edge sensitive input that allows the output to be cleared to a preprogrammed 12-bit code. This code is user-programmable via a per-channel 12-bit clear code register. For a channel to be cleared, set the CLR_EN bit in the DAC control register for that channel. If the clear function on a channel is not enabled, the output remains in its current state, independent of the level of the CLEAR pin. When the CLEAR signal returns low, the relevant outputs remain cleared until a new value is programmed to them. Rev. E | Page 34 of 45 Data Sheet AD5737 PACKET ERROR CHECKING WATCHDOG TIMER To verify that data has been received correctly in noisy environments, the AD5737 offers the option of packet error checking based on an 8-bit cyclic redundancy check (CRC-8). The device controlling the AD5737 should generate an 8-bit frame check sequence using the following polynomial: When enabled, an on-chip watchdog timer generates an alert signal if 0x195 is not written to the software register within the programmed timeout period. This feature is useful to ensure that communication is not lost between the MCU and the AD5737 and that the datapath lines are working properly (that is, SDIN, SCLK, and SYNC). If 0x195 is not received by the software register within the timeout period, the ALERT pin signals a fault condition. The ALERT pin is active high and can be connected directly to the CLEAR pin to enable a clear in the event that communication from the MCU is lost. C(x) = x8 + x2 + x1 + 1 This value is added to the end of the data-word, and 32 bits are sent to the AD5737 before SYNC goes high. If the AD5737 sees a 32-bit frame, it performs the error check when SYNC goes high. If the error check is valid, the data is written to the selected register. If the error check fails, the FAULT pin goes low and the PEC error bit in the status register is set. After the status register is read, FAULT returns high (assuming that there are no other faults), and the PEC error bit is cleared automatically. It is not recommended to tie both AD1 and AD0 low as a short low on SDIN could possibly lead to a zero-scale update for DAC A. To enable the watchdog timer and set the timeout period (5 ms, 10 ms, 100 ms, or 200 ms), program the main control register (see Table 20 and Table 21). ALERT OUTPUT The AD5737 is equipped with an ALERT pin. This pin is an active high CMOS output. The AD5737 also has an internal watchdog timer. When enabled, the watchdog timer monitors SPI communications. If 0x195 is not received by the software register within the timeout period, the ALERT pin is activated. UPDATE ON SYNC HIGH SYNC INTERNAL REFERENCE SCLK MSB D23 SDIN The AD5737 contains an integrated 5 V voltage reference with initial accuracy of ±5 mV maximum and a temperature coefficient of ±10 ppm/°C maximum. The reference voltage is buffered and is externally available for use elsewhere within the system. REFOUT must be connected to REFIN to use the internal reference. LSB D0 24-BIT DATA 24-BIT DATA TRANSFER—NO ERROR CHECKING EXTERNAL CURRENT SETTING RESISTOR UPDATE ON SYNC HIGH ONLY IF ERROR CHECK PASSED SYNC SCLK MSB D31 FAULT 24-BIT DATA D7 D0 8-BIT CRC FAULT PIN GOES LOW IF ERROR CHECK FAILS 10067-180 SDIN LSB D8 32-BIT DATA TRANSFER WITH ERROR CHECKING Figure 54. PEC Timing Packet error checking can be used for transmitting and receiving data packets. If status readback during a write is enabled, ignore the PEC values returned during the status readback operation. If status readback during a write is disabled, the user can still use the normal readback operation to monitor status register activity with PEC. If PEC is enabled when receiving data packets, there must be no activity on SCLK between the read command and the NOP command, or an incorrect PEC may be read back. See Figure 5 and the Readback Operation section for further information. RSET is an internal sense resistor that is part of the voltage-tocurrent conversion circuitry (see Figure 49). The stability of the output current value over temperature is dependent on the stability of the RSET value. To improve the stability of the output current over temperature, the internal RSET resistor, R1, can be bypassed and an external, 15 kΩ, low drift resistor can be connected to the RSET_x pin of the AD5737. The external resistor is selected via the DAC control register (see Table 23). Table 1 provides the performance specifications for the AD5737 with both the internal RSET resistor and an external, 15 kΩ RSET resistor. The use of an external RSET resistor allows for improved performance over the internal RSET resistor option. The external RSET resistor specifications assume an ideal resistor; the actual performance depends on the absolute value and temperature coefficient of the resistor used. This directly affects the gain error of the output and, thus, the total unadjusted error. To arrive at the gain/TUE error of the output with a specific external RSET resistor, add the absolute error percentage of the RSET resistor directly to the gain/TUE error of the AD5737 with the external RSET resistor, as shown in Table 1 (expressed in % FSR). Rev. E | Page 35 of 45 AD5737 Data Sheet HART CONNECTIVITY Table 36. Slew Rate Update Clock Options The AD5737 has four CHART pins, one corresponding to each output channel. A HART signal can be coupled into these pins. The HART signal appears on the corresponding current output, if the output is enabled. Table 35 shows the recommended input voltages for the HART signal at the CHART pin. If these voltages are used, the current output meets HART amplitude specifications. SR_CLOCK 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Table 35. CHART Input Voltage to HART Output Current RSET Internal RSET External RSET CHART Input Voltage 150 mV p-p 170 mV p-p Current Output (HART) 1 mA p-p 1 mA p-p Figure 55 shows the recommended circuit for attenuating and coupling the HART signal. A minimum capacitance of C1 + C2 is required to ensure that the 1.2 kHz and 2.2 kHz HART frequencies are not significantly attenuated at the output. The recommended values are C1 = 22 nF and C2 = 47 nF. Update Clock Frequency1 64 kHz 32 kHz 16 kHz 8 kHz 4 kHz 2 kHz 1 kHz 500 Hz 250 Hz 125 Hz 64 Hz 32 Hz 16 Hz 8 Hz 4 Hz 0.5 Hz C1 CHARTx C2 1 10067-076 HART MODEM OUTPUT Table 37. Slew Rate Step Size Options Figure 55. Coupling the HART Signal Digitally controlling the slew rate of the output is necessary to meet the analog rate of change requirements for HART. If the HART feature is not required, leave the CHART pins open circuit. DIGITAL SLEW RATE CONTROL The digital slew rate control feature of the AD5737 allows the user to control the rate at which the output value changes. With the slew rate control feature disabled, the output value changes at a rate limited by the output drive circuitry and the attached load. To reduce the slew rate, the user can enable the digital slew rate control feature using the SREN bit of the slew rate control register (see Table 28). When slew rate control is enabled, the output, instead of slewing directly between two values, steps digitally at a rate defined by the SR_CLOCK and SR_STEP parameters. These parameters are accessible via the slew rate control register (see Table 28). • • These clock frequencies are divided down from the 13 MHz internal oscillator (see Table 1, Figure 46, and Figure 47). SR_CLOCK defines the rate at which the digital slew is updated; for example, if the selected update rate is 8 kHz, the output is updated every 125 µs. SR_STEP defines by how much the output value changes at each update. Together, these parameters define the rate of change of the output value. Table 36 and Table 37 list the range of values for the SR_CLOCK and SR_STEP parameters, respectively. SR_STEP 000 001 010 011 100 101 110 111 Step Size (LSB) 1 2 4 16 32 64 128 256 The following equation describes the slew rate as a function of the step size, the update clock frequency, and the LSB size. Slew Rate = Output Change Step Size × Update Clock Frequency × LSB Size where: Slew Rate is expressed in seconds. Output Change is expressed in amperes. The update clock frequency for any given value is the same for all output ranges. The step size, however, varies across output ranges for a given value of step size because the LSB size is different for each output range. When the slew rate control feature is enabled, all output changes occur at the programmed slew rate (see the DC-to-DC Converter Settling Time section for more information). For example, if the CLEAR pin is asserted, the output slews to the clear value at the programmed slew rate (assuming that the channel is enabled to be cleared). Rev. E | Page 36 of 45 Data Sheet AD5737 The AD5737 provides integrated dynamic power control using a dc-to-dc boost converter circuit. This circuit reduces power consumption compared with standard designs. In standard current input module designs, the load resistor values can range from typically 50 Ω to 750 Ω. Output module systems must source enough voltage to meet the compliance voltage requirement across the full range of load resistor values. For example, in a 4 mA to 20 mA loop when driving 20 mA, a compliance voltage of >15 V is required. When driving 20 mA into a 50 Ω load, a compliance voltage of only 1 V is required. The AD5737 circuitry senses the output voltage and regulates this voltage to meet the compliance requirements plus a small headroom voltage. The AD5737 is capable of driving up to 24 mA through a 1 kΩ load. DC-TO-DC CONVERTERS The AD5737 contains four independent dc-to-dc converters. These are used to provide dynamic control of the VBOOST_x supply voltage for each channel (see Figure 49). Figure 56 shows the discrete components needed for the dc-to-dc circuitry, and the following sections describe component selection and operation of this circuitry. AV CC CIN ≥10µF 10µH CDCDC 4.7µF RFILTER 10Ω SWx VBOOST_x CFILTER 0.1µF 10067-077 DDCDC LDCDC When a channel current output is enabled, the converter regulates the VBOOST_x supply to 7.4 V (±5%) or (IOUT × RLOAD + Headroom), whichever is greater (see Figure 31 for a plot of headroom supplied vs. output current). When the output is disabled, the converter regulates the VBOOST_x supply to 7.4 V (±5%). DC-to-DC Converter Settling Time The settling time for a step greater than ~1 V (IOUT × RLOAD) is dominated by the settling time of the dc-to-dc converter. The exception to this is when the required voltage at the IOUT_x pin plus the compliance voltage is below 7.4 V (±5%). Figure 26 shows a typical plot of the output settling time. This plot is for a 1 kΩ load. The settling time for smaller loads is faster. The settling time for current steps less than 24 mA is also faster. DC-to-DC Converter VMAX Functionality The maximum VBOOST_x voltage is set in the dc-to-dc control register (23 V, 24.5 V, 27 V, or 29.5 V; see Table 27). When the maximum voltage is reached, the dc-to-dc converter is disabled, and the VBOOST_x voltage is allowed to decay by ~0.4 V. After the VBOOST_x voltage decays by ~0.4 V, the dc-to-dc converter is reenabled, and the voltage ramps up again to VMAX, if still required. This operation is shown in Figure 57. 29.6 29.3 29.2 29.1 28.7 Manufacturer Coilcraft® Murata Diodes, Inc. It is recommended that a 10 Ω, 100 nF low-pass RC filter be placed after CDCDC. This filter consumes a small amount of power but reduces the amount of ripple on the VBOOST_x supply. DC-to-DC Converter Operation The on-board dc-to-dc converters use a constant frequency, peak current mode control scheme to step up an AVCC input of 4.5 V to 5.5 V to drive the AD5737 output channel. These converters are designed to operate in discontinuous conduction mode with a duty cycle of <90% typical. Discontinuous conduction mode refers to a mode of operation where the inductor current goes to zero for an appreciable percentage of the switching cycle. The dc-to-dc converters are nonsynchronous; that is, they require an external Schottky diode. fSW = 410kHz 28.9 Table 38. Recommended Components for a DC-to-DC Converter Value 10 µH 4.7 µF 0.55 VF DC-DC MaxV BITS = 29.5V DC-DCx BIT = 1 29.0 Figure 56. DC-to-DC Circuit Component XAL4040-103 GRM32ER71H475KA88L PD3S160-7 0mA TO 24mA RANGE, 24mA OUTPUT OUTPUT UNLOADED 29.4 28.8 Symbol LDCDC CDCDC DDCDC VMAX DC-DCx BIT 29.5 TA = 25°C DC-DCx BIT = 0 28.6 0 0.5 1.0 1.5 2.0 2.5 TIME (ms) 3.0 3.5 4.0 Figure 57. Operation on Reaching VMAX As shown in Figure 57, the DC-DCx bit in the status register is asserted when the AD5737 ramps up to the VMAX value but is deasserted when the voltage decays to VMAX − ~0.4 V. DC-to-DC Converter On-Board Switch The AD5737 contains a 0.425 Ω internal switch. The switch current is monitored on a pulse-by-pulse basis and is limited to 0.8 A peak current. Rev. E | Page 37 of 45 10067-183 DYNAMIC POWER CONTROL DC-to-DC Converter Output Voltage VBOOST_x VOLTAGE (V) If more than one channel is enabled for digital slew rate control, care must be taken when asserting the CLEAR pin. If a channel under slew rate control is slewing when the CLEAR pin is asserted, other channels under slew rate control may change directly to their clear code not under slew rate control. AD5737 Data Sheet DC-to-DC Converter Switching Frequency and Phase The AD5737 dc-to-dc converter switching frequency can be selected from the dc-to-dc control register (see Table 27). The phasing of the channels can also be adjusted so that the dc-to-dc converters can clock on different edges. For typical applications, a 410 kHz frequency is recommended. At light loads (low output current and small load resistor), the dc-to-dc converter enters a pulse-skipping mode to minimize switching power dissipation. DC-to-DC Converter Inductor Selection For typical 4 mA to 20 mA applications, a 10 µH inductor (such as the XAL4040-103 from Coilcraft), combined with a switching frequency of 410 kHz, allows up to 24 mA to be driven into a load resistance of up to 1 kΩ with an AVCC supply of 4.5 V to 5.5 V. It is important to ensure that the inductor can handle the peak current without saturating, especially at the maximum ambient temperature. If the inductor enters saturation mode, efficiency decreases. The inductance value also drops during saturation and may result in the dc-to-dc converter circuit not being able to supply the required output power. DC-to-DC Converter External Schottky Diode Selection The AD5737 requires an external Schottky diode for correct operation. Ensure that the Schottky diode is rated to handle the maximum reverse breakdown voltage expected in operation and that the maximum junction temperature of the diode is not exceeded. The average current of the diode is approximately equal to the ILOAD current. Diodes with larger forward voltage drops result in a decrease in efficiency. DC-to-DC Converter Compensation Capacitors Because the dc-to-dc converter operates in discontinuous conduction mode, the uncompensated transfer function is essentially a single-pole transfer function. The pole frequency of the transfer function is determined by the output capacitance, input and output voltage, and output load of the dc-to-dc converter. The AD5737 uses an external capacitor in conjunction with an internal 150 kΩ resistor to compensate the regulator loop. Alternatively, an external compensation resistor can be used in series with the compensation capacitor by setting the DC-DC comp bit in the dc-to-dc control register (see Table 27). In this case, a resistor of ~50 kΩ is recommended. The advantages of this configuration are described in the AICC Supply Requirements— Slewing section. For typical applications, a 10 nF dc-to-dc compensation capacitor is recommended. DC-to-DC Converter Input and Output Capacitor Selection The output capacitor affects the ripple voltage of the dc-to-dc converter and indirectly limits the maximum slew rate at which the channel output current can rise. The ripple voltage is caused by a combination of the capacitance and the equivalent series resistance (ESR) of the capacitor. For typical applications, a ceramic capacitor of 4.7 µF is recommended. Larger capacitors or parallel capacitors improve the ripple at the expense of reduced slew rate. Larger capacitors also affect the current requirements of the AVCC supply while slewing (see the AICC Supply Requirements—Slewing section). The capacitance at the output of the dc-to-dc converter must be >3 µF under all operating conditions. The input capacitor provides much of the dynamic current required for the dc-to-dc converter and must be a low ESR component. For the AD5737, a low ESR tantalum or ceramic capacitor of 10 µF is recommended for typical applications. Ceramic capacitors must be chosen carefully because they can exhibit a large sensitivity to dc bias voltages and temperature. X5R or X7R dielectrics are preferred because these capacitors remain stable over wider operating voltage and temperature ranges. Care must be taken if selecting a tantalum capacitor to ensure a low ESR value. AICC SUPPLY REQUIREMENTS—STATIC The dc-to-dc converter is designed to supply a VBOOST_x voltage of VBOOST_x = IOUT × RLOAD + Headroom (2) See Figure 31 for a plot of headroom supplied vs. output current. Therefore, for a fixed load and output voltage, the output current of the dc-to-dc converter can be calculated by the following formula: AI CC = Power Out Efficiency × AVCC = I OUT × VBOOST ηVBOOST × AVCC where: IOUT is the output current from IOUT_x in amperes. ηVBOOST is the efficiency at VBOOST_x as a fraction (see Figure 33 and Figure 34). Rev. E | Page 38 of 45 (3) Data Sheet AD5737 AICC SUPPLY REQUIREMENTS—SLEWING Adding an External Compensation Resistor The AICC current requirement while slewing is greater than in static operation because the output power increases to charge the output capacitance of the dc-to-dc converter. This transient current can be quite large (see Figure 58), although the methods described in the Reducing AICC Current Requirements section can reduce the requirements on the AVCC supply. A compensation resistor can be placed at the COMPDCDC_x pin in series with the 10 nF compensation capacitor. A 51 kΩ external compensation resistor is recommended. This compensation increases the slew time of the current output but reduces the AICC transient current requirements. Figure 59 shows a plot of AICC current for a 24 mA step through a 1 kΩ load when using a 51 kΩ compensation resistor. The compensation resistor reduces the current requirements through smaller loads even further, as shown in Figure 60. 0.7 AICC CURRENT (A) 0.6 AICC CURRENT (A) 0.6 0mA TO 24mA RANGE 1kΩ LOAD fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) TA = 25°C 0.5 0.4 20 15 0.3 10 0.2 AICC IOUT VBOOST 0.1 5 0 0 0 0.5 1.0 1.5 TIME (ms) 2.0 2.5 24 0.5 20 0.4 16 0.3 12 0.2 8 AICC IOUT VBOOST 0.1 4 0 0 0 0.5 1.0 1.5 TIME (ms) 2.0 2.5 Figure 59. AICC Current vs. Time for 24 mA Step Through 1 kΩ Load with External 51 kΩ Compensation Resistor 0.8 Figure 58. AICC Current vs. Time for 24 mA Step Through 1 kΩ Load with Internal Compensation Resistor 32 AICC IOUT VBOOST 0.7 0mA TO 24mA RANGE 500Ω LOAD fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) TA = 25°C Two main methods can be used to reduce the AICC current requirements. One method is to add an external compensation resistor, and the other is to use slew rate control. These methods can be used together. AICC CURRENT (A) 0.6 Reducing AICC Current Requirements 28 24 0.5 20 0.4 16 0.3 12 0.2 8 0.1 4 IOUT_x CURRENT (mA)/ VBOOST_x VOLTAGE (V) 25 28 0 0 0 0.5 1.0 1.5 TIME (ms) 2.0 2.5 Figure 60. AICC Current vs. Time for 24 mA Step Through 500 Ω Load with External 51 kΩ Compensation Resistor Rev. E | Page 39 of 45 10067-186 0.7 10067-184 30 IOUT_x CURRENT (mA)/ VBOOST_x VOLTAGE (V) 0.8 32 0mA TO 24mA RANGE 1kΩ LOAD fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) TA = 25°C IOUT_x CURRENT (mA)/ VBOOST_x VOLTAGE (V) 0.8 10067-185 If not enough AICC current can be provided, the AVCC voltage drops. Due to this AVCC drop, the AICC current required for slewing increases further, causing the voltage at AVCC to drop further (see Equation 3). In this case, the VBOOST_x voltage and, therefore, the output voltage, may never reach their intended values. Because the AVCC voltage is common to all channels, this voltage drop may also affect other channels. AD5737 Data Sheet Using Slew Rate Control EXTERNAL PMOS MODE Using slew rate control can greatly reduce the current requirements of the AVCC supply, as shown in Figure 61. The AD5737 can also be used with an external PMOS transistor per channel, as shown in Figure 62. This mode can be used to limit the on-chip power dissipation of the AD5737, although this mode does not reduce the power dissipation of the total system. The IGATEx functionality is not typically required when using the dynamic power control feature; therefore, Figure 62 shows the configuration of the device for a fixed VBOOST_x supply. 0.8 AICC CURRENT (A) 0.6 28 24 AICC IOUT VBOOST 0.5 20 0.4 16 0.3 12 0.2 8 0.1 4 0 0 1 2 3 TIME (ms) 4 5 6 0 In this configuration, the SWx pin is left floating, and the GNDSWx pin is grounded. The VBOOST_x pin is connected to a minimum supply of 7.4 V and a maximum supply of 33 V. This supply can be sized according to the maximum load required to be driven. The IGATEx functionality works by holding the gate of the external PMOS transistor at (VBOOST_x − 5 V). This means that the majority of the power dissipation of the channel takes place in the external PMOS transistor. 10067-187 0.7 IOUT_x CURRENT (mA)/ VBOOST_x VOLTAGE (V) 32 0mA TO 24mA RANGE 1kΩ LOAD fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) TA = 25°C Select the external PMOS transistor to tolerate a VDS voltage of at least the VBOOST_x voltage, as well as to handle the power dissipation required. Choose the VGS to accommodate for the IOUT headroom. The external PMOS transistor typically has minimal effect on the current output performance. Figure 61. AICC Current vs. Time for 24 mA Step Through 1 kΩ Load with Slew Rate Control When using slew rate control, it is important to remember that the output cannot slew faster than the dc-to-dc converter. The dc-to-dc converter slews slowest at higher currents through large loads (for example, 1 kΩ). The slew rate is also dependent on the configuration of the dc-to-dc converter. Two examples of the dc-to-dc converter output slew are shown in Figure 59 and Figure 60. (VBOOST corresponds to the output voltage of the dc-to-dc converter.) SWA VBOOST_A (OPEN CIRCUIT) R2 R3 DAC A IOUT_A (VBOOST_A – 5V) IGATEA CURRENT OUTPUT R1 RLOAD RSET_A CHARTA DAC CHANNE L A 10067-190 AVCC 5.0V GNDSWA Figure 62. Configuration of Channel A Using IGATEx Rev. E | Page 40 of 45 Data Sheet AD5737 APPLICATIONS INFORMATION CURRENT OUTPUT MODE WITH INTERNAL RSET When using the internal RSET resistor, the current output is significantly affected by how many other channels using the internal RSET are enabled and by the dc crosstalk from these channels. The internal RSET specifications in Table 1 are for all four channels enabled with the internal RSET selected and outputting the same code. For every channel enabled with the internal RSET, the offset error decreases. For example, with one current output enabled using the internal RSET, the offset error is 0.075% FSR. This value decreases proportionally as more current channels are enabled; the offset error is 0.056% FSR on each of two channels, 0.029% FSR on each of three channels, and 0.01% FSR on each of four channels. Similarly, the dc crosstalk when using the internal RSET is proportional to the number of current output channels enabled with the internal RSET. For example, with the measured channel at 0x8000 and another channel going from zero to full scale, the dc crosstalk is −0.011% FSR. With two other channels going from zero to full scale, the dc crosstalk is −0.019% FSR, and with all three other channels going from zero to full scale, it is −0.025% FSR. For the full-scale error measurement in Table 1, all channels are at 0xFFFF. This means that as any channel goes to zero scale, the full-scale error increases due to the dc crosstalk. For example, with the measured channel at 0xFFFF and three channels at zero scale, the full-scale error is 0.025% FSR. Similarly, if only one channel is enabled with the internal RSET, the full-scale error is 0.025% FSR + 0.075% FSR = 0.1% FSR. PRECISION VOLTAGE REFERENCE SELECTION To achieve the optimum performance from the AD5737 over its full operating temperature range, a precision voltage reference must be used. Take care with the selection of the precision voltage reference. The voltage applied to the reference inputs is used to provide a buffered reference for the DAC cores. Therefore, any error in the voltage reference is reflected in the outputs of the AD5737. Four possible sources of error must be considered when choosing a voltage reference for high accuracy applications: initial accuracy, long-term drift, temperature coefficient of the output voltage, and output voltage noise. Initial accuracy error on the output voltage of an external reference can lead to a full-scale error in the DAC. Therefore, to minimize these errors, a reference with a low initial accuracy error specification is preferred. Choosing a reference with an output trim adjustment, such as the ADR435, allows a system designer to trim out system errors by setting the reference voltage to a voltage other than the nominal. The trim adjustment can be used at any temperature to trim out any error. Long-term drift is a measure of how much the reference output voltage drifts over time. A reference with a tight long-term drift specification ensures that the overall solution remains relatively stable over its entire lifetime. The temperature coefficient of the reference output voltage affects INL, DNL, and TUE. Choose a reference with a tight temperature coefficient specification to reduce the dependence of the DAC output voltage on ambient temperature. In high accuracy applications, which have a relatively low noise budget, reference output voltage noise must be considered. Choosing a reference with as low an output noise voltage as practical for the system resolution required is important. Precision voltage references such as the ADR435 (XFET® design) produce low output noise in the 0.1 Hz to 10 Hz bandwidth. However, as the circuit bandwidth increases, filtering the output of the reference may be required to minimize the output noise. DRIVING INDUCTIVE LOADS When driving inductive or poorly defined loads, a capacitor may be required between the IOUT_x pin and the AGND pin to ensure stability. A 0.01 µF capacitor between IOUT_x and AGND ensures stability of a load of 50 mH. The capacitive component of the load may cause slower settling, although this may be masked by the settling time of the AD5737. There is no maximum capacitance limit for the current output of the AD5737. Table 39. Recommended Precision Voltage References Part No. ADR445 ADR02 ADR435 ADR395 AD586 Initial Accuracy (mV Maximum) ±2 ±3 ±2 ±5 ±2.5 Long-Term Drift (ppm Typical) 50 50 40 50 15 Rev. E | Page 41 of 45 Temperature Coefficient (ppm/°C Maximum) 3 3 3 9 10 0.1 Hz to 10 Hz Noise (µV p-p Typical) 2.25 10 8 8 4 AD5737 Data Sheet TRANSIENT VOLTAGE PROTECTION AD5737-to-ADSP-BF527 Interface The AD5737 contains ESD protection diodes that prevent damage from normal handling. The industrial control environment can, however, subject I/O circuits to much higher transients. To protect the AD5737 from excessively high voltage transients, external power diodes and a surge current limiting resistor (RP) are required, as shown in Figure 63. A typical value for RP is 10 Ω. The two protection diodes and the resistor (RP) must have appropriate power ratings. The AD5737 can be connected directly to the SPORT interface of the ADSP-BF527, an Analog Devices, Inc., Blackfin® DSP. Figure 64 shows how the SPORT interface can be connected to control the AD5737. (FROM DC-TO-DC CONVERTER) AD5737 SPORT_TFS SYNC SPORT_TSCLK SCLK SPORT_DT0 SDIN RFILTER ADSP-BF527 CFILTER 0.1µF GPIO0 VBOOST_x RP IOUT_x AGND Figure 64. AD5737-to-ADSP-BF527 SPORT Interface D1 AD5737 D2 LDAC 10067-080 10Ω LAYOUT GUIDELINES RLOAD 10067-079 CDCDC 4.7µF Figure 63. Output Transient Voltage Protection Further protection can be provided using transient voltage suppressors (TVSs), also referred to as transorbs. These components are available as unidirectional suppressors, which protect against positive high voltage transients, and as bidirectional suppressors, which protect against both positive and negative high voltage transients. Transient voltage suppressors are available in a wide range of standoff and breakdown voltage ratings. The TVS must be sized with the lowest breakdown voltage possible while not conducting in the functional range of the current output. Grounding In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5737 is mounted must be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5737 is in a system where multiple devices require an AGND-to-DGND connection, the connection must be made at one point only. The star ground point must be established as close as possible to the device. It is recommended that all field connected nodes be protected. The GNDSWx pin and the ground connection for the AVCC supply are referred to as PGND. PGND must be confined to certain areas of the board, and the PGND-to-AGND connection must be made at one point only. MICROPROCESSOR INTERFACING Supply Decoupling Microprocessor interfacing to the AD5737 is via a serial bus that uses a protocol compatible with microcontrollers and DSP processors. The communication channel is a 3-wire minimum interface consisting of a clock signal, a data signal, and a latch signal. The AD5737 requires a 24-bit data-word with data valid on the falling edge of SCLK. The AD5737 must have ample supply bypassing of 10 µF in parallel with 0.1 µF on each supply, located as close to the package as possible, ideally right up against the device. The 10 µF capacitors are the tantalum bead type. The 0.1 µF capacitors must have low effective series resistance (ESR) and low effective series inductance (ESL), such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. The DAC output update is initiated either on the rising edge of LDAC or, if LDAC is held low, on the rising edge of SYNC. The contents of the registers can be read using the readback function. Rev. E | Page 42 of 45 Data Sheet AD5737 Traces GALVANICALLY ISOLATED INTERFACE The power supply lines of the AD5737 must use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks must be shielded with digital ground to prevent radiating noise to other parts of the board and must never be run near the reference inputs. A ground line routed between the SDIN and SCLK traces helps reduce crosstalk between them (not required on a multilayer board that has a separate ground plane, but separating the lines helps). It is essential to minimize noise on the REFIN line because it couples through to the DAC output. In many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common-mode voltages that may occur. The Analog Devices iCoupler® products can provide voltage isolation in excess of 2.5 kV. The serial loading structure of the AD5737 makes it ideal for isolated interfaces because the number of interface lines is kept to a minimum. Figure 65 shows a 4-channel isolated interface to the AD5737 using an ADuM1411. For more information, visit www.analog.com. MICROCONTROLLER ADuM1411 SERIAL CLOCK OUT VIA SERIAL DATA OUT VIB SYNC OUT CONTROL OUT VIC VID ENCODE DECODE ENCODE DECODE ENCODE DECODE ENCODE DECODE VOA VOB VOC VOD TO SCLK TO SDIN TO SYNC TO LDAC DC-to-DC Converters Figure 65. 4-Channel Isolated Interface to the AD5737 To achieve high efficiency, good regulation, and stability, a well-designed printed circuit board layout is required. Follow these guidelines when designing printed circuit boards (see Figure 56): • • • • • • Keep the low ESR input capacitor, CIN, close to AVCC and PGND. Keep the high current path from CIN through the inductor (LDCDC) to SWx and PGND as short as possible. Keep the high current path from CIN through the inductor (LDCDC), the diode (DDCDC), and the output capacitor (CDCDC) as short as possible. Keep high current traces as short and as wide as possible. The path from CIN through the inductor (LDCDC) to SWx and PGND must be able to handle a minimum of 1 A. Place the compensation components as close as possible to the COMPDCDC_x pin. Avoid routing high impedance traces near any node connected to SWx or near the inductor to prevent radiated noise injection. Rev. E | Page 43 of 45 10067-081 Avoid crossover of digital and analog signals. Traces on opposite sides of the board must run at right angles to each other to reduce the effects of feedthrough on the board. A microstrip technique is by far the best method, but it is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground plane, and signal traces are placed on the solder side. AD5737 Data Sheet INDUSTRIAL HART CAPABLE ANALOG OUTPUT APPLICATION For transient overvoltage protection, a 24 V transient voltage suppressor (TVS) is placed on the IOUT/VOUT connection. For added protection, clamping diodes are connected from the IOUT_x/VOUT_x pin to the AVDD and GND power supply pins. A 5 kΩ current limiting resistor is also placed in series with the +VSENSE_x input. This is to limit the current to an acceptable level during a transient event. The recommended external band-pass filter for the AD5700 HART modem includes a 150 kΩ resistor, which limits current to a sufficiently low level to adhere to intrinsic safety requirements. In this case, the input has higher transient voltage protection and, therefore, does not require additional protection circuitry, even in the most demanding of industrial environments. Many industrial control applications have requirements for accurately controlled current output signals, and the AD5737 is ideal for such applications. Figure 66 shows the AD5737 in a circuit design for a HART-enabled output module, specifically for use in an industrial control application. The design provides for a HART-enabled current output, with the HART capability provided by the AD5700/AD5700-1 HART modem, the industry’s lowest power and smallest footprint HARTcompliant IC modem. For additional space-savings, the AD5700-1 offers a 0.5% precision internal oscillator. The HART_OUT signal from the AD5700 is attenuated and ac-coupled into the CHARTx pin of the AD5737. Such a configuration results in the AD5700 HART modem output modulating the 4 mA to 20 mA analog current without affecting the dc level of the current. This circuit adheres to the HART physical layer specifications as defined by the HART Communication Foundation. 10µF +15V +5V AVDD AVCC 0.1µF 2.7V TO 5.5V DVDD 10µF 0.1µF 10kΩ SW(X4) VBOOST(X4) IOUT B,C,D RESET ALERT CHART B,C,D FAULT CLEAR SYNC MCU AD5737 D2 SCLK RP IOUTA SDIN SDO UART INTERFACE D1 LDAC D3 4.20mA CURRENTLOOP RL DGND REFOUT REFIN CHART A GND 0.1µF 0.1µF TXD 22nF C1 47nF C2 VCC HART_OUT RXD RTS CD AD5700/AD5700-1 REF 1µF 1.2MQ 150kΩ ADC_IP 1.2MQ 300pF 150pF Figure 66. AD5737 in HART Configuration Rev. E | Page 44 of 45 10067-065 GND Data Sheet AD5737 OUTLINE DIMENSIONS 9.10 9.00 SQ 8.90 0.60 MAX 0.60 MAX 64 49 1 PIN 1 INDICATOR 48 PIN 1 INDICATOR 8.85 8.75 SQ 8.65 0.50 BSC 0.50 0.40 0.30 33 32 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.20 REF COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 06-13-2012-C SEATING PLANE 16 7.50 REF 0.80 MAX 0.65 TYP 12° MAX 17 BOTTOM VIEW TOP VIEW 1.00 0.85 0.80 7.25 7.10 SQ 6.95 EXPOSED PAD Figure 67. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm × 9 mm Body, Very Thin Quad (CP-64-3) Dimensions shown in millimeters ORDERING GUIDE Model1 AD5737ACPZ AD5737ACPZ-RL7 1 Resolution (Bits) 12 12 Temperature Range −40°C to +105°C −40°C to +105°C Z = RoHS Compliant Part. ©2011–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10067-0-9/14(E) Rev. E | Page 45 of 45 Package Description 64-Lead LFCSP_VQ 64-Lead LFCSP_VQ Package Option CP-64-3 CP-64-3
