24-Bit, 8.5 mW, 115 dB, 32 kHz ADC
AD7766-2-KGD
Known Good Die
FEATURES
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS
Low power PCI/USB data acquisition systems
Low power wireless acquisition systems
Vibration analysis
Instrumentation
High precision medical acquisition
AVDD AGND MCLK
VREF+
VIN+
SUCCESSIVE
APPROXIMATION
ADC
SERIAL INTERFACE
AND
CONTROL LOGIC
REFGND
CS
AD7766-2-KGD
SCLK DRDY SDO
SDI
Figure 1.
The AD7766-2-KGD includes an on-board digital filter (complete
with linear phase response) that acts to eliminate out-of-band
noise by filtering the oversampled input voltage. The oversampled
architecture also reduces front-end antialiasing requirements.
Other features of the AD7766-2-KGD include a SYNC/PD
(synchronization/power-down) pin that allows synchronizing
of multiple AD7766-2-KGD devices or that powers down
the AD7766-2-KGD. The addition of an SDI pin provides the
option of daisy chaining multiple AD7766-2-KGD devices.
The AD7766-2-KGD operates from a 2.5 V supply using a 5 V
reference. The device operates from −40°C to +105°C.
Additional application and technical information can be found
in the AD7766-2 data sheet.
Known Good Die (KGD): this die is fully guaranteed to data
sheet specifications.
RELATED DEVICES
Table 1. 24-Bit ADCs
The AD7766-2-KGD is a high performance, 24-bit, oversampled
SAR analog-to-digital converter (ADC). The AD7766-2-KGD
combines the benefits of a large dynamic range and input
bandwidth, consuming 8.5 mW power.
Part No.
AD7760
Rev. 0
DIGITAL
FIR FILTER
SYNC/PD
VIN–
GENERAL DESCRIPTION
Ideal for ultralow power data acquisition (such as PCI-based
and USB-based systems), the AD7766-2-KGD provides 24-bit
resolution. The combination of exceptional signal-to-noise ratio
(SNR), wide dynamic range, and outstanding dc accuracy make
the AD7766-2-KGD ideally suited for measuring small signal
changes over a wide dynamic range. This device is particularly
suitable for applications where small changes on the input are
measured on larger ac or dc signals. In such an application, the
AD7766-2-KGD accurately gathers both ac and dc information.
DVDD VDRIVE DGND
13806-001
Oversampled successive approximation (SAR) architecture
High performance ac and dc accuracy, low power 115.5 dB
typical dynamic range, 32 kHz output data rate (ODR)
−112 dB typical total harmonic distortion (THD)
Exceptionally low power
8.5 mW, 32 kHz ODR
High dc accuracy
24 bits, no missing codes (NMC)
Integral nonlinearity (INL): ±6 ppm (typical), ±15 ppm
(maximum)
Low temperature drift
Zero error drift: 15 nV/°C typical
Gain error drift: 0.4 ppm/°C typical
On-chip low-pass FIR filter
Linear phase response
Pass-band ripple: ±0.005 dB maximum
Stop-band attenuation: 100 dB minimum
2.5 V supply with 1.8 V/2.5 V/3 V/3.6 V logic interface options
Flexible interfacing options
Synchronization of multiple devices
Daisy-chain capability
Power-down function
Temperature range: −40°C to +105°C
AD7762/
AD7763
AD7764
AD7765
AD7767
AD7767-1
AD7767-2
1
Description
2.5 MSPS, 100 dB dynamic range,1 on-board differential
amp and reference buffer, parallel, variable decimation
625 kSPS, 109 dB dynamic range,1 on-board differential
amp and reference buffer, parallel/serial, variable
decimation
312 kSPS, 109 dB dynamic range,1 on-board differential
amp and reference buffer, variable decimation (pin)
156 kSPS, 112 dB dynamic range,1 on-board differential
amp and reference buffer, variable decimation (pin)
128 kSPS, 109.5 dB,1 15 mW, 18-bit INL, serial interface
64 kSPS 112.5 dB,1 10.5 mW, 18-bit INL, serial interface
32 kSPS, 115.5 dB,1 8.5 mW, 18-bit INL, serial interface
Dynamic range at maximum output data rate.
Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD7766-2-KGD
Known Good Die
TABLE OF CONTENTS
Features .............................................................................................. 1
Timing Specifications ...................................................................5
Applications ....................................................................................... 1
Absolute Maximum Ratings ............................................................8
General Description ......................................................................... 1
ESD Caution...................................................................................8
Functional Block Diagram .............................................................. 1
Pin Configuration and Function Descriptions..............................9
Related Devices ................................................................................. 1
Outline Dimensions ....................................................................... 11
Revision History ............................................................................... 2
Die Specifications and Assembly Recommendations ........... 11
Specifications..................................................................................... 3
Ordering Guide .......................................................................... 11
REVISION HISTORY
1/16—Revision 0: Initial Version
Rev. 0 | Page 2 of 11
Known Good Die
AD7766-2-KGD
SPECIFICATIONS
AVDD = DVDD = 2.5 V ± 5%, VDRIVE = 1.8 V to 3.6 V, VREF+ = 5 V, MCLK = 1 MHz, common-mode input = VREF+/2, TA = −40°C to +105°C,
unless otherwise noted.
Table 2.
Parameter
OUTPUT DATA RATE (ODR)
ANALOG INPUT
Differential Input Voltage
Absolute Input Voltage
Test Conditions/Comments
Decimate by 32
VIN+ − VIN−
VIN+
Typ
−0.1
VIN−
Common-Mode Input Voltage
Input Capacitance
DYNAMIC PERFORMANCE
Dynamic Range
Signal-to-Noise Ratio (SNR)
Spurious-Free Dynamic Range (SFDR)
Total Harmonic Distortion (THD)
Intermodulation Distortion (IMD)
Second-Order Terms
Third-Order Terms
DC ACCURACY
Resolution
Differential Nonlinearity
Integral Nonlinearity
Zero Error
Gain Error
Zero Error Drift
Gain Error Drift
Common-Mode Rejection Ratio
DIGITAL FILTER RESPONSE
Group Delay
Settling Time (Latency)
Pass-Band Ripple
Pass Band
−3 dB Bandwidth
Stop-Band Frequency
Stop-Band Attenuation
REFERENCE INPUT
VREF+ Input Voltage
DIGITAL INPUTS (Logic Levels)
Logic Low Voltage (VIL)
Logic High Voltage (VIH)
Input Leakage Current
Input Capacitance
Master Clock Rate
Serial Clock Rate
DIGITAL OUTPUTS
Data Format
Logic Low Voltage (VOL)
Logic High Voltage(VOH)
Min
−0.1
VREF+/2 − 5%
Decimate by 32, ODR = 32 kHz
Shorted inputs
Full-scale input amplitude, 1 kHz tone
Full-scale input amplitude, 1 kHz tone
Full-scale input amplitude, 1 kHz tone
Tone A = 11.7 kHz, Tone B = 12.3 kHz
114
112
VREF+/2
22
115.5
113.5
−128
−112
Max
32
Unit
kHz
±VREF+
+VREF+ + 0.1
V p-p
V
+VREF+ + 0.1
VREF+/2 + 5%
V
V
pF
−116
−103
−137
−108
For all devices
No missing codes
Guaranteed monotonic to 24 bits
16-bit linearity
24
Bits
50 Hz tone
±6
20
0.0075
15
0.4
−110
Complete settling
37/ODR
74/ODR
±15
0.075
±0.005
0.453 × ODR
0.49 × ODR
0.547 × ODR
100
µs
µs
dB
Hz
Hz
Hz
dB
2 × AVDD
V
−0.3
0.7 × VDRIVE
+0.3 × VDRIVE
VDRIVE + 0.3
±1
V
V
µA/pin
pF
MHz
Hz
1.024
1/t8
Rev. 0 | Page 3 of 11
ppm
µV
% FS
nV/°C
ppm/°C
dB
2.4
5
Serial 24 bits, twos complement (MSB first)
Sink current (ISINK) = +500 µA
Source current (ISOURCE) = −500 µA
dB
dB
dB
dB
dB
dB
dB
0.4
VDRIVE − 0.3
V
V
AD7766-2-KGD
Parameter
POWER REQUIREMENTS
AVDD
DVDD
VDRIVE
CURRENT SPECIFICATIONS
Operational Current
Analog Quiescent Current (AIDD)
Digital Quiescent Current (DIDD)
Reference Current (IREF)
Static Current with MCLK Stopped
AIDD
DIDD
Power-Down Mode Current
AIDD
DIDD
POWER DISSIPATION
Operational Power
Known Good Die
Test Conditions/Comments
Min
Typ
1.7
±5%
±5%
Max
Unit
2.5
2.5
2.5
3.6
V
V
V
1.3
1.37
0.35
1.5
1.86
0.425
mA
mA
mA
0.9
1
1
93
mA
µA
0.1
1
6
93
µA
µA
8.5
10.5
mW
MCLK = 1.024 MHz
32 kHz output data rate
MCLK = 1.024 MHz
32 kHz output data rate
Rev. 0 | Page 4 of 11
Known Good Die
AD7766-2-KGD
TIMING SPECIFICATIONS
AVDD = DVDD = 2.5 V ± 5%, VDRIVE = 1.7 V to 3.6 V, VREF+ = 5 V, common-mode input = VREF+/2, TA = −40°C (TMIN) to +105°C (TMAX),
unless otherwise noted. Sample tested during initial release to ensure compliance. All input signals are specified with rise time (tR) = fall
time (tF) = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.7 V.
Table 3.
Parameter
DRDY OPERATION
t1
t2 1
t3 1
t4
t5
tREAD
tDRDY
READ OPERATION
t6
t7
t8
t9
t10
t11
tSCLK
t12
t13
READ OPERATION WITH CS LOW
t14
t15
DAISY-CHAIN OPERATION
t16
t17
SYNC/PD OPERATION
t18
t19
t20
t21
tSETTLING
1
Limit at tMIN, tMAX
Unit
510
100
900
71
492
tDRDY − t5
ns typ
ns min
ns max
ns typ
ns typ
ns typ
Description
See Figure 2
MCLK rising edge to DRDY falling edge
MCLK high pulse width
MCLK low pulse width
MCLK rising edge to DRDY rising edge
DRDY pulse width
DRDY low period, read data during this period
32 × tMCLK
ns typ
DRDY period
0
6
60
50
25
24
10
10
10
1/t8
6
0
ns min
ns max
ns max
ns max
ns max
ns max
ns min
ns min
ns min
sec min
ns max
ns min
See Figure 3 and Figure 4
DRDY falling edge to CS setup time
CS falling edge to SDO tristate disabled
Data access time after SCLK falling edge (VDRIVE = 1.7 V)
Data access time after SCLK falling edge (VDRIVE = 2.3 V)
Data access time after SCLK falling edge (VDRIVE = 2.7 V)
Data access time after SCLK falling edge (VDRIVE = 3.0 V)
SCLK falling edge to data valid hold time (VDRIVE = 3.6 V)
SCLK high pulse width
SCLK low pulse width
Minimum SCLK period (not shown in the timing figures)
Bus relinquish time after CS rising edge
CS rising edge to DRDY rising edge
0
0
ns min
ns max
See Figure 3
DRDY falling edge to data valid setup time
DRDY rising edge to data valid hold time
1
2
ns min
ns max
1
20
1
510
2357
ns typ
ns typ
ns min
ns typ
tMCLK
See Figure 5
SDI valid to SCLK falling edge setup time
SCLK falling edge to SDI valid hold time
See Figure 6
SYNC/PD falling edge to MCLK rising edge
MCLK rising edge to DRDY rising edge going into SYNC/PD mode
SYNC/PD rising edge to MCLK rising edge
MCLK rising edge to DRDY falling edge coming out of SYNC/PD mode
Filter settling time (in MCLK periods) after a reset or power-down
t2 and t3 allow a ~90% to 10% duty cycle to be used for the MCLK input, where the minimum is 10% for the clock high time and 90% for MCLK low time. The maximum
MCLK frequency is 1.024 MHz.
Rev. 0 | Page 5 of 11
AD7766-2-KGD
Known Good Die
Timing Diagrams
t2
8×n
1
MCLK
t3
1
8×n
t4
t1
t5
t5
13806-002
tREAD
DRDY
tDRDY
Figure 2. DRDY vs. MCLK Timing Diagram, n = 4 (Decimate by 32)
tDRDY
tREAD
DRDY
t13
t6
CS
t10
1
t8
t7
SDO
23
t11
t9
t12
MSB
D22
D21
D20
D1
LSB
23
24
13806-003
SCLK
Figure 3. Serial Timing Diagram, Reading Data Using CS
CS = 0
tDRDY
tREAD
DRDY
t14
t10
1
t8
SDO
DATA
INVALID
MSB
D22
t11
t9
D21
D20
t15
D1
Figure 4. Serial Timing Diagram, Reading Data Setting CS Logic Low
Rev. 0 | Page 6 of 11
LSB
DATA
INVALID
13806-004
SCLK
Known Good Die
AD7766-2-KGD
1
MCLK
DRDY (A)
CS
MSB (A)
SDO (A)
LSB (A) MSB (B)
LSB (B) MSB (C)
LSB (C)
LSB (B) MSB (C)
LSB (C) MSB (D)
LSB (D)
SCLK
MSB (B)
SDI (A) = SDO (B)
t17
13806-015
t16
Figure 5. Daisy-Chain SDI Setup and Hold Timing
PART OUT OF POWER-DOWN
FILTER RESET
BEGINS SAMPLING
PART IN POWER-DOWN
MCLK (I)
A
B
t18
C
D
t20
SYNC/PD (I)
t21
t19
SDO (O)
VALID DATA
INVALID DATA
Figure 6. Reset, Synchronization, and Power-Down Timing
Rev. 0 | Page 7 of 11
VALID DATA
13806-005
tSETTLING
DRDY (O)
AD7766-2-KGD
Known Good Die
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
AVDD to AGND
DVDD to DGND
AVDD to DVDD
VREF+ to REFGND
REFGND to AGND
VDRIVE to DGND
VIN+, VIN− to AGND
Digital Inputs to DGND
Digital Outputs to DGND
AGND to DGND
Input Current to Any Pin Except Supplies 1
Operating Temperature Range
Storage Temperature Range
Junction Temperature
Electrostatic Discharge (ESD)
1
Rating
−0.3 V to +3 V
−0.3 V to +3 V
−0.3 V to +0.3 V
−0.3 V to +7 V
−0.3 V to +0.3 V
−0.3 V to +6 V
−0.3 V to VREF+ + 0.3 V
−0.3 V to VDRIVE + 0.3 V
−0.3 V to VDRIVE + 0.3 V
−0.3 V to +0.3 V
±10 mA
−40°C to +105°C
−65°C to +150°C
150°C
1 kV
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Transient currents of up to 100 mA do not cause SCR latch-up.
Rev. 0 | Page 8 of 11
Known Good Die
AD7766-2-KGD
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
23 22
21
20
1
19
2
18
17
3
4
16
5a
5b
15
14
13
12
6
7
8
9
10
13806-007
11
Figure 7. Pad Configuration
Table 5. Pad Function Descriptions
Pad No.
1
X-Axis (μm)
−773
Y-Axis (μm)
+1064
Mnemonic
REFGND
Pad Type
Single
2
−773
+916
REFGND
Single
3
4
5a
5b
6
−773
−773
−773
−773
−561
+600
+426
+93
+18
−1326
VIN+
VIN−
AGND
AGND
SYNC/PD
Single
Single
Double
Double
Single
Description
Reference Ground. Ground connection for the reference voltage.
Decouple the input reference voltage (VREF+) to this pin.
Reference Ground. Ground connection for the reference voltage.
Decouple the input reference voltage (VREF+) to this pin.
Positive Input of the Differential Analog Input.
Negative Input of the Differential Analog Input.
Power Supply Ground for Analog Circuitry.
Power Supply Ground for Analog Circuitry.
Synchronization (SYNC) Pin. The SYNC pin can synchronize multiple
AD7766-2-KGD devices.
Power-Down Input Pin (PD). The PD pin puts the AD7766-2-KGD
device into power-down mode
Rev. 0 | Page 9 of 11
AD7766-2-KGD
Known Good Die
Pad No.
7
X-Axis (µm)
−353
Y-Axis (µm)
−1319
Mnemonic
DVDD
Pad Type
Single
8
−141
−1317
DVDD
Single
9
+105
−1340
VDRIVE
Single
10
+601
−1336
VDRIVE
Single
11
+799
−1161
SDO
Double
12
13
14
15
+784
+784
+784
+800
−944
−826
−677
−517
DGND
DGND
DGND
DRDY
Single
Single
Single
Single
16
+800
+363
SCLK
Single
17
+800
+663
MCLK
Single
18
19
+800
+800
+850
+1051
SDI
CS
Single
Single
20
21
22
−125
−333
−561
+1319
+1319
+1317
AVDD
AVDD
VREF+
Single
Single
Single
23
−667
+1317
VREF+
Single
Description
Digital Power Supply Input, 2.5 V. In cases where a logic voltage of
2.5 V for interfacing is used (2.5 V applied to VDRIVE pin), the DVDD and
VDRIVE pins can be connected to the same voltage supply rail.
Digital Power Supply Input, 2.5 V. In cases where a logic voltage of
2.5 V for interfacing is used (2.5 V applied to VDRIVE pin), the DVDD and
VDRIVE pins can be connected to the same voltage supply rail.
Logic Power Supply Input, 1.8 V to 3.6 V. The voltage supplied at this
pin determines the operating voltage of the digital logic interface.
Logic Power Supply Input, 1.8 V to 3.6 V. The voltage supplied at this
pin determines the operating voltage of the digital logic interface.
Serial Data Output. The conversion result from the AD7766-2-KGD is
output on the SDO pin as a 24-bit, twos complement, MSB first, serial
data stream.
Digital Logic Power Supply Ground.
Digital Logic Power Supply Ground.
Digital Logic Power Supply Ground.
Data Ready Output. A falling edge on the DRDY signal indicates that
a new conversion data result is available in the output register of the
AD7766-2-KGD.
Serial Clock Input. The SCLK input provides the serial clock for all
serial data transfers with AD7766-2-KGD devices.
Master Clock Input. The sampling frequency of the AD7766-2-KGD is
equal to the MCLK frequency.
Serial Data Input. This pin is the daisy-chain input of the AD7766-2-KGD.
Chip Select Input. The CS input selects a specific AD7766-2-KGD
device and acts as an enable on the SDO pin. In cases where CS is
used, the MSB of the conversion result is clocked onto the SDO line
on the CS falling edge. The CS input allows multiple AD7766-2-KGD
devices to share the same SDO line. This function allows the user to
select the appropriate device by supplying it with a logic low CS
signal, which enables the SDO pin of the concerned device.
Analog Power Supply, 2.5 V.
Analog Power Supply, 2.5 V.
Reference Input for the AD7766-2-KGD. Apply an external reference
to this input pin. The VREF+ input ranges from 2.4 V to 5 V. The
reference voltage input is independent of the voltage magnitude
applied to the AVDD pin.
Reference Input for the AD7766-2-KGD. Apply an external reference
to this input pin. The VREF+ input ranges from 2.4 V to 5 V. The
reference voltage input is independent of the voltage magnitude
applied to the AVDD pin.
Rev. 0 | Page 10 of 11
Known Good Die
AD7766-2-KGD
OUTLINE DIMENSIONS
2.95
0.25
TOP VIEW
0.07 × 0.07
0.08
(CIRCUIT SIDE)
SIDE VIEW
11-03-2015-A
1.87
Figure 8. 23-Pad Bare Die [CHIP]
(C-23-1)
Dimensions shown in millimeters
DIE SPECIFICATIONS AND ASSEMBLY RECOMMENDATIONS
Table 6. Die Specifications
Parameter
Chip Size
Scribe Line Width
Die Size
Thickness
Backside
Passivation
Bond Pads (Minimum)
Bond Pad Composition
ESD
Value
2870 (x) × 1790 (y)
80 (x) × 80 (y)
2950 (x) × 1870 (y)
305
Bare silicon
Nitride
70 × 70
AlCu (0.5%)
1
Unit
μm
μm
μm
μm
Not applicable
Not applicable
μm
%
kV
Table 7. Assembly Recommendations
Assembly Component
Die Attach
Bonding Method
Bonding Sequence
Recommendation
No special recommendations
Gold ball or aluminum wedge
Pad 1 and Pad 2 first
ORDERING GUIDE
Model
AD7766-2-KGD-WP
Temperature Range
−40°C to +105°C
Package Description
23-Pad Bare Die [CHIP], Waffle Pack
©2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13806-0-1/16(0)
Rev. 0 | Page 11 of 11
Package Option
C-23-1