>10 W, GaN Power Amplifier,
0.01 GHz to 1.1 GHz
HMC1099
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
1
2
3
4
5
6
7
8
HMC1099
Extended battery operation for public mobile radios
Power amplifier stage for wireless infrastructures
Test and measurement equipment
Commercial and military radars
General-purpose transmitter amplification
GND
NIC
NIC
NIC
NIC
NIC
NIC
GND
APPLICATIONS
24
23
22
21
20
19
18
17
GND
NIC
NIC
RFOUT/VDD
RFOUT/VDD
NIC
NIC
GND
PACKAGE
BASE
NIC = NO INTERNAL CONNECTION. THESE PINS
ARE NOT CONNECTED INTERNALLY.
13525-001
GND
NIC
NIC
RFIN/VGG
RFIN/VGG
NIC
NIC
GND
9
10
11
12
13
14
15
16
High saturated output power (PSAT): 40.5 dBm typical
High small signal gain: 18.5 dB typical
High power added efficiency (PAE): 69% typical
Instantaneous bandwidth: 0.01 GHz to 1.1 GHz
Supply voltage: VDD = 28 V at 100 mA
Internal prematching
Simple and compact external tuning for optimal
performance
32-lead, 5 mm × 5 mm, LFCSP package: 25 mm2
32 GND
31 NIC
30 NIC
29 NIC
28 NIC
27 NIC
26 NIC
25 GND
FEATURES
Figure 1.
GENERAL DESCRIPTION
The HMC1099 is a gallium nitride (GaN), broadband power
amplifier delivering >10 W with up to 69% PAE across an
instantaneous bandwidth of 0.01 GHz to 1.1 GHz, and with a
±0.5 dB typical gain flatness.
The HMC1099 is ideal for pulsed or continuous wave (CW)
applications, such as wireless infrastructure, radars, public
mobile radios, and general-purpose amplification.
The HMC1099 amplifier is externally tuned using low cost,
surface-mount components and is available in a compact
LFCSP package.
Multifunction pin names may be referenced by their relevant
function only.
Rev. 0
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Technical Support
www.analog.com
HMC1099
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Interface Schematics .....................................................................6
Applications ....................................................................................... 1
Typical Performance Characteristics ..............................................7
General Description ......................................................................... 1
Theory of Operation ...................................................................... 13
Functional Block Diagram .............................................................. 1
Applications Information .............................................................. 14
Revision History ............................................................................... 2
Typical Application Circuit ....................................................... 14
Specifications..................................................................................... 3
Evaluation PCB ........................................................................... 15
Electrical Specifications ............................................................... 3
Bill of Materials ........................................................................... 15
Total Supply Current by VDD ....................................................... 4
Outline Dimensions ....................................................................... 16
Absolute Maximum Ratings ............................................................ 5
Ordering Guide .......................................................................... 16
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
REVISION HISTORY
1/16—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
Data Sheet
HMC1099
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
TA = 25°C, VDD = 28 V, IDD = 100 mA, frequency range = 0.01 GHz to 0.4 GHz.
Table 1.
Parameter
FREQUENCY RANGE
GAIN
Small Signal Gain
Gain Flatness
RETURN LOSS
Input
Output
POWER
Output Power for 4 dB Compression
Power Gain for P4dB Compression
Saturated Output Power
Power Gain for PSAT
Power Added Efficiency
OUTPUT THIRD-ORDER INTERCEPT
NOISE FIGURE
TOTAL SUPPLY CURRENT
Symbol
Min
0.01
Typ
18
20
±1
dB
dB
12
15
dB
dB
40
15
40.5
13
73
49
8
100
dBm
dB
dBm
dB
%
dBm
dB
mA
P4dB
PSAT
PAE
IP3
IDD
Max
0.4
Unit
GHz
Test Conditions/Comments
>10 W saturated output power
Measurement taken at POUT/tone = 30 dBm
Adjust the gate bias control voltage (VGG) between
−8 V to 0 V to achieve an IDD = 100 mA typical
TA = 25°C, VDD = 28 V, IDD = 100 mA, frequency range = 0.4 GHz to 0.7 GHz.
Table 2.
Parameter
FREQUENCY RANGE
GAIN
Small Signal Gain
Gain Flatness
RETURN LOSS
Input
Output
POWER
Output Power for 4 dB Compression
Power Gain for P4dB Compression
Saturated Output Power
Power Gain for PSAT
Power Added Efficiency
OUTPUT THIRD-ORDER INTERCEPT
NOISE FIGURE
TOTAL SUPPLY CURRENT
Symbol
P4dB
PSAT
PAE
IP3
IDD
Min
0.4
Typ
Max
0.7
16.5
18.5
±0.25
dB
dB
9.5
14
dB
dB
40.5
14
40.5
13
69
48
5.5
100
dBm
dB
dBm
dB
%
dBm
dB
mA
Rev. 0 | Page 3 of 16
Unit
GHz
Test Conditions/Comments
>10 W saturated output power
Measurement taken at POUT/tone = 30 dBm
Adjust the gate bias control voltage (VGG) between
−8 V to 0 V to achieve an IDD = 100 mA typical
HMC1099
Data Sheet
TA = 25°C, VDD = 28 V, IDD = 100 mA, frequency range = 0.7 GHz to 1.1 GHz.
Table 3.
Parameter
FREQUENCY RANGE
GAIN
Small Signal Gain
Gain Flatness
RETURN LOSS
Input
Output
POWER
Output Power for 4 dB Compression
Power Gain for P4dB Compression
Saturated Output Power
Power Gain for PSAT
Power Added Efficiency
OUTPUT THIRD-ORDER INTERCEPT
NOISE FIGURE
TOTAL SUPPLY CURRENT
Symbol
Min
0.7
Typ
16.5
18.5
±0.5
dB
dB
12
17
dB
dB
41.5
14
41.5
13.5
69
47
5
100
dBm
dB
dBm
dB
%
dBm
dB
mA
P4dB
PSAT
PAE
IP3
IDD
Max
1.1
Unit
GHz
Test Conditions/Comments
>10 W saturated output power
Measurement taken at POUT/tone = 30 dBm
Adjust the gate bias control voltage (VGG) between
−8 V to 0 V to achieve an IDD = 100 mA typical
TOTAL SUPPLY CURRENT BY VDD
Table 4.
Parameter
SUPPLY CURRENT
VDD = 24 V
VDD = 28 V
Symbol
IDD
Min
Typ
100
100
Max
Unit
Test Conditions/Comments
Adjust the gate bias control voltage (VGG) between −8 V to 0 V to achieve an
IDD = 100 mA typical
mA
mA
Rev. 0 | Page 4 of 16
Data Sheet
HMC1099
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter1
Drain Bias Voltage (VDD)
Gate Bias Voltage (VGG)
Radio Frequency (RF) Input Power (RFIN)
Maximum Forward Gate Current
Maximum Voltage Standing Wave Ratio
(VSWR)2
Channel Temperature
Maximum Peak Reflow Temperature (MSL3)3
Continuous Power Dissipation, PDISS (TA = 85°C,
Derate 89 mW/°C Above 85°C)
Thermal Resistance (Junction to Back of
Paddle)
Storage Temperature Range
Operating Temperature Range
ESD Sensitivity (Human Body Model)
Rating
32 V dc
−8 V to 0 V dc
33 dBm
4 mA
6:1
225°C
260°C
12.5 W
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
11.2°C/W
−55°C to +150°C
−40°C to +85°C
Class 1B,
passed 500 V
When referring to a single function of a multifunction pin in the parameters,
only the portion of the pin name that is relevant to the Absolute Maximum
Rating is listed. For full pin names of multifunction pins, refer to the Pin
Configuration and Function Descriptions section.
2
Restricted by maximum power dissipation.
3
See the Ordering Guide for additional information.
1
Rev. 0 | Page 5 of 16
HMC1099
Data Sheet
32 GND
31 NIC
30 NIC
29 NIC
28 NIC
27 NIC
26 NIC
25 GND
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
HMC1099
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
GND
NIC
NIC
RFOUT/VDD
RFOUT/VDD
NIC
NIC
GND
NOTES
1. EXPOSED PAD. EXPOSED PAD MUST
BE CONNECTED TO RF/DC GROUND.
2. NO INTERNAL CONNECTION. THESE PINS
ARE NOT CONNECTED INTERNALLY.
13525-002
GND 9
NIC 10
NIC 11
NIC 12
NIC 13
NIC 14
NIC 15
GND 16
GND
NIC
NIC
RFIN/VGG
RFIN/VGG
NIC
NIC
GND
Figure 2. Pin Configuration
Table 6. Pad Function Descriptions
Pin No.
1, 8, 9, 16, 17, 24, 25, 32
2, 3, 6, 7, 10 to 15, 18,
19, 22, 23, 26 to 31
4, 5
Mnemonic
GND
NIC
20, 21
RFOUT/VDD
RFIN/VGG
EPAD
Description
Ground. These pins must be connected to RF/dc ground. See Figure 3 for the GND interface schematic.
No Internal Connection. These pins are not connected internally. However, all data was measured
with these pins connected to RF/dc ground externally.
RF Input (RFIN)/Gate Bias Control Voltage (VGG). This pin is a multifunction pin. The RFIN/VGG pin is
dc-coupled with internal prematching and requires external matching to 50 Ω, as shown in Figure 38.
See Figure 4 for the RFIN/VGG interface schematic.
RF Output (RFOUT)/Drain Bias Voltage (VDD). This is a multifunction pin. The RFOUT/VDD pin is dc-coupled
and requires external matching to 50 Ω, as shown in Figure 38. See Figure 4 for the RFOUT/VDD interface
schematic.
Exposed Pad. The exposed pad must be connected to RF/dc ground.
INTERFACE SCHEMATICS
RFIN/VGG
Figure 3. GND Interface
13525-004
GND
13525-003
RFOUT/VDD
Figure 4. RFIN/VGG and RFOUT/VDD Interface
Rev. 0 | Page 6 of 16
Data Sheet
HMC1099
TYPICAL PERFORMANCE CHARACTERISTICS
30
25
20
21
GAIN (dB)
RESPONSE (dB)
10
0
–10
17
13
–20
9
0
0.2
0.4
1.0
0.8
0.6
1.2
1.4
FREQUENCY (GHz)
5
13525-005
–40
0
0.2
0.4
0.6
0.8
1.0
1.2
FREQUENCY (GHz)
Figure 5. Response (Gain and Return Loss) vs. Frequency
13525-008
+85°C
+25°C
–40°C
S11
S21
S22
–30
Figure 8. Gain vs. Frequency at Various Temperatures
0
0
+85°C
+25°C
–40°C
–5
–5
RETURN LOSS (dB)
RETURN LOSS (dB)
–10
–10
–15
–15
–20
–25
–30
–20
0.2
0.4
0.6
0.8
1.0
1.2
FREQUENCY (GHz)
–40
0
21
17
17
GAIN (dB)
21
13
0.2
0.4
0.6
0.8
1.0
FREQUENCY (GHz)
1.2
0.8
1.0
1.2
13
9
24V
28V
13525-007
GAIN (dB)
25
0
0.6
Figure 9. Output Return Loss vs. Frequency at Various Temperatures
25
5
0.4
FREQUENCY (GHz)
Figure 6. Input Return Loss vs. Frequency at Various Temperatures
9
0.2
Figure 7. Gain vs. Frequency at Various Supply Voltages
150mA
100mA
50mA
5
0
0.2
0.4
0.6
0.8
1.0
FREQUENCY (GHz)
Figure 10. Gain vs. Frequency at Various Supply Currents
Rev. 0 | Page 7 of 16
1.2
13525-010
0
13525-006
–25
13525-009
+85°C
+25°C
–40°C
–35
HMC1099
Data Sheet
44
45
43
40
41
P4dB (dBm)
40
39
38
30
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
FREQUENCY (GHz)
25
13525-011
36
Figure 11. Power Output (POUT ) vs. Frequency
0
0.1
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
FREQUENCY (GHz)
Figure 14. Output Power for 4 dB Compression (P4dB) vs. Frequency at
Various Temperatures
45
40
40
PSAT (dBm)
45
35
35
30
30
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
FREQUENCY (GHz)
25
13525-012
25
0
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
FREQUENCY (GHz)
Figure 12. Output Power for 4 dB Compression (P4dB) vs. Frequency at
Various Supply Voltages
Figure 15. Saturated Output Power (PSAT) vs. Frequency at
Various Temperatures
45
40
40
P4dB (dBm)
45
35
0.1
13525-015
+85°C
+25°C
–40°C
24V
28V
30
35
30
150mA
100mA
50mA
24V
28V
25
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
FREQUENCY (GHz)
Figure 13. Saturated Output Power (PSAT) vs. Frequency at
Various Supply Voltages
1.1
25
13525-013
PSAT (dBm)
0.2
13525-014
+85°C
+25°C
–40°C
P4dB
PIN = 27dBm
PSAT
37
P4dB (dBm)
35
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
FREQUENCY (GHz)
0.8
0.9
1.0
1.1
13525-016
POUT (dBm)
42
Figure 16. Output Power for 4 dB Compression (P4dB) vs. Frequency at
Various Supply Currents
Rev. 0 | Page 8 of 16
Data Sheet
HMC1099
45
20
16
POWER GAIN (dB)
PSAT (dBm)
40
35
12
8
30
4
0.1
0.3
0.2
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
FREQUENCY (GHz)
0
0
0.1
52
49
49
IP3 (dBm)
52
46
+85°C
+25°C
–40°C
0.6
0.7
0.8
0.9
1.0
1.1
46
43
24V
28V
40
0.4
0.6
0.8
1.0
FREQUENCY (GHz)
40
13525-018
IP3 (dBm)
55
0.2
0.5
Figure 20. Power Gain vs. Frequency
55
0
0.4
FREQUENCY (GHz)
Figure 17. Saturated Output Power (PSAT) vs. Frequency at
Various Supply Currents
43
0.3
0.2
0
0.2
0.4
0.6
1.0
0.8
FREQUENCY (GHz)
Figure 18. Output Third-Order Intercept (IP3) vs. Frequency at
Various Temperatures, POUT/Tone = 30 dBm
13525-021
0
13525-017
25
P4dB
PIN = 27dBm
PSAT
13525-020
150mA
100mA
50mA
Figure 21. Output Third-Order Intercept (IP3) vs. Frequency at
Various Supply Voltages, POUT/Tone = 30 dBm
65
55
1GHz
0.5GHz
0.1GHz
60
52
50
IM3 (dBc)
49
46
45
40
35
150mA
100mA
50mA
30
40
0
0.2
0.4
0.6
0.8
1.0
FREQUENCY (GHz)
Figure 19. Output Third-Order Intercept (IP3) vs. Frequency at
Various Supply Currents, POUT/Tone = 30 dB
25
10
12
14
16
18
20
22
24
26
28
30
POUT/TONE (dBm)
Figure 22. Output Third-Order Intermodulation (IM3) vs.
POUT/TONE at VDD = 24 V
Rev. 0 | Page 9 of 16
32
13525-022
43
13525-019
IP3 (dBm)
55
HMC1099
Data Sheet
90
80
POUT (dBm), GAIN (dB), PAE (%)
55
45
40
35
30
14
16
18
20
22
24
26
28
30
32
POUT/TONE (dBm)
POUT
GAIN
PAE
IDD
40
400
30
300
20
200
10
100
12
16
20
24
28
INPUT POWER (dBm)
Figure 24. Power Output (POUT), GAIN, Power Added Efficiency (PAE), and
Total Supply Current (IDD) vs. Input Power at 0.5 GHz
20
200
10
100
0
4
8
12
16
20
24
28
850
POUT
GAIN
PAE
IDD
750
650
50
550
40
450
30
350
20
250
10
150
50
0
4
0
8
12
16
20
24
28
INPUT POWER (dBm)
Figure 27. Power Output (POUT), GAIN, Power Added Efficiency (PAE), and
Total Supply Current (IDD) vs. Input Power at 1 GHz
90
0
80
–10
REVERSE ISOLATION (dB)
70
60
50
40
30
20
+85°C
+25°C
–40°C
10
0
0
0.1
0.2
0.3
–20
–30
–40
–50
+85°C
+25°C
–40°C
–60
0.4
0.5
0.6
0.7
0.8
0.9
1.0
FREQUENCY (GHz)
1.1
13525-025
PAE (%)
300
60
13525-024
0
8
30
70
POUT (dB), GAIN (dB), PAE (%)
500
4
400
80
600
50
0
40
Figure 26. Power Output (POUT), GAIN, Power Added Efficiency (PAE), and
Total Supply Current (IDD) vs. Input Power at 0.1 GHz
700
0
500
INPUT POWER (dBm)
IDD (mA)
POUT (dB), GAIN (dB), PAE (%)
60
50
0
800
70
600
0
Figure 23. Output Third-Order Intermodulation (IM3) vs.
POUT/TONE at VDD = 28 V
80
60
13525-027
12
13525-023
25
10
700
Figure 25. Power Added Efficiency (PAE) vs. Frequency at
Various Temperatures
–70
0
0.2
0.4
0.6
0.8
1.0
1.2
FREQUENCY (GHz)
Figure 28. Reverse Isolation vs. Frequency at Various Temperatures
Rev. 0 | Page 10 of 16
13525-028
IM3 (dBc)
50
70
800
IDD (mA)
60
900
POUT
GAIN
PAE
IDD
13525-026
1GHz
0.5GHz
0.1GHz
IDD (mA)
65
Data Sheet
HMC1099
45
GAIN
P4dB (dBm)
PSAT (dBm)
35
30
25
20
15
10
24
25
26
27
28
VDD (V)
Figure 29. Gain, Output Power for 4 dB Compression (P4dB), and Saturated
Output Power (PSAT) vs. Supply Voltage (VDD) at 0.5 GHz
GAIN
P4dB (dBm)
PSAT (dBm)
35
30
25
20
15
10
50
70
110
130
150
Figure 32. Gain, Output Power for 4 dB Compression (P4dB), and Saturated
Output Power (PSAT) vs. Supply Current (IDD) at 0.5 GHz
30
+85°C
+25°C
–40°C
24V
28V
25
SECOND HARMONIC (dBc)
25
20
15
10
5
20
15
10
0.2
0.4
0.6
0.8
1.0
FREQUENCY (GHz)
0
13525-030
0
Figure 30. Second Harmonic vs. Frequency at Various Temperatures
0
0.4
0.2
0.6
1.0
0.8
FREQUENCY (GHz)
13525-033
5
0
Figure 33. Second Harmonic vs. Frequency at Various Supply Voltages
30
10
1GHz
0.5GHz
0.1GHz
9
25
POWER DISSIPATION (W)
8
20
15
10
5dBm
10dBm
15dBm
20dBm
25dBm
0.2
0.4
0.6
FREQUENCY (GHz)
0.8
5
4
3
2
1
0
0
7
6
1.0
Figure 31. Second Harmonic vs. Frequency at Various Input Power Levels
Rev. 0 | Page 11 of 16
0
0
4
8
12
16
INPUT POWER (dBm)
20
24
28
13525-034
5
13525-031
SECOND HARMONIC (dBc)
90
IDD (mA)
30
SECOND HARMONIC (dBc)
40
13525-032
GAIN (dB), P4dB (dBm), PSAT (dBm)
40
13525-029
GAIN (dB), P4dB (dBm), PSAT (dBm)
45
Figure 34. Power Dissipation vs. Input Power at Various Frequencies
Data Sheet
12
10
10
8
6
4
+85°C
+25°C
–40°C
2
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
FREQUENCY (GHz)
Figure 35. Noise Figure vs. Frequency at Various Temperatures
8
6
4
24V
28V
32V
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
FREQUENCY (GHz)
13525-037
NOISE FIGURE (dB)
10
0
4
150mA
100mA
50mA
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
FREQUENCY (GHz)
Figure 37. Noise Figure vs. Frequency at Various Supply Currents
12
2
6
2
0
0
8
Figure 36. Noise Figure vs. Frequency at Various Supply Voltages
Rev. 0 | Page 12 of 16
13525-036
NOISE FIGURE (dB)
12
13525-035
NOISE FIGURE (dB)
HMC1099
Data Sheet
HMC1099
THEORY OF OPERATION
The HMC1099 is a >10 W, gallium nitride (GaN), power amplifier
that consists of a single gain stage that effectively operates like a
single field effect transistor (FET). The device is internally
prematched so that a simple, external matching network
optimizes the performance across the entire operating
frequency range. The recommended dc bias conditions put the
device in deep Class AB operation, resulting in high saturated
output power (40.5 dBm typical) at improved levels of power
efficiency (69% typical).
Rev. 0 | Page 13 of 16
HMC1099
Data Sheet
APPLICATIONS INFORMATION
The recommended power-down bias sequence follows:
The drain bias voltage is applied through the RFOUT/VDD pin,
and the gate bias voltage is applied through the RFIN/VGG pin.
For operation of a single application circuit across the entire
frequency range, it is recommended to use the external matching
components specified in the typical application circuit (L1, C1, L3,
and C8) shown in Figure 38. If operation is only required across
a narrower frequency range, performance may be optimized
additionally through the implementation of alternate matching
networks. Capacitive bypassing of VDD and VGG is recommended.
1.
2.
3.
4.
All measurements for this device were taken using the typical
application circuit, configured as shown in the assembly diagram
(see Figure 38). The bias conditions shown in the electrical
specifications table (see Table 1 to Table 3) are the operating
points recommended to optimize the overall performance.
Unless otherwise noted, the data shown was taken using the
recommended bias conditions. Operation of the HMC1099
under other bias conditions may provide performance that
differs from what is shown in the Typical Performance
Characteristics section.
The recommended power-up bias sequence follows:
1.
2.
3.
4.
5.
Turn off the RF signal.
Set VGG to −8 V to pinch off the drain current.
Set VDD to 0 V.
Set VGG to 0 V.
Connect to the GND pin.
Set VGG to −8 V to pinch off the drain current.
Set VDD to 28 V (drain current is pinched off).
Adjust VGG more positive (approximately −2.5 V to −3.0 V)
until a quiescent of IDD = 100 mA is obtained.
Apply the RF signal.
The evaluation printed circuit board (PCB) provides the HMC1099
in its typical application circuit, allowing easy operation using
standard dc power supplies and 50 Ω RF test equipment.
TYPICAL APPLICATION CIRCUIT
VDD
VGG
C6
10µF
C9
10µF
C7
10µF
C10
10µF
32
R1
68.1Ω
C2
2200pF
RFIN
C8
3.3pF
L3
5.6nH
30
29
28
27
26
25
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
10
11
12
13
14
15
C5
2200pF
L2
0.9µH
L1
5.4nH
C3
2200pF
RFOUT
C1
3.3pF
16
13525-038
C4
2200pF
31
Figure 38. Typical Application Circuit
Rev. 0 | Page 14 of 16
Data Sheet
HMC1099
EVALUATION PCB
13525-039
Use RF circuit design techniques for the circuit board used in
the application. Provide 50 Ω impedance for the signal lines and
directly connect the package ground leads and exposed paddle
to the ground plane, similar to that shown in Figure 39. Use a
sufficient number of via holes to connect the top and bottom
ground planes. The evaluation circuit board shown in Figure 39
is available from Analog Devices, Inc., upon request.
Figure 39. Evaluation Printed Circuit Board
BILL OF MATERIALS
Table 7. Bill of Materials for Evaluation PCB EV1HMC1099LP5D
Item
J2, J3
J1
J4
C1, C8
C2 to C5
C6, C7, C9, C10
L1
L2
L3
R1
U1
PCB
Description
SMA connectors
DC pin
Preform jumper
3.3 pF capacitors, 0603 package
2200 pF capacitors, 0603 package
10 µF capacitors, 1210 package
5.4 nH inductor, 0906 package
0.9 µH inductor, 1008 package
5.6 nH inductor, 0402 package
68.1 Ω resistor, 0603 package
HMC1099LP5DE
600-00625-00-2 evaluation PCB, circuit board material: Rogers 4350 or Arlon 25FR
Rev. 0 | Page 15 of 16
HMC1099
Data Sheet
OUTLINE DIMENSIONS
PIN 1
INDICATOR
0.30
0.25
0.18
PIN 1
INDICATOR
32
25
24
1
0.50
BSC
3.15
3.00 SQ
2.85
EXPOSED
PAD
8
17
TOP VIEW
6° BSC
SIDE VIEW
0.55
0.50
0.35
1.53
1.34
1.15
COPLANARITY
0.08
16
9
BOTTOM VIEW
3.50 REF
0.50 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
PKG-000000
SEATING
PLANE
08-06-2015-A
5.10
5.00 SQ
4.90
Figure 40. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body and 1.34 mm Package Height
(HCP-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1, 2
HMC1099LP5DE
Temperature
−40°C to +85°C
MSL Rating 3
MSL3
Description 4
32-Lead Lead Frame Chip Scale Package [LFCSP]
Package Option
HCP-32-2
HMC1099LP5DETR
−40°C to +85°C
MSL3
32-Lead Lead Frame Chip Scale Package [LFCSP]
HCP-32-2
EV1HMC1099LP5D
Evaluation PCB
The HMC1099LP5DE and the HMC1099LP5DETR are LFCSP premolded copper alloy lead frame and RoHS Compliant.
When ordering the evaluation board only, reference the model number, EV1HMC1099LP5D.
3
See the Absolute Maximum Ratings section for additional information.
4
The lead finish of the HMC1099LP5DE and the HMC1099LP5DETR are nickel palladium gold (NiPdAu).
5
The 4-digit lot number for the HMC1099LP5DE and the HMC1099LP5DETR are represented by XXXX.
1
2
©2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13525-0-1/16(0)
Rev. 0 | Page 16 of 16
Branding 5
H1099
XXXX
H1099
XXXX