Ultralow Distortion, High Speed
0.95 nV/Hz Voltage Noise Op Amp
AD8099
FEATURES
APPLICATIONS
Ultralow noise: 0.95 nV/√Hz, 2.6 pA/√Hz
Ultralow distortion
2nd harmonic RL = 1 kΩ , G = +2
−92 dB @ 10 MHz
3rd harmonic RL = 1 kΩ , G = +2
−105 dB @ 10 MHz
High speed
GBWP: 3.8 GHz
–3 dB bandwidth:
700 MHz (G = +2)
550 MHz (G = +10)
Slew rate:
475 V/μs (G = +2)
1350 V/μs (G = +10)
New pinout
Custom external compensation, gain range –1, +2 to +10
Supply current: 15 mA
Offset voltage: 0.5 mV max
Wide supply voltage range: 5 V to 12 V
Pre-amplifiers
Receivers
Instrumentation
Filters
IF and baseband amplifiers
A-to-D drivers
DAC buffers
Optical electronics
FEEDBACK 1
8
DISABLE
VOUT
–IN 2
7
+VS
6
CC
+IN 3
6
VOUT
5
–VS
–VS 4
5
CC
DISABLE 1
8
+VS
FEEDBACK 2
7
–IN 3
+IN 4
NOTES
1. SOLDER THE EXPOSED PADDLE TO
THE GROUND PLANE.
Figure 1. 8-Lead LFCSP (CP-8-2)
NOTES
1. SOLDER THE EXPOSED PADDLE TO
THE GROUND PLANE.
Figure 2. 8-Lead SOIC-EP (RD-8-1)
GENERAL DESCRIPTION
The AD8099 drives 100 Ω loads at breakthrough performance
levels with only 15 mA of supply current. With the wide supply
voltage range (5 V to 12 V), low offset voltage (0.1 mV typ),
wide bandwidth (700 MHz for G = +2), and a GBWP up to
3.8 GHz, the AD8099 is designed to work in a wide variety of
applications.
Rev. D
–40
G = +2
= 2V p-p
V
–50 VOUT
S = ±5V
RL = 1k
–60
–70
–80
–90
–100
–110
–120
–130
0.1
SOLID LINE – SECOND HARMONIC
DOTTED LINE – THIRD HARMONIC
1.0
FREQUENCY (MHz)
10.0
04511-A-013
The AD8099 features external compensation, which lets the
user set the gain bandwidth product. External compensation
allows gains from +2 to +10 with minimal trade-off in bandwidth. The AD8099 also features an extremely high slew rate of
1350 V/μs, giving the designer flexibility to use the entire
dynamic range without trading off bandwidth or distortion.
The AD8099 settles to 0.1% in 18 ns and recovers from
overdrive in 50 ns.
The AD8099 is available in a 3 mm × 3 mm lead frame chip
scale package (LFCSP) with a new pinout that is specifically
optimized for high performance, high speed amplifiers. The
new LFCSP package and pinout enable the breakthrough
performance that previously was not achievable with amplifiers.
The AD8099 is rated to work over the extended industrial
temperature range, −40°C to +125°C.
HARMONIC DISTORTION (dBc)
The AD8099 is an ultralow noise (0.95 nV/√Hz) and distortion
(–92 dBc @10 MHz) voltage feedback op amp, the combination
of which make it ideal for 16- and 18-bit systems. The AD8099
features a new, highly linear, low noise input stage that increases
the full power bandwidth (FPBW) at low gains with high slew
rates. ADI’s proprietary next generation XFCB process enables
such high performance amplifiers with relatively low power.
Figure 3. Harmonic Distortion vs. Frequency and Gain (SOIC)
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 ©2003–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
04511-0-002
CONNECTION DIAGRAMS
04511-0-001
Data Sheet
AD8099
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Using the AD8099 ...................................................................... 16
Applications ....................................................................................... 1
Circuit Components .................................................................. 16
Connection Diagrams ...................................................................... 1
Recommended Values ............................................................... 17
General Description ......................................................................... 1
Circuit Configurations .............................................................. 17
Specifications..................................................................................... 3
Performance vs. Component values ........................................ 19
Specifications with ±5 V Supply ................................................. 3
Total Output Noise Calculations and Design ......................... 20
Specifications with +5 V Supply ................................................. 4
Input Bias Current and DC Offset ........................................... 21
Absolute Maximum Ratings ............................................................ 5
DISABLE Pin and Input Bias Cancellation............................. 21
Maximum Power Dissipation ..................................................... 5
16-Bit ADC Driver ..................................................................... 22
ESD Caution .................................................................................. 5
Circuit Considerations .............................................................. 23
Typical Performance Characteristics ............................................. 6
Design Tools and Technical Support ....................................... 23
Theory of Operation ...................................................................... 15
Outline Dimensions ....................................................................... 24
Applications ..................................................................................... 16
Ordering Guide ............................................................................... 25
REVISION HISTORY
8/13—Rev. C to Rev. D
1/04—Data Sheet changed from Rev. 0 to Rev. A
Changes to Figure 42 Caption....................................................... 12
Changes to Figure 49 ...................................................................... 13
Changes to Ordering Guide .......................................................... 25
Inserted new Figure 3 ...................................................................1
Changes to Specifications .............................................................3
Inserted new Figures 22 to 34 ......................................................8
Inserted new Figures 51 to 55 ................................................... 14
Changes to Theory of Operation section ................................ 16
Changes to Circuit Components section ................................ 17
Changes to Table 4...................................................................... 18
Changes to Figure 60.................................................................. 18
Changes to Total Output Noise Calculations and
Design section ........................................................................ 21
Changes to Figure 60.................................................................. 22
Changes to Figure 62.................................................................. 23
Changes to 16-Bit ADC Driver section ................................... 23
Changes to Table 6...................................................................... 23
Additions to PCB Layout section ............................................. 23
1/13—Rev. B to Rev. C
Added EPAD Note to Figure 1 and Figure 2 ................................. 1
Changes to PCB Layout Section and Design Tools and
Technical Support Section ............................................................. 23
Deleted Figure 72, Figure 73, Evaluation Boards Section, and
Table 7 .............................................................................................. 24
Updated Outline Dimensions ....................................................... 25
Changes to Ordering Guide .......................................................... 26
6/04—Data Sheet changed from Rev. A to Rev. B
Change to General Description ...................................................... 1
Changes to Maximum Power Dissipation section ....................... 5
Changes to Applications section .................................................. 16
Changes to Table 7 .......................................................................... 24
Changes to Ordering Guide .......................................................... 26
11/03—Revision 0: Initial Version
Rev. D | Page 2 of 28
AD8099
Data Sheet
SPECIFICATIONS
SPECIFICATIONS WITH ±5 V SUPPLY
TA = 25°C, G = +2, RL = 1 kΩ to ground, unless otherwise noted. Refer to Figure 60 through Figure 66 for component values and
gain configurations.
Table 1.
Parameter
DYNAMIC PERFORMANCE
–3 dB Bandwidth
Bandwidth for 0.1 dB Flatness (SOIC/LFCSP)
Slew Rate
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Harmonic Distortion (dBc) HD2/HD3
Input Voltage Noise
Input Current Noise
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Bias Current Drift
Input Bias Offset Current
Open-Loop Gain
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
DISABLE PIN
DISABLE Input Voltage
Turn-Off Time
Turn-On Time
Enable Pin Leakage Current
DISABLE Pin Leakage Current
OUTPUT CHARACTERISTICS
Output Overdrive Recovery Time (Rise/Fall)
Output Voltage Swing
Short-Circuit Current
Off Isolation
POWER SUPPLY
Operating Range
Quiescent Current
Quiescent Current (Disabled)
Positive Power Supply Rejection Ratio
Negative Power Supply Rejection Ratio
Conditions
Min
Typ
G = +5, VOUT = 0.2 V p-p
G = +5, VOUT = 2 V p-p
G = +2, VOUT = 0.2 V p-p
G = +10, VOUT = 6 V Step
G = +2, VOUT = 2 V Step
G = +2, VOUT = 2 V Step
450
205
510
235
34/25
1350
470
18
1120
435
fC = 500 kHz, VOUT = 2 V p-p, G = +10
fC = 10 MHz, VOUT = 2 V p-p, G = +10
f = 100 kHz
82
98
4
10
2
–3.7 to +3.7
105
kΩ
MΩ
pF
V
dB
<2.4
105
V
ns
39
ns
Differential mode
Common mode
Output disabled
50% of DISABLE to < 10% of final VOUT,
VIN = 0.5 V, G = +2
50% of DISABLE to < 10% of final VOUT,
VIN = 0.5 V, G = +2
DISABLE =+5 V
DISABLE = –5 V
DISABLE = Low
+VS = 4 V to 6 V, –VS = –5 V (input referred)
+VS = 5 V, –VS = –6 V to –4 V (input referred)
Rev. D | Page 3 of 28
dBc
dBc
nV/√Hz
pA/√Hz
pA/√Hz
0.1
2.3
–6
–0.1
3
0.06
85
DISABLE pin floating
DISABLE pin = +VS
VIN = -2.5 V to 2.5 V, G =+2
RL = 100 Ω
RL = 1 kΩ
Sinking and sourcing
f = 1 MHz, DISABLE = low
Unit
MHz
MHz
MHz
V/µs
V/µs
ns
–102/–111
–84/–92
0.95
2.6
5.2
f = 100 kHz, DISABLE pin floating
f = 100 kHz, DISABLE pin = +VS
VCM = ±2.5 V
Max
17
35
–3.4 to +3.5
–3.7 to +3.7
85
86
0.5
–13
–2
1
21
44
30/50
–3.6 to +3.7
–3.8 to +3.8
131/178
–61
±5
15
1.7
91
94
mV
µV/°C
µA
µA
nA/°C
µA
dB
µA
µA
ns
V
V
mA
dB
±6
16
2
V
mA
mA
dB
dB
AD8099
Data Sheet
SPECIFICATIONS WITH +5 V SUPPLY
VS = 5 V @ TA = 25°C, G = +2, RL = 1 kΩ to midsupply, unless otherwise noted. Refer to Figure 60 through Figure 66 for component
values and gain configurations .
Table 2.
Parameter
DYNAMIC PERFORMANCE
–3 dB Bandwidth
Bandwidth for 0.1 dB Flatness (SOIC/LFCSP)
Slew Rate
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Harmonic Distortion (dBc) HD2/HD3
Input Voltage Noise
Input Current Noise
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Bias Offset Current
Input Bias Offset Current Drift
Open-Loop Gain
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
DISABLE PIN
DISABLE Input Voltage
Turn-Off Time
Turn-On Time
Enable Pin Leakage Current
DISABLE Pin Leakage Current
OUTPUT CHARACTERISTICS
Overdrive Recovery Time (Rise/Fall)
Output Voltage Swing
Short-Circuit Current
Off Isolation
POWER SUPPLY
Operating Range
Quiescent Current
Quiescent Current (Disabled)
Positive Power Supply Rejection Ratio
Negative Power Supply Rejection Ratio
Conditions
Min
Typ
G = +5, VOUT = 0.2 V p-p
G = +5, VOUT = 2 V p-p
G = +2, VOUT = 0.2 V p-p
G = +10, VOUT = 2 V Step
G = +2, VOUT = 2 V Step
G = +2, VOUT = 2 V Step
415
165
440
210
33/23
715
365
18
630
340
fC = 500 kHz, VOUT = 1 V p-p, G = +10
fC = 10 MHz, VOUT = 1 V p-p, G = +10
f = 100 kHz
76
88
4
10
2
1.3 to 3.7
105
kΩ
MΩ
pF
V
dB
<2.4
105
V
ns
61
ns
Differential mode
Common mode
Output disabled
50% of DISABLE to <10% of Final VOUT,
VIN = 0.5 V, G = +2
50% of DISABLE to <10% of Final VOUT,
VIN = 0.5 V, G = +2
DISABLE = 5 V
DISABLE = 0 V
VIN = 0 to 2.5 V, G = +2
RL = 100 Ω
RL = 1 kΩ
Sinking and Sourcing
f = 1 MHz, DISABLE = Low
DISABLE = Low
+VS = 4.5 V to 5.5 V, –VS = 0 V (input referred)
+VS =5 V, -VS= –0.5 V to +0.5 V (input referred)
Rev. D | Page 4 of 28
dBc
dBc
nV/√Hz
pA/√Hz
pA/√Hz
0.1
2.5
–6.2
–0.2
0.05
2.4
81
DISABLE pin floating
DISABLE pin = +VS
VCM = 2 V to 3 V
Unit
MHz
MHz
MHz
V/µs
V/µs
ns
–82/–94
–80/–75
0.95
2.6
5.2
f = 100 kHz, DISABLE pin floating
f = 100 kHz, DISABLE pin = +VS
VOUT = 1 V to 4 V
Max
16
33
1.5 to 3.5
1.2 to 3.8
84
84
0.5
–13
–2
1
21
44
50/70
1.2 to 3.8
1.2 to 3.8
60/80
–61
±5
14.5
1.4
89
90
mV
µV/°C
µA
µA
µA
nA/°C
dB
µA
µA
ns
V
V
mA
dB
±6
15.4
1.7
V
mA
mA
dB
dB
AD8099
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Rating
12.6 V
See Figure 4
±1.8 V
±10mA
–65°C to +125°C
–40°C to +125°C
300°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8099 package is
limited by the associated rise in junction temperature (TJ) on
the die. The plastic encapsulating the die will locally reach the
junction temperature. At approximately 150°C, which is the
glass transition temperature, the plastic will change its
properties. Even temporarily exceeding this temperature limit
may change the stresses that the package exerts on the die,
permanently shifting the parametric performance of the
AD8099. Exceeding a junction temperature of 150°C for an
extended period can result in changes in silicon devices,
potentially causing failure.
The still-air thermal properties of the package and PCB (θJA),
the ambient temperature (TA), and the total power dissipated in
the package (PD) determine the junction temperature of the die.
The junction temperature can be calculated as
TJ = TA + (PD × θ JA )
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). Assuming the load (RL) is referenced to
midsupply, the total drive power is VS/2 × IOUT, some of which is
dissipated in the package and some in the load (VOUT × IOUT).
The difference between the total drive power and the load
power is the drive power dissipated in the package.
PD = Quiescent Power + (Total Drive Power – Load Power)
V V
PD = (VS × I S ) +  S × OUT
RL
 2
 VOUT 2
–

RL

RMS output voltages should be considered. If RL is referenced to
VS–, as in single-supply operation, then the total drive power is
VS × IOUT. If the rms signal levels are indeterminate, consider the
worst case, when VOUT = VS/4 for RL to midsupply:
PD = (VS × I S ) +
(VS / 4 )2
RL
In single-supply operation with RL referenced to VS–, worst case
is VOUT = VS/2.
Airflow will increase heat dissipation, effectively reducing θJA.
Also, more metal directly in contact with the package leads
from metal traces, through holes, ground, and power planes will
reduce the θJA. Soldering the exposed paddle to the ground
plane significantly reduces the overall thermal resistance of the
package. Care must be taken to minimize parasitic capacitances at the input leads of high speed op amps, as discussed in
the PCB Layout section.
Figure 4 shows the maximum safe power dissipation in the
package versus the ambient temperature for the exposed paddle
(e-pad) SOIC-8 (70°C/W), and LFCSP (70°C/W), packages on a
JEDEC standard 4-layer board. θJA values are approximations.
4.0
3.5
3.0
2.5
2.0
1.5
LFCSP AND SOIC
1.0
0.5
0.0
–40
–20
0
20
40
60
80
AMBIENT TEMPERATURE (°C)
Figure 4. Maximum Power Dissipation
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. D | Page 5 of 28
100
120
04511-0-115
Parameter
Supply Voltage
Power Dissipation
Differential Input Voltage
Differential Input Current
Storage Temperature
Operating Temperature Range
Lead Temperature Range (Soldering 10 sec)
Junction Temperature
MAXIMUM POWER DISSIPATION (Watts)
Table 3.
AD8099
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
Default Conditions: VS = ±5 V, TA = 25°C, RL = 1 kΩ tied to ground unless otherwise noted. Refer to Figure 63 through Figure 66 for
component values and gain configurations.
4
NORMALIZED CLOSED-LOOP GAIN (dB)
G = +5
1
0
–1
–2
G = +20
–3
G = +10
–4
G = –1
–5
–6
–7
–8
–9
–10
1
10
100
FREQUENCY (MHz)
1000
–4
G = +5
G = –1
–5
–6
–7
–8
G = +10
–9
10
100
FREQUENCY (MHz)
1000
G = +5
16 RL = 1k
VOUT = 0.2V p-p
RL = 100, CSP
15
CLOSED-LOOP GAIN (dB)
14
13
RL = 1k, SOIC
12
11
RL = 100, SOIC
10
9
14
VS = ±5V, SOIC
13
12
11
VS = ±2.5V, CSP
10
VS = ±5V, CSP
9
1
10
100
FREQUENCY (MHz)
1000
VS = ±2.5V, SOIC
04511-0-076
7
7
1
11
+125°C
CLOSED-LOOP GAIN (dB)
8
7
+25°C
5
4
–40°C
10
100
FREQUENCY (MHz)
1000
Figure 7. Small Signal Frequency Response for Various Temperatures (SOIC)
8
7
–40°C
6
5
4
+25°C
3
G = +2
2 V = ±5V
S
RL = 1k
1
1
04511-0-098
3
G = +2
2 V = ±5V
S
RL = 1k
1
1
+85°C
9
+85°C
6
+125°C
VOUT = 0.2V p-p
10
10
9
1000
Figure 9. Small Signal Frequency Response for Various Supply Voltages
Figure 6. Small Signal Frequency Response for Various Load Resistors
VOUT = 0.2V p-p
10
100
FREQUENCY (MHz)
04511-0-077
8
10
100
FREQUENCY (MHz)
1000
04511-0-097
CLOSED-LOOP GAIN (dB)
G = +20
–3
17
8
CLOSED-LOOP GAIN (dB)
–2
Figure 8. Small Signal Frequency Response for Various Gains (LFCSP)
15
11
0
–1
1
RL = 1k, CSP
G = +5
16 VS = ±5V
VOUT = 0.2V p-p
1
–10
Figure 5. Small Signal Frequency Response for Various Gains (SOIC)
17
G = +2
VOUT = 0.2V p-p
3 VS = ±5V
R
2 LOAD = 1k
04511-0-073
G = +2
VOUT = 0.2V p-p
3 VS = ±5V
2 RLOAD = 1k
04511-0-074
NORMALIZED CLOSED-LOOP GAIN (dB)
4
Figure 10. Small Signal Frequency Response for Various Temperatures (LFCSP)
Rev. D | Page 6 of 28
AD8099
Data Sheet
MAGNITUDE
70
15
14
1pF, SOIC
13
12
1pF, CSP
PHASE
1000
04511-0-104
10
100
FREQUENCY (MHz)
1
40
–105
30
–120
20
–135
10
–150
VS = ±5V
0 R = 1k
L
UNCOMPENSATED
–10
0.001
0.01
0.1
5pF, SOIC
9
–90
50
11
10
–75
Figure 11. Small Signal Frequency Response for Various Capacitive Loads
1
NORMALIZED CLOSED-LOOP GAIN (dB)
–4
G = +5
–6
–7
–8
10
100
FREQUENCY (MHz)
1000
04511-0-011
Figure 12. Large Signal Frequency Response for Various Gains (SOIC)
VS = ±5V
G = +2
6.4
RL = 150
–2
G = +20
–3
–4
–5
–6
G = +5
–7
VS = ±5V
–8 VOUT = 2V p-p
RLOAD = 1k
–9
1
10
100
FREQUENCY (MHz)
1000
Figure 15. Large Signal Frequency Response for Various Gains (LFCSP)
6.5
VOUT = 1.4V p-p
VS = ±5V
G = +2
RL = 150
6.4
6.3
VOUT = 1.4V p-p
CLOSED-LOOP GAIN (dB)
6.3
6.2
6.1
6.0
5.9
VOUT = 200mV p-p
5.8
5.7
6.2
6.1
6.0
5.9
VOUT = 200mV p-p
5.8
5.7
5.6
5.6
5.5
1
10
FREQUENCY (MHz)
100
04511-0-009
CLOSED-LOOP GAIN (dB)
G = +10
0
–1
Figure 13. 0.1 dB Flatness (SOIC)
5.5
1
10
FREQUENCY (MHz)
Figure 16. 0.1 dB Flatness (LFCSP)
Rev. D | Page 7 of 28
100
04511-0-008
NORMALIZED CLOSED-LOOP GAIN (dB)
G = +20
–3
6.5
1000
G = +2
1
VS = ±5V
–9 VOUT = 2V p-p
RLOAD = 1k
–10
1
100
Figure 14. Open Loop Frequency Response
G = +10
–1
–5
–180
1.0
10
FREQUENCY (MHz)
2
G = +2
0
–2
–165
04511-0-080
16
–60
60
OPEN-LOOP GAIN (dB)
17
OPEN-LOOP PHASE (Degrees)
–45
80
18
CLOSED-LOOP GAIN (dB)
–30
90
5pF, CSP
G = +5
19 VS = ±5V
04511-0-012
20
AD8099
Data Sheet
15
15
RL = 1k, CSP
13
13
CLOSED-LOOP GAIN (dB)
RL = 100, CSP
12
RL = 100, SOIC
11
10
9
8
RL = 1k, SOIC
7
G = +5
6
VS = ±5V
V
= 2V p-p
5 OUT
1
10
100
FREQUENCY (MHz)
1000
Figure 17. Large Signal Frequency Response for Various Load Resistances
VS = ±2.5V, CSP
12
11
VS = ±5V, SOIC
10
9
8
7
VS = ±2.5V, SOIC
G = +5
6 R = 1k
L
VOUT = 2V p-p
5
1
04511-0-078
CLOSED-LOOP GAIN (dB)
VS = ±5V, CSP
14
10
100
FREQUENCY (MHz)
1000
04511-0-079
14
Figure 20. Large Signal Frequency Response for Various Supply Voltages
–10
100.0
G = +2
RL = 1k
–20 VS = ±5V
VDIS = 0V
10.0
OFF ISOLATION (dB)
INPUT IMPEDANCE (k)
–30
1.0
0.1
–40
CSP
–50
SOIC
–60
–70
0.01
1
10
100
FREQUENCY (MHz)
1000
–90
0.1
Figure 18. Input Impedance vs. Frequency
10
FREQUENCY (MHz)
100
1000
Figure 21. Off Isolation vs. Frequency
100
–50
G = +5
VOUT = 2V p-p
–60 VS = ±5V
RL = 100
HARMONIC DISTORTION (dBc)
G = +5
10
G = +10
G = +2
1
0.1
–70
–80
SOIC
–90
–100
CSP
VS = ±5V
0.01
0.1
1
10
FREQUENCY (MHz)
100
1000
–120
0.1
SOLID LINES – SECOND HARMONICS
DOTTED LINES
LINE – –THIRD
THIRDHARMONICS
HARMONICS
1.0
FREQUENCY (MHz)
10.0
Figure 22. Harmonic Distortion vs. Frequency
Figure 19. Output Impedance vs. Frequency for Various Gains
Rev. D | Page 8 of 28
04511-A-008
–110
04511-0-100
OUTPUT IMPEDANCE ()
1
04511-0-094
0.001
04511-0-105
–80
VS = ±5V
G = +2
AD8099
Data Sheet
–50
–50
G = +5
VOUT = 2V p-p
–60 VS = ±5V
RL = 1k
HARMONIC DISTORTION (dBc)
–70
–80
–90
–100
–110
–80
–90
–100
–110
1.0
FREQUENCY (MHz)
10.0
–130
0.1
Figure 23. Harmonic Distortion vs. Frequency (SOIC)
HARMONIC DISTORTION (dBc)
–80
–90
–100
–110
SOLID
SOLID
LINES
LINE––SECOND
SECONDHARMONICS
HARMONIC
DOTTED
DOTTED
LINE
LINE
– THIRD
– THIRD
HARMONICS
HARMONIC
1.0
FREQUENCY (MHz)
10.0
G = +2
= 2V p-p
V
–50 VOUT
S = ±5V
RL = 1k
–60
–70
–80
–90
–100
–110
–120
04511-A-010
HARMONIC DISTORTION (dBc)
–70
–130
0.1
Figure 24. Harmonic Distortion vs. Frequency (SOIC)
HARMONIC DISTORTION (dBc)
–70
–80
–90
–100
–110
SOLID LINE – SECOND HARMONIC
DOTTED LINE – THIRD HARMONIC
10.0
1.0
FREQUENCY (MHz)
10.0
G = –1
= 2V p-p
V
–50 VOUT
S = ±5V
RL = 1k
–60
–70
–80
–90
–100
–110
–120
04511-A-011
HARMONIC DISTORTION (dBc)
1.0
FREQUENCY (MHz)
–40
G = –1
= 2V p-p
V
–50 VOUT
S = ±5V
RL = 1k
–60
–130
0.1
SOLID LINE – SECOND HARMONIC
DOTTED LINE – THIRD HARMONIC
Figure 27. Harmonic Distortion vs. Frequency (LFCSP)
–40
–120
10.0
–40
G = +2
= 2V p-p
V
–50 VOUT
S = ±5V
RL = 1k
–60
–130
0.1
1.0
FREQUENCY (MHz)
Figure 26. Harmonic Distortion vs. Frequency (LFCSP)
–40
–120
SOLID LINE – SECOND HARMONIC
DOTTED LINE – THIRD HARMONIC
04511-A-013
–130
0.1
04511-A-012
–120
SOLID LINE – SECOND HARMONIC
DOTTED LINE – THIRD HARMONIC
04511-A-009
–120
–70
Figure 25. Harmonic Distortion vs. Frequency (SOIC)
–130
0.1
SOLID LINE – SECOND HARMONIC
DOTTED LINE – THIRD HARMONIC
1.0
FREQUENCY (MHz)
10.0
Figure 28. Harmonic Distortion vs. Frequency (LFCSP)
Rev. D | Page 9 of 28
04511-A-014
HARMONIC DISTORTION (dBc)
G = +5
VOUT = 2V p-p
–60 VS = ±5V
RL = 1k
AD8099
–50
G = +10
RL = 1k
–60
HARMONIC DISTORTION (dBc)
VS = ±2.5V
VOUT = 1V p-p
–70
–80
–90
–100
VS = ±5V
VOUT = 2V p-p
–110
SOLID LINES – SECOND HARMONICS
DOTTED LINES – THIRD HARMONICS
–120
0.1
1.0
FREQUENCY (MHz)
10.0
Figure 29. Harmonic Distortion vs. Frequency and Supply Voltage (SOIC)
–70
–80
–90
–100
VS = ±5V
VOUT = 2V p-p
SOLID LINES – SECOND HARMONICS
DOTTED LINES
LINE – –THIRD
THIRDHARMONICS
HARMONICS
–120
0.1
1.0
10.0
FREQUENCY (MHz)
Figure 32. Harmonic Distortion vs. Frequency for Various Supplies (LFCSP)
–40
–40
G = +5
VS = ±5V
–50 f = 10MHz
RL = 100
HARMONIC DISTORTION (dBc)
G = +5
VS = ±5V
–50 f = 10MHz
RL = 100
–60
–70
–80
–90
–70
–80
–90
–110
1
2
3
4
5
OUTPUT AMPLITUDE (V p-p)
6
7
SOLID LINE – SECOND HARMONIC
DOTTED LINE – THIRD HARMONIC
–110
1
Figure 30. Harmonic Distortion vs. Output Amplitude (SOIC)
2
3
4
5
OUTPUT AMPLITUDE (V p-p)
6
7
04511-A-019
–100
SOLID LINE – SECOND HARMONIC
DOTTED LINE – THIRD HARMONIC
04511-A-016
–100
–60
Figure 33. Harmonic Distortion vs. Output Amplitude (LFCSP)
–40
–40
G = +5
VS = ±5V
–50 f = 10MHz
RL = 1k
HARMONIC DISTORTION (dBc)
G = +5
VS = ±5V
–50 f = 10MHz
RL = 1k
–60
–70
–80
–90
–100
–70
–80
–90
–100
–110
SOLID LINE – SECOND HARMONIC
DOTTED LINE – THIRD HARMONIC
–120
1
2
3
4
5
OUTPUT AMPLITUDE (V p-p)
6
7
04511-A-017
–110
–60
Figure 31. Harmonic Distortion vs. Output Amplitude (SOIC)
SOLID LINE – SECOND HARMONIC
DOTTED LINE – THIRD HARMONIC
–120
1
2
3
4
5
OUTPUT AMPLITUDE (V p-p)
6
7
Figure 34. Harmonic Distortion vs. Output Amplitude (LFCSP)
Rev. D | Page 10 of 28
04511-A-021
HARMONIC DISTORTION (dBc)
VS = ±2.5V
VOUT = 1V p-p
–110
04511-A-015
HARMONIC DISTORTION (dBc)
–60
HARMONIC DISTORTION (dBc)
G = +10
RL = 1k
04511-A-018
–50
Data Sheet
AD8099
Data Sheet
0.20
0.20
10pF, 20 RSNUB
10pF, 20 RSNUB
0.15
0.15
0.05
0
–0.05
RSNUB
–0.10
CL
–0.20
0
5
10
0
–0.05
RSNUB
–0.10
RL
CL
G = +5
VS = ±5V
RL = 1k
–0.15
1pF
0.05
15
20
25
30
TIME (ns)
35
40
45
50
Figure 35. Small Signal Transient Response for Various Capacitive Loads
(SOIC)
0.15
RL
G = +5
VS = ±5V
RL = 1k
–0.15
–0.20
0
5
10
15
20
25
30
TIME (ns)
35
40
45
50
04511-0-096
OUTPUT VOLTAGE (V)
0.10
1pF
04511-0-095
OUTPUT VOLTAGE (V)
0.10
Figure 38. Small Signal Transient Response for Various Capacitive Loads
(LFCSP)
0.20
VS = ±5.0V
AND ±2.5V, CSP
VS = ±2.5V
CSP
VS = ±5.0V
CSP
0.15
0.10
–0.05
–0.10
VS = ±5.0V
AND ±2.5V, SOIC
G = +10
RL = 1k
–0.15
0
10
20
30
40
50
TIME (ns)
Figure 36. Small Signal Transient Response for Various Supply Voltages
0.05
VS = ±5.0V
SOIC
0
–0.05
VS = ±2.5V
SOIC
–0.10
–0.15 RL = 1k, 100
VOUT = 200mV p-p
G = +5
–0.20
0
10
20
30
40
50
TIME (ns)
04511-0-102
OUTPUT VOLTAGE (V)
0
04511-0-107
OUTPUT VOLTAGE (V)
0.10
0.05
Figure 39. Small Signal Transient Response for Various Supply Voltages
5
3.5
INPUT × 2
4
3.0
TURN OFF
INPUT
TURN ON
INPUT
2.5
OUTPUT VOLTAGE (V)
RL = 100
2
1
0
–1
–2
RL = 1k
2.0
1.5
VS = ±5V
G=2
1.0
0.5
–3
–5
0
100
200
300
400 500 600
TIME (ns)
700
800
900
1000
TURN ON
TURN OFF
–0.5
0
50
100
150
TIME (ns)
Figure 40. Disable/Enable Switching Speed
Figure 37. Output Overdrive Recovery for Various Resistive Loads
Rev. D | Page 11 of 28
200
04511-0-010
0
–4
04511-A-017
OUTPUT VOLTAGE (V)
3
AD8099
Data Sheet
1.5
0.3%
1.5
OUTPUT
VS = ±2.5V
0
–0.5
G = +10
RL = 1k
0
VS = ±5.0V
10
20
30
40
50
TIME (ns)
04511-0-106
–1.0
INPUT
0.1%
0.5
0%
0
ERROR
–0.1%
–0.5
–1.0
G = +2
RLOAD = 1k
Vs = ±5V
–1.5
0
5
15
20
25
TIME (ns)
30
35
40
–0.3%
45
Figure 44. Short Term Settling Time (LFCSP)
Figure 41. Large Signal Transient Response vs. Supply Voltage (LFCSP)
1.5
10
–0.2%
04511-0-052
0.5
–1.5
0.2%
1.0
OUTPUT/INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
1.0
0.3%
1.5
VS = ±5.0V
OUTPUT
–0.5
G = +10
RL = 1k
0
10
20
30
40
50
TIME (ns)
04511-0-118
–1.0
0.1%
0%
0
ERROR
–0.1%
–0.5
–1.0
G = +2
RLOAD = 1k
Vs = ±5V
–1.5
0
5
20
25
TIME (ns)
30
35
1.5
VS = ±5V
40
OUTPUT/INPUT VOLTAGE (V)
VS = ±2.5V
0
–0.5
RL = 1k, 100
G = +5
–1.5
0
10
20
30
TIME (ns)
40
50
04511-0-101
–1.0
0.30%
0.20%
1.0
0.5
–0.3%
45
G = +2
VS = ±5V
OUTPUT
1.0
OUTPUT VOLTAGE (V)
15
Figure 45. Short Term Settling Time (SOIC)
Figure 42. Large Signal Transient Response vs. Supply Voltage (SOIC)
1.5
10
–0.2%
04511-0-051
0
INPUT
0.5
INPUT
0.10%
0.5
0%
0
ERROR
–0.5
–0.10%
–1.0
–0.20%
–1.5
Figure 43. Large Signal Transient Response for Various Supply Voltages and
Load Resistances (SOIC and LFCSP)
Rev. D | Page 12 of 28
0
50
100
150
200 250 300
TIME (s)
350
400
Figure 46. Long Term Settling Time
450
–0.30%
500
04511-0-050
VS = ±2.5V
0.5
–1.5
0.2%
1.0
OUTPUT/INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
1.0
AD8099
Data Sheet
G = +5
–10 RL = 1k
–40
–50
–60
–70
–80
–90
–100
–20
–30
NEGATIVE
–40
–50
–60
POSITIVE
–70
–80
100
1000
Figure 47. Common-Mode Rejection vs. Frequency
1.0
10
FREQUENCY (MHz)
100
1G
INPUT CURRENT NOISE (pA Hz)
1000
100
1
10
100
1k
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
04511-0-004
10
1
100
10
1
1
10
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 48. Input Current Noise vs. Frequency (DISABLE = Open)
Figure 51. Input Current Noise vs. Frequency (DISABLE = +VS)
100
VS = ±5V
N = 1,200
X = –70V
 = 80V
120
100
10
COUNT
80
1
60
40
20
0.1
1
10
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
1G
04511-0-005
INPUT VOLTAGE NOISE (nV Hz)
1000
Figure 50. Power Supply Rejection vs. Frequency
1000
INPUT CURRENT NOISE (pA Hz)
0.10
04511-0-114
10
FREQUENCY (MHz)
–100
0.01
04511-0-003
1.0
04511-0-113
–90
–110
0.1
0
–300
–200
–100
0
VOFFSET (V)
100
Figure 52. Input Offset Voltage Distribution
Figure 49. Input Voltage Noise vs. Frequency
Rev. D | Page 13 of 28
200
04511-0-075
COMMON-MODE REJECTION (dB)
–30
0
G = +2
RL = 1k
POWER SUPPLY REJECTION (dB)
–20
AD8099
Data Sheet
400
20
18
VS = 5V
SUPPLY CURRENT (mA)
200
100
0
VS = ±5V
14
12
–25
–10
5
20
35
50
65
TEMPERATURE (C)
80
95
110
125
8
–40
Figure 53. Input Offset Voltage vs. Temperature
–10
5
20
35
50
65
TEMPERATURE (C)
80
95
110
125
110
125
Figure 56. Supply Current vs. Temperature
–5.4
1.0
0.8
IB+, VS = ±5V
–5.6
IB+, VS = ±5V
0.6
BIAS CURRENT (A)
–5.8
IB–, VS = ±5V
–6.0
IB–, VS = 5V
–6.2
0.4
0.2
0 IB–, VS = ±5V
IB+, VS = 5V
–0.2
–0.4
–0.6
–6.4
IB+, VS = 5V
–6.6
–40
–25
–10
5
20
35
50
65
TEMPERATURE (C)
80
95
110
125
Figure 54. Input Bias Current vs. Temperature (DISABLE Pin Floating)
–VS + VOUT
VS = ±5V
1.20
+VS – VOUT
1.18
–VS + VOUT
1.16
+VS – VOUT
VS = 5V
–25
–10
–5
20
35
50
65
TEMPERATURE (C)
80
95
110
125
04511-A-005
1.14
1.12
–40
–1.0
–40
–25
–10
5
20
35
50
65
TEMPERATURE (C)
80
95
Figure 57. Input Bias Current vs. Temperature (DISABLE Pin = +VS)
1.24
1.22
IB–, VS = 5V
–0.8
04511-A-004
BIAS CURRENT (A)
–25
04511-A-006
–200
–40
OUTPUT SATURATION VOLTAGE (V)
VS = 5V
10
04511-A-003
–100
VS = ±5V
16
04511-A-007
OFFSET VOLTAGE (V)
300
Figure 55. Output Saturation Voltage vs. Temperature
Rev. D | Page 14 of 28
AD8099
Data Sheet
THEORY OF OPERATION
The AD8099 is a voltage feedback op amp that employs a new
highly linear low noise input stage. With this input stage, the
AD8099 can achieve better than 90 dB distortion for a 2 V p-p,
10 MHz output signal with an input referred voltage noise of
less than 1 nV/√Hz. This noise level and distortion
performance has been previously achievable only with fully
uncompensated amplifiers. The AD8099 achieves this level of
performance for gains as low as +2. This new input stage also
triples the achievable slew rate for comparably compensated
1 nV/√Hz amplifiers.
gm
VOUT
BUFFER
R1
CC
RL
04511-0-060
The simplified AD8099 topology is shown in Figure 58. The
amplifier is a single gain stage with a unity gain output buffer
fabricated in Analog Devices’ extra fast complimentary bipolar
process (XFCB). The AD8099 has 85 dB of open-loop gain and
maintains precision specifications such as CMRR, PSRR, VOS,
and VOS/T to levels that are normally associated with
topologies having two or more gain stages.
Figure 58. AD8099 Topology
The AD8099 can be externally compensated down to a gain of 2
through the use of an RC network. Above gains of 15, no external compensation network is required. To realize the full gain
bandwidth product of the AD8099, no PCB trace should be
connected to or within close proximity of the external compensation pin for the lowest possible capacitance.
External compensation allows the user to optimize the closedloop response for minimal peaking while increasing the gain
bandwidth product in higher gains, lowering distortion errors
that are normally more prominent with internally compensated
parts in higher gains. For a fixed gain bandwidth, wideband
distortion products would normally increase by 6 dB going
from a closed-loop gain of 2 to 4. Increasing the gain bandwidth
product of the AD8099 eliminates this effect with increasing
closed-loop gain.
The AD8099 is available in both a SOIC and an LFCSP, each of
which has a thermal pad for lower operating temperature. To
help avoid this pad in board layout, both packages have an extra
output pin on the opposite side of the package for ease in connecting a feedback network to the inputs. The secondary output
pin also isolates the interaction of any capacitive load on the
output and self-inductance of the package and bond wire from
the feedback loop. While using the secondary output for feedback, inductance in the primary output will now help to isolate
capacitive loads from the output impedance of the amplifier.
Since the SOIC has greater inductance in its output, the SOIC
will drive capacitive loads better than the LFCSP. Using the
primary output for feedback with both packages will result in
the LFCSP driving capacitive load better than the SOIC.
The LFCSP and SOIC pinouts are identical, except for the
rotation of all pins counterclockwise by one pin on the LFCSP.
This isolates the inputs from the negative power supply pin,
removing a mutually inductive coupling that is most prominent
while driving heavy loads. For this reason, the LFCSP second
harmonic, while driving a heavy load, is significantly better
than that of the SOIC.
A three-state input pin is provided on the AD8099 for a high
impedance power-down and an optional input bias current
cancellation circuit. The high impedance output allows several
AD8099s to drive the same ADC or output line time interleaved. Pulling the DISABLE pin low activates the high
impedance state. See Table 5 for threshold levels. When the
DISABLE pin is left floating, the AD8099 operates normally.
With the DISABLE pin pulled within 0.7 V of the positive
supply, an optional input bias current cancellation circuit is
turned on, which lowers the input bias current to less than 200
nA. In this mode, the user can drive the AD8099 with a high dc
source impedance and still maintain minimal output referred
offset without having to use impedance matching techniques. In
addition, the AD8099 can be ac-coupled while setting the bias
point on the input with a high dc impedance network. The
input bias current cancellation circuit will double the input
referred current noise, but this effect is minimal as long as
wideband impedance is kept low (see Figure 48 and Figure 51).
A pair of internally connected diodes limits the differential
voltage between the noninverting input and the inverting input
of the AD8099. Each set of diodes has two series diodes, which
are connected in anti-parallel. This limits the differential
voltage between the inputs to approximately 1.8 V. All of the
AD8099 pins are ESD protected with voltage limiting diodes
connected between both rails. The protection diodes can handle
5 mA of steady state current. Currents should be limited to
5 mA or less through the use of a series limiting resistor.
Rev. D | Page 15 of 28
AD8099
Data Sheet
APPLICATIONS
USING THE AD8099
CF—Creates a zero in the loop response to compensate the pole
The AD8099 offers unrivaled noise and distortion performance
in low signal gain configurations. In low gain configurations
(less than15), the AD8099 requires external compensation. The
amount of gain and performance needed will determine the
compensation network.
created by the input capacitance (including stray capacitance)
and the feedback resistor RF. CF helps reduce high frequency
peaking and ringing in the closed-loop response. Typical range
is 0.5 pF to 1.5 pF for evaluation circuits used here.
Understanding the subtleties of the AD8099 gives the user
insight on how to exact its peak performance. Use the
component values and circuit configurations shown in the
Applications section as starting points for designs. Specific
circuit applications will dictate the final configuration and value
of your components.
CIRCUIT COMPONENTS
The circuit components are referenced in Figure 59, the
recommended noninverting circuit schematic for the AD8099.
See Table 4 for typical component values and performance data.
CF
+VS
RF
C3
0.1µF
1
RG
2
7
AD8099
R1
DISABLE
VOUT
6
5
3
4
8
RC
C1
C5
0.1µF
CC
C4
10µF
–VS
04511-0-061
RS
VIN
C2
10µF
Figure 59. Wideband Noninverting Gain Configuration (SOIC)
RF and RG—The feedback resistor and the gain set resistor
determine the noise gain of the amplifier; typical RF values
range from 250 Ω to 499 Ω.
R1—This resistor terminates the input of the amplifier to the
source resistance of the signal source, typically 50 Ω. (This is
application specific and not always required.)
RS—Many high speed amplifiers in low gain configurations
require that the input stage be terminated into a nominal
impedance to maintain stability. The value of RS should be kept
to 50 Ω or lower to maintain low noise performance. At higher
gains, RS may be reduced or even eliminated. Typical range is
0 Ω to 50 Ω.
CC—The compensation capacitor decreases the open-loop gain
at higher frequencies where the phase is degrading. By decreasing the open-loop gain here, the phase margin is increased and
the amplifier is stabilized. Typical range is 0 pF to 5 pF. The
value of CC is gain dependent.
RC—The series lead inductance of the package and the compensation capacitance (CC) forms a series resonant circuit. RC
dampens this resonance and prevents oscillations. The
recommended value of RC is 50 Ω for a closed-loop gain of 2.
This resistor introduces a zero in the open-loop response and
must be kept low so that this zero occurs at a higher frequency.
The purpose of the compensation network is to decrease the
open-loop gain. If the resistance becomes too large, the gain will
be reduced to the resistor value, and not necessarily to 0 Ω,
which is what a single capacitor would do over frequency.
Typical value range is 0 Ω to 50 Ω.
C1—To lower the impedance of RC , C1 is placed in parallel with
RC. C1 is not required, but greatly reduces peaking at low
closed-loop gains. The typical value range is 0 pF to 2 pF.
C2 and C3—Bypass capacitors are connected between both
supplies for optimum distortion and PSRR performance. These
capacitors should be placed as close as possible to the supply
pins of the amplifier. For C3, C5, a 0508 case size should be
used. The 0508 case size offers reduced inductance and better
frequency response.
C4 and C2—Electrolytic bypass capacitors.
Rev. D | Page 16 of 28
AD8099
Data Sheet
RECOMMENDED VALUES
Table 4. Recommended Values and AD8099 Performance
Feedback
Network Values
Compensation
Network Values
RG
RS CF
RC
CC
C1
−3 dB SS
Bandwidth
(MHz)
−1, 2
SOIC
250
2
LFCSP
250
−1
LFCSP
250
5 LFCSP/SOIC 499
10 LFCSP/SOIC 499
250
250
250
124
54
50
50
50
20
0
1.5
0.5
1.0
0.5
0
50
50
50
50
0
4
5
5
1
0.5
1.5
2
2
0
0
440/700
700
420
510
550
515
475
475
735
1350
0.3/3.1
3.2
0.8
1.4
0.8
2.1
2.1
2.1
4.9
9.6
4
4
4
8.6
13.3
20 LFCSP/SOIC 499
26
0
0
0
0
0
160
1450
0
19
23.3
Gain
Package
RF
Slew Rate
(V/s)
Output Noise Total Output Noise
Peaking (AD8099 Only) Including Resistors
(nV/√Hz)
(nV/√Hz)
(dB)
CIRCUIT CONFIGURATIONS
Figure 60 through Figure 66 show typical schematics for the
AD8099 in various gain configurations. Table 4 data was
collected using the schematics shown in Figure 60 through
Figure 66. Resistor R1, as shown in Figure 60 through Figure 66,
CF
1.5pF
+VS
RF
250
RF
250
C3
0.1F
2
VIN
7
AD8099
6
RL
1k
5
3
4
2
3
R1
50
VOUT
RS
50
8
AD8099
C1
1.5pF
DISABLE
C5
0.1F
+VS
RF
250
04511-0-116
6
RL
1k
5
4
RS
50
VOUT
VIN
RC
50
C1
1.5pF
DISABLE
C5
0.1F
CC
4pF
8
AD8099
RL
1k
5
VOUT
1
RC
50
C1
2pF
C5
0.1F
CC
5pF
C4
10F
–VS
Figure 61. Amplifier Configuration for SOIC Package, Gain = +2
7
6
4
R1
50
8
–VS
2
3
AD8099
C2
10F
C3
0.1F
RG
250
7
C4
10F
+VS
RF
250
04511-0-054
DISABLE
CF
0.5pF
C2
10F
1
3
R1
50
–VS
C3
0.1F
2
C1
2pF
Figure 62. Amplifier Configuration for LFCSP Package, Gain =–1
Figure 60. Amplifier Configuration for SOIC Package, Gain = –1
VIN
VOUT
CC
5pF
C4
10F
–VS
CF
1.5pF
RC
50
C5
0.1F
CC
4pF
C4
10F
RS
50
RL
1k
5
1
RC
50
RG
250
7
6
4
8
DISABLE
C2
10F
C3
0.1F
RG
250
1
RS
50
R1
50
+VS
04511-0-108
VIN
CF
1pF
C2
10F
04511-0-053
RG
250
is the test equipment termination resistor. R1 is not required for
normal operation, but is shown in the schematics for
completeness.
Figure 63. Amplifier Configuration for LFCSP Package, Gain = +2
Rev. D | Page 17 of 28
AD8099
Data Sheet
+VS
+VS
RF
499Ω
RG
124Ω
RF
499Ω
RG
26Ω
C3
0.1µF
RS
20Ω
+
VO
CC
RL
1kΩ
VIN
VOUT
DISABLE
RC
50Ω
C5
0.1µF
04511-0-055
+VS
C3
0.1µF
FB
+V
+
R1
50Ω
DISABLE
C2
10µF
VO
CC
–V
RL
1kΩ
VOUT
D
C5
0.1µF
CC
0.5pF
C4
10µF
–VS
04511-0-056
VIN
VOUT
C5
0.1µF
Figure 66. Amplifier Configuration for LFCSP and SOIC Packages, Gain = +20
RF
499Ω
AD8099
RL
1kΩ
D
–VS
Figure 64. Amplifier Configuration for LCSP and SOIC Package, Gain = +5
–
–V
VO
CC
C4
10µF
CC
1pF
–VS
RG
54Ω
+
R1
50Ω
D
C4
10µF
+V
AD8099
–V
R1
50Ω
DISABLE
FB
+V
AD8099
C2
10µF
C3
0.1µF
–
FB
–
VIN
C2
10µF
04511-0-057
CF
0.5pF
Figure 65. Amplifier Configuration for LFCSP and SOIC Packages, Gain = +10
Rev. D | Page 18 of 28
AD8099
Data Sheet
PERFORMANCE VS. COMPONENT VALUES
The influence that each component has on the AD8099
frequency response can be seen in Figure 67 and Figure 68. In
Figure 67 and Figure 68, all component values are held
constant, except for the individual component shown, which is
varied. For example, in the RS performance plot of Figure 68, all
components are held constant except RS, which is varied from
0 Ω to 50 Ω.; and clearly indicates that RS has a major influence
on peaking and bandwidth of the AD8099.
+VS
RF
9
C2
10F
CLOSED-LOOP GAIN (dB)
1
2
7
AD8099
RS
VIN
VOUT
6
5
3
4
8
DISABLE
RC
C1
C5
0.1F
C4
10F
–VS
SOIC PINOUT SHOWN
10
VS = ±5V
9 G = +2
RLOAD = 1k
8 SOIC PACKAGE
5
4
3
2
1
C1 = 1.5pF
C1 = 2pF
100
FREQUENCY (MHz)
1000
3000
10
VS = ±5V
9 G = +2
RLOAD = 1k
8 SOIC PACKAGE
CC = 3pF
CC = 4pF
CLOSED-LOOP GAIN (dB)
7
6
5
6
0 VS = ±5V
G = +2
–1 RLOAD = 1k
SOIC PACKAGE
–2
1
10
CC
04511-0-117
R1
C1 = 0pF
7
C3
0.1F
RG
CC = 5pF
4
3
2
7
RC = 50
6
5
4
3
2
RC = 20
1
0
0
–1
1
10
100
FREQUENCY (MHz)
1000
3000
RC = 35
–1
1
10
100
FREQUENCY (MHz)
Figure 67. Frequency Response for Various Values of C1, CC, RC
Rev. D | Page 19 of 28
1000
3000
04511-0-030
1
04511-0-024
CLOSED-LOOP GAIN (dB)
8
04511-0-020
CF
AD8099
Data Sheet
10
9
8
8
7
7
6
5
RF = RG = 300
4
3
RF = RG = 250
2
1 VS = ±5V
G = +2
0 R
LOAD = 1k
SOIC PACKAGE
–1
1
10
100
FREQUENCY (MHz)
1000
3000
CF = 0.5pF
6
CF = 1pF
5
CF = 1.5pF
4
3
2
1 VS = ±5V
G = +2
0 R
LOAD = 1k
SOIC PACKAGE
–1
10
1
100
FREQUENCY (MHz)
CF
12
RS = 0
+VS
RF
11
6
DISABLE
4
3
2 VS = ±5V
G = +2
1 RLOAD = 1k
SOIC PACKAGE
0
1
10
RS = 20
100
FREQUENCY (MHz)
4
8
RC
10000
CC
–VS
SOIC PINOUT SHOWN
C1
C5
0.1F
C4
10F
1000
VOUT
6
5
3
R1
RS = 50
5
7
AD8099
RS
VIN
04511-0-034
CLOSED-LOOP GAIN (dB)
2
7
C2
10F
1
RG
8
3000
C3
0.1F
10
9
1000
04511-0-058
CLOSED-LOOP GAIN (dB)
9
04511-0-117
RF = RG = 200
04511-0-032
CLOSED-LOOP GAIN (dB)
10
Figure 68. Frequency Response for Various Values of RF, CF, RS
TOTAL OUTPUT NOISE CALCULATIONS AND DESIGN
To analyze the noise performance of an amplifier circuit, the
individual noise sources must be identified. Then determine if
the source has a significant contribution to overall noise performance of the amplifier. To simplify the noise calculations, we
will work with noise spectral densities, rather than actual
voltages to leave bandwidth out of the expressions (noise
spectral density, which is generally expressed in nV/Hz, is
equivalent to the noise in a 1 Hz bandwidth).
The noise model shown in Figure 69 has six individual noise
sources: the Johnson noise of the three resistors, the op amp
voltage noise, and the current noise in each input of the
amplifier. Each noise source has its own contribution to the
noise at the output. Noise is generally specified RTI (referred to
input), but it is often simpler to calculate the noise referred to
the output (RTO) and then divide by the noise gain to obtain
the RTI noise.
All resistors have a Johnson noise of (4kBTR), where k is
Boltzmann’s Constant (1.38 × 10–23 J/K), T is the absolute
temperature in Kelvin, B is the bandwidth in Hz, and R is the
resistance in ohms. A simple relationship, which is easy to
remember, is that a 50 Ω resistor generates a Johnson noise of
1 nVHz at 25C. The AD8099 amplifier has roughly the same
equivalent noise as a 50 Ω resistor.
Rev. D | Page 20 of 28
AD8099
Data Sheet
VN, R2
GAIN FROM
=
"A" TO OUTPUT
4kTR2
B
VN, R1
R1
NOISE GAIN =
NG = 1 + R2
R1
IN–
VN
A
4kTR1
VN, R3
For RTO calculations, the input offset voltage and the voltage
generated by the bias current flowing through R3 are multiplied
by the noise gain of the amplifier. The voltage generated by IB–
through R2 is summed together with the previous offset
voltages to arrive at a final output offset voltage. The offset
voltage can also be referred to the input (RTI) by dividing the
calculated output offset voltage by the noise gain.
R2
VOUT
R3
IN+
GAIN FROM
R2
=–
"B" TO OUTPUT
R1
4kTR3
R2
VN + 4kTR3 + 4kTR1
R1 + R2
As seen in Figure 70 if IB+ and IB– are the same and R3 equals the
parallel combination of R1 and R2, then the RTI offset voltage
can be reduced to only VOS. This is a common method used to
reduce output offset voltage. Keeping resistances low helps to
minimize offset error voltage and keeps the voltage noise low.
2
2
+ IN+2R32 + IN–2 R1 × R2
R1 + R2
2
+ 4kTR2
R1
R1 + R2
2
RTO NOISE = NG × RTI NOISE
04511-0-070
RTI NOISE =
DISABLE PIN AND INPUT BIAS CANCELLATION
Figure 69. Op Amp Noise Analysis Model
In applications where noise sensitivity is critical, care must be
taken not to introduce other significant noise sources to the
amplifier. Each resistor is a noise source. Attention to the
following areas is critical to maintain low noise performance:
design, layout, and component selection. A summary of noise
performance for the amplifier and associated resistors can be
seen in Table 4.
The AD8099 DISABLE pin performs three functions; enable,
disable, and reduction of the input bias current. When the
DISABLE pin is brought to within 0.7 V of the positive supply,
the input bias current is reduced by an approximate factor of 60.
However, the input current noise doubles to 5.2 pA/Hz.
Table 5 outlines the DISABLE pin functionality.
Table 5. DISABLE Pin Truth Table
INPUT BIAS CURRENT AND DC OFFSET
In high noise gain configurations, the effects of output offset
voltage can be significant, even with low input bias currents and
input offset voltages. Figure 70 shows a comprehensive offset
voltage model, which can be used to determine the referred to
output (RTO) offset voltage of the amplifier or referred to input
(RTI) offset voltage.
Supply Voltage
±5 V
+5 V
Disable
Enable
Low Input Bias Current
–5 to +2.4
Open
4.3 to 5
0 to 2.4
Open
4.3 to 5
R2
GAIN FROM
=
"A" TO OUTPUT
B
R1
NOISE GAIN =
R2
NG = 1 +
R1
IB–
VOS
A
R3
VOUT
IB+
GAIN FROM
= – R2
"B" TO OUTPUT
R1
OFFSET (RTO) = VOS 1 + R2 + IB+ × R3 1 + R2 – IB– × R2
R1
R1
R1 × R2
R1 + R2
FOR BIAS CURRENT CANCELLATION:
OFFSET (RTI) = VOS
IF IB+ = IB– AND R3 = R1 × R2
R1 + R2
04511-0-071
OFFSET (RTI) = VOS + IB+ × R3 – IB–
Figure 70. Op Amp Total Offset Voltage Model
Rev. D | Page 21 of 28
AD8099
Data Sheet
DVDD
AVDD
0.1µF
0.1µF
REF
+VS
RF
150Ω
R7
15Ω
6
RC
50Ω
C5
0.1µF
C1
2pF
CC
9pF
C4
10µF
R2
590Ω
INGND
C6
2.7nF
04511-0-072
R1
590Ω
IN
5
4
8
+2.5V
DVDD
AD7667
7
AD8099
DISABLE
DGND
REFGND
2
3
AVDD
47µF
1
RS
50Ω
VIN
1µF
C2
0.1µF
RG
150Ω
AGND
REF
C1
10µF
–VS
Figure 71. ADC Driver
16-BIT ADC DRIVER
Ultralow noise and distortion performance make the AD8099
an ideal ADC driver. Even though the AD8099 is not unity gain
stable, it can be configured to produce a net gain of +1
amplifier, as shown in Figure 71. This is achieved by combining
a gain of +2 and a gain of –1 for a net gain of +1. The input
range of the ADC is 0 V to 2.5 V.
Table 6 shows the performance data of the AD8099 and the
Analog Devices AD7667 a 1 MSPS 16-bit ADC.
Table 6. ADC Driver Performance, fC = 20 kHz,
VOUT = 2.24 V p-p
Parameter
Second Harmonic Distortion
Third Harmonic Distortion
THD
SFDR
SNR
Rev. D | Page 22 of 28
Measurement (dB)
–111.4
–103.2
–101.4
102.2
88.1
AD8099
Data Sheet
Grounding
CIRCUIT CONSIDERATIONS
Optimizing the performance of the AD8099 requires attention
to detail in layout and signal routing of the board. Power supply
bypassing, parasitic capacitance, and component selection all
contribute to the overall performance of the amplifier. The
AD8099 features an exposed paddle on the backs of both the
LFCSP and SOIC packages. The exposed paddle provides a low
thermal resistive path to the ground plane. For best
performance, solder the exposed paddle to the ground plane.
PCB Layout
The compensation network is determined by the amplifier gain
requirements. For lower gains, the layout and component
placement are more critical. For higher gains, there are fewer
compensation components, which results in a less complex
layout. With diligent consideration to layout, grounding, and
component placement, the AD8099 evaluation boards have
been optimized for peak performance. These are the same
evaluation boards that are available to customers; see the
Ordering Guide for ordering information.
Parasitics
The area surrounding the compensation pin is very sensitive to
parasitic capacitance. To realize the full gain bandwidth product
of the AD8099, there should be no trace connected to or within
close proximity of the external compensation pin for the lowest
possible capacitance. When compensation is required, the
traces to the compensation pin, the negative supply, and the
interconnect between components (i.e. CC, C1, and RC in
Figure 59) should be made as wide as possible to minimize
inductance.
All ground and power planes under the pins of the AD8099
should be cleared of copper to prevent parasitic capacitance
between the input and output pins to ground. A single mounting pad on a SOIC footprint can add as much as 0.2 pF of
capacitance to ground as a result of not clearing the ground or
power plane under the AD8099 pins. Parasitic capacitance can
cause peaking and instability, and should be minimized to
ensure proper operation.
The new pinout of the AD8099 reduces the distance between
the output and the inverting input of the amplifier. This helps to
minimize the parasitic inductance and capacitance of the
feedback path, which, in turn, reduces ringing and second
harmonic distortion.
When possible, ground and power planes should be used.
Ground and power planes reduce the resistance and inductance
of the power supply feeds and ground returns. If multiple planes
are used, they should be “stitched” together with multiple vias.
The returns for the input, output terminations, bypass
capacitors, and RG should all be kept as close to the AD8099 as
possible. Ground vias should be placed at the very end of the
component mounting pad to provide a solid ground return. The
output load ground and the bypass capacitor grounds should be
returned to a common point on the ground plane to minimize
parasitic inductance and improve distortion performance. The
AD8099 packages feature an exposed paddle. For optimum
performance, solder this paddle to ground. For more information on PCB layout and design considerations, refer to
section 7-2 of the 2002 Analog Devices Op Amp Applications
book.
Power Supply Bypassing
The AD8099 power supply bypassing has been optimized for
each gain configuration as shown in Figure 60 through
Figure 66 in the Circuit Configurations section. The values
shown should be used when possible. Bypassing is critical for
stability, frequency response, distortion, and PSRR
performance. The 0.1 µF capacitors shown in Figure 60 through
Figure 66 should be as close to the supply pins of the AD8099 as
possible and the electrolytic capacitors beside them.
Component Selection
Smaller components less than 1206 SMT case size, offer smaller
mounting pads, which have less parasitics and allow for a more
compact layout. It is critical for optimum performance that high
quality, tight tolerance (where critical), and low drift components be used. For example, tight tolerance and low drift is
critical in the selection of the feedback capacitor used in
Figure 60. The feedback compensation capacitor in Figure 60 is
1.5pF. This capacitor should be specified with NPO material.
NPO material typically has a ±30 ppm/°C change over –55°C to
+125°C temperature range. For a 100°C change, this would
result in a 4.5 fF change in capacitance, compared to an X7R
material, which would result in a 0.23 pF change, a 15% change
from the nominal value. This could introduce excessive
peaking, as shown in Figure 68, CF vs. Frequency Response.
DESIGN TOOLS AND TECHNICAL SUPPORT
Analog Devices is committed to the design process by providing
technical support and online design tools. ADI offers technical
support via evaluation boards, sample ICs, SPICE models,
interactive evaluation tools, application notes, phone and email
support—all available at www.analog.com.
Rev. D | Page 23 of 28
AD8099
Data Sheet
OUTLINE DIMENSIONS
5.00
4.90
4.80
2.29
0.356
6.20
6.00
5.80
5
8
4.00
3.90
3.80
2.29
0.457
4
1
BOTTOM VIEW
1.27 BSC
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE CONNECTION DIAGRAMS
SECTION OF THIS DATA SHEET.
3.81 REF
TOP VIEW
SEATING
PLANE
0.50
0.25
0.10 MAX
0.05 NOM
COPLANARITY
0.10
0.51
0.31
8°
0°
45°
0.25
0.17
1.04 REF
1.27
0.40
06-02-2011-B
1.65
1.25
1.75
1.35
COMPLIANT TO JEDEC STANDARDS MS-012-A A
Figure 72. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP]
Narrow Body
(RD-8-1)
Dimensions shown in millimeters
0.60 MAX
5
TOP
VIEW
PIN 1
INDICATOR
2.95
2.75 SQ
2.55
8
12° MAX
SEATING
PLANE
0.50
0.40
0.30
0.70 MAX
0.65 TYP
0.05 MAX
0.01 NOM
0.30
0.23
0.18
0.20 REF
1.60
1.45
1.30
EXPOSED
PAD
(BOTTOM VIEW)
4
0.90 MAX
0.85 NOM
0.50
BSC
0.60 MAX
1
1.89
1.74
1.59
PIN 1
INDICATOR
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE CONNECTION DIAGRAMS
SECTION OF THIS DATA SHEET.
Figure 73. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD]
3 mm × 3 mm Body, Very Thin, Dual Lead
(CP-8-2)
Dimensions shown in millimeters
Rev. D | Page 24 of 28
04-04-2012-A
3.25
3.00 SQ
2.75
AD8099
Data Sheet
ORDERING GUIDE
Model 1
AD8099ARD
AD8099ARD-REEL
AD8099ARD-REEL7
AD8099ARDZ
AD8099ARDZ-REEL
AD8099ARDZ-REEL7
AD8099ACPZ-R2
AD8099ACPZ-REEL
AD8099ACPZ-REEL7
AD8099ACPI-EBZ
AD8099ACPN-EBZ
AD8099ARDI-EBZ
AD8099ARDN-EBZ
1
Ordering
Quantity
98
2,500
1,000
98
2,500
1,000
250
5,000
1,500
Temperature Range
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Package Description
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead Lead Frame Chip Scale Package [LFCSP_VD]
8-Lead Lead Frame Chip Scale Package [LFCSP_VD]
8-Lead Lead Frame Chip Scale Package [LFCSP_VD]
Evaluation Board for Inverting 8-Lead LFCSP_VD
Evaluation Board for Noninverting 8-Lead LFCSP_VD
Evaluation Board for Inverting 8-Lead SOIC_N_EP
Evaluation Board for Noninverting 8-Lead SOIC_N_EP
Z = RoHS Compliant Part.
Rev. D | Page 25 of 28
Branding
HDB
HDB
HDB
Package
Option
RD-8-1
RD-8-1
RD-8-1
RD-8-1
RD-8-1
RD-8-1
CP-8-2
CP-8-2
CP-8-2
AD8099
Data Sheet
NOTES
Rev. D | Page 26 of 28
AD8099
Data Sheet
NOTES
Rev. D | Page 27 of 28
AD8099
Data Sheet
NOTES
© 2003–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04511–0–8/13(D)
Rev. D | Page 28 of 28