Altera JESD204B IP Core and ADI AD9680 Hardware
Checkout Report
2015.05.11
AN-710
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The Altera JESD204B IP core is a high-speed point-to-point serial interface intellectual property (IP).
The JESD204B IP core has been hardware-tested with a number of selected JESD204B-compliant ADC
(analog-to-digital converter) devices.
This report highlights the interoperability of the JESD204B IP core with the AD9680 converter evaluation
module (EVM) from Analog Devices Inc. (ADI). The following sections describe the hardware checkout
methodology and test results.
Related Information
• JESD204B IP Core User Guide
• ADI AD9680 Datasheet
Hardware Requirements
The hardware checkout test requires the following hardware and software tools:
•
•
•
•
•
Stratix V Advanced Systems Development Kit with 15 V power adaptor
Arria 10 FPGA Development Kit
ADI AD9680 EVM with 4.5 V power adaptor (1)
Mini-USB cable
Clock source card capable of generating configurable device clock frequencies
Related Information
• Parameter Configuration on page 12
(1)
The power adaptor is not needed for the production version of AD9680-1000EBZ EVM (as shown in Figure
3).
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
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trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
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Hardware Setup for Stratix V Advanced Systems Development Kit
Hardware Setup for Stratix V Advanced Systems Development Kit
Figure 1: Hardware Setup
A Stratix V Advanced Systems Development Kit is used with the ADI AD9680 daughter card module (3)
attached to the FMC connector on the development board.
• The AD9680 EVM derives power from 4.5 V power adaptor.
• The FPGA and ADC device clock is supplied by external clock source card through the SMA
connectors on the AD9680 EVM.
• Both the FPGA and ADC device clock must be sourced from the same clock source card with two
different frequencies, one for the FPGA and one for ADC.
• For subclass 1, the FPGA generates SYSREF for the JESD204B IP core as well as the AD9680 device.
Transceiver Lanes
Device Clock
rx_dev_sync_n
sysref
SPI
Stratix V Advanced Systems Development Kit
ADI AD9680 EVM
(3)
The AD9680 EVM used in this report differs from the production version of AD9680-1000EBZ EVM.
However, there is no difference in terms of functionality between these two EVM.
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Hardware Setup for Stratix V Advanced Systems Development Kit
Figure 2: System Diagram
The system-level diagram shows how the different modules connect in this design.
In this setup, where LMF=421, the data rate of transceiver lanes is 12.5 Gbps. An external clock source
card provides 312.5 MHz clock to the FPGA and 1250 MHz sampling clock to AD9680 device.
jesd204b_ed_top.sv
Stratix V FPGA #1
FMC
AD9680 EVM
mgmt_clk
jesd204b_ed.sv
ADC
rx_serial_data[3:0] (12.5Gbps)
SignalTap II
L0 – L3
ADC
Qsys System
JTAG to Avalon
Master Bridge
Avalon MM
Slave
Translator
Design Example
Avalon-MM
Interface
signals
global_rst_n
PIO
sclk, ss_n[0], miso, mosi
device_clk (312.5MHz)
link_clk (312.5MHz)
JESD204B
IP Core
(Duplex)
L=4,M=2,F=1
Sysref
generator
4-wire
AD9680
Conversion
circuit
3-wire
SMA
sysref_out (39.0625MHz @ K=32)
CLK &
SYNC
rx_dev_sync_n
sync_n
sysref
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SPI
Slave
SMA
1.25 GHz
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Hardware Setup for Arria 10 FPGA Development Kit
Hardware Setup for Arria 10 FPGA Development Kit
Figure 3: Hardware Setup
An Arria 10 FPGA Development Kit is used with the ADI AD9680 daughter card module attached to the
FMC connector on the development board. (4)
• The FPGA and ADC device clock is supplied by external clock source card through the SMA
connectors on the AD9680 EVM.
• Both the FPGA and ADC device clock must be sourced from the same clock source card with two
different frequencies, one for the FPGA and one for ADC.
• For subclass 1, the FPGA generates SYSREF for the JESD204B IP core as well as the AD9680 device.
Arria 10 FPGA Development Kit
Clock Source
ADI AD9680 EVM
(4)
The AD9680 EVM used in this report differs from the production version of AD9680-1000EBZ EVM.
However, there is no difference in terms of functionality between these two EVM.
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Hardware Checkout Methodology
Figure 4: System Diagram
The system-level diagram shows how the different modules connect in this design.
In this setup, where LMF=222, the data rate of transceiver lanes is 12.5 Gbps. An external clock source
card provides 312.5 MHz clock to the FPGA and 625 MHz sampling clock to AD9680 device.
jesd204b_ed_top.sv
FMC
Arria 10 FPGA
AD9680 EVM
mgmt_clk
jesd204b_ed.sv
ADC
rx_serial_data[1:0] (12.5 Gbps)
SignalTap II
L0 – L3
ADC
Qsys System
JTAG to Avalon
Master Bridge
Avalon MM
Slave
Translator
Design Example
Avalon-MM
Interface
signals
global_rst_n
PIO
sclk, ss_n[0], miso, mosi
device_clk (312.5 MHz)
4-wire
3-wire
link_clk (312.5 MHz)
JESD204B
IP Core
(Duplex)
L=2,M=2,F=2
Sysref
generator
AD9680
Conversion
circuit
SPI
Slave
sysref_out (19.53 MHz @ K=32)
CLK &
SYNC
rx_dev_sync_n
sync_n
sysref
625 MHz
External
Clock Source
Hardware Checkout Methodology
The following section describes the test objectives, procedure, and the passing criteria. The test covers the
following areas:
•
•
•
•
Receiver data link layer
Receiver transport layer
Descrambling
Deterministic latency (Subclass 1)
Receiver Data Link Layer
This test area covers the test cases for code group synchronization (CGS) and initial frame and lane
synchronization.
On link start up, the receiver issues a synchronization request and the transmitter transmits /K/ (K28.5)
characters. The SignalTap II Logic Analyzer tool monitors the receiver data link layer operation.
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Code Group Synchronization (CGS)
Code Group Synchronization (CGS)
Table 1: CGS Test Cases
Test Case
Objective
Description
Passing Criteria
The following signals in <ip_variant_
name>_inst_phy.v are tapped:
CGS.1
Check whether
sync request is
deasserted after a
correct reception
of four successive /
K/ characters.
• /K/ character or K28.5 (0xBC) is
observed at each octet of the
jesd204_rx_pcs_data bus.
• jesd204_rx_pcs_data[(L*32)• The jesd204_rx_pcs_data_
1:0]
valid signal is asserted to
• jesd204_rx_pcs_data_valid[Lindicate that data from the PCS
1:0]
is valid.
• jesd204_rx_pcs_kchar_
•
The jesd204_rx_pcs_kchar_
data[(L*4)-1:0](5)
data signal is asserted whenever
control
characters like /K/, /R/, /
The following signals in <ip_variant_
Q/
or
/A/
characters are
name>.v are tapped:
observed.
• rx_dev_sync_n
• The rx_dev_sync_n signal is
• jesd204_rx_int
deasserted after a correct
reception of at least four
The rxlink_clk is used as the
successive /K/ characters.
SignalTap II sampling clock.
• The jesd204_rx_int signal is
Each lane is represented by 32-bit data
deasserted if there is no error.
bus in the jesd204_rx_pcs_data
signal. The 32-bit data bus is divided
into 4 octets.
CGS.2
Check full CGS at The following signals in <ip_variant_
the receiver after name>_inst_phy.v are tapped:
correct reception
• jesd204_rx_pcs_
of another four
errdetect[(L*4)-1:0]
8B/10B characters.
• jesd204_rx_pcs_disperr[(L*4)-
The jesd204_rx_pcs_errdetect,
jesd204_rx_pcs_disperr, and
jesd204_rx_int signals should not
be asserted during CGS phase.
1:0] (5)
The following signal in <ip_variant_
name>.v is tapped:
• jesd204_rx_int
The rxlink_clk is used as the
SignalTap II sampling clock.
(5)
L is the number of lanes.
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Initial Frame and Lane Synchronization
7
Initial Frame and Lane Synchronization
Table 2: Initial Frame and Lane Synchronization Test Cases
Test
Case
ILA.
1
Objective
Check whether the
initial frame
synchronization
state machine
enters FS_DATA
state upon
receiving non /K/
characters.
Description
The following signals in <ip_variant_
name>_inst_phy.v are tapped:
• jesd204_rx_pcs_data[(L*32)•
•
1:0]
jesd204_rx_pcs_data_valid[L1:0]
jesd204_rx_pcs_kchar_
data[(L*4)-1:0](5)
The following signals in <ip_variant_
name>.v are tapped:
• rx_dev_sync_n
• jesd204_rx_int
The rxlink_clk is used as the
SignalTap II sampling clock.
Each lane is represented by 32-bit data
bus in jesd204_rx_pcs_data. signal.
The 32-bit data bus for is divided into 4
octets.
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Passing Criteria
• /R/ character or K28.0 (0x1C) is
observed after /K/ character at
the jesd204_rx_pcs_data bus.
• The jesd204_rx_pcs_data_
valid signal must be asserted to
indicate that data from the PCS
is valid.
• The rx_dev_sync_n and
jesd204_rx_int signals are
deasserted.
• Each multiframe in ILAS phase
ends with /A/ character or K28.3
(0x7C).
• The jesd204_rx_pcs_kchar_
data signal is asserted whenever
control characters like /K/, /R/, /
Q/ or /A/ characters are
observed.
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Receiver Transport Layer
Test
Case
Objective
ILA.
2
Check the
JESD204B
configuration
parameters from
ADC in second
multiframe.
Description
The following signals in <ip_variant_
name>_inst_phy.v are tapped:
• jesd204_rx_pcs_data[(L*32)1:0]
• jesd204_rx_pcs_data_valid[L1:0](5)
The following signal in <ip_variant_
name>.v is tapped:
Passing Criteria
• /R/ character is followed by /Q/
character or K28.4 (0x9C) at the
beginning of second multiframe.
• The jesd204_rx_int signal is
deasserted if there is no error.
• Octets 0-13 read from these
registers match with the
JESD204B parameters in each
test setup.
• jesd204_rx_int
The rxlink_clk is used as the
SignalTap II sampling clock.
The system console accesses the
following registers:
•
•
•
•
ilas_octet0
ilas_octet1
ilas_octet2
ilas_octet3
The content of 14 configuration octets
in the second multiframe is stored in
these 32-bit registers—ilas_octet0, ilas_
octet1, ilas_octet2, and ilas_octet3.
ILA.
3
Check the lane
alignment
The following signals in <ip_variant_
name>_inst_phy.v are tapped:
• jesd204_rx_pcs_data[(L*32)•
1:0]
jesd204_rx_pcs_data_valid[L1:0](5)
The following signals in <ip_variant_
name>.v are tapped:
• rx_somf[3:0]
• dev_lane_aligned
• jesd204_rx_int
• The dev_lane_aligned signal is
asserted upon the last /A/
character received by the ILAS,
which is followed by the first
data octet.
• The rx_somf signal marks the
start of multiframe in user data
phase.
• The jesd204_rx_int signal is
deasserted if there is no error.
The rxlink_clk is used as the
SignalTap II sampling clock.
Receiver Transport Layer
To check the data integrity of the payload data stream through the RX JESD204B IP core and transport
layer, the ADC is configured to output PRBS-9 test data pattern. The ADC is also set to operate with the
same configuration as set in the JESD204B IP core. The PRBS checker in the FPGA fabric checks data
integrity for one minute.
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Descrambling
9
Figure 5: Data Integrity Check Using PRBS Checker
This figure shows the conceptual test setup for data integrity checking.
ADC
PRBS
Generator
TX Transport
Layer
TX PHY
and Link Layer
RX Transport
Layer
RX JESD204B
IP Core
PHY and Link Layer
FPGA
PRBS
Checker
The SignalTap II Logic Analyzer tool monitors the operation of the RX transport layer.
Table 3: Transport Layer Test Cases
Test Case
TL.1
Objective
Check the
transport layer
mapping using
PRBS-9 test
pattern.
Description
The following signal in altera_
jesd204_transport_rx_top.sv are
tapped:
• jesd204_rx_data_valid
Passing Criteria
• The jesd204_rx_data_valid
signal is asserted.
• The data_error and jesd204_
rx_int signals are deasserted.
The following signals in jesd204b_ed.v
are tapped:
• data_error
• jesd204_rx_int
The rxframe_clk is used as the
SignalTap II sampling clock.
The data_error signal indicates a pass
or fail for the PRBS checker.
Descrambling
The PRBS checker at the RX transport layer checks the data integrity of descrambler.
The SignalTap II Logic Analyzer tool monitors the operation of the RX transport layer.
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Deterministic Latency (Subclass 1)
Table 4: Descrambler Test Cases
Test Case
SCR.1
Objective
Description
Check the
functionality of
the descrambler
using PRBS-9 test
pattern.
Passing Criteria
Enable scrambler at the ADC and
descrambler at the RX JESD204B IP
core.
The signals that are tapped in this test
case are similar to test case TL.1
• The jesd204_rx_data_valid
signal is asserted.
• The data_error and jesd204_
rx_int signals are deasserted.
Deterministic Latency (Subclass 1)
Figure below shows the block diagram of deterministic latency test setup. A SYSREF generator provides a
periodic SYSREF pulse for both the AD9680 and JESD204B IP core. The SYSREF generator is running in
link clock domain and the period of SYSREF pulse is configured to the desired multiframe size. The
SYSREF pulse restarts the LMF counter and realigns it to the LMFC boundary.
Figure 6: Deterministic Latency Test Setup Block Diagram for Stratix V FPGA
mgmt_clk
jesd204b_ed_top.sv
Stratix V FPGA #1
FMC
AD9680 EVM
jesd204b_ed.sv
SignalTap II
ADC
rx_serial_data[3:0] (12.5Gbps)
Deterministic
Latency
Measurement
L0 – L3
ADC
Qsys System
JTAG to Avalon
Master Bridge
Avalon MM
Slave
Translator
sclk, ss_n[0], miso, mosi
Design Example
Avalon-MM
Interface
signals
global_rst_n
PIO
JESD204B
IP Core
(Duplex)
L=4,M=2,F=1
device_clk (312.5MHz)
link_clk (312.5MHz)
Sysref
generator
4-wire
AD9680
Conversion
circuit
3-wire
SMA
sysref_out (39.0625MHz @ K=32)
CLK &
SYNC
rx_dev_sync_n
sync_n
sysref
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Slave
SMA
1.25GHz
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Deterministic Latency (Subclass 1)
Figure 7: Deterministic Latency Test Setup Block Diagram for Arria 10 FPGA
mgmt_clk
jesd204b_ed_top.sv
FMC
Arria 10 FPGA
AD9680 EVM
jesd204b_ed.sv
SignalTap II
ADC
rx_serial_data[1:0] (12.5 Gbps)
Deterministic
Latency
Measurement
L0 – L3
ADC
Qsys System
4-wire
sclk, ss_n[0], miso, mosi
JTAG to Avalon
Master Bridge
Design Example
Avalon-MM
Interface
signals
Avalon MM
Slave
Translator
JESD204B
IP Core
(Duplex)
global_rst_n L=2,M=2,F=2
PIO
AD9680
Conversion
circuit
device_clk (312.5 MHz)
3-wire
link_clk (312.5 MHz)
SPI
Slave
sysref_out (19.53 MHz @ K=32)
Sysref
generator
CLK &
SYNC
rx_dev_sync_n
sync_n
sysref
625 MHz
External
Clock Source
Figure 8: Deterministic Latency Measurement Timing Diagram
Link Clock
State
ILAS
USER_DATA
SYNC~
RX Valid
sync_to_rxvalid_cnt
1
2
3
n-1
n
With the setup above, three test cases are defined to prove deterministic latency. The continuous SYSREF
detection mode is enabled on the JESD204B IP core and AD9680 for this deterministic measurement.
Table 5: Deterministic Latency Test Cases
Test Case
DL.1
Objective
Check the FPGA
SYSREF single
detection.
Description
Check that the FPGA detects the first
rising edge of SYSREF pulse.
The value of sysref_singledet
identifier should be zero.
Read the status of sysref_singledet
(bit[2]) identifier in the syncn_sysref_
ctrl register at address 0x54.
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Passing Criteria
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JESD204B IP Core and ADC Configurations
Test Case
DL.2
Objective
Description
Passing Criteria
Check the SYSREF Check that the FPGA and ADC
capture.
capture SYSREF correctly and restart
the LMF counter. Both the FPGA and
ADC are also reset repetitively.
If the SYSREF is captured correctly
and the LMF counter restarts, for
every reset, the rbd_count value
should only vary by two integers
due to word alignment.
Read the value of rbd_count
(bit[10:3]) identifier in rx_status0
register at address 0x80.
DL.3
Check the latency
from start of
SYNC~ deasser‐
tion to first user
data output.
Check that the latency is fixed for
every FPGA reset and power cycle.
Record the number of link clocks from
the start of SYNC~ deassertion to the
first user data output, which is the
assertion of jesd204_rx_link_valid
signal.
Consistent latency from the start of
SYNC~ deassertion to the assertion
of jesd204_rx_link_valid. signal.
JESD204B IP Core and ADC Configurations
The JESD204B IP core parameters (L, M and F) in this hardware checkout are natively supported by the
AD9680 device's quick configuration register at address 0x570. The transceiver data rate, sampling clock
frequency, and other JESD204B IP core parameters comply with the AD9680 operating conditions.
The hardware checkout testing implements the JESD204B IP core with the following parameter configu‐
ration.
Table 6: Parameter Configuration
Configuration
Setting
LMF
112
124
211
212
222
411
412
421
422
HD
0
0
1
0
0
1
0
1
0
S
1
1
1
2
1
2
4
1
2
N
14
14
14
14
14
14
14
14
14
N’
16
16
16
16
16
16
16
16
16
CS
0
0
0
0
0
0
0
0
0
CF
0
0
0
0
0
0
0
0
0
ADC Device
Clock (MHz)
625
312.5
1250
1250
625
1250
1250
1250
1250
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Test Results for Stratix V and Arria 10 FPGA
Configuration
13
Setting
ADC Sampling
Clock (MHz)
625
312.5
1250
1250
625
1250
1250
1250
1250
FPGA Device
Clock (MHz) (6)
312.5
312.5
312.5
312.5
312.5
156.25
312.5
312.5
312.5
FPGA
Management
Clock (MHz)
100
100
100
100
100
100
100
100
100
FPGA Frame
Clock (MHz) (7)
312.5
312.5
312.5
312.5
312.5
156.25
312.5 or 312.5
156.25
(For
Arria
10)
312.5
FPGA Link
Clock (MHz) (7)
312.5
312.5
312.5
312.5
312.5
156.25
156.25
312.5
312.5
12.5
12.5
12.5
12.5
6.25
6.25
12.5
12.5
Lane Rate (Gbps) 12.5
Character
Replacement
Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled
Data Pattern
PRBS-9 PRBS-9 PRBS-9 PRBS-9 PRBS-9 PRBS-9 PRBS-9 PRBS-9 PRBS-9
Ramp(8) Ramp(8) Ramp(8) Ramp(8) Ramp(8) Ramp(8) Ramp(8) Ramp(8) Ramp(8)
Test Results for Stratix V and Arria 10 FPGA
Table 7: Results Definition
Result
(6)
(7)
(8)
Definition
PASS
The Device Under Test (DUT) was observed to exhibit conformant behavior.
PASS with
comments
The DUT was observed to exhibit conformant behavior. However, an additional explana‐
tion of the situation is included, such as due to time limitations only a portion of the
testing was performed.
FAIL
The DUT was observed to exhibit non-conformant behavior.
Warning
The DUT was observed to exhibit behavior that is not recommended.
The device clock is used to clock the transceiver.
The frame clock and link clock is derived from the device clock using an internal PLL.
The ramp pattern is used in deterministic latency measurement test cases DL.1, DL.2, and DL.3only.
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Test Results for Stratix V and Arria 10 FPGA
Result
Definition
Refer to
comments
From the observations, a valid pass or fail could not be determined. An additional
explanation of the situation is included.
The following table lists the results for test cases CGS.1, CGS.2, ILA.1, ILA.2, ILA.3, TL.1, and SCR.1 with
different values of L, M, F, K, subclass, data rate, sampling clock, link clock, and SYSREF frequencies.
Table 8: Test Results
Test
L
M
F
Subclass
SCR
K
Data rate
(Mbps)
Sampling
Clock (MHz)
Link Clock
(MHz)
Result
1
1
1
2
1
0
16
12500
625
312.5
Pass
2
1
1
2
1
1
16
12500
625
312.5
Pass
3
1
1
2
1
0
32
12500
625
312.5
Pass
4
1
1
2
1
1
32
12500
625
312.5
Pass
5
2
1
1
1
0
20
12500
1250
312.5
Pass
6
2
1
1
1
1
20
12500
1250
312.5
Pass
7
2
1
1
1
0
32
12500
1250
312.5
Pass
8
2
1
1
1
1
32
12500
1250
312.5
Pass
9
2
1
2
1
0
16
12500
1250
312.5
Pass
10
2
1
2
1
1
16
12500
1250
312.5
Pass
11
2
1
2
1
0
32
12500
1250
312.5
Pass
12
2
1
2
1
1
32
12500
1250
312.5
Pass
13
4
1
1
1
0
20
6250
1250
156.25
Pass
14
4
1
1
1
1
20
6250
1250
156.25
Pass
15
4
1
1
1
0
32
6250
1250
156.25
Pass
16
4
1
1
1
1
32
6250
1250
156.25
Pass
17
4
1
2
1
0
16
6250
1250
156.25
Pass
18
4
1
2
1
1
16
6250
1250
156.25
Pass
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Test Results for Stratix V and Arria 10 FPGA
Test
L
M
F
Subclass
SCR
K
Data rate
(Mbps)
Sampling
Clock (MHz)
Link Clock
(MHz)
Result
19
4
1
2
1
0
32
6250
1250
156.25
Pass
20
4
1
2
1
1
32
6250
1250
156.25
Pass
21
1
2
4
1
0
16
12500
312.5
312.5
Pass
22
1
2
4
1
1
16
12500
312.5
312.5
Pass
23
1
2
4
1
0
32
12500
312.5
312.5
Pass
24
1
2
4
1
1
32
12500
312.5
312.5
Pass
25
2
2
2
1
0
16
12500
625
312.5
Pass
26
2
2
2
1
1
16
12500
625
312.5
Pass
27
2
2
2
1
0
32
12500
625
312.5
Pass
28
2
2
2
1
1
32
12500
625
312.5
Pass
29
4
2
1
1
0
20
12500
1250
312.5
Pass
30
4
2
1
1
1
20
12500
1250
312.5
Pass
31
4
2
1
1
0
32
12500
1250
312.5
Pass
32
4
2
1
1
1
32
12500
1250
312.5
Pass
33
4
2
2
1
0
16
12500
1250
312.5
Pass
34
4
2
2
1
1
16
12500
1250
312.5
Pass
35
4
2
2
1
0
32
12500
1250
312.5
Pass
36
4
2
2
1
1
32
12500
1250
312.5
Pass
The following table shows the Stratix V FPGA results for test cases DL.1, DL.2, and DL.3 with different
values of L, M, F, K, subclass, data rate, sampling clock, link clock, and SYSREF frequencies.
Table 9: Test Results For Deterministic Latency Measurement (Stratix V)
Test
DL.1
L
1
M
1
F
2
Subclass
1
K
32
Data rate
(Mbps)
12500
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Sampling Link Clock
Clock (MHz)
(MHz)
625
312.5
Result
Pass
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Test Results for Stratix V and Arria 10 FPGA
Test
L
M
F
Subclass
K
Data rate
(Mbps)
Sampling Link Clock
Clock (MHz)
(MHz)
Result
DL.2
1
1
2
1
32
12500
625
312.5
Pass
DL.3
1
1
2
1
32
12500
625
312.5
Pass with comments.
Link clock observed
= 115–116 with
ADC LMFC offset
register set to 0x00
DL.1
2
1
1
1
32
12500
1250
312.5
Pass
DL.2
2
1
1
1
32
12500
1250
312.5
Pass
DL.3
2
1
1
1
32
12500
1250
312.5
Pass with comments.
Link clock observed
= 75 with ADC
LMFC offset register
set to 0x00
DL.1
2
1
2
1
32
12500
1250
312.5
Pass
DL.2
2
1
2
1
32
12500
1250
312.5
Pass
DL.3
2
1
2
1
32
12500
1250
312.5
Pass with comments.
Link clock observed
= 115 with ADC
LMFC offset register
set to 0x0C
DL.1
4
1
1
1
32
6250
1250
156.25
Pass
DL.2
4
1
1
1
32
6250
1250
156.25
Pass
DL.3
4
1
1
1
32
6250
1250
156.25
Pass with comments.
Link clock observed
= 67 with ADC
LMFC offset register
set to 0x00
DL.1
4
1
2
1
32
6250
1250
156.25
Pass
DL.2
4
1
2
1
32
6250
1250
156.25
Pass
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Test
DL.3
L
4
M
1
F
2
Subclass
1
K
32
Data rate
(Mbps)
6250
Sampling Link Clock
Clock (MHz)
(MHz)
1250
156.25
17
Result
Pass with comments.
Link clock observed
= 115–116 with
ADC LMFC offset
register set to 0x08
DL.1
1
2
4
1
32
12500
312.5
312.5
Pass
DL.2
1
2
4
1
32
12500
312.5
312.5
Pass
DL.3
1
2
4
1
32
12500
312.5
312.5
Pass with comments.
Link clock observed
= 195 with ADC
LMFC offset register
set to 0x00
DL.1
2
2
2
1
32
12500
625
312.5
Pass
DL.2
2
2
2
1
32
12500
625
312.5
Pass
DL.3
2
2
2
1
32
12500
625
312.5
Pass with comments.
Link clock observed
= 115–116 with
ADC LMFC offset
register set to 0x00
DL.1
4
2
1
1
32
12500
1250
312.5
Pass
DL.2
4
2
1
1
32
12500
1250
312.5
Pass
DL.3
4
2
1
1
32
12500
1250
312.5
Pass with comments.
Link clock observed
= 75 with ADC
LMFC offset register
set to 0x14
DL.1
4
2
2
1
32
12500
1250
312.5
Pass
DL.2
4
2
2
1
32
12500
1250
312.5
Pass
DL.3
4
2
2
1
32
12500
1250
312.5
Pass with comments.
Link clock observed
= 115 with ADC
LMFC offset register
set to 0x10
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Test Results for Stratix V and Arria 10 FPGA
The following table shows the Arria 10 FPGA results for test cases DL.1, DL.2, and DL.3 with different
values of L, M, F, K, subclass, data rate, sampling clock, link clock, and SYSREF frequencies.
Table 10: Test Results For Deterministic Latency Measurement (Arria 10)
Test
L
M
F
Subclass
K
Data rate
(Gbps)
Sampling
Clock
(MHz)
Link Clock
(MHz)
Result
DL.1
1
1
2
1
32
12.5
625
312.5
PASS
DL.2
1
1
2
1
32
12.5
625
312.5
PASS
DL.3
1
1
2
1
32
12.5
625
312.5
PASS with
comments.
Link clock
observed = 115
with ADC LMFC
offset register set
to 0x00.
DL.1
1
2
4
1
32
12.5
312.5
312.5
PASS
DL.2
1
2
4
1
32
12.5
312.5
312.5
PASS
DL.3
1
2
4
1
32
12.5
312.5
312.5
PASS with
comments.
Link clock
observed = 195
with ADC LMFC
offset register set
to 0x00.
DL.1
2
1
1
1
32
12.5
1250
312.5
PASS
DL.2
2
1
1
1
32
12.5
1250
312.5
PASS
DL.3
2
1
1
1
32
12.5
1250
312.5
PASS with
comments.
Link clock
observed = 67
with ADC LMFC
offset register set
to 0x00.
DL.1
2
1
2
1
32
12.5
1250
312.5
PASS
DL.2
2
1
2
1
32
12.5
1250
312.5
PASS
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Test
DL.3
L
2
M
1
F
2
Subclass
1
K
32
Data rate
(Gbps)
12.5
Sampling
Clock
(MHz)
1250
Link Clock
(MHz)
312.5
19
Result
PASS with
comments.
Link clock
observed = 99
with ADC LMFC
offset register set
to 0x00.
DL.1
2
2
2
1
32
12.5
625
312.5
PASS
DL.2
2
2
2
1
32
12.5
625
312.5
PASS
DL.3
2
2
2
1
32
12.5
625
312.5
PASS with
comments.
Link clock
observed = 115
with ADC LMFC
offset register set
to 0x00.
DL.1
4
1
1
1
32
6.25
1250
156.25
PASS
DL.2
4
1
1
1
32
6.25
1250
156.25
PASS
DL.3
4
1
1
1
32
6.25
1250
156.25
PASS with
comments.
Link clock
observed = 67
with ADC LMFC
offset register set
to 0x00.
DL.4
4
1
1
1
32
6.25
1250
156.25
PASS
DL.1
4
1
2
1
32
6.25
1250
156.25
PASS
DL.2
4
1
2
1
32
6.25
1250
156.25
PASS
DL.3
4
1
2
1
32
6.25
1250
156.25
PASS with
comments.
Link clock
observed = 99
with ADC LMFC
offset register set
to 0x00.
DL.1
4
2
1
1
32
12.5
1250
312.5
PASS
DL.2
4
2
1
1
32
12.5
1250
312.5
PASS
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Test Result Comments
Test
DL.3
L
4
M
2
F
1
Subclass
1
K
32
Data rate
(Gbps)
12.5
Sampling
Clock
(MHz)
1250
Link Clock
(MHz)
312.5
Result
PASS with
comments.
Link clock
observed = 67
with ADC LMFC
offset register set
to 0x00.
DL.1
4
2
2
1
32
12.5
1250
312.5
PASS
DL.2
4
2
2
1
32
12.5
1250
312.5
PASS
DL.3
4
2
2
1
32
12.5
1250
312.5
PASS with
comments.
Link clock
observed = 99
with ADC LMFC
offset register set
to 0x00.
The following figure shows the SignalTap II waveform of the clock count from the deassertion of SYNC~
to the assertion of jesd204_rx_link_valid signal, the first output of the ramp test pattern (DL.3 test
case). The clock count measures the first user data output latency.
Figure 9: Deterministic Latency Measurement Ramp Test Pattern Diagram
Test Result Comments
In each test case, the RX JESD204B IP core successfully initialize from CGS phase, ILA phase, and until
user data phase. No data integrity issue is observed by the PRBS checker. For test case with LMF=411 and
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412, the data rate is reduced to 6250 Mbps to limit the ADC sampling rate to 1250 Msps. The following
table describes the scenarios where there is a difference in the data rate.
Table 11: Sample Rate Implication for Test Case with LMF=411 and 412
Item
Scenario 1
Scenario 2
Remark
Data rate
12500 Mbps
6250Mbps
Data rate is within the operating
condition of AD9680 device.
Link clock = data rate/40
312.5 MHz
156.25 MHz
Link clock frequency is
determined by the data rate.
ADC sample clock must be ≤
ADC maximum sampling rate
2500 Msps
1250 Msps
Sample clock frequency in
scenario 1 is beyond the
operating condition of AD9680
device.
In deterministic measurement test case DL.3, the link clock count in the FPGA depends on the board
layout and the LMFC offset value set in the ADC register. The link clock count varies by only one link
clock when the FPGA and ADC are reset or power cycled. The link clock variation in the deterministic
latency measurement is caused by word alignment, where the control characters fall into the next cycle of
data some time after realignment. This makes the duration of ILAS phase longer by one link clock some
time after reset or power cycle.
AN 710 Document Revision History
Date
Version
Changes
May 2015
2014.05.11
Added Arria 10 FPGA Development Kit hardware setup,
parameter configurations, and test results.
July 2014
2014.07.10
Initial release.
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