Altera JESD204B IP Core and ADI AD9625 Hardware
Checkout Report
2014.10.13
AN-712
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The Altera® JESD204B IP core is a high-speed point-to-point serial interface intellectual property (IP).
The JESD204B IP core has been hardware-tested with a number of selected JESD204B-compliant ADC
(analog-to-digital converter) devices.
This report highlights the interoperability of the JESD204B IP core with the AD9625 converter evaluation
module (EVM) from Analog Devices Inc. (ADI). The following sections describe the hardware checkout
methodology and test results.
Related Information
• JESD204B IP Core User Guide
• ADI AD9625 Datasheet
Hardware Requirements
The hardware checkout test requires the following hardware and software tools:
•
•
•
•
Stratix V Advanced Systems Development Kit with 15 V power adaptor
ADI AD9625 EVM
Mini-USB cable
Clock source card capable of generating device clock frequencies
Hardware Setup
A Stratix V Advanced Systems Development Kit is used with the ADI AD9625 daughter card module attached
to the FMC connector of the development board.
• The AD9625 EVM derives power through the development kit FMC connector.
• The ADC device clock is supplied by external clock source card through the SMA connector on the
AD9625 EVM.
• The AD9625 divides the sampling clock by four and supplies this divided clock through its DIVCLK pins
to the FPGA.
• For subclass 1, the FPGA generates SYSREF for the JESD204B IP core as well as the AD9625 device.
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Hardware Setup
Figure 1: Hardware Setup
Transceiver Lanes
Device Clock
rx_dev_sync_n FPGA 1
sysref
SPI
Power
2.5 GHz
External Clock
FPGA 2
Stratix V Advanced Systems Development Kit
ADI AD9625 EVM
Figure 2: System-Level Block Diagram
mgmt_clk jesd204b_ed_top.sv
Stratix V FPGA #1
jesd204b_ed.sv
Design Example
SignalTap II
Qsys System
JTAG to
Avalon Master
Bridge
Avalon-MM
Slave
Translator
AD9625 EVM
AD9625
rx_serial_data[7:0]
(6.25 Gbps) L0 - L7
sclk, ss_n[0], miso, mosi
ADC
4 Wire
Conversion
Circuit
link_clk (156.25 MHz)
Avalon-MM
Interface
Signals
3 Wire
Sysref
Generator
device_clk (625 MHz)
global_rst_n
PIO
FMC
JESD204B
MegaCore IP
L = 8, M = 1, F =1
sysref_out
(19.5313 MHz)
SPI Slave
Clock and
Sync
rx_dev_sync_n
SMA
2.5 GHz
The system-level block diagram shows how the different modules connect in this design. In the setup depicted
above, LMF=811 and the data rate of transceiver lanes is 6.25 Gbps. An external clock source card provides
2.5 GHz sampling clock to the AD9625 device and the ADC supplies 625 MHz FPGA device clock through
its DIVCLK pin.
Related Information
• JESD204B IP Core and ADC Configurations on page 8
More information about other configurations.
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Hardware Checkout Methodology
3
Hardware Checkout Methodology
The following section describes the test objectives, procedure, and the passing criteria. The test covers the
following areas:
•
•
•
•
Receiver data link layer
Receiver transport layer
Descrambling
Deterministic latency (Subclass 1)
Receiver Data Link Layer
This test area covers the test cases for code group synchronization (CGS) and initial frame and lane
synchronization.
On link start-up, the receiver issues a synchronization request and the transmitter transmits /K/ (K28.5)
characters. The SignalTap II Logic Analyzer tool monitors the receiver data link layer operation.
Code Group Synchronization (CGS)
Table 1: CGS Test Cases
Test Case
Objective
Description
CGS.1
Check whether
sync request is
deasserted after
correct reception
of four successive /
K/ characters.
The following signals in <ip_variant_
name>_inst_phy.v are tapped:
(1)
Passing Criteria
• /K/ character or K28.5 (0xBC) is
observed at each octet of the
jesd204_rx_pcs_data bus.
• jesd204_rx_pcs_data[(L*32)• The jesd204_rx_pcs_data_
1:0]
valid signal is asserted to
• jesd204_rx_pcs_data_valid[Lindicate data from the PCS is
1:0]
valid.
• jesd204_rx_pcs_kchar_
•
The jesd204_rx_pcs_kchar_
(1)
data[(L*4)-1:0]
data signal is asserted whenever
control characters like /K/, /R/, /
The following signals in <ip_variant_
Q/ or /A/ characters are
name>.v are tapped:
observed.
• rx_dev_sync_n
• The rx_dev_sync_n signal is de• jesd204_rx_int
asserted after correct reception
of at least four successive /K/
The rxlink_clk is used as the
characters.
SignalTap II sampling clock.
• The jesd204_rx_int signal is
Each lane is represented by 32-bit data
deasserted if there is no error.
bus in jesd204_rx_pcs_data signal.
The 32-bit data bus is divided into 4
octets.
L indicates the number of lanes.
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Initial Frame and Lane Synchronization
Test Case
CGS.2
Objective
Description
Check full CGS at The following signals in <ip_variant_
the receiver after name>_inst_phy.v are tapped:
correct reception
of another four 8B/ • jesd204_rx_pcs_errdetect[(L*4)
-1:0]
10B characters.
• jesd204_rx_pcs_disperr[(L*4)1:0]
Passing Criteria
The jesd204_rx_pcs_errdetect,
jesd204_rx_pcs_disperr, and
jesd204_rx_int signals should not
be asserted during CGS phase.
(1)
The following signal in <ip_variant_
name>.v are tapped:
• jesd204_rx_int
The rxlink_clk is used as the
SignalTap II sampling clock.
Initial Frame and Lane Synchronization
Table 2: Initial Frame and Lane Synchronization Test Cases
Test Case
Objective
Description
ILA.1
Check whether the
initial frame
synchronization
state machine
enters FS_DATA
state upon
receiving non /K/
characters.
The following signals in <ip_variant_
name>_inst_phy.v are tapped:
(2)
Passing Criteria
• /R/ character or K28.0 (0x1C) is
observed after /K/ character at
the jesd204_rx_pcs_data bus.
• jesd204_rx_pcs_data[(L*32)• The jesd204_rx_pcs_data_
1:0]
valid signal must be asserted to
• jesd204_rx_pcs_data_valid[Lindicate that data from the PCS
1:0]
is valid.
• jesd204_rx_pcs_kchar_
•
The rx_dev_sync_n and
(2)
data[(L*4)-1:0]
jesd204_rx_int signals are
deasserted.
The following signals in <ip_variant_
• Each multiframe in ILAS phase
name>.v are tapped:
ends with /A/ character or K28.3
• rx_dev_sync_n
(0x7C).
• jesd204_rx_int
• The jesd204_rx_pcs_kchar_
data signal is asserted whenever
The rxlink_clk is used as the
control characters like /K/, /R/, /
SignalTap II sampling clock.
Q/ or /A/ characters are
Each lane is represented by 32-bit data
observed.
bus in jesd204_rx_pcs_data. The 32-bit
data bus is divided into 4 octets.
L indicates the number of lanes.
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Receiver Transport Layer
Test Case
ILA.2
Objective
Description
Check the
The following signals in <ip_variant_
JESD204B configu- name>_inst_phy.v are tapped:
ration parameters
• jesd204_rx_pcs_data[(L*32)from ADC in
1:0]
second multiframe.
• jesd204_rx_pcs_data_valid[L1:0]
(2)
The following signal in <ip_variant_
name>.v is tapped:
5
Passing Criteria
• /R/ character is followed by /Q/
character or K28.4 (0x9C) at the
beginning of second multiframe.
• The jesd204_rx_int signal is
deasserted if there is no error.
• Octets 0–13 read from these
registers match with the
JESD204B parameters in each
test setup.
• jesd204_rx_int
The rxlink_clk is used as the
SignalTap II sampling clock.
The system console accesses the
following registers:
•
•
•
•
ilas_octet0
ilas_octet1
ilas_octet2
ilas_octet3
The content of 14 configuration octets
in the second multiframe is stored in
these 32-bit registers—ilas_octet0, ilas_
octet1, ilas_octet2, and ilas_octet3.
ILA.3
Check the lane
alignment
The following signals in <ip_variant_
name>_inst_phy.v are tapped:
• jesd204_rx_pcs_data[(L*32)1:0]
• jesd204_rx_pcs_data_valid[L1:0]
(2)
The following signals in <ip_variant_
name>.v are tapped:
• rx_somf[3:0]
• dev_lane_aligned
• jesd204_rx_int
• The dev_lane_aligned signal
is asserted upon the last /A/
character of the ILAS is received,
which is followed by the first data
octet.
• The rx_somf signal marks the
start of multiframe in user data
phase.
• The jesd204_rx_int signal is
deasserted if there is no error.
The rxlink_clk is used as the
SignalTap II sampling clock.
Receiver Transport Layer
The ADC is configured to output ramp test data pattern to check the data integrity of the payload data stream
through the RX JESD204B IP core and transport layer. The ADC is also set to operate with the same
configuration as in the JESD204B IP core. The ramp pattern checker in the FPGA fabric checks data integrity
for one minute.
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Descrambling
Figure 3: Data Integrity Check Using Ramp Pattern Checker
This figure shows the conceptual test setup for data integrity checking.
ADC
Ramp
Pattern
Generator
TX Transport
Layer
TX PHY
and Link Layer
RX Transport
Layer
RX JESD204B
IP Core
PHY and Link Layer
FPGA
Ramp
Pattern
Checker
The SignalTap II Logic Analyzer tool monitors the operation of the RX transport layer.
Table 3: Transport Layer Test Case
Test Case
TL.1
Objective
Description
Passing Criteria
Check the
The following signal in altera_jesd204_ • The jesd204_rx_data_valid
transport layer
transport_rx_top.sv are tapped:
signal is asserted.
mapping using
•
The data_error and jesd204_
• jesd204_rx_data_valid
ramp test pattern.
rx_int signals are deasserted.
The following signals in jesd204b_ed.sv
are tapped:
• data_error
• jesd204_rx_int
The rxframe_clk is used as the
SignalTap II sampling clock.
The data_error signal indicates a pass
or fail for the ramp checker.
Descrambling
The ramp checker at the RX transport layer checks the data integrity of descrambler. The SignalTap II Logic
Analyzer tool monitors the operation of the RX transport layer.
Table 4: Descrambler Test Case
Test Case
SCR.1
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Objective
Description
Passing Criteria
Check the
Enable scrambler at the ADC and
• The jesd204_rx_data_valid
functionality of the descrambler at the RX JESD204B IP
signal is asserted.
descrambler using core.
• The data_error and jesd204_
ramp test pattern.
rx_int signals are deasserted.
The signals that are tapped in this test
case are similar to test case TL.1
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7
Deterministic Latency (Subclass 1)
Deterministic Latency (Subclass 1)
Figure below shows the block diagram of deterministic latency test setup. A SYSREF generator provides a
periodic SYSREF pulse for both the AD9625 and JESD204B IP core. The SYSREF generator is running in
link clock domain and the period of SYSREF pulse is configured to the desired multiframe size. The SYSREF
pulse restarts the LMF counter and realigns it to the LMFC boundary.
Figure 4: Deterministic Latency Test Setup Block Diagram
mgmt_clk jesd204b_ed_top.sv
Stratix V FPGA #1
SignalTap II
Deterministic
Latency
Measurement
Qsys System
JTAG to
Avalon Master
Bridge
FMC
AD9625 EVM
AD9625
jesd204b_ed.sv
Design Example
rx_serial_data[7:0]
(6.25 Gbps) L0 - L7
sclk, ss_n[0], miso, mosi
ADC
4 Wire
Conversion
Circuit
link_clk (156.25 MHz)
Avalon-MM
Interface
Signals
Avalon-MM
Slave
Translator
3 Wire
Sysref
Generator
sysref_out
(19.5313 MHz)
device_clk (625 MHz)
global_rst_n
PIO
JESD204B
MegaCore IP
L = 8, M = 1, F =1
SPI Slave
Clock and
Sync
rx_dev_sync_n
SMA
2.5 GHz
Figure 5: Deterministic Latency Measurement Timing Diagram
Link Clock
State
ILAS
USER_DATA
SYNC~
RX Valid
Link Clock Count
1
2
3
n-1
n
With the setup above, four test cases were defined to prove deterministic latency. By default, the JESD204B
IP core does single SYSREF detection. The next SYSREF mode is enabled on the AD9625 register 0x03A for
this deterministic latency measurement.
Table 5: Deterministic Latency Test Cases
Test Case
DL.1
Objective
Check the FPGA
SYSREF single
detection.
Description
Check that the FPGA detects the first
rising edge of SYSREF pulse.
The value of sysref_singledet
identifier should be zero.
Read the status of sysref_singledet
(bit[2]) identifier in syncn_sysref_ctrl
register at address 0x54.
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Passing Criteria
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JESD204B IP Core and ADC Configurations
Test Case
Objective
Description
Passing Criteria
DL.2
Check the SYSREF Check that the FPGA and ADC capture If the SYSREF is captured correctly
capture.
SYSREF correctly and restart the LMF and the LMF counter restarts, for
counter for every reset and power cycle. every reset and power cycle, the rbd_
count value should only vary by two
Read the value of rbd_count (bit[10:3])
integers due to the word alignment.
identifier in rx_status0 register at
address 0x80.
DL.3
Check the latency
from start of
SYNC~ deassertion
to first user data
output.
Check that the latency is fixed for every Consistent latency from the start of
FPGA and ADC reset and power cycle. SYNC~ deassertion to the assertion
of jesd204_rx_link_valid signal.
Record the number of link clocks count
from the start of SYNC~ deassertion to
the first user data output, which is the
assertion of jesd204_rx_link_valid
signal. The deterministic latency
measurement block in Figure 4 has a
counter to measure the link clock count.
JESD204B IP Core and ADC Configurations
The JESD204B IP core parameters (L, M and F) in this hardware checkout are natively supported by the
AD9625 device's quick configuration register at address 0x05E. The transceiver data rate, sampling clock
frequency, and other JESD204B parameters comply with the AD9625 operating conditions.
The hardware checkout testing implements the JESD204B IP core with the following parameter configuration.
Table 6: Parameter Settings
Configuration
Setting
LMF
118
214
412
611
811
HD
0
0
0
1
1
S
4
4
4
4
4
N
16 (3)
12
12
12
12
N’
16
16
16
12
16
CS
0
0
0
0
0
CF
0
0
0
0
0
ADC Device Clock (MHz)
2500
625
1250
2500
2500
625
1250
2500
2500
ADC Sampling Clock (MHz) 156.25
(3)
This 16-bit test pattern is output from the JESD204X Test Pattern block in the AD9625 device.
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Test Results
Configuration
9
Setting
FPGA Device Clock (MHz) (4) 625
156.25
312.5
625
625
FPGA Management Clock
(MHz)
100
100
100
100
FPGA Frame Clock (MHz) (5) 78.125
156.25
312.5
156.25
156.25
FPGA Link Clock (MHz) (5)
156.25
156.25
156.25
156.25
156.25
Character Replacement
Enabled
Enabled
Enabled
Enabled
Enabled
Data Pattern
Ramp
Ramp
Ramp
Ramp
Ramp
100
Test Results
The following table contains the possible results and their definition.
Table 7: Results Definition
Result
Definition
PASS
The Device Under Test (DUT) was observed to exhibit conformant behavior.
PASS with comments
The DUT was observed to exhibit conformant behavior. However, an additional
explanation of the situation is included, such as due to time limitations only a
portion of the testing was performed.
FAIL
The DUT was observed to exhibit non-conformant behavior.
Warning
The DUT was observed to exhibit behavior that is not recommended.
Refer to comments
From the observations, a valid pass or fail could not be determined. An additional
explanation of the situation is included.
The following table shows the results for test cases CGS.1, CGS.2, ILA.1, ILA.2, ILA.3, TL.1, and SCR.1 with
different values of L, M, F, K, subclass, data rate, sampling clock and link clock frequencies.
Table 8: Results for Test Cases CGS.1, CGS.2, ILA.1, ILA.2, ILA.3, TL.1, and SCR.1
Set
number
(4)
(5)
L
M
F
Subclass
SCR
K
Data rate
ADC
FPGA Link
(Mbps) Sampling
Clock
Clock
(MHz)
(MHz)
Result
1
1
1
8
0
0
16
6250
156.25
156.25
Pass
2
1
1
8
0
1
16
6250
156.25
156.25
Pass
The device clock is used to clock the transceiver.
The frame clock and link clock is derived from the device clock using an internal PLL.
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Test Results
Set
number
L
M
F
Subclass
SCR
K
Data rate
ADC
FPGA Link
(Mbps) Sampling
Clock
Clock
(MHz)
(MHz)
Result
3
1
1
8
0
0
32
6250
156.25
156.25
Pass
4
1
1
8
0
1
32
6250
156.25
156.25
Pass
5
1
1
8
1
0
16
6250
156.25
156.25
Pass
6
1
1
8
1
1
16
6250
156.25
156.25
Pass
7
1
1
8
1
0
32
6250
156.25
156.25
Pass
8
1
1
8
1
1
32
6250
156.25
156.25
Pass
9
2
1
4
0
0
16
6250
625
156.25
Pass
10
2
1
4
0
1
16
6250
625
156.25
Pass
11
2
1
4
0
0
32
6250
625
156.25
Pass
12
2
1
4
0
1
32
6250
625
156.25
Pass
13
2
1
4
1
0
16
6250
625
156.25
Pass
14
2
1
4
1
1
16
6250
625
156.25
Pass
15
2
1
4
1
0
32
6250
625
156.25
Pass
16
2
1
4
1
1
32
6250
625
156.25
Pass
17
4
1
2
0
0
16
6250
1250
156.25
Pass
18
4
1
2
0
1
16
6250
1250
156.25
Pass
19
4
1
2
0
0
32
6250
1250
156.25
Pass
20
4
1
2
0
1
32
6250
1250
156.25
Pass
21
4
1
2
1
0
16
6250
1250
156.25
Pass
22
4
1
2
1
1
16
6250
1250
156.25
Pass
23
4
1
2
1
0
32
6250
1250
156.25
Pass
24
4
1
2
1
1
32
6250
1250
156.25
Pass
25
6
1
1
0
0
20
6250
2500
156.25
Pass with
comments
26
6
1
1
0
1
20
6250
2500
156.25
Pass with
comments
27
6
1
1
0
0
32
6250
2500
156.25
Pass with
comments
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Test Results
Set
number
L
M
F
Subclass
SCR
K
Data rate
ADC
FPGA Link
(Mbps) Sampling
Clock
Clock
(MHz)
(MHz)
11
Result
28
6
1
1
0
1
32
6250
2500
156.25
Pass with
comments
29
6
1
1
1
0
20
6250
2500
156.25
Pass with
comments
30
6
1
1
1
1
20
6250
2500
156.25
Pass with
comments
31
6
1
1
1
0
32
6250
2500
156.25
Pass with
comments
32
6
1
1
1
1
32
6250
2500
156.25
Pass with
comments
33
8
1
1
0
0
20
6250
2500
156.25
Pass
34
8
1
1
0
1
20
6250
2500
156.25
Pass
35
8
1
1
0
0
32
6250
2500
156.25
Pass
36
8
1
1
0
1
32
6250
2500
156.25
Pass
37
8
1
1
1
0
20
6250
2500
156.25
Pass
38
8
1
1
1
1
20
6250
2500
156.25
Pass
39
8
1
1
1
0
32
6250
2500
156.25
Pass
40
8
1
1
1
1
32
6250
2500
156.25
Pass
Table 9: Results For Deterministic Latency Test
Test
L
M
F
Subclass
K
Data rate
(Mbps)
ADC
Sampling
Clock
(MHz)
FPGA Link
Clock
(MHz)
Result
DL.1
1
1
8
1
32
6250
312.5
156.25
Pass
DL.2
1
1
8
1
32
6250
312.5
156.25
Pass
DL.3
1
1
8
1
32
6250
312.5
156.25
Pass with
comments.
Link clock
observed = 323
DL.1
2
1
4
1
32
6250
625
156.25
Pass
DL.2
2
1
4
1
32
6250
625
156.25
Pass
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Test Results
Test
DL.3
L
2
M
1
F
4
Subclass
1
K
32
Data rate
(Mbps)
6250
ADC
Sampling
Clock
(MHz)
625
FPGA Link
Clock
(MHz)
156.25
Result
Pass with
comments.
Link clock
observed = 163
with FPGA
LMFC offset =
0x1C at IP core
register 0x54.
DL.1
4
1
2
1
32
6250
1250
156.25
Pass
DL.2
4
1
2
1
32
6250
1250
156.25
Pass
DL.3
4
1
2
1
32
6250
1250
156.25
Pass with
comments.
Link clock
observed = 99100 with ADC
LMFC offset
register set to
0x14.
DL.1
6
1
1
1
32
6250
2500
156.25
Pass
DL.2
6
1
1
1
32
6250
2500
156.25
Pass
DL.3
6
1
1
1
32
6250
2500
156.25
Pass with
comments.
Link clock
observed = 67
with ADC LMFC
offset register set
to 0x02.
DL.1
8
1
1
1
32
6250
2500
156.25
Pass
DL.2
8
1
1
1
32
6250
2500
156.25
Pass
DL.3
8
1
1
1
32
6250
2500
156.25
Pass with
comments.
Link clock
observed = 67
with ADC LMFC
offset register set
to 0x02.
Altera Corporation
Altera JESD204B IP Core and ADI AD9625 Hardware Checkout Report
Send Feedback
AN-712
2014.10.13
Test Result Comments
13
The following figure shows the SignalTap II waveform of the clock count from the deassertion of SYNC~ to
the assertion of the jesd204_rx_link_valid signal, the first output of the ramp test pattern (DL.3 test case).
The clock count measures the first user data output latency.
Figure 6: Deterministic Latency Measurement Ramp Test Pattern Diagram
Test Result Comments
In each test case, the RX JESD204B IP core successfully initialize from CGS phase, ILA phase, and until user
data phase. Except for LMF=611 test cases, no data integrity issue is observed by the ramp checker. For
LMF=611 test cases, no data integrity check is performed because Altera transport layer does not support
N'=12 configuration.
In deterministic measurement test case DL.3, the link clock count in the FPGA depends on board layout
and the LMFC offset value set in the ADC register. The link clock count varies by only one link clock when
the FPGA and ADC are reset or power cycled. The link clock variation in the deterministic latency
measurement is caused by word alignment, where control characters fall into the next cycle of data some
time after realignment. This makes the duration of ILAS phase longer by one link clock some time after reset
or power cycle. For LMF=214 test case, the LMFC offset value is tuned at the FPGA IP core instead of at the
ADC for consistent latency.
Document Revision History
Date
October 2014
Version
2014.10.13
Changes
Initial release.
Altera JESD204B IP Core and ADI AD9625 Hardware Checkout Report
Send Feedback
Altera Corporation