a
ONE TECHNOLOGY WAY
• P.O.
AN-419
APPLICATION NOTE
BOX 9106
• NORWOOD,
MASSACHUSETTS 02062-9106
• 617/329-4700
A Discrete, Low Phase Noise, 125 MHz Crystal Oscillator
for the AD9850 Complete Direct Digital Synthesizer
By Richard Cushing, Analog Devices, Inc.; Steven Swift, Novatech Instruments, Inc.
The AD9850 complete direct digital synthesizer (DDS) is
a popular device used to implement a low cost, high
speed, digital synthesis system. Clocking the AD9850 at
its maximum rate of 125 MHz may present some technical challenges especially in applications where the
phase noise of the sine output is a major concern.
Numerous requests for recommended high speed clocking solutions to drive the AD9850 have prompted this
application note.
The discretely implemented Butler oscillator* circuit
(see Figure 1) is a less expensive alternative clock source
that has relatively good phase noise performance compared to the typical clock oscillator. The implementation of
a Butler oscillator circuit described below uses a single
supply (+5 V), incorporates a TTL output stage, and has
a parts cost of $20 to $25. This solution represents a
good compromise among low phase noise performance,
circuit complexity, and cost.
Inexpensive commercial sources for a 125 MHz CMOS
clock oscillator to drive the AD9850 are not readily available. One clock oscillator that suits the AD9850 Evaluation Board is made by Champion Technologies (Model
K1300, approximately $45). This is a simple and easily
implemented clock source, but it may be cost prohibitive
and, generally speaking, these clock oscillators are not
known for outstanding phase noise performance.
Reference oscillator phase noise, in conjunction with the
residual phase noise of the AD9850, constitutes the total
phase noise of the DDS output signal. Residual phase
noise of the AD9850 at 1 kHz offset from a 5 MHz carrier
with a 125 MHz reference clock is –134 dBc. DDS, by virtue of its frequency division characteristic, will reduce
the reference oscillator’s phase noise contribution by
TB1
+5V
GROUND
L1
1008CS
0.01mH
C6
10µF
C5
0.01µF
R7
2kΩ
C8
2200pF
R6
2kΩ
L3
1008CS
C7
10µF
120nH
C2
2200pF
L4
BEAD
R2
200Ω
Q1
MPSH10
R4
100Ω
C1
15pF
C4
0.01µF
U1
MC10ELT21
1
8
2
7
3
6
4
5
C10
0.01µF
R3
2kΩ
R9
2kΩ
BNC
J3
125 MHz
OUTPUT
C3
0.01µF
C9
27pF
R8
2kΩ
Y1
125 MHz
7TH OVERTONE
L2
1008CS
390nH
R1
61.9Ω
R5
332Ω
Figure 1. Schematic Diagram and Parts List
*Butler oscillator circuit provided by Steven Swift, P.E., of Novatech Instruments, Inc., Seattle, Washington. 206/322-1562. http://www.eskimo.com/~ntsales
The prototype clock oscillator is built on a 2" × 2" doublesided copper clad board (Figures 2 and 3). The output
will drive 2 V p-p into a 50 Ω load and slightly less than
4 V p-p (Figure 4) into a high impedance load. Chip
capacitors, chip resistors and chip inductors are used
throughout. Q1 can be practically any high frequency
NPN with an FT 3 to 5 times greater than the oscillation
frequency—MPS918 and MPSH10 are representative
choices. The crystal is seventh overtone, series resonant
mode, in an HC-49 holder. U1, the PECL (positive ECL
logic) to TTL translator, is a Motorola ECLinPS “Lite”
(single gate) surface mount device. U1 will provide
Circuit description: L2/R1 resonate with the crystal stray
capacitance to prevent spurious oscillations. The tank
circuit containing L3 is resonant near 125 MHz to allow
the crystal to operate at its seventh overtone series resonant frequency. R6 reduces the tank circuit Q and prevents self-oscillation and frequency misalignment with
the crystal frequency. The MC10ELT21 PECL to TTL
translator output is ac-coupled to the midpoint voltage
of 2.5 V set up by R3 and R9. The translator requires
>200 mV p-p signal input to produce TTL output levels.
The oscillator output configuration requires a high load
impedance to maintain the 2.5 V dc offset and 4 V signal
swing to drive the CMOS input of the AD9850. If actual
TTL levels are desired, C10, R3 and R9 should be removed and a wire jumper soldered in place of C10.
Figure 2. PCB Component Placement
Figure 3. PCB Interconnections
E2176–7.5–9/96
standard TTL output levels or, in this case, CMOS compatible levels that have been externally level-shifted to
1/2 the supply voltage of the AD9850. Proper clocking of
the AD9850 occurs when the signal is at least 3 V p-p and
centered at VDD/2.
20 LOG (Output Frequency/Reference Frequency). For
example, the Butler oscillator’s phase noise contribution
to the AD9850 output signal is reduced from a typical
–110 dBc to –138 dBc when clocking at 125 MHz and outputting 5 MHz. As the DDS output frequency becomes a
greater percentage of the reference oscillator frequency,
the oscillator’s contribution to the DDS output phase
noise will increase.
VDD
2
T
Ø V A2
Ax2
1.00 V
M 5.00 ns
Ax2
2.46 V
Figure 4. Digital Scope Printout of Oscillator Output
–2–
PRINTED IN U.S.A.
∆: 3.84 V
@: 4.20 V