AN-1141
APPLICATION NOTE
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
Powering a Dual Supply Precision ADC with Switching Regulators
by Rui Du
INTRODUCTION
Compared with an LDO device, a switching regulator always
dissipates much less heat and provides higher efficiency. Therefore, a switching regulator is suitable for powering different
kinds of portable devices or the nodes in a wireless sensor
network to lengthen battery time. Unfortunately, a switching
regulator intrinsically generates ripple and noise at both the
output rail and the ground. At the same time, a switching
regulator brings electromagnetic radiation. These interferences
are almost inevitable due to the continuously on-off operation
of the power switch. With the parasitic parameters involved, the
noise will be present at unexpected frequency points besides the
integer multiple of the switching frequency.
10481-001
NOISE
RIPPLE
Figure 1. Typical Ripple and Noise at the Output of a Switching Regulator
Although damaged from the noise issues, if the interference of
the switching regulator can be effectively controlled while the
circuit is powered by a switching regulator, which has a strong
anti-interference capacity, then the degrading of the system
performance will be slight.
For a typical application, when a data converter is powered by a
switching mode power supply (SMPS), keep the total noise over
the band of interest lower than the noise floor to prevent it from
being seen by the converter. Although the in-band noise from
the switching regulator is normally greater than the noise floor,
because of the power rejection ratio of the ADC, the noise will
be sharply attenuated before entering the signal path; as a result,
the switching noise will not degrade the performance of the
ADC.
There are two options to power the ADC with switching
regulators:
A. Select a low noise switching regulator and then use
carefully designed filtering and shielding methods
to remove as much of the noise as possible.
B. Estimate the noise suppressing capability of the data
converter, and then select the product, which has good
noise-immunity performance.
In practice, both options can be used at the same time so
that the power solution of using a switching regulator can
be acceptable in most cases. The switching regulator solution
includes the benefits of high efficiency and low temperature.
In CN-0137, a dual-output synchronous buck switching
regulator, ADP2114, is used to power the 16-bit, 125 MSPS
analog-to-digital converter, AD9268. The outputs of ADP2114
are filters using an extra stage of an LC filter (ferrite bead).
Compared with the linear supplies solution, the testing result
shows that using a dc-to-dc supply has nearly no influences on
the performance of the ADC (see Table 1).
Table 1. Experiment Results Reported in CN-0137
Analog Input
Frequency (MHz)
10.3
70.0
100.3
140.3
170.3
200.3
Linear Supplies
SNR
SFDR
(dBFS)
(dBc)
79.2
92.2
78.5
91.0
77.8
85.8
76.9
85.0
76.2
84.3
75.0
76.9
DC-to-DC Supply
SNR
SFDR
(dBFS)
(dBc)
79.2
92.3
78.4
90.8
77.7
85.6
76.9
84.8
75.9
84.6
75.0
77.0
The noise performance of the ADP2114 is guaranteed by
multiple technologies implemented in the design. The typical
voltage ripple is less than 1 mV. Using additional filtering, its
noise performance can even align with linear supplies.
Rev. 0 | Page 1 of 8
AN-1141
Application Note
TABLE OF CONTENTS
Introduction ...................................................................................... 1
Filtering Considerations ...................................................................7
Experiment Results........................................................................... 3
Conclusion..........................................................................................8
Experiment 1 ................................................................................. 5
References ...........................................................................................8
Experiment 2 ................................................................................. 6
REVISION HISTORY
2/12—Revision 0: Initial Version
Rev. 0 | Page 2 of 8
Application Note
AN-1141
EXPERIMENT RESULTS
100
In this application note, a switching regulator is used to power
the ADC without any additional filtering or shielding measures,
only the necessary external components kept for normal operation of the dc-to-dc power supply. According to the second
option mentioned previously, two power-insensitive ADCs,
the AD7610 and AD7612 are used for testing. This application
note aims at finding out how much harm is brought by the
SMPS to the ADC and whether it is acceptable.
90
80
CMRR (dB)
70
40
20
0
1
10
100
FREQUENCY (kHz)
1k
10k
10481-004
10
Figure 4. Analog Input CMRR vs. Frequency of AD7610 or AD7612
More importantly, the AD7610 and AD7612 provide excellent
power rejection ratio. They are very insensitive to power supply
variations on AVDD over a wide frequency range (see Figure 2).
80
EXTERNAL REF
75
70
PSRR (dB)
50
30
The AD7610 and AD7612 are 16-bit charge redistribution
successive approximation register (SAR) analog-to-digital
converters. They feature true bipolar analog input range.
The analog input signal should never exceed the supply rails
by more than 0.3 V. For ±10 V input, a typical power supply
is ±12 V. See the AD7610 and AD7612 data sheets available
from www.analog.com.
For powering the AD7610 and AD7612, a 5 V to ±12 V power
module using the ADP1613 (the boost dc-to-dc converts 5 V
to 12 V) and ADP2301 (the inverting dc-to-dc converts +5 V
to −12 V) was designed. For more information about the
inverting converter application of ADP2301, refer to the
AN-1083 Application Note.
The power solution is made to help those customers, who only
have 5 V on-board to generate ±12 V with high-current ability
and high-efficiency (see Figure 5).
INTERNAL REF
65
60
60
L
55
50
D
45
VIN
40
EN
ADP1613
CIN
35
100
FREQUENCY (kHz)
1k
10k
Rf2
SS
Figure 2. AVDD PSRR vs. Frequency of AD7610 or AD7612
Figure 3 shows an equivalent circuit for the input structure of
the AD7610 and AD7612. The analog input is first handled
by the high voltage branches (powered by VCC and VEE) and
scaled down to 0 V to 5 V.
VIN
D2
D4
RIN
BST
L
CIN
SW
IN+ OR IN–
D
Rf1
GND
EN
VEE
AGND
10481-003
CPIN
CBOOT
ADP2301
CP
D3
COUT
RCOMP
CCOMP
CIN
AVDD
D1
COMP
GND
0V TO 5V
RANGE ONLY
VCC
GND
CSS
FB
GND
Rf2
VOUT–
Figure 3. Simplified Analog Input Structure of AD7610 or AD7612
This analog input structure allows the sampling of the differential signal between IN+ and IN−. By using this differential
input, small signals common to both inputs are rejected as
shown in Figure 4, which represents the typical CMRR over
frequency.
COUT
Figure 5. Schematic of the 5 V to ±12 V Power Module Using ADP1613 or
ADP2301
Rev. 0 | Page 3 of 8
10481-005
10
10481-002
1
Rf1
FB
FREQ
30
VOUT+
SW
VIN
AN-1141
Application Note
For a SMPS, the output-voltage ripple can be suppressed by
using a big inductor and output capacitor in the topology. To
deal with the switching noise, an extra filter at the output can
be used. By doing this, the PCB area will be sacrificed.
T
The basic configuration of the 5 V to ±12 V power modules is
shown in Table 2.
Configuration
Switching Frequency
Output Inductor
Input Capacitor
Output Capacitor
Maximum Load
+12 V
1.3 MHz
10 µH
10 µF
10 µF
400 mA
Output
−12 V
1.4 MHz
8.2 µH
10 µF
44 µF
200 mA
CH1 20.0mV
BW
0.00V
Figure 8. AC-Coupled Output Voltage of the −12 V Rail
T
Note the following about the ripple and noise performance
under the typical loading (50% of full load):
•
M 1.00µs
A CH1
T
172.000ns
10481-008
Table 2. Basic Configuration for the ±12 V Power Modules
For the +12 V rail of the power module:
the ripple ≈ 20 mV p-p
the noise ≈ 140 mV p-p (oscilloscope in 1 MΩ mode)
For the −12 V rail of the power module:
•
the ripple ≈ 10 mV p-p
•
the noise ≈ 50 mV p-p (oscilloscope in 1 MΩ mode)
•
•
CH1 20.0mV
BW
M 100µs
A CH1
T
200.000ns
0.00V
10481-009
T
Figure 9. Filtered Output Voltage of the −12 V Rail (AC-Coupled)
CH1 50.0mV
BW
M 400ns
T
0.00000s
A CH1
0.00V
10481-006
When 2-stage filters are added to the output (the first stage
is the LC filter, and the second stage is the bead + decoupling
capacitor), most of the ripple and noise can be removed. However, in all the experiments mentioned in this application note,
the original output, no extra filters, was used.
Figure 6. AC-Coupled Output Voltage of the +12 V Rail
T
CH1 20.0mV
BW
M 40.0µs
A CH1
T
160.000ns
0.00V
10481-007
•
Figure 7. Filtered Output Voltage of the +12 V Rail (AC-Coupled)
Rev. 0 | Page 4 of 8
Application Note
AN-1141
NUMBER OF COUNTS
The first experiment was performed based on AD7612-EVAL
and ADuC7026-EVAL. The ADuC7026-EVAL was used to read
the conversion results.
The input range of AD7612 is configured as ±5 V.
The analog inputs of AD7612 (IN+ and IN−) are both
directly grounded, the input buffers on the evaluation
board are bypassed (see Figure 10).
10481-010
AD7612
Figure 10. Simplified Schematic for Experiment 1. The 3 dB Bandwidth of the
Input Anti-Aliasing Filter is about 4 MHz.
0
Two power supply configurations were used in the experiment:
Configuration A: VCC and VEE of the AD7612 are
powered by the ±12 V power module based on ADP1613
and ADP2301. The +5 V AVDD and DVDD are powered
by high quality linear dc power.
Configuration B: For comparison, VCC, VEE, AVDD, and
DVDD are all provided by the high quality linear dc power.
•
•
During the test, 16,384 conversions were performed.
1
2
LSB
LSB
0x0000
0x0001
0x0002
0x0003
0x0004
µ
δ
3
NUMBER
OF COUNTS
0
717
13769
1898
0
2.0721
0.393
4
Figure 12. Testing Results—Histogram for Power Supply Configuration B
Following are the calculations for mean and variance:
For Configuration A,
mu (μ) = 2.0729 LSB
sigma (δ) = 0.3857 LSB
The peak-to-peak noise ≈ 2.5456 LSB
14500
14000
13500
13000
12500
12000
11500
11000
10500
10000
9500
9000
8500
8000
7500
7000
6500
6000
5500
5000
4500
4000
3500
3000
2500
2000
1500
1000
500
0
peak-to-peak resolution ≈
 216 
 ≈ log 2 10 × 4.411 ≈ 14.65 bits
log 2 
 2.5456 
For an interval estimation,
The 95% confidence interval of μ is [2.0670, 2.0788]
The 95% confidence interval of δ is [0.3816, 0.3900]
For Configuration B,
mu (μ) = 2.0721 LSB
sigma (δ) = 0.3930 LSB
The peak-to-peak noise ≈ 2.5938 LSB
0
1
2
LSB
LSB
0x0000
0x0001
0x0002
0x0003
0x0004
µ
δ
3
NUMBER
OF COUNTS
0
664
13862
1857
1
2.0729
0.3857
peak-to-peak resolution ≈
4
 216 
 ≈ log 2 10 × 4.403 ≈ 14.63 bits
log 2 
 2.5938 
10481-011
NUMBER OF COUNTS
The testing results for Configuration A and Configuration B are
shown in Figure 11 and Figure 12.
14500
14000
13500
13000
12500
12000
11500
11000
10500
10000
9500
9000
8500
8000
7500
7000
6500
6000
5500
5000
4500
4000
3500
3000
2500
2000
1500
1000
500
0
10481-012
EXPERIMENT 1
Figure 11. Testing Results—Histogram for Power Supply Configuration A
For an interval estimation,
The 95% confidence interval of μ is [2.0661, 2.0781]
The 95% confidence interval of δ is [0.3888, 0.3973]
The change of peak-to-peak resolution is within 0.03 bit, using
SNR = 6.02 N + 1.76. The change of the SNR is within 0.2 dB.
Rev. 0 | Page 5 of 8
AN-1141
Application Note
EXPERIMENT 2
–0.0003
The second experiment was performed based on the
AD7610-EVAL. The FIFO board (EVAL-Control BRDXZ)
and the evaluation software were used to analyze the
conversion results.
am
–0.0004
–0.0005
The input range of AD7610 is configured as ±5 V.
–0.0006
–0.0007
–0.0008
0
AD8021
AD7610
0.02
0.04
0.06
0.08
0.10
0.12
Figure 15. Time Domain Waveform for Power Supply, Configuration B
10481-013
4500
AD8021
0.14
10481-015
The input buffers are enabled (AD8021). The inputs of AD8021s
are both grounded. The AD8021 is dual-supply operation, using
the same ±12 V rails as AD7610 (see Figure 13).
m
4000
Figure 13. Simplified Schematic for Experiment 2. The 3 dB Bandwidth of the
Input Anti-Aliasing Filter is about 4 MHz.
3500
3000
Two power supply configurations were used in the experiment:
2000
1500
1000
500
0
7FF9
The testing results for Configuration A and Configuration B are
shown in Figure 14 to Figure 19.
–0.0003
2500
7FFA
7FFB
7FFC
7FFD
7FFE
7FFF
8000
10481-016

Configuration A: Using high quality linear dc power to
provide +12 V VCC, −12 V VEE, +5 V AVDD, and +5 V
DVDD (and power the input buffer).
Configuration B: Using high quality linear dc power to
provide +5 V AVDD, +5 V DVDD; using ±12 V SMPS
to provide +12 V VCC, −12 V VEE (and to power the
input buffer).
Figure 16. Histogram for Power Supply, Configuration A
5500
m
5000
am
4500
–0.0004
4000
3500
3000
–0.0005
2500
2000
–0.0006
1500
1000
–0.0007
–0.0008
0
0.005
0.010
0.015
0.020
0.025
0.030
0.035
10481-014
500
Figure 14. Time Domain Waveform for Power Supply, Configuration A
Rev. 0 | Page 6 of 8
0
7FF9
7FFA
7FFB
7FFC
7FFD
7FFE
7FFF
Figure 17. Histogram for Power Supply, Configuration B
8000
10481-017

Application Note
–70
AN-1141
FILTERING CONSIDERATIONS
d
–80
As a second-order filter, the LC filter provides a sharp roll-off
above its resonant frequency and is widely used at the output of
the dc-to-dc power supply. However, normally the performance
of the switching regulator is only specified for the resistive load.
If a LC filter is inserted between the dc-to-dc power supply and
the resistive load, the dc-to-dc power supply sees a new complex
load present at the output:
–90
–100
–110
–120
–130
–140
–150
–160
–170
ZL 
–180
–190
–210
0
20
40
60
80
100
120
140
10481-018
–200
R  sL  s 2 LCR
1  sCR
where s is the complex variable in Laplace transform.
ZIN
ZL
Figure 18. Spectrum for Power Supply, Configuration A
DC-DC
d
10481-020
–70
–80
–90
Figure 20. DC-to-DC with Input/Output LC Filters
–100
From this point of view, as a closed-loop system, the load condition affects the dc-to-dc’s loop transfer function. The bandwidth
and the phase margin of the closed-loop system are altered, which
may even cause stability issues. The influence of the additional
filter on the dc-to-dc is complicated. As an approximation,
within an appropriate range, the transient behavior of the dcto-dc power supply with an extra LC filter is similar to the
step response of a series RLC tank.
–110
–120
–130
–140
–150
–160
–180
0
20
40
60
80
100
120
140
10481-019
–170
Figure 19. Spectrum for Power Supply, Configuration B
For Configuration A,
SNR = 93.40 dB
SINAD = 93.39 dB
Following are some semi-experiential guidelines for choosing
the LC filter, which may help to improve the stability of the
design.

For Configuration B,
SNR = 93.20 dB
SINAD = 93.18 dB

The impact on the noise performance of the AD7610 and
AD7612 caused by the SMPS is very limited. The SNR has
only about 0.1 dB to 0.2 dB variation and there is almost no
change in ENOB. If an extra filter is added for the SMPS, the
results should be even better.
In the AD7610 and AD7612 data sheets, the frequency response
of PSRR for AVDD is specified. From the experiment results,
it seems that VCC and VEE also have impressive PSRR specifications.
Rev. 0 | Page 7 of 8
Normally it’s safe to set the resonant frequency of the LC
filter to be higher than the original loop bandwidth of the
dc-to-dc.
If the resonant frequency had to be made lower, try to use
smaller inductance and bigger capacitance (lower Q).
AN-1141
Application Note
Figure 21 and Figure 22 shows the simulation results for the
frequency response and the transient response of different
LC filters. A group of inductance and capacitance is used,
while the resonant frequency of the LC tank remains unchanged.
Figure 21 and Figure 22 show the waveform of the output
voltage during load-transient courses: the excessive waveform
is measured before the additional LC filter; the lagging
waveform is measured after the additional LC filter. With
the increasing of inductance, ringing is present during
the load-transient.
A measured result for ADP1613 (12 V output) is shown in
Figure 23. With an extra LC filter added to the output (L =
4.7 µH, C = 10 µF), the noise is greatly reduced, while the
transient response doesn’t change a lot, and the system is stable.
ORIGINAL OUTPUT
1T
2T
FILTERED OUTPUT
50
0
–50
LOAD STEP
3
10481-023
IZI (dBΩ)
–100
–150
–200
Figure 23. Transient Response of ADP1613 (12 V Output) with the Output LC
Filter Inserted
–250
CONCLUSION
–350
–400
1
2
3
4
FREQUENCY (kHz)
5
6
7
8 9 10
10481-021
L = 30µH, C = 33µF
L = 20µH, C = 50µF
L = 10µH, C = 100µF
–300
3.6
3.5
3.4
3.3
3.2
3.1
3.0
3.50
3.45
3.40
3.35
3.30
3.25
3.20
3.15
3.10
3.05
3.45
3.40
3.35
3.30
3.25
3.20
3.15
3.10
L = 30µH
C = 33µF
ORIGINAL OUTPUT
FILTERED OUTPUT
L = 20µH
C = 50µF
ORIGINAL OUTPUT
FILTERED OUTPUT
REFERENCES
AD7610 Data Sheet. Analog Devices, Inc. 2006.
2.6
2.8
AD7612 Data Sheet. Analog Devices, Inc. 2006.
ORIGINAL OUTPUT
FILTERED OUTPUT
L = 10µH
C = 100µF
3.0
3.2
3.4
3.6
TIME (ms)
3.8
CN-0137. Powering the AD9268 Dual Channel, 16-bit, 125 MSPS
4.0
4.2
4.4
Analog-to-Digital Converter with the ADP2114 Synchronous
Step-Down DC-to-DC Regulator for Increased Efficiency. Analog
Devices, Inc. 2009.
10481-022
VOLTAGE (V)
Figure 21. Frequency Response of Different LC Filters (with a Fixed Resistive
Load)
The AD7610 and AD7612 have excellent power rejection
performance. Their differential inputs ensure the commonmode rejection capability within a certain frequency range.
When the power supply is designed for these kinds of ADCs, a
switching regulator can be considered. With the help of external
filtering and shielding units, the noise characters of the SMPS
will be improved further. For energy-constrained applications,
if the system to be powered has good noise rejection ability,
coupled with the filtering and the shielding measures, use of
SMPS will improve the energy efficiency but not degrade the
performance of the system.
Figure 22. Transient Response of the DC-DC with Different Output LC Filters
Inserted
Kessler, Matthew C. AN-1083 Application Note. Designing an
Inverting Buck Boost Using the ADP2300 and ADP2301
Switching Regulators. Analog Devices, Inc.
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
AN10481-0-2/12(0)
Rev. 0 | Page 8 of 8