Applications Engineering Notebook
MT-200
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
Minimizing Jitter in ADC Clock
Interfaces
by the Applications Engineering Group
Analog Devices, Inc.
POWER SUPPLY
INPUT
VREF
ANALOG
INPUT
IN THIS NOTEBOOK
Since jitter around the threshold region of a clock interface
can corrupt the dynamic performance of an analog-todigital converter (ADC), this notebook provides an overview
of clocking considerations and jitter-reduction techniques.
CLOCK
INPUT
DATA
OUTPUT
ADC
FPGA
INTERFACE
CONTROL
The Applications Engineering Notebook Educational Series
TABLE OF CONTENTS
Clock Input Noise..............................................................................2
Frequency Domain View ............................................................. 3
Time Domain View.......................................................................2
Phase Domain View ..................................................................... 4
Effect of Slew Rate.....................................................................3
Solutions for Clocking Converters ............................................. 5
REVISION HISTORY
1/12—Revision 0: Initial Version
Rev. 0 | Page 1 of 8
MT-200
Applications Engineering Notebook
CLOCK INPUT NOISE
TIME DOMAIN VIEW
dV
Noise in the circuit between the clock and ADC is the root
cause of clock jitter. Random jitter is caused by random noise,
which is distinguished by its unbounded character and follows
statistical distributions. Major random noise sources include
•
•
•
Thermal (Johnson or Nyquist) noise is caused by Brownian
motion of the charge carriers.
Shot noise is related to the dc current flow across a
potential barrier that is not continuous and smooth, but
instead is the result of pulses of current caused by the
individual flow of carriers.
Flicker noise occurs when a dc current is flowing. It is
caused by traps in semiconductors that hold carriers that
would normally constitute a dc current flow for a short
period before releasing them.
Burst, or popcorn, noise is caused by contamination and
crystal lattice dislocation at the surface of the silicon that
captures and releases carriers in a random manner.
Deterministic jitter is caused by interference that shifts the
threshold in certain ways that are usually bounded by nature.
There are three ways to view the noise in a clock signal:
•
•
•
Time domain
Frequency domain
Phase domain
ENCODE
Q1
RECTANGULAR
BI-MODEL
NORMAL
IDEAL
Figure 1. Time Domain View of Jitter
Clock jitter is the sample-to-sample variation of the encode
clock which includes both external and internal jitter. Full-scale
SNR is jitter limited by
SNR jitter = 20 log(
S rms
1
) = 20 log(
)
N rms
2πf ana log t jitter
For example, at 1 Ghz with 100 FS rms jitter, the SNR is 64 dB.
Viewed in the time domain, variation of the encode edge in
the x-axis direction causes a y-axis error with a magnitude
dependent on the rise time of the edge. Aperture jitter produces
errors in the ADC output as shown in Figure 2. The jitter can
occur internally in the ADC or externally in the sampling clock
or interface circuitry.
ΔV =
ANALOG
INPUT
dV
× Δt
dt
ΔVRMS = APERTURE JITTER ERROR
dV
= SLOPE
dt
NOMINAL
HELD
OUTPUT
ΔtRMS = APERTURE JITTER
HOLD
TRACK
Figure 2. Effects of Aperture Jitter and Sampling Clock Jitter
Rev. 0 | Page 2 of 8
10338-002
•
ERROR VOLTAGE
10338-001
Jitter around the threshold region of the clock interface can
corrupt the timing of an analog-to-digital converter (ADC). For
example, jitter can cause the ADC to capture a sample at the
wrong time, resulting in false sampling of the analog input and
reducing the signal to noise (SNR) ratio of the device. A
reduction in jitter can be achieved in a number of different
ways, including improving the clock source, filtering, frequency
division, and clock circuit hardware. This document provides
suggestions on how to improve the clock system to achieve the
best possible performance from an ADC.
Applications Engineering Notebook
MT-200
90
SNR OF ADC AT 200MHz, AIN VARIES
WITH CLOCK JITTER
ADC
84dB
200
150
DIGITAL
OUTPUT
100
ANALOG
INPUT
80
78dB
50
SAMPLING
CLOCK
75
72dB
50fS
66dB
100fS
0
65
60dB
400fS
55
FREQUENCY DOMAIN VIEW
800fS
EACH LINE SHOWS
CONSTANT RMS
CLOCK JITTER IN fs
45
100
1000
FULL-SCALE ANALOG INPUT (MHz)
Figure 3. As Analog Signal Increases, Clock Jitter Increases SNR
Close-in noise occurs in the region between the center
frequency of the sample clock to a single sideband (SSB) offset
equal to half the signal bandwidth. Wideband noise extends
from the SSB offset to ½ the bandwidth of the clock receiver.
The jitter-based SNR and the effective number of bits (ENOB)
are related by the equation: SNR = 6.02 N + 1.76 dB where N =
ENOB. For full-scale 100 MHz input, 14-bit ENOB requires that
the rms jitter be no greater than 0.125 ps or 125 fs. The equation
assumes an ADC of infinite resolution where the only error is
noise produced by the clock jitter.
130
0.125ps
0.25ps
0.5ps
1ps
SNR
2ps
110
100
RMS JITTER < 1ps
IS VERY HIGH
PERFORMANCE
TO DC
1
= 20 log10
2 ftjitter
90
12 BITS
ENOB
80
Figure 6. Frequency Domain View
70
10 BITS
60
50
IF SAMPLING ADCs
ANALOG FREQUENCY 70MHz TO 300MHz,
SNR 60dB TO 80dB
30
1
10
TO ENCODE
BANDWIDTH
WIDEBAND
NOISE
14 BITS
40
CLOSE IN NOISE
16 BITS
100
FULL-SCALE ANALOG INPUTFREQUENCY (MHz)
1000
10338-004
SIGNAL TO NOISE RATE (dB)
120
6
10338-006
1
SNRjit = 20log
2πftjitter
4
Figure 5. Increasing Slew Rate Reduces Jitter
AIN = 200MHz
50
2
CLOCK WITH
PHASE NOISE
60
0
INPUT SLEW RATE (V/ns)
200fS
10338-005
70
10338-003
SIGNAL TO NOISE RATIO (dB)
85
the slew rate. Figure 5 shows how increasing the slew rate
reduces jitter because only noises in the threshold range
contribute to jitter.
RMS JITTER (fs)
Figure 3 shows the effects of jitter on SNR. Five traces are
shown in Figure 3, each representing a different value of jitter.
The x-axis is full-scale analog input frequency, and the y-axis is
the SNR due to the jitter as opposed to the total ADC SNR.
Jitter on a clock is defined from the fSTART and fSTOP offset
frequency. For example, a clock may have 200 fsec of jitter
integrated from 1 kHz to fs/2 and 170 fsec of jitter integrated
from 10 kHz to fs/2. The integration range is dependent upon
the end application.
Multiplication in time is convolution in the frequency domain.
Therefore, any skirt on the clock is applied to the digitized
signal. This increases the EVM of the signal and degrades
overall performance. The amount convolved onto the sample
signal depends on the relationship of the analog frequency to
the sample frequency.
Figure 4. Theoretical SNR and ENOB Due Jitter as a Function of Full-Scale
Sinewave Analog Input Frequency
Effect of Slew Rate
Increasing the slew rate of the clock edge reduces the effects of
noise and jitter by leaving the circuit less exposed. On the other
hand, a faster slew rate increases the difficulty of circuit design,
may cause electromagnetic interference (EMI) issues and may
cause interference in other circuits. Note that an oscilloscope
with very low input capacitance is needed to accurately measure
Rev. 0 | Page 3 of 8
SampledOutput = ClockSignal + 20 log(
f signal
f clock
)
MT-200
Applications Engineering Notebook
The spur is at −74.1 dBc as determined by the following
equation:
–120
–120
− 66 + 20 log(
–130
30.62
) = −74.1 dBc
78
–135
–10
–140
–20
–145
–30
–150
–40
dBc
PHASE NOISE (dBc/Hz)
–125
–155
–50
–60
–160
10
100
1k
10k
100k
1M
10M
100M
–70
FREQUENCY (Hz)
–80
–90
30.25
30.50
30.75
31.00
31.25
FREQUENCY (MHz)
10338-009
–100
Figure 9. 30.62 MHz Signal when Sampled with a Noisy Clock
DESIRED SIGNAL
Clock designers typically provide a phase noise, but not a jitter
specification. The phase noise specification can be converted to
jitter by first determining the noise on the clock and then
comparing noise to the main clock component using small
angle math.
The phase noise power is integrated by calculating the gray area
in Figure 10.
10338-007
PHASE
NOISE
SKIRTS
PHASE
NOISE
SKIRTS
Figure 7. The Noise Convolved onto the Sampled Signal Depends on the
Relationship of the Analog Frequency to the Sample Frequency
Vphase_noise
rise
Ф ≈ run =
Vmain_clock
PHASE DOMAIN VIEW
MODULATION
ANGLE Ф
Phase noise is cause by variations in the time period between
each clock cycle. The end result is that the clock signal varies
around a fundamental frequency. This spread of frequencies
will degrade the ADC’s SNR.
MAIN
COMPONENT
OF CLOCK
PHASE NOISE
COMPONENT
OF CLOCK
PHASE,
FREQUENCY AND
AMPLITUDE NOISE
ON CLOCK
Figure 8. Phase Domain View of Jitter
In the example shown below, a spur is added to a 78 MHz
clock at level of −66 dBc and is used to control an ADC
sampling a 30.62 MHz analog signal.
INTEGRATE TO
ENCODE BANDWIDTH
–160
10k
100k
1M
10M
100M
1G
(Hz)
10338-010
SAMPLE INSTANT: PHASE = 0
i.e. POSITIVE GOING
0 CROSSING
10338-008
ANGULAR RATE OF
ENCODE CLOCK
PHASE NOISE (dBc/Hz)
ANGULAR RATE
OF ENCODE CLOCK
Figure 10. Integrating the Noise from Close-In to the Clock Out to the
Bandwidth of the Encode
The height is −160 dBc and the width is 10 KHz to 245.76 MHz.
Therefore, 10×log(245.7e6 − 10e3) = 83.9 dB and −160 + 83.9 dB
= 76.1 dBc of integrated noise.
Rev. 0 | Page 4 of 8
Applications Engineering Notebook
MT-200
PNoise = −160 dBc / Hz + 10 log(245.76 × 10 6 − 10.0 × 10 3 = −76.1 dBc
Jitterphase ≅ 2 × 10 PNoise / 10= = 2 × 10 −76.1/10 = 2.217 × 10 −4 radians for small angles
Jitter =
JitterPhase
2.217 × 10 −4
=
= .1435 pS
2πf Osc
2π × 245.76 × 10 6
At different offsets from the carrier, the slope of the noise can
be different. For example, the A1 region is typically 1/f noise
while the A4 region is considered broadband noise.
2 + 10 × log(30 M)=-87.3 dBc
RSS
10^(−87.9/10)+10^(−85.2/10)+10^(−87.3/10) = −81.7 dBc
PNoise = −81.7 dBc
Jitterphase ≅ 2 × 10 PNoise / 10= = 2 × 10 −81.7 / 10 =
INTEGRATE TO
ENCODE BANDWIDTH
10k
A2
A3
100k
1M
for small angles
A4
10M
100M
1G
(Hz)
Jitter =
10338-011
A1
1.163 × 10 −4 radians
Figure 11. Case Where Noise Varies Across Frequency Range
JitterPhase
1.163 × 10 −4
=
= .151 fS
2πf Osc
2π × 12288 × 10 6
The calculated value is close to the measured value of 158 fS.
A = Area = integrated phase noise power (dBc).
SOLUTIONS FOR CLOCKING CONVERTERS
The jitter can be determined by integrating the noise from
close-in to the clock out to the bandwidth of the encode. The
frequency range must be broken down into smaller bands and
added together to get the total.
A phase locked loop (PLL) can be used to lock the reference
clock output to the desired frequency. Figure 12 shows a
reference clock with high noise at a bandwidth of about
100 kHz. The green and two blue traces are noise sources in
an AD9516 clock generator. The red trace is the noise of the
external reference feeding the AD9516. The brown trace is
the total noise of the AD9516. The graph shows that the dirty
reference clock is the reason for the noise problem.
A = 10 log10 (A1 + A2 + A3 + A4)
Rms phase jitter (radians) ≈
–40
A
2 × 10 10
fOsc = oscillator frequency
10 k to 100 k
(−133.5 + −141.6) = −137.5
2 + 10 × log(90 k)=−87.9 dBc
REFERENCE CLK NOISE
FINAL AD9516 OUTPUT NOISE (PECL OUTPUT)
VCO NOISE
AD9516 PLL NOISE
LOOP FILTER NOISE
REF-IN OPEN LOOP
–60
2πf Osc
PHASE NOISE (dBc/Hz)
Rms jitter (seconds) ≈
A
10
2 × 10
–80
–100
–120
–130
100 k to 1 M
–180
10
(−141.5 + −147.8) = −144.7
(−161.7 + −162.5) = −162.1
1k
10k
100k
1M
10M
FREQUENCY (Hz)
2 + 10 × log(900 k)=−85.2 dBc
10 M to 40 M
100
100M
10338-012
–160
Figure 12. Jitter Caused by Dirty Reference Clock
In this example, a PLL is used to filter the output of the
reference clock. The PLL bandwidth is set to 30 Hz and a
good quality VCXO is used. The PLL removes the unwanted
jitter from the recovered system clock as shown in Figure 13.
Rev. 0 | Page 5 of 8
MT-200
Applications Engineering Notebook
–45
INPUT, 20 log (|INOUTi|)
VCXO, 20 log (|VCOi|)
TOTAL OUT, 20 log (|Ti|)
–55
PHASE NOISE (dBc/Hz)
–65
–75
–85
–95
–105
–115
–125
–135
–155
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
10338-013
–145
Figure 13. PLL Removes Unwanted Jitter
In this example, an ADF4002 is used as the PLL to clean the recovered input reference clock. The AD9516 clock generator is then used to
produce multiple clocks.
Tx LO EXT
ZIF OR CIF UP
TO 184MHz
DAC
Tx DLK
π
ATTN
90
AD9122
EXTERNAL PA
RF OUTPUT
0dBm TO +10dBm
PIN
DIODE
ADL5541
DAC
ADL5375
ADL5320
DAC
AD5601/AD5611/
AD5621
AD8375
π
ATTN
ADC
AD9434
AD9516
AAF
TYPICAL
IF-184MHz
ADF4002 +
VCXO
PLL
ADF4150 +
VCO
ADCLK925
ADF4002 +
VCXO
ADCLK905
ADF4350
PLL
PLL
CLOCK
CLEANUP
(61.44MHz)
Rx LO EXT
CLOCK
GENERATION,
FANOUT,
DISTRIBUTION
LO CLEANUP
(13.0MHz)
DIRECT SPI FROM FPGA
CLOCK
REF IN
(n × 30.72MHz)
NOISY INPUT
REFERENCE
CLOCK
PLL
TO SPI
DEVICES
SPI BRIDGE
MASTER
CLOCK
OUT
USB
MICROCONTROLLER
LOCAL SPI
(OPTIONAL)
TO DEVICES WITH
CONTROL PINS
MCP23S17
16-BIT PORT EXPANDER
AUX USB INTERFACE
CLEAN UP
INPUT NOISE
10338-014
POWER
IMAGE REJECT
ADL5367/
ADL5365
CLOCK GENERATION,
FANOUT,
DISTRIBUTION
NETWORK
CLKOUT
ATTENUATED
RF OUTPUT
Figure 14.
The AD9523, AD9524, and AD9523-1 clock generators integrate the functions of jitter clean and clock generation/distribution into a
single device. The AD9524 device has seven outputs while the AD9523 and AD9523-1 have 15 outputs.
Rev. 0 | Page 6 of 8
Applications Engineering Notebook
MT-200
Tx LO EXT
ZIF OR CIF UP
TO 184MHz
DAC
Tx DLK
π
ATTN
90
AD9122
EXTERNAL PA
RF OUTPUT
0dBm TO +10dBm
PIN
DIODE
ADL5320
ADL5541
DAC
ADL5375
DAC
AD5601/AD5611/
AD5621
AD8375
π
ATTN
ADC
AD9434
AAF
TYPICAL
IF-184MHz
ATTENUATED
RF OUTPUT
IMAGE REJECT
ADL5367/
ADL5365
NETWORK
CLKOUT
PLL
ADF4150 +
VCO
CLOCK SYNTHESIS
AND DISTRIBUTION
ADF4002 +
VCXO
ADCLK905
ADF4350
PLL
PLL
CLOCK
CLEANUP
(61.44MHz)
PLL
Rx LO EXT
LO CLEANUP
(13.0MHz)
POWER
TO SPI
DEVICES
DIRECT SPI FROM FPGA
SPI BRIDGE
AD9523
NOISY INPUT
REFERENCE CLOCK
MASTER
CLOCK
OUT
USB
MICROCONTROLLER
LOCAL SPI
(OPTIONAL)
MCP23S17
16-BIT PORT EXPANDER
AUX USB INTERFACE
10338-015
CLOCK
REF IN
(n × 30.72MHz)
TO DEVICES WITH
CONTROL PINS
INTEGRATED CLOCK CLEAN UP,
GENERATION, FANOUT
Figure 15.
The driver design of the Analog Devices AD9523, AD9524, and AD9523-1 offer multimode output which means that it’s possible to use a
common 100 Ω differential resistor and change a register value to change from LVPECL, LVDS, and HSTL signal formats. Each signal
format has advantages and disadvantages as shown in the charts below. All signal formats have different voltage swings. Select the format
with best swing for the application but remember that a lower swing uses less power.
Rev. 0 | Page 7 of 8
MT-200
Applications Engineering Notebook
10338-017
3.3V
GND
Figure 16.
Table 1. LVPECL Signal Format Pros and Cons
Pros
quasidifferential
high slew rates
can accept near/far termination
fanout capability
relatively quiet such that it doesn’t corrupt other signals
easily
Cons
high power
requires a bipolar device that is not available on CMOS processes
3.5mA
10338-016
3.5mA
Figure 17.
Table 2. LVDS Signal Format Pros and Cons
Pros
true differential
some variants can accept near/far termination
Cons
low signaling (±0.4 V) often does not yield highest slew
care needs to be taken to insure aggressor signals equally couple to differential
LVDS lines
quiet such that it doesn’t corrupt other signals easily
low power rates at receiver resulting in higher noise than
LVPECL
Table 3. CML Signal Format Pros and Cons
Pros
true differential
high slew rate
particularly suitable for the most
demanding applications
quiet
Cons
common mode voltage near ground or VCC
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
MT10338-0-1/12(0)
Rev. 0 | Page 8 of 8