ACS Technical Instrument Report 99-03
Justification and Requirements for
On-Board ACS FPR/EPER CTE
Calibration
Michael R. Jones, Mark Clampin, Gerhardt Meurer and Ronald Schrein
2 November 1999
ABSTRACT
On-orbit experience with WFPC2 and, to a lesser degree, STIS has shown that Charge
Transfer Efficiency (CTE) charge loss has a significant impact on the photometric precision of the CCD detectors. The magnitude of the error increases with time as displacement damage due to radiation exposure accumulates. In order to track the degradation of
the ACS HRC and WFC CCD detectors, some on-board means of accurately and efficiently measuring CTE should be defined. To accomplish this goal, we advocate the development of a set of special clock timing patterns that will be used to measure CTE via the
First Pixel Response (FPR) and Extended Pixel Edge Response (EPER) methods. We
present a general description of how both methods work and delineate specific requirements for on-board implementation of the FPR and EPER tests.
1. Introduction
The experience of WFPC2 has shown that severe long-term effects occur as a result of
the radiation environment in which HST operates [Reference 1]. The primary impacts are
CTE degradation and increased dark current, both of which will limit the ability to perform deep imaging of faint sources with ACS as a function of time. Detailed analysis and
interpretation of CTE charge loss effects for WFPC2 has required considerable amounts of
pointed calibration time with HST and a substantial data analysis effort.
We propose for ACS to increase the frequency of CTE monitoring in comparison to
WFPC2, while reducing the overall level of effort required to accomplish this calibration
task. The FPR test, in conjunction with the EPER test, will be used to track the CTE performance of the HRC and WFC CCD detectors on a bimonthly basis. Compared to the
pointed WFPC2 CTE calibration observations of globular cluster Omega Cen (NGC
5139), the FPR and EPER tests are advantageous from an operational standpoint because
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ACS Technical Instrument Report 99-03
neither test requires external pointed observations. Instead, both tests utilize the internal
ACS calibration lamps and can be performed at any point in the orbit without the additional overhead associated with slewing the observatory.
The FPR and EPER tests can be used to measure CTE with high signal resolution by
taking lamp exposures through different filters and by varying the integration time. High
signal resolution is of particular importance for ACS because the CCD imagers in the
HRC and WFC detectors incorporate 3 µm mini-channel implants. Our goal is to measure
the CTE from just above the detector noise floor to full well. HRC FPR CTE measurements obtained during the ACS thermal-vacuum test extended over a signal range of ~5080,000 electrons [References 2 and 3]. Based on this experience, we are reasonably confident that our goal of measuring the CTE over the full dynamic range of the HRC and WFC
detectors can be very nearly attained in practice.
Through on-board implementation of the FPR and EPER tests, we will be able to
obtain high-resolution CTE measurements every two to three months for a relatively low
cost. Scene dependence can be addressed by developing separate models for high and low
background fields based on the EPER and FPR data, respectively. These measurements
will be supplemented once a year by a more detailed study using external pointed observations of Omega Cen. As with WFPC2, observations of Omega Cen will be used to track
and characterize the true photometric performance of ACS as a function of source signal
level and location within the CCD arrays. This also enables us to directly compare the relative degradation of the CCD detectors in the two instruments as a function of time.
2. First Pixel Response (FPR) CTE Measurement
The FPR method of CTE measurement is an electronic knife-edge test. An optical
analogy may prove useful in understanding how the method works. A semi-infinite halfplane knife-edge mask is positioned in front of the CCD. The edge of the mask is aligned
either with the center row or the center column of the image area. With the mask in place,
a flat field image is acquired. The masked half of the frame will be dark and the exposed
area will contain one half of a normal flat field image. When the frame is read out, signal
electrons in the leading row (or column) of the half-flat image will be captured by traps in
the dark unexposed image area. Measurement of the charge deficit in the leading row (or
column) yields the parallel (or serial) CTE for a specific signal level.
Although straightforward in theory, acquisition of a perfect half-frame CCD image
using a mask is extremely difficult, if not impossible, to achieve in practice. Errors in
aligning the mask with the center row or column of the detector are inevitable. Blurring
caused by diffraction along the edge of the mask will compromise the sharpness of the
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ACS Technical Instrument Report 99-03
knife-edge. Finally, optical synthesis of a perfect half-frame image is not a viable option
for ACS because a knife-edge mask is not available for either detector.
We intend to implement the FPR method to measure the serial CTE of the HRC and
WFC detectors and the parallel CTE of the HRC detector. Synthesis of the optical knifeedge described above will be accomplished electronically by exploiting the half-frame
architecture of the SITe CCD imagers. The on-chip bus lines that drive the serial gates in
the HRC and WFC CCD detectors are split at the center column of the image area. This
facilitates simultaneous independent clocking of the left and right halves of the serial register. In addition, the parallel gate bus lines in the HRC detector are split at the center row.
The capability therefore exists for simultaneous independent clocking of the upper and
lower halves of the vertical registers in the HRC detector.
Figure 1 depicts in flow chart form the acquisition and clocking sequence we will
employ to electronically synthesize a perfect knife-edge. Of the three operations shown in
the flow chart, the flat field exposure sequence and the full-frame read out sequence are
standard procedures that are currently supported. Special clock patterns are required to
execute the half-frame flush sequence. A horizontal (or vertical) knife-edge is formed by
holding the clocks in one half of the image area static while simultaneously flushing the
other half without analog-to-digital conversion. The flat field exposure is held in the static
half of the image. FPR data is acquired using the same horizontal and vertical pixel transfer times as full-frame science data.
Figure 2 is an idealization of a row or column of data extracted from an FPR image.
CTE is computed as follows:
1
--∆Q n n

CTE(Q o, n) =  1 – -----------
Qo 

Equation 1
Variables Qo and ∆Qn represent the reference signal level and leading row (or column)
charge deficit, respectively, after n transfers of the leading row (or column). The CTE versus signal curve is measured by varying the value of Qo.
Since the leading edge of the half-flat is clocked through the flushed half of the image
during read out, FPR tends to yield a conservative measure of CTE. The half-frame flush
empties traps that would otherwise be filled by signal electrons. FPR is preferable to
EPER for modeling and calibration of charge loss effects in images of sparse fields or for
modeling of fields with a low background.
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3. Extended Pixel Edge Response (EPER) CTE Measurement
Unlike FPR, the EPER method of CTE characterization is not a knife-edge test. Measurement of CTE using the EPER technique only requires a slight modification of the standard full-frame flat field calibration sequence. Serial CTE is measured by clocking past
the last physical image pixel in each line of data. Parallel CTE is measured by clocking
beyond the last physical row of each column of data. Signal electrons in the trailing rows
and columns of the flat field image are captured in traps during read out of the image.
When the captured electrons escape from the traps, an exponential tail of deferred charge
appears behind the last physical row (or column) of the image. The CTE is determined by
measuring the total amount of deferred charge contained in the exponential tail. No
changes in clock timing are required for EPER.
An idealized representation of the trailing edge of a row (or column) of data extracted
from an EPER image is shown in Figure 3. Equation 1 is used to calculate the CTE. In
the case of EPER, variable ∆Qn equals the total amount of deferred charge in the exponential tail after n transfers of the last row (or column) of the physical image.
Signal electrons in the flat will be captured in traps when the EPER image is read out.
Traps in the pixels that precede the deferred charge tail will therefore be partially or completely filled. For this reason, EPER generally yields a higher value of CTE for a given
signal level than FPR or Fe55. EPER is most appropriate for modeling of CTE effects in
images with a high background or for modeling of crowded fields. EPER and FPR are
complementary tests that will provide an upper and lower bound, respectively, for the
CTE.
4. Generic Requirements
Both the generic and detector specific requirements for the ACS FPR and EPER tests
are based on hands-on experience gained through the WFC CCD radiation testing program and the HRC CTE measurements performed during the thermal-vacuum test. We
have endeavored to justify each requirement on technical grounds.
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4.1 Output Amplifier Selection
Requirement: The output amplifier used for read out of the FPR/EPER image(s) shall be
selectable.
Justification: Flexibility in selection of the output amplifier is required to ensure that the
amplifier with the lowest read out noise can be used for the FPR/EPER tests. In the event
of an on-orbit failure of one or more of the output amplifiers, the ability to rapidly switch
to a functional amplifier will minimize the impact on our proposed periodic CTE calibration program. Read noise measurements are not currently available to aid in the selection
of the output amplifier.
4.2 Output Amplifier Gain Setting
Requirement: The output amplifier gain setting shall be selectable.
Justification: At low signal levels, a gain setting of 1 will be used. A higher gain setting
must be used at high signal levels to avoid ADC saturation.
4.3 Filter Selection
Requirement: The filter wheel position shall be selectable. Support for crossed filters
shall be provided.
Justification: In order to obtain CTE measurements over the full dynamic range of the
CCD detectors, different filters must be used. Maximum efficiency is achieved by minimizing the integration time necessary to accumulate the desired reference signal level Qo.
This goal was met in the HRC thermal-vacuum CTE tests by using the F502N and F625W
filters for low and high signal levels, respectively [References 2 and 3]. Crossed F555W
and F435W filters were required to obtain low signal level exposures during the dry run of
the WFC thermal-vacuum CTE monitor test.
Implementation: The crossed filter requirement may be satisfied by specifying both filters in the spectral elements entry of the CTE proposal.
4.4 Exposure Time
Requirement: The exposure time shall be selectable.
Justification: For a given filter, the exposure time must be varied as necessary to achieve
the desired signal level Qo. As the detector operating temperature is gradually lowered
over time to offset radiation damage, adjustments in the exposure time for each signal
level may be needed to compensate for the decrease in QE. Exposure times of 0.5-17.0
seconds were required for the HRC thermal-vacuum thorough FPR test to measure the
CTE over the full dynamic range of the detector [Reference 3].
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4.5 Parallel Overscan
Requirement: 75 virtual overscan rows shall be acquired during EPER read out.
Justification: We have found through experience that the accuracy of the EPER CTE measurement hinges on how precisely the background can be estimated. The background is
modeled by fitting a line to the pixels trailing the deferred charge tail. Since the tail is
exponential, the number of overscan rows must be large enough to clearly discern where
the tail ends and the background begins. The uniqueness and numerical stability of the
linear fit will depend on the length of the background baseline. As the radiation damage in
the CCD detectors accumulates over time, the portion of the deferred charge tail that is
detectable above the noise floor will lengthen. In the ACS WFC radiation test program,
we determined through experimentation that 75 virtual overscan rows were required for
accurate post-rad EPER CTE measurements after proton irradiation equivalent to 2.5
years on-orbit (will be documented after the final round of radiation testing has been completed). The standard full-frame image format for both the HRC and WFC detectors
includes 20 virtual overscan rows [Reference 4]. Our parallel overscan requirement can
be satisfied by adding 55 additional virtual rows.
4.6 Serial Overscan
Requirement: 75 total (physical+virtual) trailing pixels (columns) shall be acquired during serial transfer of each line of an EPER image.
Justification: Serial overscan is necessary to perform the EPER serial CTE measurement.
The justification for 75 total trailing serial overscan pixels is the same as that for the parallel overscan requirement (section 4.5).
4.7 Repeats
Requirement: The number of repeats at each signal level shall be selectable.
Justification: Repeat measurements were shown in the HRC thermal-vacuum thorough
CTE test to be important for error analysis and for obtaining a more accurate estimate of
the mean CTE at a given signal level. All signal levels were repeated 2 times. Two additional repeats were obtained at a selected subset of signal levels [Reference 3].
Implementation: Entering a separate exposure in the CTE proposal for each repeat will
satisfy this requirement.
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4.8 FPR/EPER Clock Timing and Voltage Rails
There are no special clocking requirements for EPER or FPR. Clock times for parallel
row shift and serial pixel transfer are the same as for standard full-frame read out. No
changes are required in the high and low voltage rails of the parallel and serial clocks.
5. Specific Requirements for the ACS HRC Detector
5.1 Output Amplifier Selection
Requirement: Read out through amplifier A, B, C or D shall be selectable.
Justification: Flowed down from generic requirement 4.1.
Implementation: This requirement may be satisfied by setting an optional parameter in
the CTE proposal equal to the name of the timing program for the desired output amplifier.
5.2 Output Amplifier Gain Setting
Requirement: The output amplifier gain setting shall have a selectable value of 1, 2 or 4.
Justification: Flowed down from generic requirement 4.2. Gain settings of 2 and 4 were
required for the 70,000 electron and 90,000 electron HRC thermal-vacuum CTE measurements [Reference 3].
Implementation: Setting an optional parameter in the CTE proposal equal to the desired
gain setting will satisfy this requirement.
5.3 Serial Overscan
Requirement: 56 trailing virtual pixels (columns) shall be acquired during serial transfer
of each line of an EPER image.
Justification: Flowed down from generic requirement 4.6. The standard full-frame image
format for HRC includes 19 trailing physical serial pixels (columns) [Reference 4].
5.4 Calibration Lamp
Requirement: The Tungsten-4 lamp shall be used for all FPR/EPER exposures.
Justification: The thermal-vacuum HRC thorough CTE and CTE monitor tests were performed using the Tungsten-3 calibration lamp [References 2 and 3]. Subsequent analysis
of flats obtained with the Tungsten-3 and Tungsten-4 lamps indicates that the Tungsten-4
lamp produces a smoother illumination pattern [Reference 5]. Non-uniform illumination
contributes to the uncertainty in the reference signal level measurement, so the smoother
field of the Tungsten-4 lamp is preferable for the FPR/EPER exposures.
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5.5 Scan Sequence
Requirement: FPR/EPER data shall be acquired at a total of 18 selectable exposure levels. The data shall be acquired in one or more standard sequences. Two bias frames, one
at the beginning of a sequence and one at the end of a sequence, shall be acquired.
Justification: An 18 level sequence was successfully employed for the HRC thermal-vacuum thorough CTE test. SMS procedure JTVH05A_.SMS was used to execute this
sequence.
Implementation: To provide flexibility in on-orbit scheduling and to ease data storage
requirements, the 18 exposure levels can be split between two or more non-contiguous
sequences. A standard sequence can be executed by entering a separate exposure in the
CTE proposal for each desired signal level.
5.6 FPR Special Half-Frame Flush Clock Patterns
Parallel FPR: Generic clock patterns for parallel half-frame flush through the AB serial
register are shown in Appendix A. Clock patterns for half-frame flush through the CD
serial register can be deduced from the patterns for the AB serial register by similarity.
Serial FPR: As currently implemented in the instrument, the serial FPR half-frame flush
procedure differs slightly from the sequence described in Section 2. Figure 1 implies that
all 1024 rows are half-flushed before standard read out of the FPR frame begins. The
sequence employed in the instrument executes the half-row flush and standard read lineby-line. Two clock patterns, one pattern for standard line read and one pattern for halfrow flush, are stored in computer memory. Immediately following parallel transfer of a
line into the serial register, the half-row flush pattern is executed. The pattern for standard
line read is then loaded and executed. This sequence is repeated for all 1024 rows. The
final image is functionally equivalent to the idealized serial FPR image depicted in Figure
1.
Appendix A documents the generic clock patterns for half-row flush through amplifier A.
Patterns for half-row flush through the other amplifiers can be deduced from the HRC fuctional diagram by similarity.
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ACS Technical Instrument Report 99-03
6. Specific Requirements for the ACS WFC detector
6.1 Output Amplifier Selection
Requirement: Read out through amplifier C or D of Chip 1 shall be selectable. Read out
through amplifier A or B of chip 2 shall be selectable.
Justification: Flowed down from generic requirement 4.1.
Implementation: This requirement may be satisfied by setting an optional parameter in
the CTE proposal equal to the name of the timing program for the desired output amplifiers.
6.2 Output Amplifier Gain Setting
Requirement: The output amplifier gain setting shall have a selectable value of 1 or 2.
Justification: Flowed down from generic requirement 4.2. WFC has a full well capacity
of ~60,000 electrons. A gain setting of 2 will be sufficient to prevent ADC saturation at
high signal levels.
Implementation: Setting an optional parameter in the CTE proposal equal to the desired
gain setting will satisfy this requirement.
6.3 Serial Overscan
Requirement: 51 trailing virtual pixels (columns) shall be acquired during serial transfer
of each line of an EPER image.
Justification: Flowed down from generic requirement 4.6. The standard full-frame image
format for WFC includes 24 trailing physical serial pixels (columns) [Reference 4].
6.4 Calibration Lamp
Requirement: The Tungsten-2 calibration lamp shall be used for all FPR/EPER exposures.
Justification: Preliminary analysis of the WFC Tungsten-1 and Tungsten-2 lamps indicates that although Tungsten-1 is brighter, the illumination pattern produced by Tungsten2 is more uniform. Non-uniform lamp illumination contributes to the uncertainty in the
reference signal level measurement, so Tungsten-2 is preferable to Tungsten-1 for the FPR
and EPER tests.
6.5 Scan Sequence
Requirement: FPR/EPER data shall be acquired at a total of 17 selectable exposure lev-
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ACS Technical Instrument Report 99-03
els. The data shall be acquired in one or more standard sequences. Two bias frames, one
at the beginning of a sequence and one at the end of a sequence, shall be acquired.
Justification: A 17 level sequence was developed, but not verified, for the WFC thermalvacuum thorough CTE test. This sequence is based on thermal-vacuum procedure 5w.
Procedure 5w incorporates the same FPR timing pattern that was successfully used for the
ACS WFC radiation test program. 17 signal levels will provide sufficient resolution over
the dynamic range of the detector.
Implementation: To provide flexibility in on-orbit scheduling and to ease data storage
requirements, the 17 exposure levels can be split between two or more non-contiguous
sequences. A standard sequence can be executed by entering a separate exposure in the
CTE proposal for each desired signal level.
6.6 FPR Special Half-Frame Flush Clock Patterns
Serial FPR: WFC serial half-frame flush is performed with a procedure similar to that utilized for HRC (see requirement 5.6). Two alternating clock patterns for half-row flush and
standard serial line read are executed for each of the 2048 rows. The generic clock patterns for half-row flush through the A amplifier are documented in Appendix B. Generic
clock patterns for the other amplifiers can be deduced from the WFC functional diagram
by similarity.
7. Ground System Time Allocation
For each readout mode, the time allotted for ground system commanding Tc has been
determined according to the following algorithm:
T c = ceil(1.1 ⋅ T r + 1)
Equation 2
Variables Tc and Tr are in units of seconds. Function ceil() denotes round-up to the nearest integer. Tr is the readout time derived from the serial and parallel transfer times. As of
the date of publication of this report, the serial transfer time is 22 µsec/pixel for both HRC
and WFC. Parallel transfer times are 1408 µsec/line and 3212 µsec/line for HRC and
WFC, respectively.
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ACS Technical Instrument Report 99-03
7.1 FPR Time Allocation
HRC: Timing calculations for the special parallel half-frame flush clock pattern, serial
half-frame flush clock pattern and standard full-frame read are summarized in Tables 1, 2
and 3, respectively. The combined readout times for half-frame flush and standard fullframe read are 37.824336 seconds and 38.545232 seconds for serial and parallel FPR,
respectively. The corresponding time allotments for ground system commanding are 43
seconds and 44 seconds, respectively, for serial and parallel FPR.
WFC Serial: Tables 4 and 5 summarize the timing calculations for the special half-row
flush clock pattern and standard full-frame read, respectively. The total readout time is
288.533872 seconds. WFC serial FPR readout requires a time allocation of 319 seconds
for ground system commanding.
7.2 EPER Time Allocation
Serial and parallel EPER are combined in a single frame. Because half-frame flush is
not required for the EPER test, the timing calculations for HRC and WFC are simple
extensions of the standard format full-frame readout calculation.
HRC: The calculated readout time is 28.578396 seconds, as shown in Table 6. A time
allocation of 33 seconds is required for ground system commanding.
WFC: From Table 7, the calculated readout time for the WFC EPER test is 202.750746
seconds. The time allocation required for gound system commanding is 225 seconds.
8. References
1.
2.
3.
4.
5.
'Time Dependence of the Charge Transfer Efficiency on the WFPC2', B. Whitmore, TIR
WFPC2 98-01, 21 July, 1998.
T/V CTE Monitor Results', Michael R. Jones, Preliminary ACS Calibration Report
(ISR to be published), September 1999.
T/V Thorough CTE Calibration Results', Michael R. Jones, Preliminary ACS Calibration Report (ISR to be published), September 1999.
'Format of the ACS CCD Data', Robert Jedrzejewski, George Hartig, Mark Clampin,
TIR ACS-98-04.
'Tungsten Lamp Results', Joanna Schafer, Preliminary ACS Calibration Report, August
1999.
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ACS Technical Instrument Report 99-03
Figure 1: Flow chart of the FPR acquisition and clocking sequence.
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Figure 2: Idealized depiction of a row or a column of an FPR image.
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Figure 3: Idealized depiction of a row or a column of an EPER image.
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Readout
Timing (µsec)
Transfers
Total (µsec)
leading and trailing
serial physical
overscan
22
19 x 2
836
full-line flush at
standard read rate
22
1024
22528
parallel transfer of
one line into serial
register
1408
1
1408
total for one line
-
-
24772
total for 512 lines
-
-
12683264
Table 1. HRC parallel FPR half-frame flush timing.
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Readout
Timing (µsec)
Transfers
Total (µsec)
leading serial physical overscan
22
19
418
half-line flush at
standard read rate
22
512
11264
total for one line
-
-
11682
total for 1024 lines
-
-
11962368
Table 2. HRC serial FPR half-frame flush timing.
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ACS Technical Instrument Report 99-03
Readout
Timing (µsec)
Transfers
Total (µsec)
leading and trailing
serial physical
overscan
22
19 x 2
836
line read
22
1024
22528
1408
1
1408
total for one line
-
-
24772
total for 1024
image lines
-
-
25366528
total for 20 virtual
lines
-
-
495440
overall
-
-
25861968
parallel transfer of
one line into serial
register
Table 3. HRC standard full-frame readout timing.
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Readout
Timing (µsec)
Transfers
Total (µsec)
leading serial physical overscan
22
24
528
half-line flush at
standard read rate
22
2048
45056
total for one line
-
-
45584
total for 2048 lines
-
-
93356032
Table 4. WFC serial FPR half-frame flush timing.
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Readout
Timing (µsec)
Transfers
Total (µsec)
leading and trailing
serial physical
overscan
22
24 x 2
1056
line read
22
4096
90112
3212
1
3212
total for one line
-
-
94380
total for 2048
image lines
-
-
193290240
total for 20 virtual
lines
-
-
1887600
overall
-
-
195177840
parallel transfer of
one line into serial
register
Table 5. WFC standard full-frame readout timing.
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Readout
Timing (µsec)
Transfers
Total (µsec)
leading and trailing
serial physical
overscan
22
19 x 2
836
trailing serial virtual overscan
22
56
1232
line read
22
1024
22528
1408
1
1408
total for one line
-
-
26004
total for 1024
image lines
-
-
26628096
total for 75 virtual
lines
-
-
1950300
overall
-
-
28578396
parallel transfer of
one line into serial
register
Table 6. HRC EPER readout timing.
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Readout
Timing (µsec)
Transfers
Total (µsec)
leading and trailing
serial physical
overscan
22
24 x 2
1056
trailing serial virtual overscan
22
51
1122
line read
22
4096
90112
3212
1
3212
total for one line
-
-
95502
total for 2048
image lines
-
-
195588096
total for 75 virtual
lines
-
-
7162650
overall
-
-
202750746
parallel transfer of
one line into serial
register
Table 7. WFC EPER readout timing.
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Appendix A
Generic Clock Patterns for HRC Half-Frame Flush
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Definitions:
U=upper 512 image rows closest to the AB serial register
L=lower 512 image rows closest to the CD serial register
A=512 serial pixels closest to A output amplifier
B=512 serial pixels closest to B output amplifier
C=512 serial pixels closest to C output amplifier
D=512 serial pixels closest to D output amplifier
S=serial register
S2AB,S2CD=common phase 2 clock pattern for all 1024 serial pixels (all serial phase 2
pixels share a common on-chip bus)
P=parallel register
TG=transfer gate
High=default high rail voltage (the same rail voltage used for normal full frame read)
Low=default low rail voltage (the same rail voltage used for normal full frame read)
MPP=operation in multi-phase pinned mode
Example 1: P1U refers to parallel phase one of any pixel located in the upper 512 rows of
the image area
Example 2: S3B refers to phase 3 of any pixel of the half of the serial register closest to
output amplifier B
Example 3: P2L (MPP) refers to operation of the lower parallel phase 2 gates in multiphase pinned mode (operation in non-MPP mode is an option)
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Figure A1: HRC functional diagram.
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Figure A2: Generic clock patterns for parallel half-frame flush through the AB serial register.
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Figure A3: Generic clock patterns for serial half-row flush through the A amplifier.
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Appendix B
Generic Clock Patterns for WFC Half-Frame Flush
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Definitions:
Chip 1=butted CCD with AB serial register (per the format convention defined in Reference 4)
Chip 2=butted CCD with CD serial register (per the format convention defined in Reference 4)
S=serial register
A=2048 serial pixels closest to A output amplifier
B=2048 serial pixels closest to B output amplifier
C=2048 serial pixels closest to C output amplifier
D=2048 serial pixels closest to D output amplifier
S1AB,S1CD=common phase 1 clock pattern for all 4096 serial pixels (all serial phase 1
pixels share a common on-chip bus)
P1=common phase 1 clock pattern for all 2048 rows
P2=common phase 2 clock pattern for all 2048 rows
P3=common phase 3 clock pattern for all 2048 rows
High=default high rail voltage (the same rail voltage used for normal full frame read)
Low=default low rail voltage (the same rail voltage used for normal full frame read)
MPP=operation in multi-phase pinned mode
Example 1: S2A refers to phase 2 of any pixel of the half of the serial register closest to
output amplifier A
Example 2: P1 (MPP) refers to operation of the parallel phase 1 gates in multi-phase
pinned mode (operation in non-MPP mode is an option)
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Figure B1: WFC functional diagram.
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Figure B2: Generic clock patterns for serial half-row flush through the A amplifier.
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