A Novel Ternary More, Less and Equality Circuit
Using Recharged Semi-Floating Gate Devices
Henning Gundersen and Yngvar Berg
Department of Informatics, Microelectronic Systems Group, University of Oslo
Blindern, NO-0316, Oslo, Norway
Email: henningg@ifi.uio.no
Abstract— This paper presents a novel Ternary More, Less
and Equality (MLE) Circuit implemented with Recharged SemiFloating Gate Transistors. The circuit is a ternary application,
and ternary structures may offer the fastest search in a tree
structure. The circuit has two ternary inputs, and one ternary
output which will be a comparison of the two ternary inputs.
The circuit is a useful building block for use in a search tree
R Analog
application. The circuit is simulated by using Cadence
Design Environment with CMOS090 GP process parameters
from STMicroelectronics, a 90 nm General Purpose Bulk CMOS
Process with 7 metal layers. The circuit operates at a 1 GHz clock
frequency. The supply voltage is +/- 0.5 Volt. All capacitors are
metal plate capacitors, based on a vertical coupling capacitance
between stacked metal plates.
I. I NTRODUCTION
Ternary numbering system gives theoretically the fastest
search path in a tree structure. An example of a ternary
structure is a telephone menu system, with eight choices. If
you are using a binary structure, you will have two choices
for each level. This gives us the performance number of 4.51 .
A ternary structure, with three choices for each level, will
have a performance number of 3.75. Which is the optimal
number. [1].
If you want to test for equality less or more to sort two
inputs, in a binary search tree, you have to use two instructions.
In a ternary search tree, you only need one instruction to sort
two inputs. This paper presents a ternary application which
uses this feature. The truth table of the presented circuit is
shown in table I. As shown we use balanced ternary notation,
’perhaps the prettiest number system of all’ as Donald Knuth
said in his book, The Art of Computer Programming [2].
The Ternary More, Less and Equality (MLE) Circuit has two
inputs, the left most row (A) and the upper row (B). If A = B
the output is 0, if A < B the output is 1 and if A > B the
output is −1.
II. F UNDAMENTAL B UILDING BLOCKS USED IN
R ECHARGE S EMI -F LOATING G ATE (RSFG) D ESIGN
This paper will not cover the fundamental theory of RSFG
devices [3]. It is only the building blocks used in the ternary
MLE circuit that will be focused in this paper.
1 The performance number gives the average choices you have to go through
to find the right choice.
TABLE I
T HE TRUTH TABLE OF THE TERNARY M ORE , L ESS AND E QUALITY (MLE)
CIRCUIT
-1
0
1
-1
0
1
1
0
-1
0
1
1
-1
-1
0
A. Floating Gate Transistors
The multiple-input FG transistors can be used to simplify
the design of multiple-valued logic [4]. The initial charge on
the floating-gates may vary significantly and therefore impose
a very severe inaccuracy, unless we do apply some form of
initialization. Some work on floating-gate reset strategies have
been presented by Kotani et.al. [5], and by Berg et.al. [3].
B. Recharge Semi-Floating Devices
As mentioned, FG circuits need to be initialized, either
once initially or frequently. The once and for all initialization
is synonymous with programming. By recharging the SFG
frequently we avoid problems with any leakage currents and
random or undesired disturbance of the floating-gate charges.
The reset or recharged scheme can be used to overcome some
problems associated with the floating-gate circuit design
[3]. The recharged condition is different than the reset in
clocked-Neuron-MOS logic proposed by Kotani et.al. [5].
When reseting or recharging a gate, the inputs are
recharged simultaneously and they are set to a reference
voltage, normally Vdd /2. While recharging, the gates are
short-circuited and the output and the semi-floating-gate of a
logic gate is forced to Vdd /2.
The recharged scheme is similar to biasing of single-ended
auto-zeroing comparators, which have been used in highspeed flash AD converters. The main purpose of the recharged
scheme is to initialize or recharge the semi-floating-gates to an
equilibrium state, which can be utilized to yield fast binary and
multiple-valued signal processing. In addition we may reduce
the effect of mismatches, especially transistor mismatches, and
power supply noise. The recharged scheme provides a simple,
fast and accurate recharge to the equilibrium state for all gates
regardless of logical depth. We use the term Recharged Logic
(RL) or Recharged Semi-Floating- Gate Logic (RSFGL) for
the circuits presented in this paper [6]. The SFG circuits are
recharged to the initial equilibrium state, namely Vdd /2 or
Gnd, since the supply voltage is +/- 0.5 Volt.
C. The simple clock generator
All RSFG devices uses a clock scheme, to generate the
precharge and recharge period [7]. The ternary MLE circuit
uses a simple clock generator, figure 1, to generate an inverted
and a non-inverted clock pulse. The clock generator circuit
uses three minimum sized inverters.
REF
a valid recharge signal [8].
The AZC has two Pass-Gate Circuits, clocked with opposite
clock phase. The upper Pass-Gate Circuit in figure 3 has VDD
2
(Gnd) as input, and the lower Pass-Gate circuit has VIN as
input. In the recharge period the upper Pass-Gate circuit will
set the output signal VOU T and it will be set to Gnd, since
the supply voltage is +Vdd and -Vss . In the precharge period,
determined by the lower Pass-Gate circuit, the output signal
VOU T will be equal to VIN .
Examples of input and output signals from the Auto-Zero
Circuit (figure 3) are shown in figure 4. This figure shows
the two inputs, VIN 1 , and VIN 2 and the two Auto Zeroed
outputs VOU T 1 and VOU T 2 , which will be the inputs to the
RSFG devices. The input signals are stairs signals, with three
significantly levels (Ternary signals).
− CLK
+ CLK
+ CLK
+ CLK
Ne
Fig. 1.
Schematic diagram of the simple Clock Generator Circuit. The
design comprises three inverters coupled in series. The transistor sizes are
P e (w=460nm, l=100nm) and N e (w=120nm, l=100nm)
VDD/2
Pe
VOUT VIN
− CLK
Ne
0.5
REF
VOUT
AZC
VIN
0
Pe
− CLK
−0.5
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
−8
x 10
− CLK
0.5
+ CLK
Fig. 3. Schematic diagram of the Auto-Zero circuit. The transistor sizes are
P e (w=130nm, l=100nm) and N e (w=130nm, l=100nm)
0
−0.5
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
−8
x 10
0.5
VIN 1
+ CLK
0.5
0
0
−0.5
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
−8
−0.5
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
−8
x 10
Fig. 2. A plot of the input and output signals from the simple Clock Generator
Circuit in figure 1
VOUT 1
0.2
0.5
0
−0.5
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
−8
0.5
0
−0.5
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
−8
x 10
VOUT 2
Figure 2 shows the characteristics of the simple clock
generator in figure 1. The non-inverted clock pulse is the
output of inverter #2 (+ CLK) and the inverted clock pulse is
the output of inverter #3 (- CLK). The input reference clock
is a 1 GHz sinus-wave (REF).
0
x 10
VIN 2
0
x 10
0.5
0
−0.5
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
−8
x 10
D. The Auto-Zero Circuit (AZC)
The input stage of an RSFG device needs an Auto-Zero
Circuit as shown in figure 3. An Auto-Zero circuit can be
seen as a signal converter, which converts an input signal to
Fig. 4. Plots of the input and output signals from the Auto-Zero Circuit in
figure 3.
+ CLK
0.5
Cf
Pe
Ci
VIN
VIN
+ CLK
Ci
Cf
VOUT VIN
0
VOUT
−0.5
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
−8
Ne
x 10
Fig. 5. Schematic diagram of the Semi Floating Gate MVL inverter, which
generates the Ternary NOT function. The transistor sizes are P e (w=460nm,
l=100nm) and N e (w=120nm, l=100nm) Ci = 2f F, Cf = 1f F
VOUT
0.5
0
−0.5
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
−8
x 10
E. The Recharge Semi-Floating Gate (RSFG) Ternary Inverter
The Recharge Semi-Floating Gate (RSFG) MVL inverter
[7] in figure 5 is an important application, it can generate
the NOT function in ternary logic. A truth table of a Ternary
NOT function is shown in table II. In order to make voltage
TABLE II
Out
-1
1
0
0
1
-1
mode multi-valued signal, high accuracy and linearity is
necessary, since the voltage levels for each level is an equal
division of the supply voltage. This is the reason why the
MVL inverter is a key element in Multi-Valued Logic [3]. A
MVL inverter, also called an analog inverter, is an inverter
with a negative feedback mechanism (Cf ). The voltage gain
T
= −1. The voltage gain is
of this circuit is Av = VVOU
IN
determined by the capacitive division factor ki and kf (
Cf
Ci
and kf = Ctotal
). The transfer characteristic is
ki = Ctotal
given by equation 1. VIN and VOU T are the voltages on the
input and the output terminals. VDD is the supply voltage [9].
VOU T = VDD − VIN
III. T HE T ERNARY M ORE , L ESS AND E QUALITY (MLE)
C IRCUIT
The Ternary More, Less and Equality (MLE) circuit in
figure 7 has two inputs, VIN 1 and VIN 2 . It is made of two
Auto-Zero Circuits (AZC) and two ternary inverters (Ternary
NOT).
T HE TRUTH TABLE OF THE TERNARY NOT FUNCTION
In
Fig. 6. A plot of the input (Vin ) and output (Vout ) signals from the SemiFloating Gate MVL Inverters in figure 5, which shows the Ternary NOT
function.
(1)
Ideally Ci = Cf , however Cf has to be smaller than Ci due to
the output conductance and the parasitic capacitance, Cgd [9].
The ternary input signal (VIN ) and the ternary output signal
(VOU T ) are shown in figure 6. The input signal is a 9 trits2
word (-1 -1 -1 0 0 0 1 1 1) and the output word is (1 1 1
0 0 0 -1 -1 -1) which corresponds with the truth table of the
Ternary NOT function, shown in table II.
2 One trit has 3 values, the values are (-1, 0, 1), it is analogous to bit in the
binary world (0, 1).
The two inputs VIN 1 and VIN 2 are stairs signals as shown
in figure 4. The input signals go through an Auto-Zero block
(AZC) , the Auto-Zero Block is seen in figure 3. The AZC
is clocked with +CLK and −CLK from the simple Clock
Generator, the two inverters are clocked with +CLK to
operate as inverters. If they where clocked with −CLK it
would have been a latch element [10].
The input vector 1 and input vector 2 are balanced ternary
signals. VIN 1 is (-1 0 1 -1 0 1 -1 0 1) and VIN 2 is (-1 -1 -1 0
0 0 1 1 1). Both input signals are Auto Zeroed (INPUT 1 and
INPUT 2). The signal amplitude is +/- 0.4V olt, supply voltage
is +/- 0.5V olt. This gives us a dynamic voltage range of 80%.
The ternary MLE circuit is made with only to ternary inverters
as shown in figure 7, which comprise a compact design. The
output of the MLE circuit is defined by equation 2:
OU T P U T = N OT (IN P U T 1 − IN P U T 2)
(2)
This is achieved by using a ternary NOT function on INPUT
2, which is a ternary inverter with voltage gain Av = −1.
The output stage of the MLE circuit is a two input Ternary
NOT with voltage gain Av = −2. The output is the inverted
SUM of the two inputs (see equation 2). The output gain
is -2, because logic levels “1” should be “-1” not ”- 12 ”.
4
Ideally C5 = C3 +C
but due to the output conductance and
2
the parasitic capacitance Cgd , mentioned in section II-E,
4
C5 = C3 +C
. The output vector in figure 8 is (0 -1 -1 1 0 -1
4
1 1 0) which verifies the truth table of the presented MLE
circuit shown in table I.
The logic levels at the output, (see figure 9), are within their
boundaries. The boundaries for logic level “-1” are between
-500mV and -300mV. Logic level “0” is defined when the
boundaries are -150mV to 150mV, and for logic level “1”
it is 300mV to 500mV. This means if the output signal is
within these boundaries, the logic levels are recognized. If the
output signal are between 150mV to 300mV and -300mV to 150mV the signal is undefined. In order to have a well-defined
balanced ternary signal, the output signal can be refreshed
using a Ternary Switching Element [8]. After the refreshing
element the signal will be in the middle of their boundaries.
AZC
INPUT 1
0.3
0.2
0.1
0
0
−0.1
−0.2
−0.3
−1
−0.4
−0.5
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
−8
x 10
+ CLK
+ CLK
− CLK
Clock Generator. The supply voltage is only +/- 0.5 Volt.
This circuit is a fundamental building block in a fast ternary
search tree structure.
C5
C2
C3
+ CLK
C1
VIN 2
1
0.4
Fig. 9. The noise margins, which shows the boundaries for the logic levels.
+ CLK
VIN 1
0.5
OUTPUT
C4
AZC INPUT 2
INPUT 2 INV
− CLK
Fig. 7. Schematic diagram of the Ternary More, Less and Equality (MLE)
circuit. The transistor sizes are P e (w=460nm, l=100nm) and N e (w=120nm,
l=100nm), C2 , C5 = 1f F and C1 , C3 , C4 = 2f F .
The More, Less and Equality (MLE) Circuit has been evaluated with CadenceR Analog Design Environment, by using the
CMOS090 GP process parameters from STMicroelectronics,
this is a 90nm General Purpose Bulk CMOS Process with 7
metal layers. All capacitors are metal plate capacitors, based
on a vertical coupling capacitance between stacked metal
plates.
INPUT 1
R EFERENCES
0.5
0
−0.5
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
−8
INPUT 2 INV
INPUT 2
x 10
0.5
0
−0.5
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
−8
x 10
0.5
0
−0.5
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
−8
OUTPUT
x 10
0.5
0
−0.5
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
−8
x 10
Fig. 8. A plot of the input and output signal from the More, Less and
Equality (MLE) Circuit in figure 7.
IV. C ONCLUSIONS
In this paper a novel ternary More, Less and Equality
(MLE) Circuit has been presented. It has a compact design
with only two ternary inverters. It operates with a clock
frequency at 1 GHz. The total power dissipation is less than
200µW att, including the Auto Zero Circuit and the Simple
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