A Balanced Ternary Multiplication Circuit Using
Recharged Semi-Floating Gate Devices
Henning Gundersen and Yngvar Berg
Department of Informatics, Microelectronic Systems Group, University of Oslo
Blindern, NO-0316, Oslo, Norway
Email: henningg@ifi.uio.no
Abstract— This paper presents a multiplier circuit using Balanced Ternary (BT) Notation. The multiplier can multiply both
negative and positive numbers, which is one of the advantage
able properties of the balanced ternary numbering systems.
By using balanced ternary notation, it is possible to take
advantage of carry free multiplication, which is exploited in
designing a fast multiplier circuit. The circuit is implemented
with Recharged Semi-Floating Gate (RSFG) devices. The circuit
operates at 1 GHz clock frequency at a supply voltage of only
R Analog
1.0 Volt. The circuit is simulated by using Cadence
Design Environment, with CMOS090 process parameters, a 90nm
General Purpose Bulk CMOS Process from STMicroelectronics
with 7 metal layers.
a) ’Ternary inversion’ [1] is easy, change 1 with 1, and vica
versa. If we use the example -23, the result will be 1011 in
balanced ternary notation.
b) The sign of a number is given by its most significant
nonzero ’trit1 ’
c) The operation of rounding to the nearest integer is identical
to truncation.
d) Addition and subtraction are essentially the same operation:
just apply the rules of ’ternary inversion’ to one of the
numbers, and afterwards doing an adding operation.
I. I NTRODUCTION
In 1840 Thomas Fowler, a self-taught English mathematician invented a ternary mechanical calculating machine which
used balanced ternary notation. All details on the calulating
machine was lost, until recently. A research project which
began in 1997 have managed to get all the information which
is needed to create a historical replica [6]. Fowler used the
terms -, 0 and + for a negative, a zero and a positive number.
We will use the terms 1, 0 and 1. Arithmetic in balanced
ternary notation is almost the same as any other alternative
base, except it can handle negative and positive numbers.
This means that it can be both negative and positive carry
to adjacent digits.
Nowadays almost all multiplication done with computers
are binary multiplications. Multiplying two positive numbers
in a binary numbering system is trivial, but if we want
to deal with negative numbers, it is not that trivial. When
doing multiplication with negative numbers you usually need
a sign bit and you have to use the 2’ complement. That
is why I suggest using balanced ternary numbering system
instead, to make a solution to the sign problem. The so-called
’Brousentsov’s Ternary Principle’ of computer design was first
realized in the Setun computer [1] and this computer used a
’ternary-symmetrical number system’, which is another name
for the balanced ternary notation. There has also been some
other attempts to implement arithmetic applications which
use the ternary numbering system, but they lack commercial
success [2] [3].
B. Balanced Ternary Arithmetic
+
=
1
A. The Balanced Ternary Number Systems
’Ternary numbering systems is the most efficient of all
integer bases’ as Brian Hayes claims in his article Third Base
[4]. Balanced ternary notation is a number system which use
base 3 representation. Balanced ternary notation is ’Perhaps
the prettiest number system of all’ as Donald Knuth said
in his book, The Art of Computer Programming [5]. In
the balanced ternary the digits are also powers of 3, as in
ordinary ternary numbers, but they are ’balanced’ since they
are symmetrical about zero. A given example of a balanced
ternary number is the decimal number 23. It is written in
balanced ternary notation as: 1011. This numeral is interpreted
as: 1x33 + 0x32 − 1x31 − 1x30 , or 27 + 0 - 3 - 1, in decimal
notation. The balanced ternary number system has also some
advantage able properties:
1
decimal 1
1
decimal 1
1
decimal 2
Examples of positive carry in balanced teranary addition.
1
1
+
1
1
decimal 2
=
1
1
decimal 4
decimal 2
Examples of negative carry in balanced teranary addition.
1 One trit has 3 values, the values are ( 1, 0, 1), it is analogous to bit in the
binary world (0 , 1).
Multiplication in balanced ternary notation is done in the
similar manner as with decimal multiplication. The truth table
of a balanced ternary multipication is shown in table I.
Multiplication is done one digit a time. The choice of each
D. The Recharged Semi-Floating Gate (RSFG) Ternary Inverter
Cf
TABLE I
+ Clk
Pe
T HE TRUTH TABLE OF A BALANCED T ERNARY M ULTIPLICATION C IRCUIT
Cf
Ci
Vin
-1
0
1
-1
1
0
-1
0
0
0
0
1
-1
0
1
digit is simple, if the digit is 1 then invert, if it is 0 then set
it to zero, if it is 1 then multiply by one. For example the
multipication og 2 x 8 = 16 (decimal) is 1 1 x 1 0 1 = 1 1 1 1
in balanced ternary notation. The calculation is done as shown
in the table II. In the first row the multiplicand is inverted by
using ’ternary inversion’. In the second row, shift one time
left, then multiply with ’0’. In the third row, shift left, then
multiply with ’1’. Then the three numbers are added together
using a balanced ternary adder.
TABLE II
A N EXAMPLE OF AN BALANCED TERNARY MULTIPLICATION .
1
0
1
1
1
0
1
1
1
Invert multiplicand
0 times multiplicand
1
Ci
+ Clk
Vout
Vin
Vout
Ne
Fig. 1.
Schematic diagram of the Recharged Semi-Floating Gate MVL
Inverter, which generates the Ternary NOT function. The transistor sizes are
Pe (w = 460nm and l = 100nm) and Ne (w = 120nm and l = 100nm)
The Recharge Semi-Floating Gate (RSFG) MVL-Inverter
in figure 1 is an important application [10]. This is a key
element in Multi-Valued Logic [9]. A MVL inverter, also
called an analog inverter, is an inverter with a negative
feedback mechanism, Cf . The voltage gain of this circuit is
out
Av = ∆V
∆Vin = −1. The transfer characteristic of the analog
inverter is given by equation1 [11].
Vout = Vdd − Vin
(1)
A MVL inverter can be used to generate the ’ternary inversion’. The truth table of the rule of ’ternary inversion’ is shown
in table III.
1 times multiplicand
TABLE III
decimal 16
T HE TRUTH TABLE OF THE RULE OF ’ TERNARY INVERSION ’
Vin
Vout
1
1
C. Recharge Semi-Floating Gate Devices
0
0
The multiple-input floating-gate (FG) transistors can be
used to simplify the design of multiple-valued logic [7]. The
initial charge on the floating-gates may vary significantly and
therefore impose a very severe inaccuracy, unless we do apply
some form of initialization. Research on floating-gate reset
strategies have been presented by Kotani et.al. [8], and by
Berg et.al. [9].
Floating-gate (FG) circuits need to be initialized, either
once initially or frequently. The once and for all initialization
is synonymous with programming. By recharging the FG
frequently we avoid problems with any leakage currents and
random or undesired disturbance of the floating-gate charges,
and we convert the non-volatile floating gates to Semi Floating
Gates (SFG)[9]. The reset or recharged scheme may be used
to overcome some problems associated with the floating-gate
circuit design.
All of the capacitors in the CMOS RSFG design presented
in this paper are metal plate capacitors, based on vertical
coupling capacitance between stacked metal plates.
1
1
II. I MPLEMENTATION OF THE BALANCED TERNARY
MULTIPLICATION CIRCUIT USING R ECHARGED
S EMI -F LOATING G ATE D EVICES
A block scheme of the proposed BT-multiplication circuit
is shown in figure 2. The input data is set into a shift register,
and here the data is shifted and leading zeros are inserted in
the input vectors X, Y and Z. From the shift register the 4-trits
data are sent to each of the vectors X,Y and Z. X Y and Z are
the input signals to the 4-trits BT-Adder. The outputs from the
BT-Multiplication (BTM) circuit are S0, S1, S2, S3 and S4.
A. A Balanced 3,2 Ternary Counter
A balanced 3,2 ternary counter, can also be seen as a 3input ternary full adder, where the carry signal can take all
three logic values (1, 0, 1). The balanced 3,2 ternary counter
C10
DATA
C12
SHIFT REGISTER
C1
+ Clk
+ Clk
C−HIGH
Z
CARRY DETECT
_
1
1
C−LOW
0
C11
C2
i4
i3
0
S1
X
_____
SUM 1
Y
0
0
0
0
Y
C7
Z
X
0
_
1
0
C9
C3
+ Clk
1
+ Clk
C4
C8
C5
Z3
Z2
Z1
Z0
Y3
Y2
Y1
Y0
X3
X2
X1
i1
i2
S0
X0
C6
4 TRITS BALANCED TERNARY ADDER
Fig. 3.
S4
Fig. 2.
S3
S2
S1
S0
The Block Scheme of the multiplication circuit
TABLE IV
T HE TRUTH TABLE OF A BALANCED 3,2 T ERNARY COUNTER
(X + Y + Z)
-3
-2
-1
0
1
2
3
S0
0
1
1
0
1
1
0
S1
1
1
0
0
0
1
1
(BTC) is shown in figure 3, the truth table of the (3,2) BTC
is shown in table IV.
The Balanced 3,2 Ternary Counter takes three ternary inputs
X, Y and Z, and generates two outputs, S0 and S1. This
counter counts from -3 to +3. The full truth table is shown
in table V. The simulation results of the (3,2) BTC is shown
in figure 4, when the logic input signal X is set to 0.
The Carry detect stage will detect when two or three of the
inputs are high or low. This will then generate the binary high(C-HIGH) or binary low- (C-LOW) carry signal. The C-HIGH
and C-LOW signal are combined to a ternary signal SU M 1.
By adding the SU M 1 with the input signals X, Y and Z, by
using a 4-input ternary inverter (i1), we get the correct SUM
0 signal. A similar balanced ternary adder were presented in
Singapore at the ISMVL2006 conference [12]. It had a two
balanced ternary inputs (X and Y) and two outputs, S0 and
S1, but the main idea of operation is almost the same.
B. The Balanced Ternary Multiplication Circuit
A balanced ternary counter is a key element in a multiplication application. To make a 4-trits BT-Adder (figure 6) we
need to use 8 balanced 3,2 ternary counters (BTC) which is
shown in figure 3. The output stage (4-trits BTA) of the 4trits balanced ternary multiplication (BTM) circuit shown in
figure 2, consists of 8 BTC’s. The SUM output signals is S0,
S1, S2, S3 and S4.
The input vectors X, Y and Z to the 4-trits BTA (the output
stage) will either be inverted, be zero or be unchanged. If we
A Block Schematic diagram of the Balanced 3,2 Ternary Counter
take the example 2 x 8 (decimal) 11 x 101 (balanced ternary)
shown in table II. The first product is the inverted, of the
multiplicand which generates the 4-trits X vector X=[1 1 0
0]. The second product should be set to 0, which gives the Y
vector Y=[0 0 0 0]. The third product is first shifted 2 times left
and then 1 times multiplicand this gives the Z vector Z=[0 0 1
1]. Figure 5 shows the input to the output stage. X is inverted
using a ternary inversion, Y is set to ’0’ and Z propagates to the
input of the 4-trits BTA. To make this possible, a multiplexerswitch must be set on the input to the BTA circuit.
Figure 6 shows the propagation of the trits in the output
stage. Since the BTC are 3,2 counter some of the inputs of
the BTCs has to be set to ’zero’ as shown in the figure 6. The
signal S0 has less delay. The signal S4 has the longest path
and this will determined the maximum operation frequency of
this circuit.
Figure 7 shows the simulated output plots of the BTMultiplication circuit. The figure shows the output vector
SUM=[S3 S2 S1 S0] = [1 1 1 1], the result of the simulation
correspond with the total sum of the multiplication done in
table II. S4 is ’zero’ and is not shown.
III. C ONCLUSIONS
In this paper a 4-trits Balanced Ternary Multiplication
(BTM) circuit has been presented. It has some advantage able
properties, it handles multiplication with both negative and
positive numbers, which is one of the benefits using balanced
ternary notation. This application shows that it is possible
to build a fast multiplier circuit if we use balanced ternary
notation, and by using a conventional CMOS Process. The
proposed BTM operates at a clock frequency at 1 GHz at a
load of 10f F .
R EFERENCES
[1] S. Stakhov, “Brousentsov’s Ternary Principle, Bergman’ Number System
and Ternary Mirror-symmetrical Arithmetic,” The Computer Journal,
Vol. 45, No.2, pp. 221–236, 2002.
[2] A. Herrfeld and S. Hentsche, “Ternary Multiplications Using 4-Input
Adder Cells and Carry Look-Ahead,” Proceedings of the 29th IEEE
International Symposium on Multiple-Valued Logic, 1999.
[3] K. Diawuo and H. T. Mouftah, “A Three-Valued CMOS Arithmetic
Logic Unit Chip,” Proceedings of the 17th IEEE International Symposium on Multiple-Valued Logic, pp. 215–220, 1987.
TABLE V
T HE FULL TRUTH TABLE OF THE BALANCED 3,2 T ERNARY C OUNTER
X
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
Y
1
1
1
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
Z
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
SUM
10
11
01
11
01
00
01
00
01
11
01
00
01
00
01
00
01
11
01
00
01
00
01
11
01
11
10
Z3
1
X
1
0
X3
Z2
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
S4
2
X2
0
Z1
0
S3
S2
S2
1
X1
0
_
1
0
Y0
X0
0
1
(3,2)
BTC
S1
_
1
0
S1
S0
0
1
’0’
0.5
0
Z0
_
1
0
(3,2)
BTC
BTC
1
Y
Y1
0
(3,2)
S3
0
−8
x 10
Y2
_
1
0
(3,2)
BTC
0.5
0
Y3
(3,2)
BTC
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
S2
2
S1
0
−8
x 10
_
1
Z
1
(3,2)
BTC
0.5
0
S3
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
S2
_
1
0
−8
SUM 0
x 10
1
(3,2)
BTC
0.5
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
’0’
2
S4
S3
0
1
−8
SUM 1
x 10
(3,2)
BTC
1
0.5
0
S4
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
0
2
−8
S4
x 10
Fig. 4. Simulation results for the Balanced 3,2 Ternary Counter shown in
figure 3.
_
1
1
S3
S2
_
1
1
S1
S0
Fig. 6. A block diagram of the 4-trits Balanced Ternary Adder showing the
propagation of the trits
1
0
0
1
__
1
0
0
S0
__
X
X
__
1
0.5
0
1
S0
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
x 10
S1
0
0
1
__
1
0
0
4 TRITS BTA
S2
0.5
0
S3
Z
S4
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
0.5
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
x 10
The input vectors to the 4-trits Balanced Ternary Adder
−9
S3
1
0.5
0
[4] B. Hayes, “Third Base,” American Scientist, Volume 89, Number 6, pp.
490–494, Nov-Dec 2001.
[5] D. Knuth, The Art of Computer Programming, Second edition. AddisonWesley Publishing Company, 1981.
[6] M. Glusker, D. M. Hogan, and P. Vass, “The Ternary Calcualating
Machine of Thomas Fowler,” IEEE Annals of the History of Computing,
pp. 4–22, 2005.
[7] T. Shibata and T. Ohmi, “A Functional MOS Transistor Featuring GateLevel Weighted Sum and Threshold Operations,” IEEE Transactions on
Electron devices, vol. 39(6), pp. 1444–1455, 1992.
[8] K. Kotani, T. Shibata, M. Imai, and T. Ohmi, “Clocked NeuronMOS Logic Circuits Employing Auto Threhold Adjustment,” IEEE
International Solid-State Circuits Conference(ISSCC), pp. 320–321,388,
1995.
[9] Y. Berg, S. Aunet, O. Mirmotahari, and M. Høvin, “Novel Recharge
Semi-Floating-Gate CMOS Logic For Multiple-Valued Systems,” Proceedings of the 2003 IEEE International Symposium on Circuits And
Systems in Bangkok, 2003.
−9
1
S2
0
0
Fig. 5.
1
x 10
0
−9
1
S1
Y
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
x 10
−9
Fig. 7. A plot of the outputs from the Balanced Ternary Multiplication circuit
[10] H. Gundersen and Y. Berg, “MAX and MIN Functions Using MultipleValued Recharged Semi-Floating Gate Circuits,” Proceedings of the
2004 IEEE International Symposium on Circuits And Systems in Vancouver, 2004.
[11] Y. Berg, T. S. Lande, Ø. Næss, and H. Gundersen, “Ultra-Low-Voltage
Floating Gate Transconductance Amplifiers,” IEEE Trans. Circuits and
Systems-II: Analog and Digital Signal Processing,vol.48,no.1, Jan. 2001.
[12] H. Gundersen and Y. Berg, “A Novel Balanced Ternary Adder Using
CMOS Recharged Semi-Floating Gate Devices,” Proceedings of the 36th
IEEE International Symposium on Multiple-Valued Logic in Singapore,
p. 18, 2006.