Power Processing and Active Protection for
Photovoltaic Energy Extraction
by
ARCHNES
MASSACHUSETTS INSTITUTE
OF rECHNOLOLGY
Arthur Hsu Chen Chang
MAR 19 2015
B.S., California Institute of Technology, 2009
M.S., California Institute of Technology, 2010
LIBRARIES
Submitted to the
Department of Electrical Engineering and Computer Science
in partial fulfillment of the requirements for the degree of
Doctor of Philosophy
at the
MASSACHUSETTS INSTITUTE OF TECHNOLOGY
February 2015
Massachusetts Institute of Technology 2015. All rights reserved.
Signature redacted
Author ....
Department of Electrical Engineering
Certified by........Signature
F?
mputer Science
January 15, 2015
redacted.................
Steven B. Leeb
Professor of Electrical Engineering and Computer Science
Thesis Supervisor
Accepted by ............
Signature redacted
Leslie A. Kolodziejski
U6
Chairman, Department Committee on Graduate Theses
2
Power Processing and Active Protection for Photovoltaic
Energy Extraction
by
Arthur Hsu Chen Chang
Submitted to the Department of Electrical Engineering and Computer Science
on January 15, 2015, in partial fulfillment of the
requirements for the degree of
Doctor of Philosophy
Abstract
Solar photovoltaic power generation is a promising clean and renewable energy technology that can draw upon the planet's most abundant power source - the sun. However,
relatively high levelized cost of energy (LCOE), the ratio of the total cost of ownership
to the total energy extracted over the lifetime of the generation system, has limited
the grid penetration of solar power.
Mismatch loss remains an important issue to address in PV systems, and a solar
power system can lose as much as 30% of its energy generation capability over a year
due to mismatch. Maximum power point tracking (MPPT) using power electronics
converters can increase the overall solar energy extraction efficiency and thus reduce the
LCOE. Many power electronics solutions have been proposed at the module and submodule levels, which only partially addresses the mismatch problem. However, scaling
the existing solutions to finer optimization granularity has been cost-prohibitive. In the
first part of this thesis, a new cell-level strategy, termed diffusion charge redistribution
(DCR), is proposed to fully recover mismatch loss. The proposed technique processes
power by leveraging the intrinsic solar cell capacitance rather than relying on externally
added intermediate energy storage in order to drastically reduce to the cost of MPPT
while enabling the finest optimization granularity. Moreover, strings balanced by this
technique exhibit power versus current curves that are convex, which simplifies the
required MPPT algorithm. Cell-level power balancing may also ease the testing and
binning criteria during manufacturing, which leads to additional cost savings.
Differential power processing (DPP) is a key concept to further improve energy
efficiency by minimizing the amount of power conversion. In the second part of this
thesis, the concept of differential power processing is introduced to the proposed
cell-level power balancing technique by rethinking the string-level power electronics
architecture. This enhancement can improve the overall efficiency of DCR by more
than 3.5% while permitting the use of a slower DCR switching frequency. It can
also be applied to many other cascaded converter architectures to reduce insertion
loss. In particular, the proposed differential DCR (dDCR) architecture simultaneously
3
achieves maximum power point tracking without any external passive components at
the cell-level, and maintains differential power processing with zero insertion loss. This
is accomplished by decoupling the MPPT functional block from the DPP functional
block. The new power optimization aims to not only maximize energy extraction
from each solar cell but also minimize the amount of processed power. The new
multi-variable optimization space for the dDCR topology is evaluated and shown to
be convex, which simplifies the required optimization algorithm.
The inverter represents a large part of the overall cost and is often the most
failure-prone component in a photovoltaic power system. In order to improve the
cost and reliability of a grid-tie inverter, switched-capacitor techniques are adopted
to reduce the required capacitance and rated voltage of the dc-link capacitor. The
proposed switched-capacitor energy buffer can improve capacitor energy utilization
by more than four times for a system with a 10% peak-to-peak ripple specification,
and enable the use of film or ceramic capacitors to prolong the system lifetime to over
a hundred years. The third part of this thesis explores the SC energy buffer design
space and examines tradeoffs regarding circuit topology, switching configuration, and
control complexity. Practical applications require control schemes capable of handling
source and load transients. A two-step control methodology that mitigates undesirable
transient responses is proposed and demonstrated in simulation.
Finally, dc power system architectures have attracted interest as a means for
achieving high overall efficiency and facilitating integration of renewable and distributed
energy sources, such as a photovoltaic system. However, to enable widespread adoption
of dc systems, the reliability of fault protection and interruption capability is essential.
A new dc breaker topology, called the series-connected Z-source circuit breaker, is
introduced to minimize the reflected fault current drawn from a source while retaining
a common return ground path. Analogous in some respects to an ac thermal-magnetic
breaker, the proposed Z-source breaker can be designed for considerations affecting
both rate of fault current rise and absolute fault current level. The proposed manual
tripping mechanism also enables protection against both instantaneous large surges in
current and longer-term over-current conditions.
Thesis Supervisor: Steven B. Leeb
Title: Professor of Electrical Engineering and Computer Science
4
Acknowledgments
There are many people whom I would like to thank for supporting me throughout my
graduate studies.
I would like to thank my research advisor, Professor Steven B. Leeb for his advice,
funding, and support. I would also like to thank the members of my thesis committee,
Professor Jeffrey H. Lang and Professor James L. Kirtley Jr., for their insights,
comments and suggestions.
I would like to acknowledge the generous funding sources. This research was
made with Government support under and awarded by DoD, Air Force Office of
Scientific Research, National Defense Science and Engineering Graduate (NDSEG)
Fellowship, 32 CFR 168a. This work was also supported by The Grainger Foundation,
the Kuwait-MIT Program, the Kuwait Foundation for Applied Sciences, and Cypress
Semiconductor Corporation.
I would like to thank my graduate counselor, Professor John G. Kassakian, for
his encouragement and guidance over the years. I would also like to thank Professor
Rahul Sarpeshkar, Professor David J. Perreault, Professor Anantha P. Chandrakasan,
and the late Professor James K. Roberge for their inspirational teaching.
I am grateful to my friends and colleagues, who have contributed to both my
professional development and personal growth. I thank Fan Huang, whom I have relied
on countless times, for her constant loving support. I thank Al-Thaddeus Avestruz
for his friendship, mentorship, and many interesting late-night conversations. I thank
Arijit Banerjee for making the lab more vibrant and for making me think about
problems that I would otherwise not have. I thank Jinyeong Moon for being the best
officemate and always sticking around for me. I would also like to acknowledge some
of my other colleagues, in particular, Jim Paris, John Donnal, Shahriar Khushrushahi,
Uzoma Orji, Chris Schantz, Matthew Angle, Brian Sennett, in the Laboratory of
Electromagnetic and Electronic Systems (LEES).
I would especially like to thank my family, without whom none of this would be
possible. I thank my parents, Ben Chang and Jenna Cheng for their unconditional
5
love and unwavering support. You have made countless sacrifices to provide the best
opportunities for me and my brother, and I will never be able to adequately express
my gratitude. I thank my brother, Albert Chang, for constantly looking out for me
and encouraging me. I thank my uncle, Rong Chang, for enlightening me and helping
me stay open-minded. I thank my grandmother, Yea-Lin Wang Chang, for always
taking care of me and providing me with warmth. I thank my aunt, Sheena Cheng,
for sharing her life experience with me and always welcoming me.
Finally, I would like to dedicate this thesis to the memory of my grandfather,
Pao-Shen Chang, who had always believed in me.
6
Contents
21
1 Introduction
22
1.2
Hot Spots and Reliability Concerns . . . . . . . . . . . . . . . . . .
24
1.3
Thesis Contributions . . . . . . . . . . . . . . . . . . . . . . . . . .
26
.
.
29
Solar Cell-Level Maximum Power Point Tracking
Motivations for Modular Optimization ............
. . .
30
2.2
Photovoltaic Cell Diffusion Capacitance ..........
. . .
31
Solar Cell Diffusion Capacitance Characterization
. . .
32
2.2.2
Single-Capacitor Diffusion Charge Redistribution
. . .
35
Capacitor-less Diffusion Charge Redistribution . . . . .
. . .
38
2.3.1
Slow-Switching Limit Power Conversion Loss . .
. . .
40
2.3.2
Fast-Switching Limit Power Conversion Loss . .
. . .
44
2.3.3
Recovered Power Loss from Process Variation
.
. . .
46
2.4
Circuit Implementation . . . . . . . . . . . . . . . . . .
. . .
48
2.5
Experimental Results . . . . . . . . . . . . . . . . . . .
. . .
51
2.6
Sum m ary . . . . . . . . . . . . . . . . . . . . . . . . .
. . .
58
.
.
.
.
.
.
2.2.1
.
2.1
2.3
59
Single-Output Switched-Ladder DCR . . . . . . . . . .
. . . . . . .
60
3.2
Differential Power Processing
. . . . . . . . . . . . . .
. . . . . . .
60
. . . . . . .
61
. . . . . . .
63
.
3.1
.
Differential Diffusion Charge Redistribution
.
3
.
Mismatch and Energy Loss . . . . . . . . . . . . . . . . . . . . . . .
3.2.1
3.3
Operation under Uniform Irradiance Condition
Current Divide Ratio Tuning . . . . . . . . . . . . . . .
.
2
1.1
7
3.4
67
3.4.1
3-2 dDCR Output Power Convexity Derivation
. . . . . . .
68
3.4.2
Generalized dDCR Output Power Convexity Derivation . . .
73
3.4.3
Simulated Output Power Contour . . . . . . . . . . . . . . .
75
3.5
Local Control and Frequency Scaling . . . . . . . . . . . . . . . . .
82
3.6
Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . . .
82
3.7
Experimental Validation . . . . . . . . . . . . . . . . . . . . . . . .
83
3.8
Sum m ary
87
.
.
.
.
.
.
.
Output Power Optimization Convexity . . . . . . . . . . . . . . . .
.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Switched-Capacitor Energy Buffer Architecture and Inverter Reliability Considerations
Failure and Reliability of a PV Plant . . .
. . . . . . . . .
89
4.2
DC-Link Capacitor Background . . . . . .
. . . . . . . . .
90
4.3
Switched-Capacitor Energy Buffer Overview
. . . . . . . . .
91
4.4
SC Energy Buffer Design Considerations .
. . . . . . . . .
93
4.4.1
Capacitor Configuration . . . . . .
. . . . . . . . .
94
4.4.2
Switching Topology Tradeoff . . . .
. . . . . . . . .
98
Two-Step Control Strategy . . . . . . . . .
.
. . . . . . . . .
101
4.5.1
Capacitor Participation Optimization
. . . . . . . . .
102
4.5.2
Switch Timing Determination . . .
. . . . . . . . .
104
4.5.3
Distortion and Phase Error
. . . .
. . . . . . . . .
109
4.5.4
Pre-charge Circuit Requirement . .
. . . . . . . . .
110
4.5.5
Over- and Under-voltage Protection
. . . . . . . . .
110
. . . . . . . . .
111
.
.
.
.
.
.
.
.
.
4.1
Simulation Results
4.7
Summary
. . . . . . . . . . . . .
.
4.6
. . . . . . . . . . . . . . . . . .
.
4.5
...... 116
117
5.1
Z-Source Breaker Overview . . . . . . . . . . . . . . . . . . . .
120
5.1.1
Fault Clearing Waveforms . . . . . . . . . . . . . . . .
121
5.1.2
Voltage Transfer Function . . . . . . . . . . . . . . . .
124
5.2
.
.
.
Z-Source Circuit Breaker and DC Power System Protection
Z-Source Breaker Design Considerations
8
. . . . . . . . . . . .
.
5
89
127
5.2.1
Minimum Detectable Fault Magnitude
. . . . . . . . . . . . .
128
5.2.2
Minimum Detectable Fault Ramp Rate . . . . . . . . . . . . .
129
5.2.3
Z-Source Inductor Relative Sizing . . . . . . . . . . . . . . . .
132
5.2.4
Constant Power and Resistive Loads
. . . . . . . . . . . . . .
136
5.2.5
SCR Reverse Recovery Time . . . . . . . . . . . . . . . . . . .
138
5.2.6
Reflected Fault Current
. . . . . . . . . . . . . . . . . . . . .
139
Extended Protection Schemes . . . . . . . . . . . . . . . . . . . . . .
140
5.3.1
Manual Tripping of Z-Source Breaker . . . . . . . . . . . . . .
141
5.3.2
Dual-Mode Fault Detection
. . . . . . . . . . . . . . . . . . .
144
5.4
Experimental Validation . . . . . . . . . . . . . . . . . . . . . . . . .
148
5.5
Summary
155
5.3
6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
157
Conclusion
A Diffusion Charge Redistribution Hardware
A.1 Schematic Drawings
161
. . . . . . . . . . . . . . . . . . . . . . . . . . .
162
A.2 PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
163
A.3 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
166
A.4 Software Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . .
167
A.4.1
FPGA Code . . . . . . . . . . . . . . . . . . . . . . . . . . . .
167
. . . . . . . . . . . . . . . . . . . . . .
172
A.4.2 FrontPanel GUI Code
B dDCR Current Divider Hardware
177
. . . . . . . . . . . . . . . . . . . . . . . . . . .
178
B.2 PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
180
B.3 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
183
B.4 Software Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . .
184
B.1 Schematic Drawings
B.4.1
PSoC C Code . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
C Z-Source Circuit Breaker Hardware
187
. . . . . . . . . . . . . . . . . . . . . . . . . . .
188
C.2 PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
191
C.1 Schematic Drawings
9
C.3 Bill of M aterials ..............................
194
C.4 Software Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . .
195
C.4.1
PSoC C Code . . . . . . . . . . . . . . . . . . . . . . . . . . .
195
C.4.2
MATLAB Code . . . . . . . . . . . . . . . . . . . . . . . . . .
197
10
List of Figures
1-1
Typical solar cell and panel configuration and the corresponding singlediode model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-2
22
Previously proposed power processing architectures for maximum power
point tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
1-3
Example embodiments of existing differential power processing converters. 25
1-4
Solar cell hot spot. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26
2-1
Commonly used single diode solar cell model.
. . . . . . . . . . . . .
31
2-2
Solar cell capacitance characterization switching circuit. . . . . . . . .
33
2-3
Solar cell capacitance characterization switching waveform. . . . . . .
33
2-4
Solar cell capacitance versus diode current. . . . . . . . . . . . . . . .
34
2-5
Single-capacitor diffusion charge redistribution experimental setup.
36
2-6
Measured output power versus output current with and without single-
.
capacitor diffusion charge redistribution. . . . . . . . . . . . . . . . .
37
2-7
Proposed fully-scalable ladder-connected DCR architecture . . . . . .
39
2-8
Charge flow in proposed cell-level power balancing architecture using a
2-9
3-2 ladder DCR string configuration. (a) phase 1 (b) phase 2. ....
41
Schematic of the 3-2 DCR ladder converter experimental prototype.
49
2-10 Diagram 3-2 DCR ladder converter experimental prototype.
. . . . .
50
2-11 Experimental measurement of output voltage and current of a 5-cell
series string by sweeping the output current at 1 ampere per second. .
52
2-12 Experimental measurement of a 3-2 DCR string compared to the 5
series string under uniform irradiance condition. . . . . . . . . . . . .
11
53
2-13 Experimental measurement of a 3-2 DCR string compared to the 5
series string with two cells 40% shaded. . . . . . . . . . . . . . . . . .
54
2-14 Experimental measurement of a 3-2 DCR string compared to the 5
series string with one cell 40% shaded and one cell 75% shaded.
3-1
. . .
Conceptual diagram of the proposed differential DCR (dDCR) architecture with dual current source inverter output. . . . . . . . . . . . .
3-2
55
62
SPICE simulation comparing the output power versus total output
current under uniform irradiance among three topologies: 9 series
string, 5-4 DCR, and 5-4 dDCR architectures. . . . . . . . . . . . . .
3-3
64
SPICE simulation comparing the output power versus total output
current with four cells shaded among three topologies: 9-series string
with per-cell bypass diodes, 5-4 DCR, and 5-4 dDCR architectures. In
the DCR and dDCR configurations, the four shaded cells are chosen to
be the ladder-connected cells.
3-4
. . . . . . . . . . . . . . . . . . . . . .
Equivalent circuit model for examining output power optimization
convexity:
(a) with DCR network shown, (b) with DCR network
replaced by effective redistribution current sources.
3-5
66
. . . . . . . . . .
69
SPICE simulated output power 3-D surface plot over the space spanned
by the total output current and the current divide ratio under uniform
irradiance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-6
77
SPICE simulated output power contour over the space spanned by
the total output current and the current divide ratio under uniform
irradiance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-7
77
SPICE simulated output power contour over the space spanned by the
total output current and the current divide ratio - spot shading with
center cell (#5) shaded by 50%. . . . . . . . . . . . . . . . . . . . . .
3-8
78
SPICE simulated output power contour over the space spanned by the
total output current and the current divide ratio - spot shading with
terminal cell (#9) shaded by 50% . . . . . . . . . . . . . . . . . . . .
12
78
3-9
SPICE simulated output power contour over the space spanned by the
total output current and the current divide ratio - combination spot
shading with center cell (#5) and terminal cell (#9) shaded by 50%.
79
3-10 SPICE simulated output power contour over the space spanned by the
total output current and the current divide ratio - linear horizontal
shading with cells (#4, #5, #6) shaded by 50%. . . . . . . . . . . . .
79
3-11 SPICE simulated output power contour over the space spanned by the
total output current and the current divide ratio - horizontal stripe
pattern shading with cells (#2, #3, #7, #8) shaded by 50%. . . . . .
80
3-12 SPICE simulated output power contour over the space spanned by the
total output current and the current divide ratio - cross pattern shading
with cells (#2, #4, #5, #6, #8) shaded by 50%.
. . . . . . . . . . .
80
3-13 SPICE simulated output power contour over the space spanned by the
total output current and the current divide ratio - random shading with
normalized photocurrent magnitudes of (0.96, 0.16, 0.97, 0.96, 0.49,
0.80, 0.14, 0.42, 0.91).
. . . . . . . . . . . . . . . . . . . . . . . . . .
81
3-14 SPICE simulated output power contour over the space spanned by the
total output current and the current divide ratio - random shading with
normalized photocurrent magnitudes of (0.79, 0.96, 0.66, 0.04, 0.85,
0.93, 0.68, 0.76, 0.74).
. . . . . . . . . . . . . . . . . . . . . . . . . .
81
3-15 An example implementation of the output current divider interface
preceding a centralized inverter. . . . . . . . . . . . . . . . . . . . . .
84
3-16 Measured output power contour over the space spanned by the two
string currents - near-uniform-irradiance with short-circuit currents of
(1.72, 1.96, 1.86, 1.80, 1.77).
. . . . . . . . . . . . . . . . . . . . . . .
85
3-17 Measured output power contour over the space spanned by the two
string currents - shading on ladder cells with short-circuit currents of
(1.72, 0.70, 1.86, 0.87, 1.77).
. . . . . . . . . . . . . . . . . . . . . . .
13
86
3-18 Measured output power contour over the space spanned by the two
string currents - shading on top cells with short-circuit currents of (1.26,
0.94, 0.34, 1.93, 1.79).
. . . . . . . . . . . . . . . . . . . . . . . . . .
86
4-1
General architecture of the SC energy buffer. . . . . . . . . . . . . . .
92
4-2
General 1-z architecture of SC energy buffer. (a) Implementation with
ground-referenced switches only for unipolar switching configuration.
(b) Implementation with four additional switches to achieve bipolar
switching configuration.
4-3
. . . . . . . . . . . . . . . . . . . . . . . . .
93
Overall energy utilization of the SC energy buffer as a function of the
capacitor configuration. These numbers are computed for SC energy
buffers with equally sized backbone and supporting capacitors using
the bipolar switching configuration. . . . . . . . . . . . . . . . . . . .
4-4
Sampling points and control variables, vc(i) and
Vd(i),
96
in relation to
the ripple cycle and the control ramps for (a) unipolar switching configuration and (b) bipolar switching configuration. . . . . . . . . . . . .
4-5
Expected ripple magnitude and the supporting capacitor voltages as a
function of power level for the 1-8 unipolar design example. . . . . . .
4-6
105
Proposed two-level SC energy buffer controller block diagram, where
vo denotes the backbone capacitor voltage, vi[n] for i = 1, 2, ...
denotes the sampled supporting capacitor voltage, v, and
Vd
,M
- 1
correspond
to the charge and discharge control signals respectively. . . . . . . . .
4-7
103
108
Steady-state bus voltage waveforms of the 1-9 SC energy buffer with
unipolar switching experiencing increasing power level from 96 W to
480 W with +48 W step size every 50 ms.
4-8
. . . . . . . . . . . . . . . 112
Steady-state bus voltage waveforms of the 1-4 bipolar SC energy buffer
with bipolar switching experiencing decreasing power level from 480 W
to 96 W with -96 W step size every 50 ms.
14
. . . . . . . . . . . . . .
113
4-9 Transient bus voltage response of the example bipolar 1-4 SC energy
buffer in a solar inverter due to 30% input power step. The power
steps from 480 W to 336 W at 50 ms and back to 480 W at 100 ms.
The second supporting capacitor voltage is shown to deviate from its
reference value shortly after 100 ms, but the two-step controller brings
it back to its reference level in less than 2 ripple cycles.
5-1
Previously proposed Z-source circuit breaker:
. . . . . . .
115
(a) crossed Z-source
topology and (b) parallel-connected Z-source topology.
. . . . . . . .
119
5-2
New series-connected Z-source circuit breaker topology. . . . . . . . .
121
5-3
Fault clearing waveforms for the three Z-source circuit breakers. Waveforms for the parallel-connected and series-connected are shifted right
by 10 ps and 20 ps respectively for clarity. . . . . . . . . . . . . . . .
5-4
122
Comparison of the reflected fault current at the source among the three
. . . . . . . . . . . . . . . . . . .
123
5-5
Z-Source breaker ac equivalent circuit models. . . . . . . . . . . . . .
124
5-6
Input-output voltage transfer function of the Z-source circuit breaker
Z-source circuit breaker topologies.
assuming resistive load. Component values are R = 6 0, C = 200 pF,
and L = 2.4 m H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-7
Minimum detectable fault magnitude vs. fault ramp rate with fixed
load to Z-source capacitor ratio of 5 and a load resistance of 6 Q.
5-8
126
. .
135
Two ways of manually tripping the Z-source breaker. (a) inducing an
external artificial fault near the output and (b) inducing an internal
artificial fault within the Z-source breaker. . . . . . . . . . . . . . . .
5-9
141
Fault clearing waveforms using manual tripping methods: (a) external
. . . .
146
5-10 Fault detection sense nodes in a Z-source circuit breaker. . . . . . . .
147
artificial fault current and (b) internal artificial fault current.
5-11 Fault clearing waveforms demonstrating negligible effects from the
current sense inductor on the normal operation of the Z-source breaker. 149
15
5-12 Photograph of the series-connected Z-source breaker experimental prototype. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
150
5-13 Experimental validation of the calculated minimum detectable fault
magnitude and the minimum detectable fault ramp rate. . . . . . . .
153
5-14 Measured fault clearing waveforms (solid blue) of the series-connected
Z-source breaker prototype compared to simulation (dashed red).
.
154
5-15 Measured manually tripped waveforms (solid blue) of the series-connected
Z-source breaker via an internal artificial fault current compared to
simulation (dashed red). . . . . . . . . . . . . . . . . . . . . . . . . .
A-1 The Eagle Cad® schematic of the 3-2 DCR.
156
. . . . . . . . . . . . . .
162
A-2 The Eagle Cad® PCB layout of the 3-2 DCR. . . . . . . . . . . . . .
163
A-3 Top copper of the 3-2 DCR PCB layout. . . . . . . . . . . . . . . . .
164
A-4 Bottom copper of the 3-2 DCR PCB layout. . . . . . . . . . . . . . .
165
B-1 The Altium Designer® schematic of the dDCR current divider power
stage..........
...................................
178
B-2 The Altium Designer® schematic of the dDCR current divider digital
control.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
179
B-3 The Altium Designer® PCB layout of the dDCR current divider. . . .
180
B-4 Top copper of the dDCR current divider. . . . . . . . . . . . . . . . .
181
B-5 Bottom copper of the dDCR current divider. . . . . . . . . . . . . . .
182
B-6 The Cypress PSoC® top-level design of the dDCR current divider control. 184
C-1 The Eagle Cad® schematic of the Z-source breaker power stage.
. .
188
C-2 The Eagle Cad® schematic of the Z-source breaker digital control and
gate drives.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
189
C-3 The Eagle Cad® schematic of the Z-source USB communication interface. 190
C-4 The Eagle Cad® PCB layout of the Z-source breaker. . . . . . . . . .
191
C-5 Top copper of the Z-source breaker PCB layout. . . . . . . . . . . . .
192
C-6 Bottom copper of the Z-source breaker PCB layout. . . . . . . . . . .
193
16
C-7 The Cypress PSoC® top-level design of the Z-source breaker control.
17
195
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18
List of Tables
2.1
SSL PV Cell Charge Multiplier for 3-2 DCR String. . . . . . . ...
43
2.2
SSL Capacitor Charge Multiplier for 3-2 DCR String . . . . . . . . .
43
2.3
FSL Switch Charge Multiplier for 3-2 DCR String . . . . . . . . . . .
45
2.4
Measured Output Power Comparison and Efficiency Summary . . . .
57
5.1
Z-Source Breaker Topology Comparison . . . . . . . . . . . . . . . . .
128
5.2
Detailed Experimental Prototype Components . . . . . . . . . . . . .
152
. . . . . . . . . . . . . . . . . .
166
. . . . . . . . . .
183
C.1 Z-source Breaker Prototype Bill of Materials . . . . . . . . . . . . . .
194
A. 1 3-2 DCR Prototype Bill of Materials
B. 1 dDCR Current Divider Prototype Bill of Materials
19
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20
Chapter
1
Introduction
Solar photovoltaic power generation is a promising clean and renewable energy technology that can draw upon the planet's most abundant power source - the sun. However,
relatively high costs of ownership has presented a barrier to adoption and limited the
grid penetration of solar power. To counter these problems, the U.S. Department
of Energy has started numerous programs and initiatives, aiming to reduce the cost
of photovoltaic systems by 75% in 2020, and ultimately push solar energy towards
grid parity [1]. The U.S. government has also promoted the use of solar energy by
providing subsidies, tax breaks, and feed-in tariff to help partially defray the steep
upfront costs.
One key metric for comparing the cost of different energy resources is the levelized
cost of energy (LCOE) [2]. This is the ratio of the total cost of ownership to the total
energy extracted from the generation system over its entire lifetime. The total cost of
ownership consists of not only the upfront equipment and installation costs, but also
LCOE = Total Cost of Ownership
Total Energy Extracted
'
the ongoing costs to keep the system up and running.
From the formulation of the LCOE, there are essentially two ways to reduce the
cost of solar energy. One objective would be to maximize the denominator term by
21
PV5
VOC
Maximum Power Point
VIV
PV4
PV2
mp sc
ILOA
Solar Cell
----- @
Q******A
** *
I
A
*
PV
IR
*SI
V
PV1
Id
V
Figure 1-1: Typical solar cell and panel configuration and the corresponding singlediode model.
ensuring the system produces as much useful energy as possible.
Simultaneously,
another objective should be to minimize the numerator term by reducing the cost of
power electronics and the associated cost of maintenance and repair. This dissertation
proposes and examines several circuit-based techniques, power conversion and system
protection architectures, to meet these two overarching system objectives.
1.1
Mismatch and Energy Loss
Solar cells are typically configured in series within a PV panel because stacking the
cells and the panels together conveniently creates a high voltage necessary to interface
with a grid-tie inverter. However, this configuration creates a "weakest-link" problem.
At the cell-level, a shaded cell can limit the power output of all the cells within a
panel. To understand the root cause of this problem, a simplified single-diode solar
cell mode is shown in Fig. 1-1. It consists of a photocurrent source in parallel with a
diode, and together they create the I-V characteristics shown on the right of Fig. 1-1.
In order to maximize power extraction, each solar must operate at its respective
22
maximum power point, where the IV product is maximized. However, the series
configuration forces the constraint of having the same current through each and every
solar cell, which means not all the cells can operate at their respective maximum
power point if there is a mismatch in irradiance. Therefore, the energy loss is not
proportional to the number of shaded cells - it is possible for a panel to lose a major
portion of its power generation capability even if only a few cells are shaded within
the panel.
This "weakest-link" problem extends to the sub-module and module-level as well.
For example, a 10% shading can lead to a 50% decline in total output power for a
photovoltaic system. At these levels, bypass diodes can be incorporated to provide an
alternative path for the current to flow around the under-performing cell. However,
this approach forfeits any potential power generation from the under-performing
cells and results in a non-convex power characteristic curve, which complicates the
required maximum power point tracking (MPPT) algorithm. With multiple local
maximums, it is much more difficult to find the global maximum power point. Thus,
shading represents a significant and ongoing barrier to extracting the entire value of
the photovoltaic installation investment.
There have been a lot of research activities focused on maximum power point
tracking, and there are essentially three hardware arrangements - cascaded dc-dc
converters, micro-inverters, and the recently proposed differential power processing
techniques [3-10]. The conceptual diagrams for these approaches are outlined in
Fig. 1-2. The cascaded dc-dc approach places a power electronics converter at the
output of each solar module, or sub-module, which adds an extra degree of freedom to
operate each element at its respective maximum power point. These converters can be
switched-inductor or switched-capacitor types. The micro-inverter approach decouples
each module from each other, and optimizes the power output of each module directly
onto the ac grid.
Differential power processing (DPP) is a key concept to further improve energy
efficiency by minimizing the amount of power conversion. By only processing the
mismatch power, and not the common-mode generated power, the DPP converters can
23
PV
PV DC/DC
Converter
DC/AC
Inverter
PV
DC/DC
Converter
Pv
DC/AC
Inverter
DC/AC
Inverter
R
Pv
Inverter
DC
Inverter
DPP
PV
DC/DC
Converter
DPP
PV
DCtDC
Converter
Pv
DPP
PV
DC/AC
Inverter
(a) Cascaded DC-DC
(b) Micro-Inverter
(c) DPP
Figure 1-2: Previously proposed power processing architectures for maximum power
point tracking.
greatly reduce insertion loss and increase the overall power conversion efficiency. If
everything is balanced in a PV string, the DPP converters can simply turn off without
processing any power, resulting in zero loss. Two embodiments using inductors for
current steering are illustrated in Fig. 1-3.
Since all three available converter types require some form of energy storage
components, i.e., inductors and capacitors, scaling the existing solutions to smaller
parts of the solar array for finer optimization granularity has been cost-prohibitive.
Indeed, it is quite difficult to imagine placing an inductor or a bank of capacitors on a
per-cell basis. Nevertheless, there are significant benefits to be gained in scaling MPPT
to the cell-level. A statistical study showed that the energy extraction improvement
can be as high as 30% with MPPT at the cell-level compared to 16% at the modulelevel [11]. In addition, solving the problem at the module level does not adequately
address some of the reliability concerns covered in the following section.
1.2
Hot Spots and Reliability Concerns
Solar panels typically have relatively long lifetimes, and many come with warranties
of at least 25 years [12]. However, partial shading creates reliability concerns that
24
PV
Pv
L
PL
PV
L
C-
L
PV
CAPV
InverterInverter
L
L
PV
L
PV
L
DC/AC
(b) PV-to-String
(a) PV-to-PV
Figure 1-3: Example embodiments of existing differential power processing converters.
may shorten the useful lifetime of solar panels. Fig. 1-4 shows an infrared image of
hot spots forming inside a solar panel and the associated circuit model. When the
output current is limited, the un-shaded cells can collectively drop a large voltage
across the shaded cell in the reverse direction. This can force the shaded cell into
the reverse breakdown region of operation, which means that the diode of the shaded
cell will conduct current in the reverse direction. Therefore, instead of producing
energy, the shaded cell now actually consumes energy. This power dissipation results
in local overheating, which can lead to destructive effects such as accelerated panel
degradation and potentially irreversible panel damage. In certain cases, it can also
cause the risk of fire danger if the power dissipation is excessive.
Another limiting factor of a photovoltaic system comes from the power electronic
used to convert and manage energy generation from the photovoltaic arrays. These
power electronics include dc-dc converters for power optimization as well as dc-ac
converters for interfacing with the grid. It was found in practice that the power
electronics in general have a much lower mean time to failure (MTTF) compared
to the PV panels. In a study conducted in 2012, PV inverters actually had to be
25
PVN-1
PV2
PvI
(a) Infrared Image
(b) Circuit Model
Figure 1-4: Solar cell hot spot.
replaced every five years on average [13]. Thus, even though inverters only accounted
for 10-20% of the initial upfront cost, their contribution to the total cost of ownership
can be quite significant.
1.3
Thesis Contributions
Existing power processing techniques for solar power optimization often have to make
tradeoffs among conversion efficiency, optimization granularity, and overall system
cost. New power processing architectures are necessary to enable high performance
and cost competitive solar energy.
In Chapter 2, the feasibility of using the solar cell's intrinsic capacitance to perform
power balancing, rather than relying on externally added energy components, is
evaluated. Analytical expressions for the solar cell's diffusion capacitance is presented
along with experimental measurement of a commercially available mono-crystalline
solar cell. A new, fully-scalable, power balancing technique, termed diffusion charge
redistribution, is proposed, and detailed analysis of the insertion loss for adopting
such a structure is presented.
The concept of differential power processing will be incorporated into the proposed
26
cell-level power balancing technique in Chapter 3 by rethinking the string-level power
electronics architecture. In contrast to the existing DPP architectures, the MPPT
functional block will be decoupled from the DPP functional block. We will show that
the new power optimization aims to not only maximize energy extraction from each
solar cell but also minimize the amount of processed power. The convexity of the
multi-variable optimization space is evaluated to understand the requirement on the
optimization algorithm.
In Chapter 4, the reliability and failure modes of a PV inverter is analyzed. A
switched-capacitor (SC) energy buffer is proposed to replace the failure-prone electrolytic dc-link capacitor. The SC energy buffer will be shown to achieve significantly
higher capacitor energy utilization, resulting in smaller required capacitor volume and
enabling the use of film or ceramic capacitors. Tradeoffs regarding capacitor configuration, switching topology, and control complexity will be presented. A new two-step
control algorithm capable of handling power transients is outlined and demonstrated
in simulation.
Finally, as dc power system architectures continue to attract interest as a means
for achieving high overall efficiency and facilitating integration of renewable and
distributed energy sources such as a photovoltaic system, appropriate and robust fault
protection methods are required. In Chapter 5, analysis and design methodology of a
new arc-less dc breaker topology, analogous in some respects to an ac thermal-magnetic
breaker, will be discussed.
27
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28
Chapter 2
Solar Cell-Level Maximum Power
Point Tracking
Photovoltaic (PV) power modules are traditionally configured as a string of solar
cells [14]. In this series-connected configuration, the overall string current is limited
by the available current of the lowest-performing solar cell in the string. Therefore,
external operating conditions such as partial shading and dirt accumulation can
severely limit the available power from the string, even if only a few cells are affected
out of a large string [3,5-10,15]. Bypass diodes in parallel with sub-strings can mitigate
this problem. This approach enables the higher-performing cells to output higher
currents, bypassing lower-performing sub-strings altogether, potentially extracting
more power from the string.
However, any possible power generation from the
lower performing cells is completely forgone and additional losses are also incurred
from the bypass diodes. Furthermore, this results in an output power characteristic
curve that is non-convex, which complicates maximum power point tracking (MPPT)
algorithms [6,8].
29
2.1
Motivations for Modular Optimization
Modular architectures such as cascaded dc-dc converters with a central inverter, microinverters, and their sub-module variants, have been proposed to allow local MPPT
through distributed control [3,4]. However, their operation requires the processing
of the full power from each PV element, which is a major disadvantage in terms of
insertion loss. In addition, it is impractical to scale these approaches down to the
cell-level, as per-cell inductors and capacitor banks may be required.
Recently, there has been a push towards differential power processing to balance
mismatches in a PV string [5-10]. By only processing the mismatch power instead of the
full power, significant reduction in power loss due to conversion efficiency and in power
electronics size can be achieved, and many different architectures based on this principle
have been proposed [5-10]. Most of these approaches also rely on the availability of
external energy storage elements. For example, the sub-module integrated converter
in [5] employs flyback converters, which require a discrete transformer per PV element
as energy storage. In the PV-to-PV differential architecture proposed in [8,9], buckboost converters with external inductors are used between adjacent PV elements.
Lastly, discrete capacitors are needed in parallel with each PV sub-module and
in between adjacent PV sub-modules in the resonant switched-capacitor converter
proposed in [6,7].
This chapter explores power optimization at the cell-level, while finding ways for
eliminating the requirement of external passive components for intermediate energy
storage. The proposed technique makes use of the intrinsic diffusion capacitance of
the solar cells as the main energy storage element, at the cost of processing part
of the common-mode generated power. This technique is termed diffusion charge
redistribution (DCR). Theoretical background for quantifying the solar cell diffusion
capacitance is presented along with experimental solar cell characterization results
in Section 2.2. Analytical derivations of the insertion loss from adopting a ladder
DCR string structures are detailed in Section 2.3. Circuit level implementation of the
experimental prototype is detailed in Section 2.4, and the experimental measurement
30
Solar Cell
~AAA
*
I
++
()
*
9
S1
Vd
__
Figure 2-1: Commonly used single diode solar cell model.
of the proposed ladder DCR string is presented in Section 2.5.
2.2
Photovoltaic Cell Diffusion Capacitance
The commonly used single-diode equivalent circuit model of photovoltaic cells proposed
in previous studies is shown in Fig. 2-1 [16-18]. The I-V characteristic of the equivalent
solar cell model can be expressed as
Isolar = ISc -
Id -
Vd
(2.1)
However, the model in Fig. 2-1 does not completely capture the dynamics of a solar
cell. There is a significant amount of diode capacitance associated with the cell,
which is often ignored as a parasitic element when MPPT at a dc operating point is
considered. The complete equivalent circuit model with a shunt diode capacitance is
illustrated in Fig. 2a.
The capacitance of a photovoltaic device is equal to the sum of the diffusion and
the depletion layer capacitance. Since the intended operating solar cell voltage is near
the maximum power voltage (Vmp), the diffusion capacitance effect dominates and
the depletion layer capacitance can be neglected [19]. Diffusion capacitance is the
capacitance due to the gradient in charge density inside the cells, and is known to
have an exponential dependence on the solar cell voltage, or a linear dependence on
the solar cell diode current [19-22]. Specifically, the diffusion capacitance Cd can be
31
expressed as
Cd =
F .
VT
.Io-ex p
Vd
77- VT
VT
(I + Id) = C +F - Id
VT
(2.2)
In (2.2), Vd is the solar cell diode voltage, Id is the solar cell diode current, VT is
the thermal voltage, and 77 is the diode factor. The current Io is the dark saturation
current of the cell due to diffusion of the minority carriers in the junction, and Co is
the dark diffusion capacitance. The time constant
TF
=T~
where T is the minority carrier lifetime and
TF
can be defined as
+ TB'1
TB
(2.3)
is the transit time of the carrier across
the diode. If the solar cell base thickness is greater than the minority carrier diffusion
length,
TF
can simply be approximated as T. In general, solar cells made from materials
with longer minority carrier lifetimes are more efficient because the light-generated
minority carriers persist for a longer time before recombining [23].
2.2.1
Solar Cell Diffusion Capacitance Characterization
Previous works have revealed that solar cells can exhibit diffusion capacitance in
the range of microfarads to hundreds of microfarads near the maximum power point
voltage [19,20]. Compared to, for example, the energy storage capacitance of seven
1 pF capacitors used in the resonant switched-capacitor converter in [6], the solar cell
itself possesses a sufficient amount of capacitance and offers a great opportunity to
drastically limit the number of external passive components. External energy storage
capacitors are required in the case of the resonant switched-capacitor converter in [6]
because power balancing is applied at the sub-module string level, and the effective
capacitance of a sub-module string may not be adequate as it is a series combination
of a large number of diffusion capacitors.
Published measurements of cell diffusion capacitance are typically performed by
applying a bias voltage across the solar cells, which may not accurately represent
32
Solar Cell
+
R,
I
Id
* Isc
9I
C
RVi.
Cd
Figure 2-2: Solar cell capacitance characterization switching circuit.
Solar Cell Diffusion Capacitance Measurement
400
350
---I ---
-
-
E
300
:S(02
-
-------------------------- --
250
200
S
------
-i 150
---
I
I
=
Cd
-- - -- - - - - -----
--
- --
- - -- - - -
- - -J-- --- - --- - ---
-- -----
- - -- -----
--
- -
-
0
Wu
0
100
50
-
-----
---
-
g-+C--
--
----------
--
----
f%
0
5
10
15
20
Time (is)
25
30
35
40
Figure 2-3: Solar cell capacitance characterization switching waveform.
33
Diffusion Capacitance vs. Diode Current
7.5
L
0
7-
6.5
00
V
C
0
c
Cu
6-
0
0
00
-
5.5
5-
4.5
0
0
'
0.05
4.64(gF) + 9 .0 6 (gF/A)*Id
Cd
'
0.1
1
0.15
I
0.2
r
0.25
0.3
Diode Current (A)
Figure 2-4: Solar cell capacitance versus diode current.
the effect of diffusion capacitance in the context of a switched-capacitor converter.
Therefore, the switching circuit shown in Fig. 2-2 is used here to characterize a
commercially available mono-crystalline solar cell (P-Maxx-2500mA) as an example.
The cell measures 15.6 cm x 6 cm, and has an open-circuit voltage of 0.55 V and
a short-circuit current of 2.5 A under maximum lighting conditions. The solar cell
capacitance is measured ratiometrically by comparing the charging slopes during the
two different phases of operation. The measurement was performed with a switching
frequency of 50 kHz and repeated over a set of known external capacitances between
10 to 30 pLF. The corresponding waveforms and the slopes are illustrated in Fig. 2-3,
and the measured capacitance showing a linear relationship to the solar cell diode
current is shown in Fig. 2-4.
The measured solar cell has a worst-case, i.e., dark, capacitance of 4.64 AF,
which matches very well with the measurement result for mono-crystalline solar cells
presented in [24]. This minimum capacitance is sufficient for DCR power balancing.
34
The relationship between the available capacitance and power conversion loss will be
discussed and quantified in Section 2.3. Note that the solar cell diode current is roughly
equal to the difference between the short-circuit current and the extracted current.
With the typical maximum power current (Imp) being approximately 80 - 95% of the
short-circuit current [3,5], the diode current is 5 - 20% of the short-circuit current
at maximum power point, assuming negligible current through the shunt resistance.
Hence, the effective diffusion capacitance for this example cell during normal operation
can be as high as 6 to 9 pF.
2.2.2
Single-Capacitor Diffusion Charge Redistribution
To demonstrate the utility of the solar cell diffusion capacitance as an energy handling
component in a power converter, an initial DCR prototype was constructed with a
single capacitor. Results from this experiment lead to a DCR architecture with no
external capacitors. The block diagram of this first experimental setup is illustrated
in Fig. 2-5. The prototype consisted of three mono-crystalline solar cells, six IRF9910
MOSFET switches, and a single flying capacitor.
The "flying" capacitor is connected to each cell sequentially to transfer the imbalance of power across the cells. Since there is no capacitor in parallel with the solar
cells to serve as intermediate energy storage when the flying capacitor is disconnected
from a cell, the solar cells must therefore rely on their own diffusion capacitance to
buffer the difference between their respective generated power and extracted power.
By having a single external energy storage element, it can be shown that differential
power processing is preserved, and that insertion loss is insignificant. That is, if
the cells are well-matched and experience the same irradiance, the cell voltages at
maximum power should be identical, resulting in nearly zero net current flow into the
flying capacitor, and therefore zero loss.
To evaluate the efficacy of using the diffusion capacitances for power balancing,
a partial shading condition was imposed by covering half of the top cell. In the
experiment, the flying capacitor is switched at approximately 300 kHz with a 33%
duty cycle for each phase. The output current is swept linearly on an HP 6063B
35
Single-CapacitorDCR
SolarCell
-IIs
R
-U-
I
*
*
*
*
6
6
I
I
-I-..
:
isc
T
C
S
I
a
-'IC'
SI
*
:
*
*
*
*
*
*
SolarCell
Isc
I
-I-.
R,
C
Rp
*
I
*
S
-1-s
ii
92
9~
*
*
*
T
I..
*
*
93
0.......................J
I
I
I
92
I
R,p
I
I
I
S
I
6
I
6
I
I
91
-I-.N*
R,.I
me
a
*
*
I
I
*
I
*
*
Solar Cell
-a-
91
*
ZK
T
*
I
S
Constant
1 'LI I
Current
I
S Electronic
K
Load
I
I
I
I
I
6
I
S
S
I
I
6
S
6
S
5
I
I
I
Figure 2-5: Single-capacitor diffusion charge redistribution experimental setup.
36
3-Cell Series Solar String Available Power under Partial Shading
0.4
-----
Series String 0n~v
0.35 _ ----- With Bypass Diode
-With
--L----I
1-------
Single-Capacitor DCR
0.30.25I
C0
--
-
-010-------L
- - ------
0.2-
0
0.15-
-
0.1
~-
-
-
---
0.050
0
- ---
0.05
0.1
0.15
--
-
-
-----
---- --
0.2
0.25
0.3
Output Current (A)
- --
0.35
0.4
0.45
Figure 2-6: Measured output power versus output current with and without singlecapacitor diffusion charge redistribution.
dc electronic load at 1 A/s and the output voltage and current are measured and
recorded. The output power versus output current curve for a series string, a series
string with bypass diodes, and a series string with single-capacitor diffusion charge
redistribution are shown in Fig. 2-6.
Under partial shading condition, the series string current is limited by the weakest
link, and therefore the extracted power is reduced dramatically. With bypass diode in
place, the system can extract additional power from the unshaded cells while bypassing
the shaded one; the resulting non-convex output power to current characteristic curve
is also illustrated in Fig. 2-6. Finally, the diffusion capacitances are shown to be very
effective in power balancing, extracting significantly more power compared to the
series string and the bypassed cases. In addition, a convex output power to current
profile is retained, allowing easy integration with existing MPPT-equipped string
inverters.
37
2.3
Capacitor-less Diffusion Charge
Redistribution
It is possible to extend the diffusion charge redistribution scheme to be completely
capacitor-less by replacing the flying capacitor with a solar cell and its diffusion
capacitance. This enables maximum power point tracking with cell-level granularity
without needing any external passive components for energy storage, which translates
to the maximum achievable tracking efficiency at the minimum possible cost for power
processing. It has been estimated that cell-level maximum-power-point tracking could
improve the energy captured in shaded conditions by as high as 30%, a substantial
improvement from the estimated 16% with only module-level granularity [11].
The proposed, fully scalable, cell-level power balancing architecture using diffusion
charge redistribution is illustrated in Fig. 2-7. In the proposed topology, a single
series string is split into two strings: a load-connected string of N cells in parallel
with a switched ladder-connected string of N - 1 cells used for charge balancing. The
load-connected cells are assigned odd designators while the ladder-connected cells are
assigned even designators. This approach allows the construction of large series-strings
to meet the interfacing voltage requirement of a grid-connected inverter, while making
the cells appear in pseudo-parallel to mitigate power loss due to mismatch conditions
in real-world applications. The switched configuration is able to convert a series-string
into an effective single "super-cell".
The reduction in external energy storage does not come without cost - the implicit
tradeoff of eliminating all external storage is having to process part of the string power,
specifically the power generated from the ladder-connected string. In the following
section, the power conversion efficiency of such a structure is carefully considered
and compared to the traditional series string. The additional power conversion loss
incurred from this structure compared to a series string under perfectly matching
condition will be characterized as an insertion loss.
The switched-capacitor analysis presented in [25] can be generalized to distributed
38
.
Ladder-Connected
Difusion Charge Redistribution
PVI
PV2
I.t
PV3
:92:92
PV4
VOWt
S91
Current
Source
SLoad
e
15
PVN-S0
F
PVs-Figueropsedfuly-salale
27:
92
:
ldde-coneced
39
CR
rchtecure
power generation for calculating the insertion loss of adopting diffusion charge redistribution. The switched-capacitor conversion loss can be characterized by two asymptotic
limits: the slow- and fast-switching limits. In the slow-switching limit (SSL), the
output impedance of the switching converter is calculated assuming all switches and
interconnects are ideal, and the capacitors experience impulses of current. In the
fast-switching limit (FSL), the capacitor voltages are assumed to be constant, and the
switch and interconnect resistances dominate the losses. After deriving both the SSL
and FSL losses, the total switched-capacitor loss can be computed as a combination
of the slow-switching and fast-switching limit losses.
2.3.1
Slow-Switching Limit Power Conversion Loss
For illustration, the SSL insertion loss calculation is performed on a 3-2 example string,
where N is equal to 3 following the convention shown in Fig. 2-7. The charge flow
diagram of the 3-2 example string in the two phases are illustrated in Fig. 2-8. The
charge flow is designated as qx, where x describes the element, i represents the index
number, and <p denotes the phase. For example, qQv 2 corresponds to the total charge
extracted from the second photovoltaic element during phase 1. For the insertion
loss calculation, it is assumed that the solar cells are perfectly matched and each
cell contains a constant photo-current source generating a total charge of
qph
over a
complete switching period. For a photo-current source in this two-phase converter,
1
2
=
=~
(2.4)
~ p/
The output is represented by a constant current load drawing a total charge of qt
over a complete switching period. That is, qt
is the sum of the output charges
delivered during phase 1 and phase 2, and therefore
qut= o=
40
qut/2
(2.5)
qsw,3
1
ph
9p1
cs
{sw,2
I,
pim
pm, 3
s
q
(b)3
igur Chrefo
2-8
3-2p
Rsrn
n
rpsdcl-lvlpwrbaacnwrhtetr
ofgrto.()pae1()pae2
snt
IadrD
41
By using capacitor charge balance in steady state, we can write
q
for i = [1, 2, ...
, 5].
= q2Vi = qph
(2.6)
By Kirchhoff's current law (KCL), we can further write (2.7a)
and (2.7b) for the two phases.
q ,, 1 + qv,2
,2, =
%v,, 2
=
qv, 3 + q,
+q
,,
v, 3 =
4
= %v,=
4
+ q,
5
2
(2.7a)
= qOt/2
(2.7b)
qout/
Solving this system of equations (2.6), (2.7a) and (2.7b) iteratively yields the relationship between the photo-current from each cell and the string output current, as
shown in (2.8).
5
3
qout = 5 - qph
(2.8)
Each charge flow can then be expressed in terms of the output charge over a
complete switching period. Following the convention in [25], the normalized charge
flow, or the charge multiplier will be defined as:
(2.9)
a",i =
The SSL charge multiplier of each photovoltaic cell in the 3-2 DCR string during
the two phases is summarized in Table 2.1. The net charge flowing into any diffusion
capacitance over a complete switching cycle in steady state will be zero. Each capacitor
in Fig. 2-8 will experience an equal but opposite charge delivery during the two phases.
The magnitude of the charge flows for the capacitors can therefore be expressed as the
difference between the charge extracted from the solar cell, and the charge generated
by the photo-current source within the cell during either phase.
ac,j =
|qc |
'~u =~
42
q/v,2i
-(.ph/1
(2.10)
Table 2.1: SSL PV Cell Charge Multiplier for 3-2 DCR String
Phase
p
SSL PV Charge Multiplier
1,1 a,2
a, 3
a/1,4
a5
4/10
1
1/10
3/10
2/10
5/10
2
5/10 12/101 3/10
4/10
1/10
Table 2.2: SSL Capacitor Charge Multiplier for 3-2 DCR String
SSL Capacitor Charge Multiplier
ac,
ac,2
ac,3
ac,4
ac,5
2/10
1/10
0
1/10
2/10
Equation (2.10) can be used to determine the SSL charge multipliers of the capacitors,
which are summarized in Table 2.2.
The capacitor charge multiplier vector can be generalized to a DCR string with
2N - 1 cells, where there are N cells in the load-connected string and N - 1 cells in
the ladder-connected string. In the general case, the output current to photo-current
ratio and the capacitor charge multiplier expressions are shown in (2.11) and (2.12)
respectively.
qaut =
ac =
'
2N - 1
N -
|qc~
_|
-
(2.11)
qph
|N - i
2
- 2
(2.12)
4N
The SSL output impedance [25] of the DCR string can then be written as
RS
2N-1
(ac, ) 2
_
CS - fw
=
1
N - (N - 1)
12
1
2N - 1
Cd - fsw
In order to calculate insertion loss, the ratio of the SSL output impedance to the
load resistance must be calculated. This can be found as an expression in terms of
the performance of each cell in steady state, operating at its maximum power point
with voltage Vmp and current Imp. Using (2.11), which effectively relates cell current
43
to output current, and the fact that the DCR string voltage equals N times the cell
voltage as shown in Fig. 2-7, the load resistance is
RL
Vout
=
V
Iout
N - Vmp
2N
p
N
'Imp
2
Nr2
V.
M-
2N - 1
Imp
N
(2.14)
The insertion loss fraction, ILSSL can be calculated as the ratio of the SSL output
impedance of the DCR string to the load resistance,
ILSSL
RSSL
RL
1 N-1
1
N(2.15)
12
N
fsw
1
1
Vmp
Imp
Cd
and the SSL efficiency of the array can be defined as one minus the SSL insertion
loss. Equation (2.15) represents a fundamental result that is dependent on technology
and material choices. It states that the SSL efficiency of a solar array configured as
a DCR string is effectively dictated by the ratio of the maximum power current to
the diffusion capacitance, for large N. For illustration, assume the following rounded
numbers for our solar cells under maximum illumination: a maximum power voltage
of 0.5 V, a maximum power current of 2 A, and a diffusion capacitance of 9 AF. For
a DCR string with N of 20 and a switching frequency of 1 MHz, the insertion loss is
calculated to be 3.5%.
The SSL insertion loss is not the only loss mechanism. It is possible for the DCR
string to operate near the SSL-FSL transition where the loss contributions are approximately equal, or deep in FSL where the FSL losses dominate. Hence, to complete the
system-level insertion loss characterization, the string output characteristics in the
fast-switching limit is considered in the next section.
2.3.2
Fast-Switching Limit Power Conversion Loss
In the fast-switching limit (FSL), the capacitor voltages are assumed to be constant
during a switching period. In addition, the duty cycle becomes an important consideration [25]. For the following analysis, a 50% duty cycle is assumed for simplicity. The
output impedance will again be derived in the context of the 3-2 DCR example string
44
Table 2.3: FSL Switch Charge Multiplier for 3-2 DCR String
FSL Switch Charge Multiplier
asw,
asw,2
asw,3
asw,4
asw,5
asw,6
4/10
2/10
2/10
2/10
2/10
4/10
for illustration, then generalized to a DCR string of arbitrary size.
From Fig. 2-8, the charge flowing through the switches can be written using the
PV cell charge multipliers as shown in (2.16).
,
-
asw,=
I %vi-avi2
a,
i odd
,
_2
e
(2.16)
even
,2
1
and a22 ,2Nare assumed to be zero. The resulting FSL
where boundary cases, i.e., atVO
charge multiplier vector for the 3-2 DCR string is summarized in Table 2.3. For a
DCR string with 2N - 1 total cells, the FSL switch charge multiplier vector can be
derived as
(N - 1)/(2N - 1)
,
i = 1, 2N
1/(2N - 1)
, otherwise
Hence, the FSL output impedance of an arbitrarily sized DCR string is
2N-1
Z
RFSL= 2 .
Reff - (asw,i
i=1
2
4
N (N
2-~~(2N -
1)
1)2
Re
~f(.8
(2.18)
where Reff is the effective resistance of the switch on-resistance in series with any
interconnect resistance. Relating the FSL output impedance back to the load resistance,
the FSL percentage insertion loss can be calculated as
ILFSL
RFSL
=
RL
-
4
2N -1
N -1
N
Imp Re
Vmp
f
(2.19)
The result in (2.19) makes intuitive sense because the loss from the fast-switching
limit is expected to be inversely proportional to the number of cells behaving like
current sources. The dissipated power in the switches is approximately constant for
45
sufficiently large N, while the total generated power increases linearly with N. Note
that the factor of 4 in (2.19) can be derived by using the fact that the power extracted
from the ladder-connected string must pass through two switching devices. In addition,
the current through the switches resemble a square wave, which gives an additional
factor of two in power.
From (2.19), it can be seen that the FSL insertion loss, or conduction loss, can
almost always be made negligible for a sufficiently large string. For example, for a
DCR string with N of 20, maximum power current of 2 A, maximum power voltage
of 0.5 V, and an effective switch on-resistance of 15 mQ, the FSL insertion loss is only
0.58%.
The total insertion loss can be calculated by combining the SSL and FSL losses.
A conservative approximation for combining the loss components, the root of the
quadratic sum of the two loss components, will be used for the remainder of this
paper [26]. That is,
I LTOT
2.3.3
V (ILSSL ) 2 + (ILFSL
(2
Recovered Power Loss from Process Variation
The DCR power processing approach also effectively corrects for process variation
between cells, which normally would limit power extraction from a string of cells. DCR,
therefore, can improve power extraction from an array of mismatched cells in comparison to other approaches for processing power. Alternatively, DCR can be viewed
as easing the manufacturing problem of assembling a solar array by accommodating
greater cell variation while maximizing power extraction.
Process variation in photovoltaic manufacturing typically refers to the I-V mismatch
between the solar cells. For a series string of solar cells, I-V mismatch can negatively
impact the overall tracking efficiency because the cells may not operate at their
individual maximum power points. Instead, they operate at a collective maximum
power current for all the cells present in the series string.
In order to improve the cell-level tracking efficiency by reducing cell-to-cell variation,
solar panel manufacturers have invested heavily in improving their manufacturing
46
process as well as evaluating different cell binning algorithms [27,28]. In the past ten
years, the manufacturers have been able to refine their production process and reduce
the power tolerance from +10% down to +3% [29]. Nevertheless, the I-V mismatch
can still have higher tolerance when cells are sorted by maximum power.
The subsequent analysis follows [15] in using a first-order approximation for cell
output power under deviation from the maximum power point operation. Assuming
approximately constant voltage near the maximum power point, the output power
(Pcei) can be assumed to be step-wise linear when the cell output current (Ice) is
slightly perturbed around the maximum power current:
Icell
(1
=
Pce = (1
-
(2.21)
5) -Imp
-
|61)
(2.22)
Pmp
To understand the effect of variation on a string, let
6
J
be a random variable which
describes the deviation of the current at the collective maximum power of the string
to the current of cell i at its maximum power operation. That is, the total power from
a series string can be written as
Pstring = E(1
-
(2.23)
|6jI) - Pmp
i
Then the expected power from a series string of N cells can be expressed as
E[Ptring] = N
- Pmp - (1 - E [161])
(2.24)
Using (2.24), the power loss due to process variation can be approximated as
the deviation from the maximum available string power N - Pmp. This represents a
conservative estimate; the actual power loss can be higher because the magnitude of
dP/dI can be much higher when I > Imp. For a more detailed treatment, a Monte
Carlo analysis of the expected power with cell-to-cell variation can be found in [15].
Assuming a uniform distribution of Si with a range of
47
5%, the loss in tracking
efficiency in a series string due to process variation is approximately 2.5%. Since
the DCR string is able to mitigate even larger partial shading mismatches, it will
be practically indifferent to the asymmetry from process variation. Hence, the loss
in tracking efficiency from cell-to-cell variation, illustrated by E[|IJ] in (2.24), can
be naturally recovered. A correction factor is introduced in the overall insertion loss
calculation, and the complete insertion loss from using a DCR string can then be
approximated as
ILDCR
(ILSSL ) 2 + (ILFSL ) 2 -
E[|I|]
(2.25)
Potentially one of the greatest value in performing cell-level MPPT with diffusion
charge redistribution lies in the fact that the string output power becomes independent
of cell-to-cell process variation. Therefore, it is possible to relax the extensive and
stringent binning process currently employed in manufacturing. It may also greatly
simplify the manufacturing and assembly processes.
2.4
Circuit Implementation
A DCR string experimental prototypes was constructed to further validate the proposed
concept. To ensure fair comparison across different configurations, the prototype
was designed to be reconfigurable between a series string, a series string with bypass
diodes, and the proposed DCR arrangements so that all measurements would be
performed using the same set of solar cells. The schematic representation of the DCR
prototype is outlined in Fig. 2-9, and the printed circuit board (PCB) implementation
is illustrated in Fig. 2-10.
The experimental prototype consisted of five P-Maxx-2500mA mono-crystalline
solar cells, six IRF9910 MOSFET switches, three MAX17600 gate-drives, and five
optional LSM115J Schottky diodes. While discrete switches, gate drives, and an
external power supply are used in this proof-of-concept prototype, all the DCR
enabling circuits can be integrated onto a single chip for real-life applications. A
discussion on the required circuit subsystems for an IC implementation is elaborated
below.
48
To E-Load(+
es
e
S*
*
..
Integrated
On-Chip
t..0..
*662
Pv 1
GD
Fro
Diia
ToSLa
Figure~~~~~
~
2-:Shmtcoute32D
Rldercnetreprietlpooye
49
lc
Figure 2-10: Diagram 3-2 DCR ladder converter experimental prototype.
As shown in Fig. 2-9, the MOSFET switches and the gate-drives are the first
targets for integration. Previously proposed ladder converter gate-drive circuits such
as the one shown in [6] can be readily adopted. Furthermore, because the chip only
processes small solar cell voltages, it is not necessary to fabricate using expensive
high-voltage process nodes. Instead, relatively inexpensive and mature technology
nodes such as the 0.35-pm CMOS and the 0.5-pm CMOS processes can be used. To
self-power the circuit from the solar cells, the IC must also include a local power
management unit consisting of an on-chip switched-capacitor dc-dc converter and a
low-dropout (LDO) regulator. Finally, digital blocks for synchronization need to be
included to control switching in all the ICs.
The number of MOSFETs and complementary gate drives to integrate onto a single
chip is determined by trading off IC fabrication cost, supply voltage requirement, ease
of integration, and integration cost. In particular, if the minimum two MOSFETS and
one complementary gate drive are integrated, one IC would be required for every two
solar cells. While the IC would only need to make contacts to two solar cells, which
keeps the integration cost at a minimum, it would have to power up from a small
50
forward voltage of a single diode. Alternatively, if more than one pair of MOSFETs
and complementary gate drives are integrated, the IC can balance multiple pairs of
solar cells, and also access a higher input voltage with a shared power management
circuit. This leads to fewer ICs per panel and can potentially reduce the overall
incremental cost per watt. However, the IC would have to make direct contacts to
more solar cells, which complicates wiring and increases integration costs. These
tradeoffs will ultimately dictate the level of integration as the photovoltaic market is
highly cost-driven.
2.5
Experimental Results
The circuit shown in Fig. 2-10 was characterized in the laboratory with a power supply,
an HP 6063B dc electronic load, and a Tektronix TDS5034B oscilloscope to collect
current and voltage data. Specifically, the characteristic output power versus output
current curve is obtained by recording both the string output voltage and the output
current as the electronic load sweeps the output current from 0 - 10 A at a slew rate
of 2 A/s. As the electronic load demands more current than the series string can
supply, the current saturates at the short-circuit current of the string, as illustrated in
Fig. 2-11. Furthermore, the effect of process variation can be observed in the voltage
waveform. That is, if the short-circuit current of the individual cells are perfectly
matched, the string is expected to have a zero output voltage at the short-circuit
current. However, if there is mismatch between the cells, cells with higher short-circuit
circuit can maintain a positive voltage as the string current is limited by the cells
with lower short-circuit current.
Figures 2-12, 2-13, 2-14 illustrate the experimental output power measurements of
a 5-cell series string with and without bypass diodes, compared to a 3-2 DCR string.
From the 5-cell series string measurement under uniform irradiance in Fig. 2-12, the
maximum power current Imp and voltage Vmp of the cells can be extracted to be
1.31 A and 0.40 V respectively. The diffusion capacitance can then be calculated from
Fig. 2c to be approximately 6.25 pLF. The DCR string has a switching frequency of
51
3
5-Cell Series String: Output Current Sweep at 1 (A/s)
2
Output Voltage
Output Current
--- - -
- - - - - - -r - - - - - -
-
- -- - ---- 2.5 - - - - ---
-
1.5
-- -
-
2
0
1.51
4--
I
0
1
0
-------- ---------0.5
-
0.5
0
0
0.5
-
1
1.5
2
-I10
2.5
Time (s)
Figure 2-11: Experimental measurement of output voltage and current of a 5-cell
series string by sweeping the output current at 1 ampere per second.
52
Output Power \s. Output Current (Uniform Irradiance)
1
----- 3-2 Ladder DCR String
..........- 5Series String
3
2------
-
- --7--
-
----
--
-
25- - - - - - - - - - -+ -.- - - - - - - - - ---- - -+
0
0
0.5
1.5
1
2
2.5
3
Output Current (A)
Figure 2-12: Experimental measurement of a 3-2 DCR string compared to the 5 series
string under uniform irradiance condition.
500 kHz, and the expected SSL conversion loss is 5.8% from (2.15). Assuming the
switch on-resistance dominates the effective resistance, the expected FSL conversion
loss is 4.1% from (2.19). Hence, the total insertion loss can be calculated from (2.20)
to be 7.1%.
The measured output power of the 5-cell series string has a peak at 2.63 W, and
the measured output power of the 3-2 DCR string has a maximum of 2.49 W. This
gives a measured efficiency of 94.7%, or a measured DCR insertion loss of 5.3%. The
lower measured insertion loss, compared to the calculated 7.1%, can be attributed to
the recovery of losses from process variation as shown in (2.25).
Figures 2-13 and 2-14 illustrate the measured output power characteristic curves
under different shading conditions, where the shading percentage is determined by
measuring the change in short-circuit current of the shaded cells. The series string
53
Output Power vs. Output Current (2 Cells 40% Shaded)
2.5
---
3-2 Ladder DCR String
5 Series String (Bypassed)
---------- 5 Series String
2
S
1.5
I
-
--
-
--
---
I
L
(D
40
I
_
1
0
0.5
0
0
0.5
1
1.5
Output Current (A)
2
2.5
Figure 2-13: Experimental measurement of a 3-2 DCR string compared to the 5 series
string with two cells 40% shaded.
54
Output Power vs. Output Current (1 Cell 40% Shaded, 1 Cell 75% Shaded)
2.5
I
I
1
1
3-2 Ladder DCR String
--5 Series String (Bypassed)
.--------- 5 Series String
-
2
I-
1.5
II
0
a-
0.
1
0.5
0
--
0
0.5
-
-
-
-
-
0
1.5
1
Output Current (A)
2
2.5
Figure 2-14: Experimental measurement of a 3-2 DCR string compared to the 5 series
string with one cell 40% shaded and one cell 75% shaded.
55
configuration loses a significant portion of the string power even when only a small
percentage of the total area is shaded. With bypass diodes in place, the string is able
to extract more power. However, the resulting output power characteristic curve is
non-convex, i.e., with multiple maxima, which introduces additional constraints for
the MPPT algorithm. In the case of the DCR string, significantly more power can be
extracted. Moreover, the output power characteristic curve remains convex, which
greatly reduces the complexity of the required MPPT algorithm.
The maximum measured power for each configuration is tabulated in Table 2.4,
where the extracted percentage column illustrates the ratio of power extracted to the
total available power under uniform irradiance for the same configuration. It can be
seen that in the case of DCR, the extracted percentage follows one minus the overall
shading percentage quite closely, which validates the effectiveness of the proposed
power balancing technique.
56
Table 2.4: Measured Output Power Comparison and Efficiency Summary
1 Cell 40% Shaded
Configuration
Uniform Irradiance
2 Cells 40\% Shaded
1 Cell 75% Shaded
(N = 3)
(No shading)
(16% Overall Shading)
(23% Overall Shading)
Extracted
Extracted
c-Ti
Conversion
Power (W)
Efficiency
Power (W)
Percentage
Power (W)
Percentage
Series String
2.63
100%
1.62
61.6%
0.64
24.3%
Series + Bypass
2.63
100%
1.71
65.0%
1.22
46.4%
DCR String
2.49
94.7%
2.075
83.3%
1.92
77.1%
2.6
Summary
A new cell-level power balancing scheme, diffusion charge redistribution, has been
presented to increase energy extraction and improve maximum power point tracking
efficiency under partial shading conditions. This technique makes an array of solar
cells behave as an effective single super-cell, which can also potentially eliminate the
need for testing and binning during production. The proposed technique trades off
processing power differentially to minimizing the number of external energy storage
components. In the limit where only the intrinsic solar cell diffusion capacitances are
used for cell-level power balancing, the finest achievable MPPT granularity can be
reached at the minimum possible cost for power electronics.
With a reduced per-converter component count, i.e., no external capacitive or
inductive energy storage, the proposed solution can potentially become cost effective
at the cell-level, which has been cost prohibitive using the current state-of-the-art
including cascaded module-level power electronics (MLPEs) such as dc power optimizers [3,15] and microinverters [4], and sub-module level differential power processing
(DPP) converters using switched-capacitor [6,7] or switched-inductor [8-10] techniques.
In addition, with power optimization granularity down to the cell-level, substantial improvement in energy capture can also be achieved compared to module and sub-module
level solutions [11].
A fully-scalable ladder-type DCR string architecture has been presented along
with the analysis method to characterize the insertion losses at the slow-switching
and fast-switching limits. A proof-of-concept system consisting of a 3-2 DCR string
has been constructed and characterized. Experimental results show the DCR string
extracting significantly more energy under various partial shading conditions compared
to the traditional series string and series string with bypass diodes.
58
Chapter 3
Differential Diffusion Charge
Redistribution
The previous chapter has shown that the intrinsic diffusion capacitance of the solar
cells can be used to perform power balancing effectively [30]. By using the diffusion
charge redistribution (DCR) technique with a scalable ladder structure of solar cells,
maximum power point tracking can scale down to the finest cell-level granularity. This
approach balances the tradeoff between differential power processing and the cost of
external passive components. In particular, by opting to process roughly half of the
common-mode generated power, the requirement of intermediate energy storage can
be completely eliminated.
This chapter builds on the existing concept of diffusion charge redistribution and
rethinks the string-level power electronics architecture to enable complete differential
power processing for maximum power point tracking at the cell-level without the use
of per-cell energy storage components. The shortcomings for the previously proposed
diffusion charge redistribution technique will be discussed in Section 3.1. The stringlevel power electronics enhancement, in particular a dual current inverter setup, will
be presented and analyzed in Section 3.2. Additional benefits in system reliability and
control simplification, along with simulation results, will also be discussed.
59
3.1
Single-Output Switched-Ladder DCR
A fully scalable, cell-level power balancing architecture using DCR was proposed in
the last chapter and illustrated in Fig. 2-7. It leverages the intrinsic capacitance of the
solar cells to act as intermediate energy storage instead of adding discrete capacitors
or inductors. Again, this hybrid approach simultaneously enables constructing long
series strings to create a sufficiently high voltage for interfacing with grid-tie inverters
and making the cells appear in pseudo-parallel to eliminate the weakest-link problem
in real-world operating conditions.
In this single-output DCR topology, power is extracted at the output of the conventional string, or the load-connected string shown on the left in Fig. 2-7. Therefore,
the power produced from the switched-ladder string must be processed through the
switching structure, regardless of the amount of mismatch present in the system. This
constitutes an insertion loss, which is the additional conversion loss compared to a
series string under perfectly matched condition. The insertion loss, though shown to be
manageable, sets design constraints on the switch sizing and especially the switching
frequency based on the available intrinsic solar cell capacitance [30]. In addition,
having insertion loss on the common-mode generated power may not be attractive for
panel manufacturers and system integrators when long-term project economics are
factored in. Therefore, in the next section, methods for enabling differential power
processing will be discussed and presented.
3.2
Differential Power Processing
One key concept for improving the photovoltaic energy conversion efficiency is the
idea of differential power processing (DPP). By only processing the generally small
mismatch in power among PV elements, the incurred power conversion loss from
performing maximum power point tracking (MPPT) can be reduced significantly.
Specifically, when the PV elements are operating under matched conditions, their
energy production should be extracted directly by the output load, such as a grid-tie
60
inverter, without any intermediate processing.
Differential power processing has been implemented at different levels of integration
using a variety of architectures and topologies [6-9]. However, these approaches
typically consist of a single modular functional block capable of achieving DPP and
MPPT simultaneously, hence requiring these blocks with either parallel current steering
inductors or voltage balancing capacitors at the desired level of MPPT granularity.
The DCR technique proposed in the last chapter has been shown to effectively
perform cell-level power balancing without needing local intermediate energy storage
components on a per-cell basis. In order to enable DPP for DCR while retaining
its main advantage of requiring no per-cell energy storage components, this chapter
illustrates a DPP-enabling circuit enhancement that is deliberately decoupled from
the MPPT functional blocks. Instead, the proposed architecture is applied to the
string-level power electronics. In particular, the string-level modification should allow
direct energy extraction from both the load-connected and the switched-ladder strings.
The conceptual diagram of differential diffusion charge redistribution (dDCR)
architecture is illustrated in Fig. 3-1. The dual current source input interface can
be implemented using two isolated string inverters, or via a current divider interface
preceding a central inverter. In this topology, cell-level power balancing and maximum
power point tracking are achieved by charge redistribution on the solar cells diffusion
capacitance.
The dual current source interface provides means for direct energy
extraction from both the load-connected and the switched-ladder strings, thereby
enabling differential power processing.
3.2.1
Operation under Uniform Irradiance Condition
When all the cells operate under perfectly matching condition, they must have the
same maximum power voltage Vmp and maximum power current mp. To extract the
maximum power from the strings, the dual current sources must extract Imp from
each and every cell, which can be accomplished by each demanding Imp from their
respective string. This corresponds to an even current division ratio of D = 0.5. Under
this condition, the solar cells would each exhibit the maximum power voltage Vmp
61
Switched Ladder
Diffusion ChargeRedistribution
Cefl,
0
C92
Ceel2
*92
Ceells
CeHC
5
eDual
Current
f]
Source
Inverter
Cens
Cefl2N-2
CeU2N-1
92
Figure 3-1: Conceptual diagram of the proposed differential DCR (dDCR) architecture
with dual current source inverter output.
62
so that no charge transfer will occur during the switching events of the ladder. As a
result, there is no power processing and no insertion loss associated with adopting
diffusion charge redistribution compared to a series string.
It can also be observed that when the maximum power current is being extracted
from the switched-ladder string of solar cells, their active elements are effectively
nulled from the perspective of the load-connected string of cells. Therefore, the
ladder-connected cells appear as a passive string of capacitors to the load-connected
string of cells. By symmetry, the same observation can be made of the load-connected
cells from the perspective of the ladder-connected cells. This effectively reduces the
circuit back to the single-capacitor DCR implementation shown in Section 2.2.2, which
is capable of DPP. Under matched condition, this means that no power from the
ladder-connected string is processed by the load-connected string, and vice versa.
To validate the differential power processing capability in the proposed topology,
a SPICE simulation is performed comparing the following three configurations: a
9-series string, a 5-4 DCR string, and a 5-4 dDCR string. In this simulation, the cells
are assumed to be matched with uniform irradiance, and each generate a short-circuit
current of ISc = 2.5 A. In addition, an even current divide ratio of D = 0.5 is used in
the dDCR string as discussed previously.
Fig. 3-2 compares the output power of the three different configurations. The
x-axis on the plot corresponds the total current extracted, which is the sum of the
load-connected and ladder-connected string currents in the case of the dDCR string.
In contrast to the single-output DCR string, the dDCR string exhibits no insertion
loss and extracts the same peak power as the series string. This result verifies the
differential power processing capability of the proposed architecture.
3.3
Current Divide Ratio Tuning
For minimum insertion loss under perfectly matching conditions, the dual current
sources should demand equal currents, in particular the maximum power current, from
their respective strings. However, given asymmetric shading conditions, the current
63
Output Power vs. Output Current (Uniform Irradiance)
1U
..
---.
-
9 8
U
7
6
0
5
0.
4
..............
..................
.
a,
3
-
2
-
- - -9
-
1
0
0
--
---1
Series String5-4 DCR String
5-4 dDCR String (D = 0.5)-
2
3
Output Current (A)
4
5
Figure 3-2: SPICE simulation comparing the output power versus total output current
under uniform irradiance among three topologies: 9 series string, 5-4 DCR, and 5-4
dDCR architectures.
64
divide ratio of the two output sources can be used as an extra degree of freedom to
minimize the amount of processed power. This is illustrated in Fig. 3-1 by the current
divide ratio D, where the current commanded by an inverter is split into D - Ist
through the load-connected string and (1- D) -It
through the switched-ladder string.
This provides additional means for optimization that was not available in the original
single-output DCR configuration.
Consider the following example to demonstrate the utility of this added tuning
capability: assume a dDCR system with all of the ladder-connected cells shaded by
50%. Because solar cells are essentially current generation sources, it is clear that in
order to maximize the extracted power from each cell while minimizing the amount
of processed power, the commanded current from the load-connected string should
roughly be twice that from the ladder-connected string. In other words, with a current
divide ratio of D = 0.67, the amount of processed power is close to zero, whereas by
keeping the current divide ratio at D = 0.5, approximately one-sixth of the generated
power has to be processed. Finally, in the case of the single-output DCR with D = 1,
approximately one-third of the generated power has to be processed. Therefore, the
dDCR topology with the added tuning ability is expected to extract a higher peak
power compared to the original DCR configuration.
A SPICE simulation comparing a 9-series string with per-cell bypass diodes, a 5-4
DCR string, and a 5-4 dDCR string is again used to illustrate the utility of the current
divide ratio tuning. In this simulation, four cells are affected by partial shading, and
partial shading conditions are simulated by decreasing the short-circuit current by 50%
in the affected cells. In the 5-4 DCR and dDCR architectures, the four shaded cells are
chosen to be the ladder-connected cells according to the discussed example. Fig. 3-3
illustrates the extractable power under this partial shading condition. It can be
observed that the DCR and dDCR configurations are able to deliver significantly more
power under mismatch by performing power balancing at the cell-level. In addition,
the benefit of having the current divide ratio tuning capability is demonstrated. By
setting the current divide ratio to minimize the amount of processed power, more
usable power can be extracted from the system.
65
Output Power vs. Output Current (4 Cells 50% Shaded)
8
--
-.-
-
-
--
-
-
5 -
-
-
7
3:I
1
0
I,'
--
4-
-
-
- -
DC
-trn
.0
-4dCSIng(
-
-
-
dDCR..r.n.(D.=...7
C
tin
d..ds,..-4
d
5-4 d In Dte DCR String (D ng0.50)
dDCR String (D
-5-4
0
=0.67),
......
0
1
2
3
Output Current (A)
4
5
Figure 3-3: SPICE simulation comparing the output power versus total output current
with four cells shaded among three topologies: 9-series string with per-cell bypass
diodes, 5-4 DCR, and 5-4 dDCR architectures. In the DCR and dDCR configurations,
the four shaded cells are chosen to be the ladder-connected cells.
66
In the general case with arbitrary shading patterns, finding the optimal current
divide ratio may not be as simple as described in the previous example. The output
power optimization must be performed over the entire space spanned by the following
two variables: the total output current Iot and the current divide ratio D. Equivalently,
the variables can be parameterized and the optimization space is spanned by the two
currents D -Iot and (1 - D) -It.
The convexity of such a multi-variable optimization
problem will be examined in the following section.
3.4
Output Power Optimization Convexity
It was illustrated in the previous chapter that the output power versus output current
characteristic for the original DCR configuration is a convex upwards function, i.e.,
there is no more than one maximum, regardless of partial shading conditions. This
is perhaps one of the most appealing benefits of adopting the DCR configuration.
Without the possibility of being stuck at a local maximum power point, the string-level
maximum power optimization algorithm can be greatly simplified.
The intuition behind the output power convexity with respect to output current of
the single-output DCR topology can be derived from the switching configuration. The
ladder switching topology effectively transforms the series string connections of the
solar cells into pseudo-parallel ones. Parallel combination of solar cells is essentially
equivalent to constructing a single large solar cell, and the pseudo-parallel combination
of solar cells then creates a single "super-cell" with rescaled voltage and current
characteristics. Regardless of scaling, if a string behaves as and exhibits characteristics
of a single cell, then the output power versus output current curve must be convex.
In the case of the two-variable optimization problem, the same intuitive argument
does not apply directly as the optimization now is trying not only to maximize the power
extraction from the solar cells, but also to minimize the amount of power processed
by diffusion charge redistribution. To evaluate convexity of this optimization, an
equivalent circuit is proposed to model the power balancing behavior while accounting
for power processing losses.
67
3.4.1
3-2 dDCR Output Power Convexity Derivation
The 3-2 dDCR equivalent circuit model is shown in Fig. 3-4 where each solar cell
is modeled as a photocurrent generation source in parallel with a diode. Based on
different illumination intensities, each solar cell i can have a different amount of
available photocurrent set by the variable Iph,i. Furthermore, the variables D and I.,
can be parameterized into
Iodd
=
D - It,
(3.1a)
Ieven
=
(1 - D) -Iout.
(3.1b)
The ladder switching network makes the solar cells appear in pseudo-parallel, which
enforces the same voltage condition on all the cells in the DCR string. Assuming the
cells are matched, this can be translated to a matching current condition. Specifically,
in order to have the same voltage on each cell where the cells exhibit the same diode
characteristics, the current flowing through each photodiode must be identical. This
common current is denoted as Id in Fig. 3-4a.
Instead of calculating the charge redistribution during each phase of operation, the
effect of the DCR switching network can be captured by the use of virtual redistributed
current sources as shown in Fig. 3-4b. The redistributed current sources describe how
much power is processed by DCR in the system, and one of the optimization objective
is then to minimize the amount of redistributed currents. Given the demanded output
currents Iodd and even, the switching network redistributes the generated photocurrent
such that KCL is met at each node. This means that the following set of equations
68
I'P,3
I
Id
Iph,4
IId
'ph)
c,
Id
'i8,
Id
p,2
(a)
Iph,5
PI~
id
Ad
Id
c'
I*,
1*,,2
Ip,3
Id
Id
1."..
4*,3
IP*'5 IdI1,,,
I*,2
4
IOA,
Id ,4
(b)
Figure 3-4: Equivalent circuit model for examining output power optimization convexity: (a) with DCR network shown, (b) with DCR network replaced by effective
redistribution current sources.
69
must be satisfied.
Id = Iph,1
+
Idcr,1 -
= Iph,2
+
dcr,2 -
Iodd
Ieven
(3.2)
= Ip,3 + 'dcr,3 - Iodd
ph,4
+
'dcr,4
= Iph,5
+
'dcr,5 -
=
Ieven
-
Iodd
In addition, using energy conservation, the redistributed currents
'dcr,i
must sum
up to zero. Hence,
Idcr,1
+
Idcr,2
+
'dcr,3
(3.3)
+ Idcr,4 + Idcr,5 = 0
Combining (3.2) and (3.3), a system of three equations can be written to solve
for the three unknown redistributed currents in terms of the available photocurrent
currents Ipj and the demanded output currents Iodd and Ieven.
Icr, 1 = -
5
dcr,2 =
(-4ph,1
+ Iph,2 + Iph,3 + Iph,4 +
1
5-
(+Iph,1 -
1
5
(+ph,1
1
5
(+Iph,1 + Iph,2 + Iph,3 -
1
5
(+Iph,1
Idcr,3 = 1
Idcr,4 = -
dcr,5 = -
4
1ph,2 + 'ph,3 + Iph,4
+ Iph,2 -
4
Iph,5
+ Iph,5
ph,3 + 'ph,4 + Iph,5
4 1
ph,4
+ Iph,2 + Iph,3 + Iph,4 -
+
21
-
3
+
2 1
+ Iph,5 -
4
1ph,5
+
odd - 2Ieven)
(3.4a)
+ 3Ieven)
(3.4b)
Iodd
odd -
2leven)
(3.4c)
3
Iodd +
3'even)
(3.4d)
2
Iodd -
2Ieven)
(3.4e)
It can be observed that in the case of uniform irradiance, the photocurrent current
terms in (5.1) all cancel out. The redistributed currents can be made zero by setting
Iodd =
'even,
which results in no insertion loss as expected from the discussion in
Section 3.2.1.
Given the redistribution currents, the diode current can be solved from (3.2), and
70
the diode voltage can be written using the standard diode equation:
I
Id =
Vd = 77
-
(Iph,1 + Iph,2 + Iph,3 + Iph,5 + Iph,5 -
31
odd - 2Ieven)
(3.5a)
(3.5b)
VT - log(Id/Io + 1)
where 77 is the diode ideality factor, VT is the thermal voltage, and 1o is the saturation
current.
Finally, we can define the output power and our optimization objective function as
5
Pout (Iodd, Ieven) =Vd
- (3Iodd + 2Ieven) - Ref f
aj I'c,j
(3.6)
i=j
where the first term calculates the total extracted power from each cell, and the
second term models the loss from diffusion charge redistribution. Note that Ref is
the effective impedance dominated by either the switch on-resistance or the capacitor
impedance. The terms Idcr,i capture the average redistributed current, and the scaling
terms ai account for the rms values of the current. For example, if the redistributed
current is roughly constant in one phase and zero in the other, then the power loss
from a square waveform should be doubled and the corresponding a would have a
value of 2. Nevertheless, the exact value of each rescaling term is not required to prove
convexity. By construction, ai ;> 0, Vi because additional power cannot be generated
from current redistribution. Also, since the current redistribution cannot be lossless,
the sum of all the ai must be strictly positive.
To determine the convexity of the output power optimization problem, all the
second partial derivatives of the output power function must be examined [31]. In
02pou
H(out)a
12pout
.
&Iodd~leven
02pou
oddaeven
Hodd
&even
71
Hcross
Hcross Heven
_2_pout
-
'
-
other words, the Hessian matrix must be derived, and it is defined by
Taking second derivatives of (3.6), the entries of the Hessian matrix for the N = 3
case can be solved,
- 9Y
(3.8a)
Heross = +X - 6Y
(3.8b)
Heven= -X
(3.8c)
Hodd = -X
- 4Y
where X and Y are:
X
=
2
-(4a 1 + 9a 2 + 4a3 + 9a 4 + 4a5 ) -Reff
(3.9a)
>0 by construction
2. (Iph,1 + Iph,2 + Iph,3 + Iph,4 + Jph,5 + 5Io) - (3Iodd + 2Ieven)
(('ph,1 + Iph,2 + 'ph,3 + Iph,4 + 'ph,5 + 5Io) - (3Iodd + 21even))2 77. VT
(3.9b)
Since ai > 0, Vi, and their sum is strictly positive, the quantity X shown in (3.9a)
must be strictly positive. Furthermore, the quantity Y must also be strictly positive
over the entire optimization space because the total extracted current from each cell
cannot exceed the total available current. Specifically, the following condition must
hold
Iph,1 + Iph,2 +
'ph,3
+
'ph,4
+ Iph,5 > 3Modd + 2leven
(3.10)
A continuous, twice differentiable function of several variables is convex upwards if
and only if its Hessian matrix is negative definite. Therefore, the eigenvalues of the
Hessian matrix are derived to evaluate convexity.
Hodd
Hcross
1
0
Heross
Heven
0
1
Solving for A:
=
Hodd + Heven k V/(Hodd + Heven )2
22
72
-
4 (Hodd. Heven - Hr2ros)
(3.12)
Since the Hessian matrix is a real and symmetric matrix, its eigenvalues must all
be real. Given X > 0 and Y > 0 over the entire optimization space, the diagonal
entries of the Hessian matrix are strictly negative. Thus, it can be shown that one of
the eigenvalue of the Hessian is strictly negative. Moreover, the determinant is the
product of the eigenvalues. In the two-variable case, if the determinant is positive,
then the eigenvalues are both negative, which implies that the Hessian is negative
definite. The determinant of the 2 x 2 matrix is defined by
Hodd - Heven - H2o
= (-X - 9Y) - (-X - 4Y) - (X - 6Y)
2
(3.13)
= 25XY
> 0
Hence, the eigenvalues of the 3-2 dDCR output power Hessian matrix are strictly
negative for any set of photocurrents {Iph,1, Iph,2,
Iph,3},
or any shading conditions,
and arbitrary current redistribution patterns described by the rms correction factors
{ a,, a2 , a3 }.
The output power optimization problem is therefore convex with only
one maximum power point.
3.4.2
Generalized dDCR Output Power Convexity
Derivation
The proof shown in the previous section can be extended to a string of arbitrary length
N, where there are N cells in the load-connected string with odd designators and
N - 1 cells in the ladder-connected string with even designators. In the generalized
case, the redistribution currents can be solved as
2N-1
2N - 1,_ (N - 1) - (odd
Idcr,i =
-
Ieven) +
N1
2N - 1
N - (leven - Iod) +
Ij
-
(2N - 1) Iph,i
2N-1
E
j=1
iphj - (2N - 1) -
P
i odd
)
1
,
i even
(3.14)
73
-T(3.18b)
The common diode current can then be expressed as the average available photocurrent
minus the average extracted output current.
I1
=N-
N - Io- (N - 1) -(3.15)
2-j=1
Using the diode voltage equation from (3.5b), diode current equation from (3.15),
and the redistribution currents in (3.14), the output power for the general case is
2N-1
Pout (Iodd, Ieven) = Vd - (N
- Iodd + (N
-
1) - Ieven)
-
Reff -
Z a3
. I2cr,j
(3.16)
j=1
Again, the first term calculates the sum of the power extracted from each solar cell,
and the second term captures the loss from performing diffusion charge redistribution.
The rms correction factors ai ;> 0, Vi, and the sum of ai must be strictly positive
because current redistribution can neither result in additional power nor be lossless.
Since the output power optimization space is still spanned by the same two variables
Iod and Ieven, the Hessian remains a 2 x 2 matrix as defined in (3.7). Taking second
derivatives of the generalized output equation (3.16), the entries of the Hessian can
be obtained.
Hodd= -X - N 2 . Y
(3.17a)
Hcross = +X - N - (N - 1) -Y
Heven= -X
(3.17b)
- (N - 1) 2 . Y
(3.17c)
where X and Y in the generalized case are defined as
X
(2N - 1)2
(N - 1)2.
j
odd
aj + N2
ak
. E
k even
(3.18a)
-Reff
>0 by construction
2. (ZN'
Ip,j+ (2N- 1)
- Io) - (N - Iodd + (N - 1) - Ieven)
Y =j+)
2
j-1 Iph~j +
(2N - 1) - Io) - (AT - Iodd + (N - 1) - Ieven))
74
V
Since ai > 0, Vi, and their sum is strictly positive, the quantity X shown in (3.18a)
is again strictly positive. Furthermore, the quantity Y must also be strictly positive
over the entire optimization space because the total extracted current from each cell
cannot exceed the total available current. In other words,
2N-1
E
Iph,j >
j=1
N - Iodd + (N - 1)
(3.19)
- Ieven
Given X > 0 and Y > 0 over the entire optimization space, the diagonal elements
of the Hessian matrix can be shown to be strictly negative. Therefore, one of the
eigenvalue of the Hessian matrix defined in (3.12) is strictly negative, and the necessary
and sufficient condition for convexity (upwards) is again reduced to having a positive
determinant. The determinant of the Hessian for the generalized dDCR configuration
is given by
Det =(-X -N
2
.Y).(-X -(N -1)
2
-Y)-(X
-N -(N -1).Y)
2
(3.20)
= (2N - 1) 2 . XY
which is again strictly positive. Thus, the output power optimization for a dDCR
string will remain convex, i.e., with only one maximum power point, over all possible
shading patterns defined by any set of photocurrents
{Iph,i},
and arbitrary current
redistribution patterns described by the rms correction factors {ai}.
Simulated Output Power Contour
3.4.3
In this section, output power simulation over key corner cases of partial shading
conditions as well as randomly generated shading patterns are illustrated to validate
the convexity proof presented in the previous section. The simulation result will be
presented in the form of output power over the space spanned by the total output
current
',t
and the current divide ratio D. In order to capture the sharp cutoff in
power once the total extracted current approaches the available photocurrents, or the
short-circuit currents, the output current It
75
sweep is broken up into 120 small steps.
The current divide ratio D is swept with a step size of 0.1 from 0.1 to 0.9. Each power
output characteristic then is the result of 1080 transient SPICE simulations.
In these SPICE simulations, a 5-4 dDCR string is used as an example. The
load-connected cells are numbered with odd indices and the ladder-connected cells
are numbered with even indices, ascending from top to bottom as shown in Fig. 3-1.
The 3-D surface plot of the output power when the system is operating under uniform
irradiance condition is shown in Fig. 3-5. In this case, it can be observed that a
current divide ratio near D = 0.5 is indeed where the peak power extraction occurs.
However, in other cases, it may be more difficult to visually evaluate convexity from
the 3-D surface plot. Hence, output power contour plots, which are projection of the
3-D surface plots, will be presented the following section. The output power contour
of the system operating under uniform irradiance is shown in Fig. 3-6. The peak
power extraction operating condition is exactly D = 0.5 as indicated by the circle
on the contour plot. Cases where the system experiences a symmetric center spot
shading, an asymmetric terminal spot shading, as well as a combination of these
spots are illustrated in Fig. 3-7, 3-8, and 3-9 respectively. Power output contours
resulting from linear shading patterns such as horizontal center shading, horizontal
stripe shading, and cross pattern shading are illustrated in Fig. 3-10, 3-11, and 3-12.
Finally, the simulated system behavior under randomly generated shading conditions
from a uniform distribution are shown in Fig. 3-13 and 3-14. These representative
cases demonstrate the general behavior of the power contours. In all simulated cases,
the output power contour has always remained convex with only a single maximum
power point over the entire space, as expected from the discussion in the previous
section.
The output power contour simulation validates the proof presented in the previous
section. There is no risk of the optimization getting stuck in a local maximum power
point. Hence, the MPPT algorithm complexity for this multi-variable optimization
problem at the string level can be greatly reduced, and well-known optimization
algorithms such as gradient descent or conjugate gradient methods can be adopted.
76
Output POVAr - Un111ftm Iradimne
....... ~.0.9"
..-.-.-.....-..
0.8,
0.7,
......-.0.5
CL 0.6,
0.4-,
.....-..-
0.1
-
1.2
0. .-
0.6
0.8 0
0.
A
.
.50.6
.
0.8
0.3 0.4
.
.....
0.7
Total Output
CurrMn Divide Ratio
CumwAn
Normalized to (2.
ISC
SNA
Figure 3-5: SPICE simulated output power 3-D surface plot over the space spanned
by the total output current and the current divide ratio under uniform irradiance.
Output Power - Uniform Irradiance
1.1
-o
11
0.9
Q
0.8
0.7
E
CLJ
z0 0.6
U)
cc
0.5
46
0.4
0.
0
0
lI-
0.3
0.2
0.1
0.1
0.2
0.3
0.6
0.5
0.4
Current Divide Ratio
0.7
0.8
0.9
Figure 3-6: SPICE simulated output power contour over the space spanned by the
total output current and the current divide ratio under uniform irradiance.
77
Output Power - Spot Shading (C5)
1.1
LO
".)
0.9
0.8
N
0
0.7
06
0.5
0.4
0
0.3
0.2
0.1
0.1
0.2
0.3
0.4
0.5
0.6
Current Divide Ratio
0.7
0.8
0.9
Figure 3-7: SPICE simulated output power contour over the space spanned by the
total output current and the current divide ratio - spot shading with center cell (#5)
shaded by 50%.
Output Power - Spot Shading (C9)
1.1
1
LO
Q
N
0
0o
z
0
I-
CL
0.9
0.8
0.7
0.6
0.5
0.4
0
a
12
0.3
0.2
0.1
0.1
0.2
0.3
0.4
0.5
0.6
Current Divide Ratio
0.7
0.8
0.9
Figure 3-8: SPICE simulated output power contour over the space spanned by the
total output current and the current divide ratio - spot shading with terminal cell
(#9) shaded by 50%.
78
Output Power - Spot Shading (C5, C9)
1
0.9
UO
11
o 0.8
0.7
.
-a
0.6
5
0.5
0.4
CL
o
0
0.3
00.1
0.2
0.1
0.2
0.3
0.4
0.5
0.6
Current Divide Ratio
0.7
0.8
0.9
Figure 3-9: SPICE simulated output power contour over the space spanned by the
total output current and the current divide ratio - combination spot shading with
center cell (#5) and terminal cell (#9) shaded by 50%.
Output Power - Linear Shading (C4, C5, C6)
0.9
U,
0.8
0.7
N_
Zo
0.6
0.5
0.4
0.3
0.2
0.1
0.1
0.2
0.3
0.4
0.5
0.6
Current Divide Ratio
0.7
0.8
0.9
Figure 3-10: SPICE simulated output power contour over the space spanned by the
total output current and the current divide ratio - linear horizontal shading with cells
(#4, #5, #6) shaded by 50%.
79
Output Power - Linear Shading (C2, C3, C7, C8)
0.9
'
.8
LO
0.7
0.6
.N
w
0.5
0
0.4
0.3
O 0.2
0.1
0.1
0.2
0.3
0.4
0.5
0.6
Current Divide Ratio
0.7
0.8
0.9
Figure 3-11: SPICE simulated output power contour over the space spanned by the
total output current and the current divide ratio - horizontal stripe pattern shading
with cells (#2, #3, #7, #8) shaded by 50%.
Output Power - Cross Pattern Shading (C2, C4, C5, C6, C8)
0.9
'
0.8
_i
0.7
LO
11
0
~0*0.6
0.5
c
z
0.4
r
o 0.3
0.3
o 0.2
12
0.1
0.1
0.2
0.3
0.4
0.5
0.6
Current Divide Ratio
0.7
0.8
0.9
Figure 3-12: SPICE simulated output power contour over the space spanned by the
total output current and the current divide ratio - cross pattern shading with cells
(#2, #4, #5, #6, #8) shaded by 50%.
80
Output Power - Uniformly Distributed Random Shading
(0.96, 0.16, 0.97, 0.96, 0.49, 0.80, 0.14, 0.42, 0.91)
0.8
LO
_)
0.
0.
0.5
0
z
CL
0.4
0.3
0
cc
0.2
0
0.
0.1
0.2
0.3
0.4
0.5
0.6
Current Divide Ratio
0.7
0.8
0.9
Figure 3-13: SPICE simulated output power contour over the space spanned by the
total output current and the current divide ratio - random shading with normalized
photocurrent magnitudes of (0.96, 0.16, 0.97, 0.96, 0.49, 0.80, 0.14, 0.42, 0.91).
Output Power - Uniformly Distributed Random Shading
(0.79, 0.96, 0.66, 0.04, 0.85, 0.93, 0.68, 0.76, 0.74)
0.9
O
0.8
11
0.7
0.6
N
0
E
z
0.5
0
0.4
0.3
0.2
0
H0.1
0.1
0.2
0.3
0.4
0.5
0.6
Current Divide Ratio
0.7
0.8
0.9
Figure 3-14: SPICE simulated output power contour over the space spanned by the
total output current and the current divide ratio - random shading with normalized
photocurrent magnitudes of (0.79, 0.96, 0.66, 0.04, 0.85, 0.93, 0.68, 0.76, 0.74).
81
3.5
Local Control and Frequency Scaling
In traditional DPP topologies, where a single functional block capable of simultaneously achieving DPP and MPPT is employed and distributed at the desired level of
optimization granularity, local MPPT control must control the duty ratio of individual
converters such that each PV element operates at its local maximum power point [8,9].
Although any of the existing and established MPPT algorithms can be adopted [32],
having local control requires additional measurement and sensing hardware for each
PV element.
In contrast, power balancing and optimization is inherent in the DCR switching
topology such that charge redistribution occurs naturally. In this case, only switch
synchronization hardware is required among adjacent converters as discussed in
Section 2.4. There is no need for full-fledged MPPT converters nor localized control
to optimize the power for each PV element.
It was shown in the previous chapter that in order to achieve low overall insertion
loss, a switching frequency in the range of hundreds of kilohertz was required given the
available diffusion capacitance to maximum power current ratio. This constraint arises
from the fact that the original DCR configuration must process the generated power
from roughly half of the solar cells at all times. In the case of dDCR, the amount of
processed power can be reduced significantly. Therefore, it is possible to decrease the
switching frequency while maintaining a certain level of overall conversion efficiency.
For example, given a solar array installation and its expected amount of mismatch, a
slower switching frequency can be determined and fixed at installation time to meet the
desirable efficiency target of the project developer. A more advanced implementation
may even adaptively adjust the switching frequency during real-time operation.
3.6
Circuit Implementation
The dual current interface can be implemented with two isolated string inverters
as mentioned in the previous section. In this configuration, the two inverters can
82
perform MPPT individually as the entire optimization space is shown to be convex.
Moreover, redundancy and fault tolerance can be gained as added benefits. If one of
the inverters fails, it does not necessarily result in total system failure and shutdown.
The remaining inverter can continue to operate the system as a single-output DCR
system with increased insertion loss, given that appropriate power rating headroom is
factored into the system design.
In systems where centralized inverters are deployed, a current divider interface
preceding the inverter can be used. An example implementation of a current divider is
shown in Fig. 3-15, and details of a fully differential design can be found in Appendix B.
In order for this topology to be adopted in practice, the conversion loss from current
dividing must be lower than the insertion loss the single-output DCR topology would
otherwise incur. In the illustration shown in Fig. 3-15, two inductors are inserted to
enable adiabatic charging and discharging of the capacitive energy buffers. In other
words, the capacitors are charged by near-constant current sources from the inductors
and discharged by a constant current from the inverter. Hence, the capacitive charging
and discharging losses can be drastically lowered, and it is possible to design this
current divider to be extremely energy efficient.
Since the current divider switches are steering currents between two strings coupled
by the DCR configuration, the maximum voltage the current divider switches have
to block at any given time is bounded by a single diode voltage. Hence, MOSFETs
with high voltage ratings are not required. Instead, MOSFETs with very high current
handling capability and low Rd,
can be selected in the design to maximize the
overall system efficiency by minimizing the gate charge that needs to be driven.
3.7
Experimental Validation
To validate the efficacy of the proposed dual-current power extraction interface, an
additional experiment was performed with the 3-2 DCR prototype shown in Fig. 2-10.
The experiment has been performed with two de electronic loads, one HP 6063B
and one BK Precision 8500 to emulate two independent string inverter with current83
CurrentDividerInterface
Switched Ladder
Diffusion ChargeRedistribution
D
s
S
(1-D)
Cefll
Ce
2
P92
CeCeR2
Ces
*
55
Current
5
Ceus-
-
Source
--
0
8
e eInp
P16
CeCll3
*
ut
S
.
92*g
Inverter
-.
Figure 3-15: An example implementation of the output current divider interface
preceding a centralized inverter.
84
Experimental Output Power Contour of 3-2 dDCR String
2
........
1.4.....
-.
0 .6
0
-
M
.
.
~1.6.........
0.5
1
1.5
2
Load-Connected String Current (A)
2.5
3
Figure 3-16: Measured output power contour over the space spanned by the two string
currents - near-uniform-irradiance with short-circuit currents of (1.72, 1.96, 1.86, 1.80,
1.77).
controlled inputs. Specifically, the output power contour versus the two string currents
is obtained by setting a constant current the BK Precision 8500 dc electronic load
while sweeping the current on the HP 6063B dc electronic load. The voltage and
current waveforms have been recorded with a Tektronix TDS5034B oscilloscope.
Figures 3-16, 3-17, and 3-18 illustrate the measured output power contour versus
the two string currents of the 3-2 DCR string now configured as dDCR with two
outputs. In Fig. 3-16, the circuit is under near-uniform-irradiance condition with
short-circuit currents of { 1.72, 1.96, 1.86, 1.80, 1.77}. The power contour is shown to
be convex as predicted, and the peak power extraction occurs when approximately
equal currents are extracted from the two strings.
Fig. 3-17 illustrates the case when the ladder string experiences some degree
of partial shading, and the short-circuit currents drop significantly. The measured
short-circuit currents were
{ 1.72, 0.70,
1.86, 0.87, 1.77}. In this case, the peak power
extraction occurs with a bias for more current on the load-connected string to avoid
processing power through DCR. Finally, Fig. 3-18 illustrates a case when the top of the
85
Experimental Output Power Contour of 3-2 dDCR String
. . ........ ...............
1.2
1
.
-..
+....
2.2
2.4
0.6
0.4
c0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
Load-Connected String Current (A)
2
Figure 3-17: Measured output power contour over the space spanned by the two string
currents - shading on ladder cells with short-circuit currents of (1.72, 0.70, 1.86, 0.87,
1.77).
Experimental Output Power Contour of 3-2 dDCR String
1.5
1
V
Q 0.5
0
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
Load-Connected String Current (A)
Figure 3-18: Measured output power contour over the space spanned by the two string
currents - shading on top cells with short-circuit currents of (1.26, 0.94, 0.34, 1.93,
1.79).
86
panel is affected by partial shading, and the power generation capability of the top three
cells are affected. The measured short-circuit currents were {1.26, 0.94, 0.34, 1.93, 1.79}.
Since the load-connected string is more severely affected by the imposed shading
condition, the output current divide ratio now favors the ladder-string for maximum
power extraction. In both of these shaded cases, the output power contours have
remained convex as predicted from the analytical derivation shown in Section 3.4.
3.8
Summary
This chapter builds on the concept of diffusion charge redistribution presented in
the previous chapter and the concept of differential power processing. The proposed
topology separates the DPP-enabling circuitry from the MPPT functional block to not
only perform maximum power point tracking with cell-level granularity without using
any external passive components, but also achieve zero insertion loss with minimal
added hardware at the string or centralized inverter level.
The functionality and benefits of the proposed architecture are illustrated analytically and validated in SPICE simulations and experimental characterizations. The
added current divide ratio tuning capability has shown to be useful in minimizing the
amount of processed power. The optimization over the space spanned by the output
current and the current divide ratio is shown to be convex over a variety of partial
shading conditions. Additional advantage includes reduced switching loss from lower
or dynamically-scaled frequency of DCR. If implemented using two properly-sized
string inverters, the system gains additional reliability from inverter redundancy. The
alternative current divider interface can also be very energy efficient with adiabatic capacitor charging and discharging, while employing switches with high current handling
capability and low on-resistance.
87
THIS PAGE INTENTIONALLY LEFT BLANK
88
Chapter 4
Switched-Capacitor Energy Buffer
Architecture and Inverter
Reliability Considerations
Chapters 2 and 3 have focused on improving the maximum power point tracking
capabilities, which increases the overall solar energy extraction and thereby reduces the
LCOE. However, system downtime and lifetime maintenance costs also directly impact
the total cost of ownership and therefore the LCOE. In this chapter, the failure mode of
a PV system is discussed, and methods for improving the overall system reliability will
be presented. In particular, given that the grid-tie inverter and its dc-link capacitor
represent the most failure-prone components, circuit techniques and control algorithms
are proposed to potentially eliminate these troublesome components.
4.1
Failure and Reliability of a PV Plant
PV systems from leading manufacturers typically come with 25 years of warranty.
However, PV inverters, which are used to efficiently convert the dc power generated
from the solar array onto the ac electrical grid, has a mean time to failure of only five
years in 2012. In fact, in a field experience of a 3.5-MW PV plant [33], even though
89
the inverters only accounted for 10 - 20% of the initial system cost, they actually
had to be replaced up to five times over the lifetime of a PV system. Furthermore,
inverter failures accounted for 37% of the unscheduled maintenance events and up to
59% of the associated costs for repair and replacement.
At the component level, it has been shown that capacitors are one of the least
reliable components.
Surveys on failures in power electronic systems, such as a
PV inverter, have revealed that capacitors failures accounted for up to 30% of all
failures, which is the highest among all power electronics components and other failure
types [34]. This can be attributed to the prevalent use of aluminum electrolytic
capacitors, whose high volumetric efficiency and low cost have made them popular in
cost-sensitive designs, such as a PV system. However, they suffer from relatively short
lifetime, and thus require considerable maintenance work [35].
4.2
DC-Link Capacitor Background
A power conversion interface between a DC and a single-phase AC system requires
an energy buffer to store the instantaneous power difference between the constant
power of the DC port and the time-varying power of the AC port. Traditionally, this
energy buffer is implemented with large electrolytic capacitors. As the system reaches
periodic steady state with unity power factor, the instantaneous power difference
manifests itself as a voltage ripple on the energy buffering capacitor at double-line
frequency. However, the single capacitor approach is known to achieve poor energy
utilization [36].
Energy utilization is defined as the ratio of the energy used to buffer the instantaneous power difference to the maximum stored energy on the capacitor. Energy
utilization for single capacitor energy buffers with respect to the peak-to-peak ripple
ratio can be derived as:
= AE
Emax
C - (V +0.5r V) 2 - C. (V - 0.5r -V)
C- (V + 0.5r - V) 2
1+ r + 0.25 -r2
90
2
(4.1)
where r is the prescribed peak-to-peak ripple ratio. For instance, in a system with
10% peak-to-peak ripple ratio, the single capacitor energy buffer implementation has
an energy utilization of less than 20%. In other words, the capacitor has to store more
than 5 times the energy as actually needed.
Many alternative techniques have been proposed to manage the double-frequency
energy flow. These approaches include parallel active circuits such as the ripple port
proposed in [36] and the parallel active filter illustrated in [37], and the series active
circuit such as the series voltage compensator shown in [35] and the dual of the
ripple port demonstrated in [38]. However, these approaches often involve introducing
additional magnetics for transformation and current control
4.3
Switched-Capacitor Energy Buffer Overview
The capacitor shift topologies [39] are known to achieve higher energy utilization and
lower voltage ripple. Using such a topology for the energy buffer capacitor could
lead to more effective capacitor utilization and smaller capacitor volume for the same
allowable voltage ripple. In contrast to previously proposed topologies, this represents
a direct active-circuit, i.e., a switched-capacitor bank, replacement of the existing DClink capacitor bank. In this case switched-capacitor (SC) energy buffer architectures
[6, 7] can achieve higher energy utilization and lower voltage ripple. Fig. 4-1 shows the
general architecture of the proposed SC energy buffer. The SC energy buffer consists
of two banks of capacitors shown as one possible example in Fig. 4-1: "backbone"
capacitors and "supporting" capacitors. The configuration will be described as y-z,
where y is the number of capacitors in the backbone bank and z is the number of
capacitors in the supporting bank.
The backbone capacitor bank contains capacitors that withstand large voltage
variations during the ripple cycle, where the voltage variations are typically much
greater than the prescribed peak-to-peak ripple allowance. In order to bring the
bus voltage ripple within bound, the supporting capacitor bank is switched so that
the voltages of the supporting capacitors are either added to or subtracted from the
91
(Optional)
High-Frequency
DC/DC Converter
Low-Frequency
High-Frequency
Interfacing Converter
SC Energy Buffer
-AC/DC
(PFC)
"Supporting" Bank
F
+
+
+N
DC Load
F
- OR
-
Vb.,
-OR-
"Backbone" Bank
TT ...T
DC/AC
(Inverter)
F.
BE
4mm
DC Source
(Solar)
F
a
Ti
Figure 4-1: General architecture of the SC mergy buffer.
voltage of the backbone capacitor bank. The switching pattern is defined such that the
resulting bus voltage satisfies the ripple specification. In the maximum utilization case,
the switching pattern loops through all the supporting capacitors for each backbone
capacitor on-period. The supporting capacitors have to withstand a much smaller
voltage variation during the ripple cycle. Specifically, in this two-bank energy buffer
architecture, the voltage variations on the supporting capacitors are limited to one-half
the specified peak-to-peak bus ripple magnitude if the supporting capacitors and
backbone capacitors are equally sized.
Using this technique with a peak-to-peak ripple ratio of 10%, energy utilization
can be improved to ~ 70% with one backbone capacitor and ~ 80% with multiple
backbone capacitors. Moreover, this technique enables the use of capacitors with
smaller capacitance and lower voltage ratings, thereby making it possible to replace
limited-life electrolytic capacitors with ceramic or film capacitors.
92
I
co-u- V0
+
Backbone
Capacitor
Y2J
.1
Supporting
Capacitors
c2T
cT
VM-1
bus
cm-1
I
Ground-
Referenced
Switches
so
3/S
S2/
SM-1
(a)
VI-L
Supp orting II
Caps citors
Sadd
tor
so (S1
VM.-
2
T _
IC --------
+
Ssu SI
-.00aSadi
CM-
6O
T o
--
4
bus
SM-'1
S2
Ss.b
C0
.C..
. V0
Backbone
Capacitor
(b)
Figure 4-2: General 1-z architecture of SC energy buffer. (a) Implementation with
ground-referenced switches only for unipolar switching configuration. (b) Implementation with four additional switches to achieve bipolar switching configuration.
4.4
SC Energy Buffer Design Considerations
There are many tradeoffs to be considered in designing an SC energy buffer. A basis for
making these tradeoffs is developed in this section. In principle, energy utilization can
be increased arbitrarily at the expense of switching frequency and buffer complexity.
Desirable transient performance implies new control requirements that also impact
SC buffer design. We consider these tradeoffs in the context of two general SC buffer
architectures, unipolar and bipolar switching configurations shown in Fig. 4-2.
A first consideration in designing the energy buffer is energy utilization when the
93
design goal is to reduce the overall amount of physical capacitance in the system.
Equation (4.1) summarizes the energy utilization for a non-switching, single capacitance
buffer. The energy utilization equation can be generalized for the SC case shown in
Fig. 4-1 by taking the sum of AE, the change in energy stored, divided by the sum of
Ema, the maximum energy stored, of all the capacitors in the energy buffer. This is
shown in (4.2).
Z= 1 AEackbone(j) +
Zj'- Emax, backbone(j) +
=
z= 1 lAEsupport(k)
Z=1 Emax,support(k)
(4.2)
The variables in (4.2) depend on not only the nominal bus voltage, the specified
ripple ratio and the selected capacitor size, but also the switching configuration. Thus,
the two cases shown in Fig. 4-2 illustrate a tradeoff between topology and switching
complexity versus capacitor utilization. Note that Fig. 4-2 illustrates the two cases
with a single backbone capacitor, i.e., y = 1 in each case, although more backbone
capacitors could be employed with arbitrary y.
4.4.1
Capacitor Configuration
For illustration, the energy utilization of an SC energy buffer with bipolar switching
configuration versus different numbers of backbone and supporting capacitors for three
different ripple ratios is shown in Fig. 4-3. These plots are generated using (4.2),
where the change in energy stored and the maximum energy stored components will
be fully developed and quantified in terms of the capacitor voltages in Section 4.4.2.
Two important conclusions can be drawn from these plots. First, for each ripple
ratio and number of backbone capacitors used, there exists an optimal number of
supporting capacitor which maximizes the energy utilization of the overall energy
buffer. Secondly, the energy utilization can be improved with diminishing return by
introducing more backbone capacitors.
94
Energy Utilization vs. Capacitor Configuration - 10% Peak-to-Peak Ripple
100
- -
--- -~~
---- ------
90
80
-- -
--
---- -------
-
-
-
70
0
60
2)
w 40
0) 30
0
2
7
y 2-y=6
--
-
--
---
------ - - ---
5
- -y
-----
-
-
-
-
16
N
- -T
y=4
y=2
- - --
10
0'
--- - ------- - - ------- - --40
35
30
25
20
15
10
Number of Supporting Capacitors (z)
5
)
----- -- -- - -----
- -
-
(a)
Energy Utilization vs. Capacitor Configuration - 5% Peak-to-Peak Ripple
100
-- -
- - - ----
--
-
---- - - - - ---------------
80
-
--- --- - --- --- ------ --------- - - ----- - ------
90
70
- -
0
-
--
--
--
60
50
2'
a'
wC
-
-
---- ---- ---------
--
-
iU
N
-
---
40
-- - ---------y --------y=6
30
-y = 5 - --- --y-
20
y=4
y=3
-~
1
~
y2--------
- ----
--
- --
-
----- - - -J---- -------L -
y=1
0'
5
30
25
20
15
10
(z)
Capacitors
Supporting
of
Number
(b)
95
35
40
Energy Utilization v. Capacitor Configuration - 2% Peak-to-Peak Ripple
100
- - --
60=
80--
----------------
---------
70 -----------
--
--
--
Lu
1)0 ---- - ----
0
5
y=57
1
y = 3
y-
-- -- -- ----
-
----
--
-- - - -
-
O
---
-----------------
y
5 0 - - - - - -- - - --- - -Ny=
0
- --
--- - -- ---- ----T----
-- -
-
80 -----
- - -
-- - - --- --
-- -=---2---
10
15
20
25
30
Number of Supporting Capacitors (z)
-
90 -- - - - ----- - -- - - -- - --- -- - ---
35
40
(c)
Figure 4-3: Overall energy utilization of the SC energy buffer as a function of
the capacitor configuration. These numbers are computed for SC energy buffers
with equally sized backbone and supporting capacitors using the bipolar switching
configuration.
However, the number of backbone capacitors cannot be increased indefinitely. The
switching frequency of the SC energy buffer is directly proportional to the number of
capacitors in the energy buffer. In particular, for every ripple cycle of two times the grid
frequency, the switching pattern steps through every single backbone capacitor; in each
backbone capacitor on-period, all the supporting capacitors and a pass-through state
via switch So are looped though. Hence, the switching frequency can be approximated
as
f.
2 - fgri -P -y (z + 1)
(4.3)
where p = 2 for unipolar switching schemes to account for the charge and discharge
cycles, and p = 4 for bipolar switching schemes for account for the charge and discharge
sub-cycles in the additive and subtractive cycles. Clearly, increasing the number of
96
capacitors would unavoidably increase the incurred switching loss. Also, excessive
number of capacitors would cause the SC buffer switching frequency to approach
that of the PFC or inverter controllers, consequently causing undesirable interactions
between the two control loops.
In order to guarantee time-scale separation between the low-frequency energy buffer
control and high-frequency PFC or inverter control, the number of capacitors must be
limited. When designing a switching converter, the switching frequency is expected to
be high with respect to the natural frequency of the energy storage elements. This
extends to the case of a SC energy buffer. While any specific case requires a control
loop and stability analysis, a similar rule-of-thumb to keeping the natural time constant
in the canonical models long compared to the switching period, e.g., 10 times the
switching period, is to have the SC buffer switching at below 1/10 the frequency of the
interfacing switching converter. As illustrated in Fig. 4-1, high-frequency switching
converters can be found on either side of the SC energy buffer.
For example, assuming the switching frequency of the high-frequency loop is on
the order of a hundred kilohertz, average switching frequency of the energy buffer
control might be constrained to be less than approximately ten kilohertz. In other
words, the relationship in (4.4) must hold:
10 kHz
P -Y- (Z + 1) <; 1fkrz(4.4)
2 - fgrid
This establishes an upper bound on the number of capacitors that can be incorporated in these SC energy buffers. Referring back to Fig. 4-3, the unfeasible
combinations of capacitor configurations are greyed out. As shown, the achievable
improvement in energy utilization is limited, albeit still significant, as this becomes a
constrained optimization problem. For peak-to-peak ripple ratios of 2%, 5%, and 10%,
the optimal achievable energy utilizations are realized with only one or two backbone
capacitors.
In a SC energy buffer, the bus voltage is no longer an accurate measure of the
energy stored in the energy buffer. Therefore, when integrating with conventional
97
power-factor correction controllers or energy-balance inverter controllers, the bus
voltage cannot be directly used as the feedback voltage. Reference [40], for example,
uses an artificial feedback voltage to ensure compatibility with existing hardware.
However, such an artificial feedback voltage is not guaranteed to be sinusoidal and
may not reliably detect under- and over-voltage conditions.
By implementing the backbone capacitor bank with only one capacitor, a voltage
feedback signal is available at the single backbone capacitor for interfacing with
conventional power-factor correction controllers or energy-balance inverter controllers.
Because there is a single path in the backbone capacitor bank through which the energy
buffering current must flow, the single backbone capacitor voltage can be treated as
an AC-scaled version of the single electrolytic capacitor voltage in traditional energy
buffers.
Energy utilization is still high with a single backbone capacitor. Specifically, in
the case of 10% peak-to-peak ripple ratio, using a single backbone capacitor reduces
the achievable energy utilization from 77.9% to 71.2%, still a sizable improvement
from 18.1%. In the cases of 5% and 2% peak-to-peak ripple ratios, the optimal energy
utilizations remain unchanged. Also, this simplification enables the exclusive use of
ground-referenced switches in unipolar switching configurations.
4.4.2
Switching Topology Tradeoff
We therefore focus on the 1-z architecture shown in Fig. 4-2, where we define M = z+ 1
as the total number of capacitors in the SC energy buffer. The backbone capacitor is
denoted as CO, and the supporting capacitors are denoted as C1 through CM-1.
Two types of switching configurations can be explored: unipolar and bipolar. In
unipolar switching, supporting capacitor voltages are added to the backbone capacitor
voltage when it is too low, but are never subtracted. With equally sized capacitors,
the resulting peak-to-peak bus voltage ripple with respect to the total number of
capacitors is
AVr,pp,unipolar =
2
z+ 2
(wo - C - VC
98
=
M+ 1
WO - C - VC
(4.5)
where P is the power level, wo is the angular frequency of the grid, C is the capacitance
of all capacitors in the SC energy buffer, and Vc is the nominal voltage of the grid.
The two in the numerator accounts for the fact that the backbone capacitor and the
supporting capacitor are connected in series, which halves the effective capacitance
and doubles the voltage ripple during the ripple buffering cycle. The denominator
includes the total number of ripple buffering cycles, where each cycle includes a
charge and discharge cycle. Each supporting capacitor contributes an additional
ripple buffering cycle while the shoot-through state contributes two cycles because
the effective buffering capacitance during the shoot-through state is not halved.
If the backbone capacitor voltage is regulated by energy balance control, i.e., to
achieve constant mean squared voltage, using the unipolar switching configuration will
result in a variable mean bus voltage. Specifically, the mean bus voltage will increase
with increasing power level, but will always be above the regulated mean voltage
of the backbone capacitor. For this reason, the unipolar switching configuration is
unsuitable for PFC applications with constant output voltage requirements. However,
it is compatible with solar inverters where the bus voltage must remain sufficiently
high in order to maintain control of the grid. In addition, because the mean bus
voltage is positively correlated to the power level, it ensures fast response time in
hysteretic current controlled inverters when the output current amplitude is increased.
Finally, the one-sided switching configuration also has the added benefit of being able
to utilize ground-referenced switches only. By rearranging the supporting capacitor
bank and the backbone capacitor as shown in Fig. 4-2a, the unipolar SC energy buffer
avoids high-side gate drives.
In the bipolar switching configuration, four additional switches are added in order
to invert the polarity of the supporting capacitor voltages during parts of the ripple
cycle. This enables ripple reduction with a constant mean bus voltage. Supporting
capacitor voltages are added to the backbone capacitor voltage when it is too low and
are subtracted from the backbone capacitor voltage when it is too high. As such, the
bipolar switching configuration is compatible with power-factor correction applications
without an additional dc-dc converter at the output. Moreover, the bipolar switching
99
configuration uses the supporting capacitors more efficiently; each supporting capacitor
contributes two ripple cycles, in the additive and subtractive cycles respectively. The
shoot-through again contributes two cycles. Hence, the bipolar switching configuration
achieves a peak-to-peak voltage ripple of
AVrppbipo=ar
=
2
2z +2
P
wo-C- Vc
1
M
(4.6)
which is approximately twice as effective, in terms of ripple reduction capability versus
number of capacitor added, compared the unipolar switching configuration. The ripple
advantage requires four extra switches and high-side gate drives, which contribute to
additional switching losses.
Given the expected ripple sizes, the required peak voltage for each supporting
capacitor for proper buffering at the maximum power rating can be calculated. As the
backbone capacitor voltage increasingly exceeds the prescribed ripple specification,
higher supporting capacitor voltages are needed to bring the combined voltage back
within bound.
Because the backbone and supporting capacitors are charged or
discharged in series, the peak voltage increments on the supporting capacitor is
half the expected ripple size shown in (4.5) and (4.6).
Hence, the steady-state
maximum supporting capacitor voltages under maximum power rating for both
switching configurations are:
Vmax,unipolar(j) =
Vmax,bpoiar(j) =
for j = {1, 2, ...
,M
M+ 1
M+1
(
P
W.C.VCj
j +1
P\
2M
.wo - C - Vc
(4.7)
(4.8)
- 1}. The plus one in the numerator accounts for starting with
the shoot-through state using only the backbone capacitor, before the backbone
capacitor goes out of bound. For the backbone capacitor, the maximum capacitor
voltage is the same for both switching configurations and can be calculated as
1P
Vmax(O) = VC + 100
(4.9)
The maximum capacitor voltages outlined here also supplement the energy utilization calculations in Section 4.4.1 and facilitate capacitor voltage rating selections.
In the following section, control strategies for both switching configurations will be
presented.
4.5
Two-Step Control Strategy
A controller capable of handling power level transients must not prescribe strict DC
voltage boundaries constraints on the bus voltage. Instead, it should allow the DC
level of the bus voltage to undergo natural settling while maintaining the AC ripple
magnitude within specification around the DC level. This enables the controller to
evenly distribute the charge buffering to the supporting capacitors instead of leaving
the terminal-state capacitors to absorb an unusual large amount of leftover charges.
Also, the controller must effectively reset its state from ripple cycle to ripple cycle in
order to guarantee the availability of reserve buffering states in the event of power
transients. Finally, the controller must intelligently manage the supporting capacitors
so they can remain effective in reducing the ripple magnitude at all time. This
translates to maintaining the reference voltage levels of the supporting capacitors
relatively constant regardless of power level.
These requirements can be satisfied by adopting a two-step control strategy:
capacitor participation optimization and switch timing determination. The controller
first determines the optimal number of capacitors to use in buffering the bus voltage,
and then compute the switch timings for the allocated supporting capacitors to
maximally reduce the bus voltage ripple. In a 1-z SC energy buffer configuration, the
single backbone capacitor voltage is used as the feedback node to either a PFC or an
inverter controller. Thus, the SC energy buffer controller discussed here passes the
regulation of the backbone capacitor voltage to an external interfacing controller.
Two design examples will be presented to better illustrate the operation and the
effectiveness of the proposed control strategy. The specification for the design examples
is a 500 W inverter with a 250 V nominal bus voltage and a 10% peak-to-peak ripple
101
ratio. For maximum energy utilization, a 1-8 SC configuration is chosen for the
unipolar switching scheme. For the bipolar switching scheme, a 1-4 SC configuration
is chosen for comparable switching complexity and ripple reduction power.
4.5.1
Capacitor Participation Optimization
In order to optimize the supporting capacitor participation, the controller samples
the current power level and calculates the minimum number of capacitors required
to keep the voltage ripple within the specification. The sampling frequency is twice
the line frequency for the unipolar switching configuration and four times the line
frequency for the bipolar switching configuration.
The sampling points with respect to the ripple cycle are illustrated in Fig. 4-4.
Note that the minimum required number should have a lower bound at 1 because the
backbone capacitor is always used. The required numbers of capacitors for adequate
ripple buffering for a given power level are derived by inverting the ripple magnitude
(4.5) and (4.6) for the two different switching topologies. Equation (4.10) shows the
solution for the unipolar switching configuration and (4.11) shows the solution for the
bipolar switching configuration. Note that P[n] is the discrete time sampled power
level during the current ripple cycle, and n is the discrete point at which the system
is being evaluated.
Munipoiar[n] = max
Mbiolar[n] = max
P[n]1
2(wo -C-VC - AK'PP
P[n]'
V
1 ,1
1)
( wo - C - VC -Avr,,) 1
102
(4.10)
I
(4.11)
DoubleiLneFrequency
a -4A
I DichargeCyclk
u
ChargeCyck
ContAl
Sampk
Point
Ramp
Sgnal
VAN)
Vc(2))
V44
Vc2)
-
Sampk
Point
Vc(3)
V44
IVc(4)
Vcf 5)
Vc(6)
Vc(7)
V47)
V4O
VO(8)
so
S1
'4
53
Ion
s5
..n
S6
..
S7
..
... Mo
000
S7
..n
56 1
o..
on
..o
en'
on
S1
..n
M
.n
(a)
SublacipeCyde
S a on
Charge
%
-Dhcharge
A ddke Cyck
S.d d on
SubtacwveCyde
on
Dicharge
U.- I -a
pr- M -"%
Dscharge
Charge
Sampk
Pot
Sampk
Poit
Vdl)
V41)
V'47)i
VA(P
V2)
V 1
Vc42)
V42)
V_(3_
VVt3)
V44)
VcO)
V43)
Vc(4)
V44)
VC(4
M
.
s2
a
s1
.
s4
o.n
o
SI 1S2
.. o.
S J
..
Sg
on
s3
S2
si
on
on
on
o
. en..o n
on
1
en,1 1
S11
Conhol
Ramp
-nx Sinal
(b)
Figure 4-4: Sampling points and control variables, vc(i) and vd(i), in relation to the ripple cycle and the control ramps for (a)
unipolar switching configuration and (b) bipolar switching configuration.
By only using the minimum required number of capacitors, the controller ensures
that there is a sufficient number of capacitors in reserve, ready to kick in during a
sudden power level increase. In addition, relatively constant energy storage in the
supporting capacitors is maintained over a wide range of power levels. Consequently,
the system is able to respond to large power transients by adjusting the number
of capacitors used, rather than drastically changing the energy stored on all the
supporting capacitors. Fig. 4-5 illustrates the supporting capacitor voltages and the
expected ripple size across all possible power levels in the 1-8 unipolar SC energy
buffer design example. The number of switching events is reduced as the power level
decreases, which improves the overall system efficiency.
4.5.2
Switch Timing Determination
Given the number of capacitors to use, the controller proceeds to compute the switch
timings for the capacitors based on the current power level. That is, the charge and
discharge cycle durations are adjusted for each supporting capacitor based on the
current sample of its voltage and its respective reference values.
Since the charging and discharging of the capacitors by the double-line frequency
energy flow are inherently nonlinear with respect to time, a nonlinear element is
inserted into the control loop to enable the use of simple linear function in the rest
of the controller. The nonlinear element takes form of a control ramp on which the
switching event is triggered. For the unipolar switching configuration, the control
ramp is a double-line frequency sine wave phase-locked to the grid. In addition, the
unipolar control ramp is assumed to be normalized with unit peak-to-peak amplitude
and ramps from 0 to 1.
For the bipolar switching configuration, the ripple cycle can be further broken
up into two cycles.
There is the additive cycle where the supporting capacitor
voltages are added to the bus voltage, and the subtractive cycle where the supporting
capacitor voltages are subtracted from the bus voltage. Thus, the same cycle duration
computation needs to be performed twice as often as in the unipolar case. The control
ramp function for the bipolar switching configuration then must be periodic at four
104
8.75
--- -- -- - -
-
7.5
- ---
- - -
- -
- - --- - - -- - - - -----------------------
C)
-
---
-
Expected Ripple Magnitude vs. Power Lewl
10
6.25
CL
a0-
5
--
---------------------
3.75
-- -
2.5
- T----- ------- ---- ------
1.25
0
0
50
100
150
200
250
300
Power Level (W)
350
400
450
500
(a)
Supporting Capacitor Voltages w. Power Level
120
V8
cc
0)
100
V7
80
V6
V5
60
V4
0)
CL
0
CL,
CU
V
40
V
20
-
0
100
200
300
Power Level (W)
400
3
2
V
500
(b)
Figure 4-5: Expected ripple magnitude and the supporting capacitor voltages as a
function of power level for the 1-8 unipolar design example.
105
times the line frequency. Specifically, the bipolar control ramp is a rectified and
inverted version of the unipolar control ramp and ramps from 0 to 0.5. The two
control ramp signals in relation to their respective control voltages and sampling
points are shown in Fig. 4-4.
Because the control ramps are assumed to be normalized, the control equations will
also be defined in a power-independent fashion. All sampled values are normalized to
the full-swing ripple magnitude on the backbone capacitor. The normalizing function
is defined as
=
v~n]
P[n|/ (wo -C - Vc
(4.12)
)
V[n]
where v[n] is the sampled supporting capacitor voltage.
Based on the normalized sampled supporting capacitor voltages at their respective
peaks, the allowable discharge duration is calculated by subtracting the normalized
maximum voltage minus a voltage increment as shown in (4.7) and (4.8).
disch(j) = max min (i [n] - D
D1
D[n] ' D.,[n]
'D.,[n])
(4.13)
Similarly, the allowable charge duration is calculated by subtracting the normalized
sampled supporting capacitor voltage at their respective peaks from the normalized
maximum voltage plus a voltage increment.
[n] + j+ 2
1
D.,[n]' D.,[n]
charg(j) = max min (-j
where j = {1, 2, ...
K
'D.,[n]
(4.14)
, M - 1} denotes the supporting capacitor index, 1/D"[n] is the
normalized step in voltage between consecutive supporting capacitors, and K E [0, 1)
determines the minimum duration. The variable x in DX[n] denotes the switching
configuration. The normalized voltage increment definition differ in the two switching
configurations and are shown in (4.15) and (4.16) respectively.
1
1a
Dunipolar
[n]
-
M
1
1 +(4.15)
Munipolar [n] + 1
106
1
_
1
Dbipolar[n]
11
2- Mpoiar[n]
(4.16)
The minimum duration defined by K determines the tradeoff between transient
ripple size and settling time. If K is very close to zero, the controller may allow the
capacitor voltages to reach their new reference values quicker by imposing a large
imbalance between their charge and discharge cycles. However, larger imbalances
between the charge and discharge cycles increase exposure of the bus voltage to the
ripples of the backbone capacitor, resulting in larger transient ripple. If K is very
close to one, the controller will maintain ripple buffer throughout more of the ripple
cycle. But the limited imbalance between the charge and discharge cycles results
in longer settling times. Note that by managing the capacitor participation based
on power level, the reference voltages for the supporting capacitors are kept fairly
constant. Therefore, K can be set very close to one for adequate buffering without
the risk of unreasonably long settling times.
Having computed the allowable charge and discharge durations for each supporting
capacitor, the actual control trigger voltages are calculated by a cumulative sum as
illustrated in Fig. 4-4. More specifically, the individual charge and discharge control
trigger levels are
M [x]-1
Vd(j) =
E
disch(m)
(4.17)
charg(m)
(4.18)
m=j
M [X]-1
vc(j) =
j
M=j
When M [n] - 1 < j, the
jth
control voltage is set to zero, which means that the
supporting capacitor Cj is not being used in the current ripple cycle. Furthermore,
higher-indexed switches have precedence over lower-indexed switches. That is, if
vC(1), vc(2), ...
, ve(J) > vramp, switches 1, 2, . . . , J- 1 are all disabled, and only switch
J is turned on. The complete two-step controller block diagram is shown in Fig. 4-6.
107
V0 Control
V1 [n] V 2 [n VMl-[n]
Capacitor
-
Pin]
00
Participation
Optimization
Ramp
Switch Timing
Determination
V,c
M[n]
Norm
Function
(Optional)
M-1
V;
v2- Disch
Vd
so
Finite
State
Machine
*
0
s,
Sdd
---
sb
Figure 4-6: Proposed two-level SC energy buffer controller block diagram, where vo denotes the backbone capacitor voltage,
vi[n] for i = 1, 2, ... , M - 1 denotes the sampled supporting capacitor voltage, v, and Vd correspond to the charge and discharge
control signals respectively.
4.5.3
Distortion and Phase Error
In the previous section, the control ramps are assumed to be perfectly sinusoidal,
or rectified sinusoidal, with zero phase error. Practical phase-locked loops may not
guarantee zero steady-state phase error. If a phase error persists between the control
ramp and the actual ripple cycle, systematic errors would be introduced to the steadystate voltages of all supporting capacitors, which would result in an increased overall
bus voltage ripple. Additionally, the grid voltage may not be perfectly sinusoidal and
the ripple voltage may exhibit distortions. Distortion from the assumed sinusoidal
profile would introduce unsystematic imbalances in the charging and discharging of the
supporting capacitors, which again causes the overall bus voltage ripple to increase.
Therefore, the generated phase-locked signal cannot always be used. Instead, the
control ramps can be derived from the backbone capacitor voltage. By passing the
AC component of the backbone capacitor voltage through a clamped capacitor circuit,
a unipolar control ramp signal from 0 V to the peak-to-peak ripple magnitude can
be extracted. Similarly, the bipolar control ramp can be created by inverse rectifying
the AC component of the backbone capacitor voltage, then processing the resulting
signal with a clamped capacitor circuit. This yields a bipolar ramp signal from 0 V to
the peak ripple amplitude. Alternatively, both control ramp signals can be produced
digitally after sampling the backbone capacitor voltage.
Generating the ramp functions directly from the backbone capacitor voltage
guarantees zero distortion and phase error between the control signals and the actual
ripple cycle. Furthermore, normalization of the sampled signals may not be required
because the normalization factor is the inverse of the peak-to-peak ripple amplitude
on the backbone capacitor. In practice, implementing control logic with the large
voltages may not be feasible. Therefore, resistive dividers can be employed as long as
the divider ratio is consistent between the control ramp generation and the supporting
capacitor sampling.
109
4.5.4
Pre-charge Circuit Requirement
It is not necessary to have a pre-charge circuit used in [40] when using the control
strategy described in the previous sections. By adjusting the switch timings, the
controller automatically introduces imbalances between the allowable charge and
discharge durations of the supporting capacitors so the capacitor voltages reach their
reference.
This is a tradeoff. The pre-charge circuit can facilitate the process of charging
the supporting capacitors to their reference levels at startup, which allows the system
to reach steady-state operation faster. Secondly, the pre-charge circuit can assist in
maintaining the charges on unused capacitors. The proposed controller only controls
charge and discharge duration on the active supporting capacitors in the ripple cycle;
it has no control over the nonparticipating capacitors in reserve. Thus, having a
pre-charge circuit adds an extra layer of security to ensure that the capacitors in
reserve remain ready in the event of a power level increase. Finally, by using a
pre-charge circuit to set up all the capacitors to known states initially, the SC energy
buffer can in principle be operated without a requirement to monitor the voltage on
every supporting capacitor in the buffer.
4.5.5
Over- and Under-voltage Protection
Aside from the over-voltage protection circuitry commonly found in PFC and inverter
controllers, the SC energy buffer controller can incorporate an additional layer of
protection to guard against large transients between sampling periods. Switching
duration computations are performed at the beginning of each sampling period. If the
transient between sampling periods is large enough, the computed and ideal switch
timings may differ significantly, resulting in over- or under-buffering conditions.
Over-buffering occurs when the actual ripple magnitude is significantly smaller
than the expectation of the controller. When such an event occurs, the boost and drop
in the bus voltage from switching the supporting capacitors will be greater than what
is actually needed. Similarly, under-buffering occurs when the actual ripple magnitude
110
is significantly larger than the expectation of the controller. Consequently, the boost
and drop in the bus voltage from switching the supporting capacitors will be smaller
than the required values. Both over- and under-buffering conditions result in larger
than expected ripples.
Such undesirable conditions can be avoided by introducing feed-forward compensation, i.e., a forced resampling triggered on over- and under-voltage thresholds.
Once the bus voltage exceeds the defined thresholds, the controller resamples the
current power level and the supporting capacitor voltages to recompute the number
of active capacitors required and recalculate the switch timings. In over-buffering
conditions, the recomputed number of active capacitors would be decreased, whereas
in under-buffering conditions, the recomputed number of active capacitors would be
increased.
4.6
Simulation Results
The unipolar 1-8 SC energy buffer and the bipolar 1-4 SC energy buffer design examples
have been successfully implemented and simulated in SPICE with a 500 W inverter.
The system is implemented with control ramps generated from the backbone capacitor
voltage to avoid distortion and phase errors. In addition, the minimum duration
constant K is set to 0.9 and a pre-charge circuit is configured to manage the voltages of
supporting capacitors in reserve. The steady-state bus voltage ripple and the backbone
capacitor feedback voltage are shown in Fig. 4-7 and 4-8 for the unipolar and bipolar
cases respectively. The simulated result matches the analytical solution quite well.
The external inverter control manages the backbone voltage and holds it to 250 V.
The peak-to-peak ripple is set to 10% by inverting (4.5) and (4.6) and solving for the
required capacitance.
111
-- - -- - - - -- -
-
m --------------------- - I ----- -- - - - - - - - - - - - - - ---- - - - - ---- - -- - - - - - - - - - - - - - - - - - - - - - --- --- - -
300
---- -------------- ---------------- ----------------
280
260
~-
220
- - -- -- -- - ------------ ------------------------------ -------------------------- ------------ ---- ---- -----0
---- -
- -- ----
-
200
--
-
--- - - --
--
----------------------------:----------
-
240
0.05
0.1
0.15
0.2
0.25
0.3
0.3
0.4
0. k5
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.
I
I
I
I
I
I
I
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
-
120 100
7IL
>
I,
20
---
0
rin
vc1LI
6
400
300
200
100
0
Time (s)
Figure 4-7: Steady-state bus voltage waveforms of the 1-9 SC energy buffer with unipolar switching experiencing increasing
power level from 96 W to 480 W with +48 W step size every 50 ms.
. ..........
. . .....
. ...
............
2-
- - - --- -- - - - -- - -- - -
--
-
3201
--
----
740
-
1260
1
00.05
0.05
0.1
0.15
0.2
02
0.1
0.15
02
0 25
0.15
0.2
*~30
0
500
40
100
0
0.05
0.1
0.25
lime (s)
Figure 4-8: Steady-state bus voltage waveforms of the 1-4 bipolar SC energy buffer with bipolar switching
experiencing decreasing
power level from 480 W to 96 W with -96 W step size every 50 ins.
.
IN W
............
The bus voltage in the unipolar switching energy buffer exhibits a power-dependent
mean as discussed in Section 4.4.2, and remains well above the grid voltage to retain
control. As the power level increases, more supporting capacitors become involved in
ripple buffering, as demonstrated by the capacitor activities in the subplot of Fig. 4-7.
Conversely, the bus voltage in the bipolar switching energy buffer has a constant
mean over the all power levels as shown in Fig. 4-8. With decreasing power level,
the supporting capacitors sequentially become inactive, leaving only the backbone
capacitor to buffer the small power ripple.
In a sampled system, the worst-case behavior occurs if a large transient occurs
immediately after sampling has taken place. Thus, this is the case chosen for the
transient response characterization. Positive and negative 30% steps in input power
level are introduced to the inverter with the bipolar 1-4 SC energy buffer. As shown in
Fig. 4-9, the positive step in power causes an under-buffering condition until the bus
voltage crosses the upper threshold. Note that the over and under-voltage thresholds
are defined to be 1.5 times the ripple specification, i.e. 15% peak-to-peak from 250 V,
and shown in Fig. 4-9 as dotted lines. At this point, the controller immediately
resamples and recomputes the switch timings to pull the bus voltage back within
bounds. Even though the transient may cause some supporting capacitor voltages,
v 2 in this particular example, to deviate from their reference values, the two-step
controller is able to bring the system back to steady-state in just a few cycles, without
any unacceptably large transient ripple.
114
ZOU
270
230
22(
0.05
0
01
0.15
70.
60
c-i-'
50
40
30
20
-ii
10
0
0
U --
Lj I rl F -
-V
V
V,
0.05
0.1
Time (s)
2
0.15
Figure 4-9: Transient bus voltage response of the example bipolar 1-4 SC energy buffer in a solar inverter due to 30% input
power step. The power steps from 480 W to 336 W at 50 ms and back to 480 W at 100 ms. The second supporting capacitor
voltage is shown to deviate from its reference value shortly after 100 ms, but the two-step controller brings it back to its reference
level in less than 2 ripple cycles.
-
-----------
4.7
Summary
Switched-capacitor energy buffers have been shown to achieve much better energy
utilization than their single electrolytic counterparts. However, overshooting and the
possibility of losing control to the grid are major concerns. The proposed control
strategy can potentially minimize the possibility of such undesirable behaviors by
maintaining an appropriate number of supporting capacitors in reserve to guard
against sudden transients in power level.
Two SC energy buffers, 1-8 with unipolar switching and 1-4 with bipolar switching,
have been examined in a 500 W inverter.
The simulated models show excellent
agreement with the calculated results. Furthermore, the system is able to maintain a
minimum bus voltage of 250 V and limit the peak-to-peak ripple to 10% under steadystate operation. It is also shown that the proposed control strategy can successfully
maintain the ripple specification under significant power level transients.
116
Chapter 5
Z-Source Circuit Breaker and DC
Power System Protection
Direct current power distribution is under examination for many applications such as
the dc or hybrid ac/dc grid networks with distributed energy resources [41-44]. The
dc power system architecture has attracted interest as a means for achieving higher
overall efficiency for dc loads, enabling easier integration of renewable and distributed
energy sources, and providing uninterruptible power with readily available energy
storage elements [45-47]. These benefits can ultimately lead to a reduction in LCOE.
However, to enable widespread adoption of dc power systems, e.g., a photovoltaic
array, the reliability of fault protection and interruption capability is essential.
The lack of a natural voltage or current zero-crossing to extinguish an are that
can occur when opening a breaker presents a well-known challenge to protecting dc
distribution systems [48-51]. Traditional solid state dc breakers typically rely on
an auxiliary solid-state switching device and a precharged commutation capacitor
or a passive network to force commutate the main solid-state switching device by
reverse biasing, which can enable fast and arc-less current interrupting capabilities.
However, the auxiliary solid-state switching device must be actively driven to reverse
bias the main switch before the fault current rises beyond the interrupt capability of
the breaker. Hence, strict detection and timing requirements must be imposed on
117
the existing design. Additional active circuitry is also needed to precharge the force
commutation circuit.
By creatively reconfiguring the Z-source inverter, the recently introduced Z-source
circuit breaker potentially mitigates these problems [52-55]. Previously proposed
Z-source circuit breaker topologies are illustrated in Fig. 5-1. The Z-source breaker
operates on the principle of natural commutation for critical fault conditions. Under
critical fault conditions, it may be difficult to ensure fast detection and accurate timing
for forced commutation. When a large transient fault occurs, the Z-source breaker
provides a fraction of the transient fault current through the Z-source capacitors and
thereby forces a current zero-crossing in the SCR (silicon controlled rectifier). Once the
current in the SCR reaches zero, the SCR naturally commutates off and the faulty load
becomes isolated from the source. Natural commutation of the Z-source configuration
allows the fault to be cleared before having to apply control signals to disable sending
gate pulses to the SCR. However, practical uses of this technique are limited because
the existing Z-source breaker does not provide steady-state overload protection and
can only guard against large transient faults. For faults of lesser severity and slower
dynamics, the fault current may not be sufficiently large to naturally commutate the
breaker. In these cases, a new forced commutation circuitry can be introduced to the
breaker topology. The boundary between natural and forced commutation will also
be derived in this chapter.
Furthermore, the previously proposed Z-source breaker topology shown in Fig. 5-1b
does not provide a common ground between the generation source and the load, and the
topology shown in Fig. 5-lb reflects a large fault current to the generation source. This
work presented in this chapter aims to address the aforementioned shortcomings by
proposing a new Z-source breaker topology which minimizes the reflected fault current
drawn from the generation source while retaining a common return ground path. This
will provide designers more flexibilities when evaluating a Z-source circuit breaker for
protection in their respective applications. Comparison to the previously proposed
Z-source breakers are discussed in Section 5.1. Comprehensive analyses, including
minimum detectable fault current magnitude and ramp rate, component sizing of the
118
* Crossed
Z-Source Breaker
SCR
source
L
A
ISCR
C
Cn
R
I
c
Rkad
L
S
S
(a)
IC
e Parallel-Connected
Z-Source Breaker
SCR
L
.
houre I
Isc-
C
*
-
S
Rdmp
R
C
S
Rfau
-
L
Fka
C
(b)
Figure 5-1: Previously proposed Z-source circuit breaker: (a) crossed Z-source topology
and (b) parallel-connected Z-source topology.
Z-source circuit breaker are presented in Section 5.2. In addition, manual tripping
mechanisms, which enable protection under both instantaneous large current surges
and longer-term over-current conditions, are introduced and analyzed in Section 5.3.
Finally, experimental results of the proposed Z-source circuit breaker with extended
protection schemes are presented in Section 5.4.
119
5.1
Z-Source Breaker Overview
The Z-source breaker consists of an SCR, a pair of L-C legs, and snubber diodes
and resistors. Different topologies of the Z-source breaker arise from different L-C
configurations while maintaining the same operating principle. When a fault occurs,
the fault current is supplied from both the load capacitor and the high-frequency
conduction path through the Z-source capacitors as illustrated in red in Fig. 5-1. Note
that the high-frequency conduction path through the Z-source capacitors, or the shootthrough path, is anti-series to the SCR forward current, which forces commutations if
the Z-source capacitor current reaches the level of the Z-source inductor current.
The Z-source topology shown in Fig. 5-1a uses a crossed L-C connection and will
therefore by referred to as the crossed Z-source configuration. The crossed Z-source
topology requires an inductor to be placed in the return path of the dc source, which
can be seen as a disadvantage in systems where a common ground is preferred. The
Z-source topology shown in Fig. 5-1b places the L-C pairs completely in-line with
the power source to provide a common ground. This topology will be referred to as
parallel-connected Z-source because the L-C legs are connected in parallel after the SCR
commutates off. The parallel-connected Z-source topology allows for common ground
connection between the source and all loads, but it reflects a large fault current at the
source because the high-frequency conduction path through the Z-source capacitors is
directly in-line with the source.
In order to preserve a common ground connection while reducing the amount of
fault current reflected to the source, a new Z-source breaker topology is proposed
and shown in Fig. 5-2. The source-connected capacitor in the parallel-connected
topology is replaced by a shunt capacitor to ground. The new topology is termed
series-connected because the L-C legs are connected in series once the SCR commutates
off. The series-connected topology provides the fault current from an energy storage
element instead of the source. Hence, the reflected current to the source during breaker
operation is greatly reduced.
120
a
Series-Connected
IC
-
SZ-Source Breaker
'-
C
e.....me......
.me--......
.m...
Figure 5-2: New series-connected Z-source circuit breaker topology.
5.1.1
Fault Clearing Waveforms
The full set of fault clearing waveforms for the three Z-source topologies is shown in
Fig. 5-3. The waveform variables are as labeled in Fig. 5-1 and 5-2. The simulated
system has a source voltage of Vsource = 6 kV with a maximum load power of 6 MW, i.e.,
a load resistance of RIcad = 6 Q. The load capacitance is assumed to be Cload = 1 mF,
and the Z-source parameters are chosen to be C = 200 pLF and L = 2.4 mH.
In the simulation, the system first operates under steady-state condition until a
fault with conductance Gfault = 5 Q-1 occurs near 100 ps. It is assumed that the fault
conductance ramps up linearly to the final value in At = 0.1 ms, which translates
to a fault conductance ramp rate of 50, 000 s-1Q-1. This corresponds to an effective
cable inductance of 20 pH, which is comparable to the estimate presented in [56]. In
addition, these numbers are chosen for illustrative purposes only. In a real system, the
fault conductance can be determined by the failure type, and the fault conductance
ramp rate can be bounded by the cable inductance.
As shown in Fig. 5-3, the characteristic fault clearing waveforms - SCR voltage
and current, Z-source inductor and capacitor currents - are shown to be identical
across all three topologies. When the fault is introduced, the transient fault current
will be supplied by both the Z-source capacitors and the load capacitor because the
Z-source inductor current cannot change instantaneously. The Z-source capacitor
current will increase until it reaches the Z-source inductor current. At this point, the
121
4
2
w 0
c'=-2
> --0 -6-
.......... VSC - crossedVSCR - parallel
-
----
0
VSCR -series
0.25
0.5
0.75
1
1.25
1.5
Time (ms)
- crossed
. . . . . .C.
-
ISCR - parallel
-.
SCR - series
)0
0
0.25
0.5
0.75
1
1.25
1.5
Time (ms)
2
~1
-----
IL - parallel
-- -1
01
0
0.25
0.5
0.75
1
- series
1.25
1.5
Time (ms)
22
.......... I - crossed
-----
IC - parallel
C -series
O0.
0
0
0.25
0.5
0.75
1
1.25
1.5
Time (ms)
Figure 5-3: Fault clearing waveforms for the three Z-source circuit breakers. Waveforms
for the parallel-connected and series-connected are shifted right by 10 Ps and 20 ps
respectively for clarity.
122
A
. source- crossed
3
.....-----
----
Isource - parallel
isource - series
0
0.25
0.5
0.75
Time (ms)
1
1.25
1.5
Figure 5-4: Comparison of the reflected fault current at the source among the three
Z-source circuit breaker topologies.
SCR experiences a current zero-crossing and is allowed to commutate off naturally.
Once the SCR turns off, the two L-C legs start a resonance where they supply the
fault from their respective energy storage. This resonance will continue until the
inductor voltage tries to become negative. At this point, the snubber diodes turn on
to steer the current away from the capacitors, and the current will continue to flow in
the snubber loop until the energy stored in the inductor decays to zero.
However, there are important differences in the amount of fault current reflected
back to the source, as illustrated in Fig. 5-4. In the case of the crossed Z-source circuit
breaker, the current drawn from the source equals the SCR current. Therefore, no
fault current is reflected to the source as soon as the SCR commutates off.
In the parallel-connected Z-source breaker, the current drawn from the source
during a fault interval equals the sum of the Z-source inductor and capacitor currents.
Hence, in order to trip the Z-source breaker, the source must be able provide a transient
current that is at least twice its maximally rated nominal steady-state current. This
large transient current requirement may be seen as a major disadvantage for this
topology and may impose additional requirements on the input filter.
In the series-connected Z-source breaker, the high-frequency conduction path is
intentionally directed away from the source by the use of a shunt capacitor. As a
result, the current drawn from the source during a fault interval becomes the Z-source
123
L
C
++
+
C
L
C
RW
Voit
i
(a) Crossed
RVj
V,,
(b) Parallel-Connected
C
L
L
(c) Series-Connected
Figure 5-5: Z-Source breaker ac equivalent circuit models.
inductor current alone. This reduces the source transient current requirement by half
compared to the parallel-connected topology.
5.1.2
Voltage Transfer Function
In this section, the ac transfer function of the unfaulted Z-source circuit will be
evaluated - the frequency response of each circuit not only indicates behavior as an
input filter, either alone or in conjunction with an explicit filter, but also highlights
issues in input stability that may arise when dc-dc converters appear as an active
load. In a photovoltaic system, the dc-dc converter is oftentimes a boost converter for
maximum power point tracking. A discussion of input filter design and the related
stability for power converters can be found in [57]. The following input-output voltage
transfer functions are derived assuming matching pairs of Z-source inductors and
capacitors, which gives the most optimal capacitive current divider ratio. The three
124
ac equivalent circuit models for the crossed, parallel-connected, and series-connected
Z-source topologies under unfaulted operation are shown in Fig. 5-5. The effect of the
capacitive current divider and its relations to the minimum detectable fault current
will be discussed at length in Section 5.2. In addition, a resistive load is used for
illustration purposes; for other loads, the designer can quickly arrive at the appropriate
transfer function by replacing Rad with a general Zoad.
=2
+(2/RioadC) - s + (1/LC)
crossed
-
parauel
-
Hse(s)
series
-s2 + (1/LC)
82 + (2/RloadC) . s + (1/LC)
s 2 + (1/LC)
((5/ S2 + (2/RIoadC)
s + (1/LC)
1C)
As shown in the above equations, all Z-source circuit topologies have unity gain with
zero phase at low frequencies. This can be understood by observing the inductor
conduction path while ignoring the presence of capacitors. However, the high-frequency
behaviors are different due to the dissimilar capacitor configurations.
For the crossed Z-source topology, the crossed capacitor connections create a unity
gain with 1800 phase at high frequencies. For the parallel-connected Z-source topology,
the capacitors form a high-frequency conduction path that results in unity gain with
zero phase at high frequencies. In particular, the crossed Z-source circuit transfer
function resembles that of a resonator and actually amplifies perturbations near the
resonant frequency. On the other hand, the parallel-connected Z-source circuit forms
a notch filter at the resonant frequency. The Bode plots for the two transfer functions
are shown in Fig. 5-6a and 5-6b. The design of a filter network is generally needed
for dc-dc converters to reduce electromagnetic interference and to achieve high input
noise rejection at the source. Since neither of these two topologies provides any
filtering capability at high frequency, when used in conjunction with downstream
dc-dc converters, explicit input filters must also be designed.
The series-connected Z-source circuit has a low-pass characteristic due to the shunt
125
Crossed Z-Source
I
II
Topology
I
I
1
1I
I
II
I
-
4
I
3 -2
J L _1 I
-
IL
1 --
--
-
I
r
-
-
I
-
-
III
I
-
--
_
Ilil
I
i
I
T
T
-
ll
-
--
r
l
U
11
1I
360
I
-
I
V
270 - - -
I
S
-
I
I
-4
r--i-
I
-
I iii
I
441-
I
4
-
-
-
I -
-4
1
I
I
I
I
'
-1,tII
-
II
4 -
-1
1|
111[
111111
I
1111
I
18o0
10
-
4
I
T,,T
-
I
225
A -4
4
I
II
I
-
-
II
'
I
I
1
-
-4'1
l,
i
1 1
I |1
-'
I
,
I
'
I
- -
II
IL
I
J
I
-
111J
i
i
'J
|11
|
-
315 - - - -
10
10
103
Frequency (Hz)
(a) Crossed Z-Source Topology
Parallel-Connected Z-Source Topology
i
-100 - -
g
- -
-
--
-200 -------31M
-
i
I
I
1-1+
]--I -
- -
-4-1-1-141-4 - -
-
-
-
-
1
1 1 1 1 1 I
I
+
-4 -
I
-i
4
-4--4.4--144--
-
1 1 1--- 1 4l
1 1
I
--
I
1
-_
1IIi
1-11|
-1
l
i
_
4
i
i
I
i
I
i
i
i
i
|
|
1
-
0
L
J
I
41
_-II--1
L _ -
-
-
I _
-
_L-i
_
400'
e
10 1
tle
1
1
l
i
10 3
10
1011
'I
Frequency (Hz)
(b) Parallel-Connected Z-Source Topology
Series-Connected Z-Source Topology
0
4
-
p a l-1 4 i-
-
-
-
-
1-.
4
4 4
-
.
20
.20
|)
I
-j40
TI
-60
---
--
l
--
7 1
I
i
--
-
-I+-
---
I i
r--F
-
II
-I+1-I--
-
--
i--I
-
IIFiIII
80
5
I
--
----
L1.
J
J
I
1
_
-I
iT1
I
11 1
T
7 i -I I
1'
I
I
I
F L
_LL
1 1 1 1
-15
I10
10
T 11
1 I
--i F17 1
_
I
- -II
-
-
-
- -
-IIi
-
- -
-
-
.90
-135 -
T
-
I
1
-
I
I
102
Frequency (Hz)
(c) Series-Connected Z-Source Topology
Figure 5-6: Input-output voltage transfer function of the Z-source circuit breaker
assuming resistive load. Component values are R = 6 Q, C = 200 pF, and L =
2.4 mH.
126
capacitor placement. Specifically, the transfer function is a second order low-pass filter
with a quality factor of
Q=
Road
C
(5.2)
The Bode plot is shown in Fig. 5-6c. The response is slightly underdamped using
the recommended inductor sizing with a Q of V/2 from Section 5.2, where Z-source
component sizing and
Q selection
will also be discussed in more detail.
Because the series-connected Z-source circuit topology offers inherent low-pass
characteristic, it is possible to incorporate the input filter as part of the breaker. This
allows dual-use of the Z-source passive components, as part of a circuit breaker and
an input filter network for dc-dc converters, to further reduce the component count.
Additional R-C damping leg can also be introduced in parallel with the shunt Zsource capacitor, without affecting normal breaker operation, to address any potential
unwanted interaction between the Z-source components and the negative effective input
impedance of a regulated dc-dc converter. Having a low-pass filter function does not
influence power transmission negatively as cable inductance and local energy storage
capacitance already impose a low-pass characteristic in the dc power distribution
system. Along with other attributes such as a common ground connection and a low
reflected fault current at the source, the new series-connected Z-source circuit topology
offers additional design flexibility not available in the previously proposed topologies,
which may enable its use in application such as building dc power distribution systems.
Table 5.1 summarizes the key differences among the three Z-source circuit breaker
topologies.
5.2
Z-Source Breaker Design Considerations
In the following sections, the transient fault response of the Z-source breaker is
analyzed and a design methodology for component sizing is presented. Since the three
Z-source breakers follow the same principle of operation, the following analyses are
universal across the three topologies unless stated otherwise. One notable exception is
127
Table 5.1: Z-Source Breaker Topology Comparison
Z-Source Topology
Crossed
Parallel
Series
Features
Common Ground
Fault Current at Source
Z-Source Transfer Function
Input Filter Integration
No
Yes
Yes
ISCR
IL + IC
IL
Resonator
Notch Filter
Low-Pass
No
No
Yes
the reflected fault current magnitude as previously discussed.
5.2.1
Minimum Detectable Fault Magnitude
One important metric for characterizing a breaker circuit is the minimum detectable
fault current, which is defined as the minimum amount of fault current required to trip
the breaker. Since the Z-source breaker consists of frequency-dependent components,
the minimum detectable fault magnitude must also be frequency dependent. However,
for this analysis, the minimum detectable fault current across all frequency range is
desired. Thus, an instantaneous load step is assumed for the following analysis.
For an instantaneous step transient in load current, i.e., with infinite fault conductance ramp rate, the current through the inductor leg during the fault transient
can be assumed constant at the nominal load level while the Z-source capacitors and
the load capacitor collectively supply the full fault current. The amount of the fault
current supplied through the Z-source capacitor path is then derived using a capacitive
current divider relationship:
iC
=
2
C+ C
loaault
where C is the capacitance of the Z-source capacitor,
(5.3)
Coad
is the capacitance of the
load capacitor, and ifault is the fault current. Note that in the crossed and parallelconnected Z-source topologies, the source inductance may have an effect on this ratio,
whereas in the series-connected topology, the relationship is exact. Nevertheless, the
128
impact of source inductance is small, and will be assumed to be negligible. Since the
Z-source would not trip unless iC
=
iL
'oad,
the minimum detectable fault current
can be calculated by inverting (5.3) as
C+
2
Coada
C
%fault
0ad
(5.4)
In other words, the fault conductance must be greater than the load conductance by
the same factor, as illustrated in (5.5).
C +
2
Coad
C
1
(55)
Road
For example, using the Z-source parameter values from the previous section, the
breaker would not trip unless the fault current exceeds 11 times the nominal operating
current. For slower transient faults, an even greater fault current is required because
the inductor current ramps up along with the shoot-through capacitor current. Even
in the limiting case where C is infinitely larger than Cload, the magnitude of the fault
current must be at least equal to that of the nominal operating current. Therefore, the
Z-source breaker offers no protection against, for example, a 20% overload condition.
The Z-source breaker offers limited longer-term over-current protection and is
only effective in protecting against large transient faults. Thus, additional tripping
mechanisms must be introduced for practical use of the Z-source breaker, as will be
discussed in Section 5.3.
5.2.2
Minimum Detectable Fault Ramp Rate
In addition to the minimum detectable fault current, the efficacy of the Z-source
breaker is also limited by a minimum detectable fault ramp rate. The minimum
detectable fault ramp rate is defined as the cutoff fault ramp rate below which the
Z-source breaker would not trip regardless of how large the fault eventually becomes.
The inductance of the Z-source breaker plays a part in determining the minimum
detectable fault ramp rate. However, even for a Z-source breaker with infinite induc-
129
tance, there exists a fundamental limit on the minimum detectable fault ramp rate
determined by the load resistance, the load capacitance, and the Z-source capacitance.
In order to compute this limit, the analytical expressions for the output voltage and
transient Z-source capacitor current will be derived while assuming an infinitely large
Z-source inductor. The size of the inductor required to asymptotically achieve this
minimum detectable fault ramp rate limit will then be derived in the next section.
In this analysis, the fault conductance is assumed to ramp linearly from zero to
the final fault conductance with a rate of
K = Gfault
At
(5.6)
where Gfault is the final fault conductance and At is the time interval for the ramp.
The fault current can then be defined using the load voltage and the fault ramp rate
as
ifault = Vout *K - (t - to)
(5.7)
for to < t < to + At, where to is the instant of time the fault occurs and vout is the
output load voltage. Without loss of generality, to will be assumed to be zero, so (5.7)
simplifies to
ifault = vot - K -t
(5.8)
for 0 < t < At.
Assuming the source inductance is negligible and the Z-source inductor current
and the load current remain constant, the amount of fault current supplied by the load
capacitor can be calculated using a capacitor divider ratio between the load capacitor
and the two Z-source capacitors. Therefore, a differential equation for the output
voltage across the load capacitor can be written as
Clow
dv_
d
dt
2
= --
Coad(
C+ 2 Coad
130
-Vou - K -t
(5.9)
Solving the above equation yields the following solution for the output load voltage
K P )(5.10)
(C +2Cload
-
Vout = Vsource . exp
and the fault current then can be rewritten as
ifault =
Vsource
-t - exp -
.K
(C +
2Cload
)
(5.11)
Combining (5.3) and (5.11) yields the analytical expression for the Z-source capacitor
current during the fault interval as shown in (5.12).
iC = Vsource-
K-t,
C + 2 Coad
-exp -
K
C+2Coad
(5.12)
Furthermore, the time at which the current is maximized can be solved as
+
tmax
2
(5.13)
Cload
2K
and the maximum Z-source capacitor current during the fault interval is
ZC,max =
K
2e - (C + 2 Cload) C
.
(5.14)
In order for the Z-source breaker to trip, the Z-source capacitor current must reach
the level of the nominal load current through the Z-source inductors during the fault
interval. In other words, the maximum Z-source capacitor current must be equal to or
greater than the nominal load current. Hence, the minimum detectable fault ramp
rate K must be
KminR=
2e -
1
C+
2
Coad
1
(5.15)
Equation (5.15) is intentionally written in an expanded form to illustrate the
intuition behind this fundamental limit. The product of the last two terms from
(5.15) is equivalent to the minimum detectable fault conductance from (5.5). So the
minimum detectable fault ramp rate is determined by the minimum detectable fault
131
conductance and the time constant set by the R-C product of the load resistance and
the Z-source capacitance. Given the component values from the previous section, the
minimum detectable fault ramp rate is roughly 8,300 s--1.
The Z-source breaker
would only trip automatically if the actual fault ramp rate K is larger than this
minimum detectable ramp rate.
The design of a dc system fault protection is dictated by the cable inductances and
the capacitance of loads that are feeding current to faults. Given the rated load current,
the load capacitance, and the cable inductance, the minimum detectable fault current
and fault ramp rate can be designed to ensure system survivability under more severe
fault conditions. For example, given the capacitance of loads that can feed current
to faults, the designer has the flexibility to choose the load-to-Z-source capacitance
ratio to set the minimum detectable fault current, or the maximum tolerable fault
current subject to manual detection and forced breaker commutation. Given the
distribution cable inductance, the Z-source capacitance can be further increased to
guarantee autonomous fault handling even when cable inductance slows down the
fault dynamics. It can be seen that increasing the Z-source capacitance can improve
both the minimum detectable fault magnitude and ramp rate.
However, it is worth noting that the tradeoff is not only an increased capacitor
volume, but also an increased inductance requirement to achieve this fundamental
limit, as will be shown in the following section. Faults that do not trip the Z-source
breaker automatically can be handled with manual tripping mechanism introduced in
Section 5.3. These types of faults are of smaller magnitude and slower dynamics, which
allow the system more time to respond. The minimum detectable fault magnitude and
ramp rate can also be designed to avoid false tripping from load steps in the output.
By setting the minimum detectable fault ramp rate faster than any possible load step,
the system is guaranteed to stay on during normal changes in the load current.
5.2.3
Z-Source Inductor Relative Sizing
Having too little Z-source inductance would not allow the Z-source breaker to achieve
the minimum detectable fault ramp rate, while having too much Z-source inductance
132
adds unnecessary cost, volume, and weight to the design. In this section, the inductor
current during the fault interval will be approximated and the inductance threshold
where this current becomes negligible will be derived.
In order to avoid non-closed form solutions, i.e., error functions, the Taylor
Expansions of (5.10) and (5.12) will be adopted for the following analysis.
K ~oai+
- t2
C + 2C, oad
-
K 2 . t4
2(+Cod2
2 (C + 2Cload)
)
Vaure --(1
=Vou Vsoyurce
Vont
(5.16)
+0 (t6)
c
Vsorce - C
K2-P
C + 2Cload
C
+ 2 Cload
(5.17)
+o (t)
By subtracting (5.16) from the source voltage, the voltage across the Z-source
inductors can be derived. Then, by integrating the voltage across the two inductors,
the inductor current can be solved as:
K
C + 2 Coad
iL = hoad + Vsource
6L
0 (5
(5.18)
Finally, combining (5.17) and (5.18) gives the current through the Z-source breaker
SCR during the fault interval, as illustrated in (5.19).
.SCR
oad
=
C+
+
*C - K
Vsource
2
Cload
source-K
C + 2COa
-0 (t5)
1
6L
C.K
C + 2Cload
(5.19)
Equation (5.19) represents a conservative approximation in terms of the Z-source
breaker operation because the capacitor current is underestimated and the inductor
current is overestimated. In addition, the contribution of the inductor current relative
to the capacitor current on the third order term is exposed. In order to achieve the
133
minimum detectable fault ramp rate limit derived in the previous section, the inductor
current must be negligible compared to the capacitor current. Thus, the following
relationship must hold
1 .'C+ 2 Coad\
L>>- 6K
C
(5.20)
Plugging in K,,i from (5.15) into (5.20) gives a minimum inductance required that
would ensure the inductor current can be safely ignored for all detectable fault ramp
rate K.
L
12e
load
C
(5.21)
Choosing an inductor approximately 10 times the limit derived in (5.21) gives the
following expression for inductor sizing.
Li
=1
R2
-C
(5.22)
Equations (5.21) and (5.22) uncover an interesting relationship between the Zsource inductance and the load resistance. The inductance requirement can actually
be relaxed as the nominal load increases, i.e., as the nominal load resistance decreases.
Furthermore, it is shown that the required inductance is directly proportional to the
Z-source capacitance.
Fig. 5-7 summarizes the relationship between the minimum detectable fault magnitude and the fault ramp rate. As expected, the minimum detectable fault magnitude
increases as the fault ramp rate increases. The minimum detectable fault ramp rate is
shown as the point when the required fault magnitude blows up. With the capacitor
ratio fixed at 5, the minimum detectable fault magnitude at high ramp rates is expected to be 11. The effect of the absolute capacitance on the minimum detectable
fault ramp rate is shown by comparing the solid blue and solid red curves.
The inductor sizing equation is verified by comparing the minimum detectable
fault ramp rate using three different Z-source inductances. Very little improvement in
minimum detectable fault ramp rate is achieved even when increasing the recommended
inductor size from (5.22) by a hundredfold. Nevertheless, decreasing the recommended
134
Minimum Detectable Fault Magnitude vs Ramp Rate (Cload/C = 5, R = 6Q)
60
C = 20 F, L = Lmin
.......... C = 200 F, L = 0.1Lr
55
.)
50--
C = 200 F, L = 100L
- --
L
45-
I
C = 200 F, L = L
-
40
-'6CE
35
---- --- --
-
E
4)
30
I I
20
I
,
-
-r-
-
25--
-
15
- --
.
-__.__ ._
10
10
)
Fault Ramp Rate K
106
(s-1Q- 1
Figure 5-7: Minimum detectable fault magnitude vs. fault ramp rate with fixed load
to Z-source capacitor ratio of 5 and a load resistance of 6 Q.
135
inductor size by a factor of ten causes a much more significant change in the minimum
detectable fault ramp rate as illustrated in Fig. 5-7.
5.2.4
Constant Power and Resistive Loads
In the above formulation, the load current is assumed to be constant during the fault
interval. However, in practical systems, a constant power load with high enough
bandwidth would draw additional current as the output voltage drops.
On the
other hand, a resistive load would draw less current as the output voltage drops.
To characterize the effect of this change in current on our analysis, the differential
equation in (5.9) is modified to incorporate the additional current contribution.
dvut
load dt
_
2 C0oad
C + 2C
.
-
K t
Vsource - V"o
Rioa
(5.23)
.
0
The plus-minus accounts for both constant power load and resistive load cases. In
particular, the plus sign with additional current draw corresponds to the case with a
constant power load with sufficiently high bandwidth, and the minus sign with less
current corresponds to the case with a resistive load.
The solution to (5.23) is shown as a Taylor series, again to avoid working with
non-closed form solutions and to illustrate the effect of having a finite load resistance
Vout=
Vsource
Vsource
+Vue
2 -t
K - t2
C + 2Cload
3. (C + 2Coad) - Rioaj
K 2 -0t
2
3 K - (C + 2 22 (CK-2
+ 2Coa)2
Caod) - R2a
+o (t5)
(5.24)
Comparing (5.24) and (5.16), it can be seen that the magnitudes second terms in the
parentheses must be negligible compared to 1 in order for the results derived under
the constant current load assumption to be valid. After rearranging by factoring out
136
the
Road
terms, these relationships can be written as:
Rjoad
Rjoad >
>
2
3 - (C +
2Coad)
2
V 3K - (C +
2Coad)
(5.25)
(5.26)
For the time period of interest, i.e., the fault interval, (5.25) can be written in terms
of the fault resistance and the fault ramp rate
2
Rload >2
3. (C +
2Coad) - K
. Rjault
(5.27)
Using the minimum detectable fault ramp rate and the minimum detectable fault
magnitude, (5.27) can be simplified to
1
C
I >> - 3e C + 2Coad
(5.28)
which is guaranteed to hold regardless of the actual nominal load resistance. Using
the component value from the previous section, the current contribution from the
change in load current is only about 1.1% of the total fault current.
A similar condition can be derived from (5.26) by using the minimum detectable
fault ramp rate, as illustrated in (5.29).
1 >
1
C
1.
2
V/ V' C+ Coad
(5.29)
Again, the inequality in (5.29) will always hold as the constant term is guaranteed to
be less than one. If the Z-source capacitance is on the same order or less than the
load capacitance, the current contribution from the load is constrained to about 10%
of the total fault current. Using the component values from before, the constant is
evaluated to be 3.2%, which is negligible.
137
5.2.5
SCR Reverse Recovery Time
To ensure complete turn-off of the SCR after a fault interruption, sufficient time must
be available for the SCR to undergo its proper reverse recovery process. Specifically,
the turn-off time of the SCR must be shorter than the time it takes the L-C resonance
to create a forward bias on the SCR. To the zeroth order, the available time can be
approximated by the L-C circuit resonance alone as discussed in [52].
However, the previous approach does not capture the initial conditions set by
source voltage and the nominal load current. Using the series-connected Z-source
breaker as an example, as the breaker responds to a fault with the SCR open-circuited
and the output shorted, two sets of L-C resonances will begin simultaneously. The
series capacitor initially holds zero voltage and will be charged to the source voltage
while the shunt capacitor initially holds the source voltage and will discharge through
the second Z-source inductor. By symmetry, the SCR will become forward biased as
the capacitor voltages reach half of the source voltage. Using the initial conditions,
the available turn-off time can be calculated to be
)
22+ vT73 \
to1 imax =
where
Q is the
2
4Q
v LU - cos' 2Q 2 +
1+ 4Q2
(5.30)
quality factor as defined in (5.2) and captures the effects of the initial
conditions by taking the load resistance into account.
The criteria in (5.30) provides additional considerations for sizing the Z-source
inductors and capacitors. Given a system with particular a set of source voltage and
nominal load current, and a SCR capable of carrying such load current and its turn-off
time, the Z-source inductor and capacitor must also be sized large enough to ensure
sufficient turn-off time for the SCR.
SCRs are still some of the most capable high power devices available, and SCRs
that can block a high voltage and carry a large current are readily available. When
scaling the Z-source breaker to higher power levels with higher rated voltage and
currents, the larger SCR may require a longer turn-off time. Hence, the Z-source
inductance and capacitance must be sized up accordingly. In general, if the inductance
138
and capacitance are kept to the same order, their required orders of magnitude can be
quickly estimated from the SCR turn-off time. To illustrate the scaling capability, let's
use the MVDC system component values mentioned in Section 5.1.1 as an example,
and an ABB 5STP 12K6500 SCR may be used. It has a peak voltage rating of 6.5 kV,
an average current rating of 1.2 kA, and a turn-off time of 800 As, which means the
required inductance and capacitance can be estimated to be on the order of 800 IH
and 800 pF respectively.
To keep the overall breaker volume small, it is also possible to utilize multiple
fast-switching SCR devices, which are typically only available at lower voltage ratings,
to construct a fast SCR switch stack [58]. For the MVDC system mentioned above,
the SCR can be constructed by a series stack of four ABB 5STF 14F2063 thyristors,
which is each capable of blocking 2 kV and carrying 1.44 kA. The assembled unit can
achieve a voltage rating of 8 kV, while achieving a fast turn-off time of 63 ps. This
allows more than an order of magnitude reduction in both inductive and capacitive
energy storage requirements.
While the above analysis was presented in the context of the series-connected
topology, similar derivations can be performed for the crossed and parallel-connected
topologies. As expected, these derivations would lead to the same result shown in
(5.30), since the principle of operation is the same across all three topologies.
5.2.6
Reflected Fault Current
The amount of reflected fault current at the source is greatly reduced by adopting
the series-connected Z-source topology. Nevertheless, it remains an important consideration when designing and sizing the inductors and capacitors for the Z-source
breaker. It also provides additional design guidelines for input filter and energy storage
requirements.
As discussed in the previous section, once a series-connected Z-source breaker has
tripped after the output is shorted to ground through a fault, the L-C circuit begins
to resonate. The source-connected inductor current will continue to increase to charge
up the series capacitor until the voltage across the series capacitor reaches the source
139
voltage. Using the initial conditions, the peak source-connected inductor current can
be calculated to be
Isource,peak
where
Q is
-
source
Rload
1 +
4Q 2
(5.31)
again the quality factor as defined in (5.2). The square root term can
be defined as the overshoot factor. The quality factor is shown to be an important
characteristic of the Z-source breaker. It not only describes the filter damping factor,
impacts the SCR reverse recovery time, but also dictates the amount of source current
overshoot under fault conditions. Equation (5.31) can be interpreted as a sizing
requirement for the Z-source inductor after selecting a Z-source capacitance. That
is, the inductance must be sufficiently large to keep the quality factor low, so that
the peak current overshoot does not exceed the maximum current rating of the input
source.
Finally, the reflected fault current at the source for a parallel-connected breaker
topology is the sum of the Z-source inductor and capacitor currents. Hence, the peak
overshoot factor for a parallel-connected topology is 2 -
1+ 4Q 2 , twice as large as
the series-connected topology.
5.3
Extended Protection Schemes
From the previous section, it is clear that the Z-source circuit breaker can only protect
against faults that exceed both the minimum detectable fault magnitude and the
minimum detectable fault ramp rate thresholds. These faults are the most critical
type and it is an inherent advantage of the Z-source breaker that they can be handled
autonomously. However, this only covers a subset of faults that can occur in practical
systems. Additional detection and triggering schemes must be introduced to the
Z-source circuit breaker to protect power systems from faults that satisfy only one or
none of these two criteria.
140
IC
L
SCR
C
DUcA
L
ISCR
am....
C
Rm,
V...
IAF
TUAF
(a)
11 IC
SCR
L
RMRae
C
C
L
mm
-)
Rf..11
IAF
V..,
UAF
C.
T
R a,,
T
(b)
Figure 5-8: Two ways of manually tripping the Z-source breaker. (a) inducing an
external artificial fault near the output and (b) inducing an internal artificial fault
within the Z-source breaker.
5.3.1
Manual Tripping of Z-Source Breaker
It is possible to trip the Z-source breaker manually via an artificially induced fault current. A sufficiently large and fast artificial fault current can force current commutation
of the Z-source SCR. This can be accomplished by introducing additional controlled
or semi-controlled devices into the breaker topology. The main artificial fault inducing
mechanism must also be able to turn off safely after the SCR commutation occurs,
i.e., the artificial short must not form a direct dc path from source to ground after
turning on.
Two embodiments are illustrated in Fig. 5-8 where the additional components for
141
manual tripping are shown in blue. In Fig. 5-8a, the artificial fault, with magnitude set
by current limiting resistor Rimit, is induced at the same point where a natural fault
would typically occur. This will be referred to as an external artificial fault. Moreover,
it would be counter-productive if the induced fault is divided between the load and
Z-source capacitors - the artificial fault current must again be 11 times the nominal
load current using the component values in the previous section. Consequently, a
blocking diode Dbl, 0 k is inserted into the design.
With the blocking diode present, the required artificial fault current becomes
independent of the capacitor ratio and is reduced to twice the nominal load current.
This can be understood by considering an artificial current larger than the nominal
load current. By KCL, the artificial fault can sink current from three places: Z-source
inductor, blocking diode, and Z-source capacitor. If the artificial fault current is larger
than the nominal load current, it would have steered away the full Z-source inductor
current, leaving no current through the blocking diode. The remaining current of the
artificial fault must then come from the Z-source capacitor conduction path. The
Z-source breaker would trip if the remainder current is at least as large as the nominal
load current, thus arriving at the artificial fault current requirement of twice the
nominal load current.
The artificial fault inducing element UAF can be either a power transistor or
an auxiliary SCR. In this arrangement, the fault inducing element does not form
a direct dc path to ground once the Z'source SCR commutates off. So the current
through in the artificial fault path will naturally decay to zero, allowing the transistor
implementation to be turned off safely and the auxiliary SCR implementation to turn
off naturally once the current drops below the SCR holding current.
In efficiency constrained designs, the additional diode conduction loss from the
blocking diode during normal operation may be seen as a disadvantage. A different
embodiment of the manual tripping circuit is proposed and shown in Fig. 5-8b to
induce an internal artificial fault current. In this configuration, the portion of the
induced fault current through the Z-source SCR, anti-series with the nominal load
142
current can be found to be
ZSCR,AF =
C + C0load
20
C+
Ioad
.AF
(5.32)
The capacitive divider in (5.32) has a minimum of one half and a maximum of one.
Hence, having an artificial fault of twice the nominal load current would guarantee
that the Z-source breaker can be properly tripped to isolate the source.
The artificial fault inducing element UAF can again be either a power transistor
or an auxiliary SCR. The auxiliary resistor and capacitor are introduced to prevent
the fault inducing element from forming a direct dc path to ground with the Z-source
inductor. When an auxiliary SCR is chosen as the fault inducing element, the auxiliary
resistor is chosen so that the current (Vsource/Raux) is less than the holding current
of the auxiliary SCR. The auxiliary capacitor is then used to set the duration of the
induced fault interval.
During normal operation, the auxiliary SCR is turned off and the auxiliary capacitor
is completely discharged by the parallel auxiliary resistor. When a fault is detected,
the auxiliary SCR is turned on to draw a surge of current to force commutation of the
Z-source SCR. This current drawn by the auxiliary SCR will gradually decrease as the
auxiliary capacitor is charged up. Once the current level drops below the SCR holding
current, the auxiliary SCR would naturally turn off and the auxiliary capacitor would
start to discharge through the auxiliary resistor again, resetting the trip mechanism.
Similarly, a power transistor can be used as the fault inducing element. The
power transistor is turned on for a fixed amount of time to force the Z-source SCR
commutation. In this case, the capacitor is chosen to set decay constant to ensure
that the current through the power transistor is sufficiently small by the end of the
fixed artificial fault interval, allowing the transistor to be turned off safely.
While both embodiments shown in Fig. 5-8 require an artificial fault current of
only twice the nominal load current, i.e., the current-limiting resistor should be half
the nominal load resistance, a greater artificial fault current may be needed in practice.
For example, any delay in the fault detection and actuation control loop translates
143
into time for the Z-source inductor current to increase from its nominal load level,
raising the amount of current required to trip the breaker.
To verify the efficacy of the two proposed manual trip modes, two simulations are
presented in Fig. 5-9, where the waveform variables are as labeled in Fig. 5-8. The
simulated system has a source voltage of Vsorce = 6 kV with a maximum load power
of 6 MW, i.e., a load resistance of Road = 6 Q. The load capacitance is assumed to
be Coad
=
1 mF, and the series-connected Z-source topology is adopted with design
values of C = 200 pF and L = 2.4 mH.
In the simulation presented in Fig. 5-9a, the external artificial fault inducing
mechanism from Fig. 5-8a is used with a current-limiting resistor of 2 Q. A value
less than half the nominal load resistance is used to provide some margin in case the
Z-source inductor current was given time to deviate from the nominal load level. The
system experiences a transient fault of Rfalt = 6 Q at 100 As, which is not sufficient
to trip the Z-source breaker automatically; only a small dip in the SCR current is
observed. However, by inducing an external artificial fault, the breaker can be tripped
successfully to isolate and protect the source as shown in Fig. 5-9a. Manual tripping
occurs near 200 ps to emulate a 100 /s delay in the fault detection and actuation
control loop.
Similarly, the internal artificial fault inducing mechanism from Fig. 5-8b is used in
the simulated fault clearing waveforms shown in Fig. 5-9b. A current-limiting resistor
of 2 Q is again used in this system. The auxiliary capacitor is set to be 200 pF to set
the fault interval time constant to 0.4 ms and the auxiliary resistor is set to 6 kQ to
limit the turn off current to be 1 A. The system again experiences a transient fault of
Rfault = 6 0 at 100 ps, and the internal artificial fault is induced at 200 As. The sum
of 1c and IAF can exceed IL in this configuration because additional current is drawn
from the source as illustrated in Fig. 5-9b.
5.3.2
Dual-Mode Fault Detection
With means of manually tripping the Z-source breaker, additional fault detection
schemes can be incorporated to protect against the types of faults that the Z-source
144
-
-
1.5
I
source
-
.............. I,
0.5-
0
0.5
0.25
0.75
1
1.25
1.5
1
1.25
1.5
Time (ms)
4
0
CO)
-2
-6
0
0.25
0.5
0.75
Time (ms)
1.5
c ........ I--.............
0.5-.I 0.5
0
0
-------............
-*L*----
0.25
.....--------
......
0.5
0.75
Time (ms)
(a)
145
1
1.25
1.5
1.5
1
C
..........
SCR
-
0.5
U)
.................................................................................................
0
)
0.25
0.5
0.75
Time (ms)
1
1.25
15
0
0.25
0.5
0.75
Time (ms)
1
1.25
1. 5
1
1.25
1.5
2
1
U)
0
-1
0 -2
-
C,,
13
1.
C
L
.......... 'C 'AF
0. 5A
I--
0
0.25
0.5
0.75
Time (ms)
(b)
Figure 5-9: Fault clearing waveforms using manual tripping methods: (a) external
artificial fault current and (b) internal artificial fault current.
146
IC
L
FSCR
C
L
ISCR
I...
IL
Rd..p
C
V sou e
Current
Rp
A ctua tio n
Signal
Sense
Fa u lt
Detection
Rfau&
C d 1,a R
jd
d/dt Sense
Figure 5-10: Fault detection sense nodes in a Z-source circuit breaker.
breaker cannot deal with autonomously. Analogous in some respects to a thermalmagnetic breaker [59], faults in the power system can be detected using two methods:
dI/dt and absolute magnitude I.
Fig. 5-10 illustrates the points of detection within a Z-source breaker. Instantaneous
current surges can be detected by monitoring the voltage across a small inductor
or a transformer winding placed in series with the high-frequency conduction path,
because this voltage is proportional the rate of change in current. The small sense
inductor must have a much lower inductance than the Z-source inductors in order to
minimize its effect on normal Z-source breaker operations. The voltage across the
small inductor in relation to the linearly ramped fault current can be approximated as
Vsense = -Lsense
* Vsource - K -
C
C + 2Cioad
(5.33)
Even though the sense voltage is negative from a sense inductor, a transformer-based
sensing scheme can easily flip the polarity while providing gain or attenuation as
needed. Assuming the load is regulated and given the control bandwidth of the power
regulator, the maximum current change rate induced by the controller is known. Any
faster changing current transient should be classified as a fault, and the detection
threshold can be calculated using (5.33).
Longer-term over-current conditions can be detected by monitoring the current
through the Z-source inductor. This can be accomplished in various manners, two of
147
which will be discussed here. First, a high-side current sense resistor circuit can be
placed in series with the Z-source inductor. This allows for accurate current reading
at the cost of additional power loss and lack of galvanic isolation. Second, in power
systems where efficiency is constrained or galvanic isolation is desired, a Hall Effect
current sensor may be used in place of the current sense resistor.
A final simulation illustrates the effect of the sense inductor and verifies the
approximation in (5.33). The same Z-source component values are used, and the
system experiences a transient fault of Gfault = 5 Q-' with a fault conductance ramp
rate of K = 50,000 s-'Q-1. Note that this fault is detectable and will trip the Z-source
breaker automatically.
The simulated results shown in Fig. 5-11 compare the fault clearing waveforms
with and without an additional sense inductor of 2.4 ptH placed in the high-frequency
conduction path as illustrated in Fig. 5-10. The sense inductor is chosen to be 3 orders
of magnitude smaller than the Z-source inductor. As shown in Fig. 5-11, the fault
clearing waveforms are nearly identical during the fault interval. The sense inductor
voltage is shown to exceed the calculated value of -65 V from (5.33) due to higher
order effects. Thus, the approximation in (5.33) is conservative and the detection
system will not make false negative type errors.
5.4
Experimental Validation
A series-connected Z-source circuit breaker experimental prototype was designed and
constructed to further validate the proposed breaker topology as well as the presented
design equations. The low-power prototype was designed for a 490 W system with an
input voltage of 35 V and a nominal load current of 14 A. In other words, the nominal
load resistance is set to be 2.5 Q. After selecting an SCR capable of carrying the
nominal load current, the Z-source components are sized using the design equations
in Sections 5.1 and 5.2, and the manual trip sub-circuit is designed based on the
discussion in Section 5.3. The fabricated experimental PCB prototype is shown in
Fig. 5-12, and the detailed component values are outlined in Table 5.2.
148
4
2
(D
0)
-
-
- w/o Lsense
----VSR -with Lsense
1
1.25
0
-2
-4
-6
-VSCR
CO
0
0.25
0.5
0.75
Time (ms)
1
C
a)
1. 5
ISCR - w/o Lsense
-------
0.5
SCR - with Lsense
0
0
0
Co
0
0.25
0.5
0.75
Time (ms)
1
1.25
1. 5
2
1.5
1
C
IL - w/o Lsense
0.5
---
0
C
0
0.25
-
C
2
0
a)
C
I
1.25
- ------
1
L-w/oL
S
- sense
IC- with Lsense
0
)
0.25
0.5
0.75
Time (ms)
1
1.25
1 5
100
0>
Vsense
*
50
(DC/)CU
1. 5
0.5
0
0.
I
1
U'
I'
I'
0*
-50-
~
~
'I
ii
II
'I
---------~
-
(D
0.75
Time (ms)
1.5
*d)
(U
0.5
IL - with Lsense
-------------
'4
-100
0
0.25
0.5
0.75
Time (ms)
1
1.25
1 5
Figure 5-11: Fault clearing waveforms demonstrating negligible effects from the current
sense inductor on the normal operation of the Z-source breaker.
149
c-fl
Figure 5-12: Photograph of the series-connected Z-source breaker experimental prototype.
The circuit was characterized in the laboratory using an HP 6012A dc power
supply. A Tektronix TDS3014B with Tektronix A6303 current probes are used to take
current measurements. An instantaneous fault is simulated by turning on a MOSFET
switch to short out the output of the breaker. Different fault conditions are simulated
by adding a fault resistor to control the fault conductance and a fault inductor to
control the fault ramp rate in series with the MOSFET.
Fig. 5-13 validates the notion of the minimum detectable fault magnitude and the
minimum detectable fault ramp rate. The manual tripping mechanism is disabled for
this part of the experiment to observe whether the Z-source breaker can automatically
trip on different fault conditions. The fault ramp rate K is approximated by adding a
series fault inductor with an inductance of 1/K. The experimental data points are
plotted with the derived limits from Section 5.2. The measured results match well
with analytical prediction. Only one corner case in the auto-trip zone failed to trip,
which can be attributed to using inductors for emulating the desired ramp rates. The
R-L combination conservative approximates the fault ramp rate - the fault current
ramps exponentially to the final value, which means the effective ramp rate is actually
slower. With experimental validation, the derived limits provide a simple framework
for designers to quickly evaluate the autonomous protection zone when designing a
Z-source circuit breaker.
Fig. 5-14 shows the fault clearing waveforms of the series-connected Z-source
breaker prototype. The measured SCR turn-off time of approximately 75 As can be
verified with (5.30) and the measured peak source current overshoot factor of 2.4 can
be compared with (5.31). The peak source current overshoot factor is larger than the
calculated factor of 2.0, and the discrepancy can be explained by accounting for the
inductor core material property. Specifically, the inductance factor AL derates under
large DC (amp-turn) bias condition. By including the 70% derating in the SPICE
simulation, the measured and simulated results are shown to be in good agreement.
Finally, the efficacy of the manual trip mechanism is validated. The internal
artificial fault current method is adopted to avoid introducing additional loss by
adding an additional SCR in the main conduction path. Fig. 5-15 illustrates the
151
Table 5.2: Detailed Experimental Prototype Components
IT(AV)
35 A
tq
35 ps
VDRM
400 V
C
Capacitance
ESR
100 pF
3 mQ
L
Inductance
200 pH
'SAT
31 A
Resistance
2.5 Q
ID
180 A
RDS(on)
3.4 mQ
ITSM
550 A
'H
60 mA
Rimit
Resistance
820 mQ
Raux
Resistance
1.2 k2
Caux
Capacitance
20 pF
SCR
Rload
Fault
UAF
152
Minimum Detectable Fault Magnitude Ns Ramp Rate - Experimental
30
-
25
--
0
0
Analytical Asymptotes
Auto-Tripped Fault
Untripped Fault
----------
0
20
c
-o-
-ng
j
15
-- --- ----
EUt
0
-
E
0
10
--
-
-
E
0
-0
0----
5
o
0U
L3
0
10
00
-0
0
.
I I I
106
Fault Ramp Rate K (s-1 0-1)
Figure 5-13: Experimental validation of the calculated minimum detectable fault
magnitude and the minimum detectable fault ramp rate.
153
- -
-r-
-
10
0
---
--
-L-
-
L--
-----
P__
---------
.
-
-
0.1
0.2
0.3
I
I
0.4
0.5
I
0.6
I
0.7
0.8
0.9
1
Time (ms)
C,,
0
20
I
I
-20
0
-r0.1
0.2
0.3
I-
---
0.4
0.5
0.6
Time (ms)
~
0 .7
0.8
--
F
-
0
-10- -7-
-
0 ----
I
I
0.9
25
-15
-35
~
-
I-
' ~
""
-
-
-
-
~
I-
-4-
I
-- I-
-
C,,
-
-
-K-
0
-
~F ~
~
LK
~~
0
0.1
0.2
0.3
0.4
0.5
0.6
Time (ms)
0.7
0.8
0.9
1
0
0.1
0.2
0.3
0.4
0.5
0.6
Time (ms)
0.7
0.8
0.9
1
30
0
30
20--0
1
10--- ---10
---
-
--.-5
1
0
0.1
0.2
0.3
- .-
.L.
-
0
-
-J
-
--
-
10
I~,)
-
IS
-
30
20 - -
--.
0.4
0.5
0.6
Time (ms)
0.7
0.8
0.9
1
Figure 5-14: Measured fault clearing waveforms (solid blue) of the series-connected
Z-source breaker prototype compared to simulation (dashed red).
154
manually tripped Z-source breaker waveforms.
The measured result shows good
matching compared to the SPICE simulation. The extension enables the breaker
to protect against any kind of fault, not just the ones that exceed the minimum
detectable fault magnitude and ramp rate.
5.5
Summary
The Z-source circuit breaker topology has promise in protecting against faults in dc
power distribution systems by creating a natural current zero-crossing. This breaker
could be evaluated and modified to enable protection for all sorts of dc distribution,
including renewable energy generation arrays such as photovoltaic and other microgrid
applications.
This chapter presents a comprehensive analysis and design methodology of the
Z-source circuit breaker and proposes a new series-connected topology to maintain a
common ground connection while mitigating the problem of reflected fault current
at the source. In addition, with the formulation of the minimum detectable fault
magnitude and ramp rate, designers can analyze the autonomous protection zone of a
Z-source breaker design. The Z-source can be designed to handle normal load steps,
instead of mistaking a large change in the load current for a fault. Manual tripping
mechanisms along with fault monitoring methods are introduced to enable dualmode protection against both instantaneous large surges in current and longer-term
over-current conditions.
155
30
10
0
a)
0.1
0.2
0.3
0.4
I
I
0.3
0.4
0.5
0.6
Time (ms)
0.7
0.8
II
0.9
1
0.9
1
20
II
I
I
I
0.5
0.6
0.7
0.8
_F
I
10K
20 -O- wI- I I I 1
-10
0
0.1
0.2
Time (ms)
Co
r%
~I
-5 - - -- -25
0
I
--
0.1
-
0.2
I
-
I
-
- -
0.3
0.4
I
-
--
0.5
0.6
0.7
_r _
-
0.8
-
-
0
0.9
1
Time (ms)
'
--
20
I
10
0-10
0
0.1
0.2
0.3
0.4
I
%7 7 7 7
0.5
0.6
0.7
0.8
0.9
I
I
1
Time (ms)
25
I
I
I
I
I
5---I
I
-5
0
-----
I
I
-_L
L-----------
-5
0.1
I
I
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Time (ms)
Figure 5-15: Measured manually tripped waveforms (solid blue) of the series-connected
Z-source breaker via an internal artificial fault current compared to simulation (dashed
red).
156
Chapter 6
Conclusion
The central theme of this dissertation is examining simple, circuit-based techniques
that improve efficiency, performance, and reliability of a power system. Specifically,
this thesis explores the design space and highlights opportunities for optimizations at
different stages of power processing in a solar photovoltaic power generation system.
The work presented spans various stages of solar power processing, from the cell-level
to the string-level power electronics.
An underlying motivation of this thesis has been to reduce the high levelized cost
of solar energy, which has been a barrier of adoption for renewable energy sources, in
order to further drive grid-penetration. The levelized cost of energy can be improve in
two ways: maximizing the energy generation and extraction of the power system and
minimizing the cost of ownership of the power system over its entire lifetime. In order
to maximize the energy generation and extraction, scalable and cost-effective power
optimization techniques are needed to enable finer power optimization granularity.
Energy extraction can be further improved by reducing the amount of power that
needs to be processed by power converters, since practical power electronics have
nonzero conversion loss. The cost of ownership can be minimized by improving system
reliability. By designing and deploying highly reliable power conversion systems, the
frequency of system downtime and the number of unscheduled maintenance events
can be minimized, which not only reduces the cost of ownership but also increases the
157
amount of energy extraction.
The thesis presentation was divided into four main chapters.
Chapter 2 has
developed in detail a new approach to perform power processing and optimization for
each and every solar cell without the use of any external passive components. The
chapter began with the theoretical background and experimental characterization of
the solar cell's diffusion capacitance, and demonstrated that this intrinsic storage alone
is sufficient for power processing. A scalable ladder-type cell-level power balancing
scheme, termed diffusion charge redistribution (DCR), was then illustrated to take
advantage of the diffusion capacitance while achieving a number of desirable features,
such as cell-level MPPT, convex output power characteristic curve, and low insertion
loss. This is the first time the intrinsic solar cell capacitance is used as the dominant
energy storage component for power processing. A complete analytical treatment
of the insertion loss, in both SSL and FSL regimes of a switched-capacitor power
converter, was also presented in the thesis to bound the insertion loss of the system.
The mono-crystalline example can achieve an insertion loss of only 3.5% without using
any auxiliary energy storage components. Despite the insertion loss, this technique
can potentially increase the improvement in energy capture by up to 30% from the
16% achieved by using the current state-of-the-art module-level power electronics.
With the global solar capacity projected to grow close to 60 GW in 2015, adopting this
technology can potentially increase the overall energy extraction by tens of GWs per
year. In addition, the cost of maximum power point tracking is reduced significantly
by not requiring external passive components. A 3-2 DCR experimental prototype
with 5 solar cells has been designed, constructed, and assembled to verify the benefits
of the proposed architecture. Experimental characterization of the prototype has
demonstrated the utility of cell-level MPPT. The overall output power is now directly
proportional to the percentage of area receiving solar irradiance, rather than being
limited by the lowest-performing cell in the string.
Chapter 3 has presented further circuit augmentation to the diffusion charge
redistribution technique. The proposed topology continues the use of diffusion charge
redistribution, which allows the use of partial MPPT converters without any external
158
energy storage components, while enabling differential power processing by introducing
a functionally-decoupled current divider interface at the string-level. This unique
combination achieves not only the finest maximum power point tracking granularity
at the cell-level and the minimum cost of power electronics without using any external
energy storage components, but also zero insertion loss with minimal added hardware
at the string or centralized inverter level power electronics. Adopting such a technique
can improve the overall conversion efficiency of the DCR topology by more than
3.5%, with the option to slow down the DCR switching frequency.
The current
divider interface also introduces an additional optimization degree of freedom; the
optimization can simultaneously maximize the power extraction from each and every
cell and minimize the amount of power processed through DCR. In addition to using a
discrete current divider module, the current splitting functionality can be realized by
using two string inverters. With proper inverter power ratings, this implementation can
also further improve overall system reliability. Mathematical analysis and computer
simulations have been developed to characterize the multi-variable optimization space
over both the output current and the current divider ratio, which is shown to be convex
over arbitrary shading conditions. An experimental prototype of the current divider
interface has been designed and assembled to augment the 3-2 DCR experimental
setup. Experimental characterization has verified a convex output power characteristic.
Chapter 4 has described an architecture for improving the energy utilization of
dc-link capacitors in dc-ac power conversion systems. Using a switched-capacitor
technique, the energy utilization of the dc-link capacitor can be improved to more
than 80% compared to an utilization of less than 20% achieved by a single capacitor
implementation given a 10% peak-to-peak ripple specification. This corresponds to a
reduction in energy storage volume by more than four times. In addition, with higher
capacitor energy utilization, ceramic and film capacitors with smaller capacitance and
lower voltage ratings can be used to replace the limited-life electrolytic capacitors
commonly found in existing systems, hence improving overall system reliability. This
can potentially enable these converters to be designed for hundred-year operation in
long-life applications. This has direct applicability in designing solar inverters, which
159
account for more than 37% of the unscheduled maintenance events and up to 59%
of the associated cost of repair and replacement. Through analytical modeling and
SPICE simulations, relevant design tradeoffs among stacked capacitor configurations,
switching topologies, and control algorithms have been examined. A new two-step
control strategy has also been introduced to mitigate undesirable transient responses
on the dc-link capacitor voltage by maintaining an appropriate number of capacitors
in reserve to guard against sudden transients in power level. These results should
serve as design guidelines for future experimental work in the area.
Chapter 5 has introduced a new arc-free dc circuit breaker based on the Z-source
topology. The newly proposed series-connected Z-source topology retains a common
ground between the power source and load, while minimizing the amount of reflected
fault current seen at the source by feeding the fault current from a shunt capacitor.
With its low-pass ac characteristic, the Z-source passive components can also act as
the input filter for power-electronic EMI suppression, leading to tighter integration
and a fewer component count. Comprehensive analysis and design methodology of
the Z-source circuit breaker have been developed to provide design insight and to
understand the limitations of the existing breaker topology. In particular, the Z-source
breaker has an associated minimum detectable fault magnitude and a characteristic
minimum detectable fault ramp rate. With the insights developed in.this thesis, the
minimum detectable fault magnitude and ramp rate can be designed to ensure system
survivability under severe fault conditions while preventing fault-trip during normal
load transitions. New techniques of manually tripping along with fault monitoring
methods have been presented for extending the protection range of the Z-source circuit
breaker by enabling dual-mode protection against both instantaneous large surges in
current and longer-term over-current conditions. This greatly extends applicability
and improves controllability of the Z-source breaker. A 490-W experimental prototype
was designed and constructed to demonstrate the automatic breaking capability and
the manual tripping techniques.
160
Appendix A
Diffusion Charge Redistribution
Hardware
* Schematic Drawings
* PCB Layout
* Bill of Materials
e Software Interface
161
A.1
x
W
1-0
1
U
1 0 1 0
N0000W
0U
H00060
30
03, 000
0
000
0
0
0
0
A
22
+1.
v0A
Schematic Drawings
-C
q(
aGA
aaA
1
aQA
zGA
9a
#0
1
h
h
0
a0A
.. A
a.A
n
G lA2.A
GGA
aaA
aaA
W
Figure A-1: The Eagle Cad® schematic of the 3-2 DCR.
162
Iii
"a
~ji
Is
A.2
PCB Layout
Figure A-2: The Eagle Cad® PCB layout of the 3-2 DCR.
163
Figure A-3: Top copper of the 3-2 DCR PCB layout.
164
Figure A-4: Bottom copper of the 3-2 DCR PCB layout.
165
m
Qty
Value
Device
Parts
H
1
470
R-USR0805
RI
CD
11
LSM115JE3
SCHOTTKY-DIODESMD
D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11
6
0.1uF
C-USC0805K
C1, C2, C3, C4, C5, C6
3
10uF
C-USC0805K
C16, C17, C18
0
3
luF
C-USC0805K
C13, C14, C15
~L
r-1
c~
o~
6
2.2uF
C-USC0805K
C7, C8, C9, C10, C11, C12
C
C
6
IRF9910
IRF9910
Q1, Q2, Q3, Q4, Q5, Q6
CD
3
MAX17600
MAX17600
U$1, U$2, U$3
3
PROBE
PROBE
U$8, U$9, U$10
5
SOLARCELL_2.5MA
SOLARCELL_2.5MA
U$4, U$5, U$6, U$7, U$11
4
TOBU3
TOBU3
X1, X2, X3, X4
1
LED 468NM BLUE
LEDSML0805
LED1
FE05-1
SV1
C
CD
1
0z
'mlw
A.4
Software Interfaces
A.4.1
FPGA Code
-
ThreePhaseGen. vhd
-
RDL to generate three- or two-phase non-overlapping clock for
-
--
solar DCR experiment.
The on-time and the deadband can be controlled in FrontPanel.
library IEEE;
use IEEE. std-logic_1164. all;
use IEEE. std-logic-arith. all;
use IEEE. std-logic-misc. all;
use IEEE. stdlogic-unsigned. all;
use IEEE. numericstd. all;
use work .FRONTPANEL. all;
entity ThreePhaseGen
is
(
port
hiin
in
STD_LOGIC VECIOR(7 downto 0);
hiout
out
STDLOGIC VECTOR(1 downto 0);
hiinout
inout STDLOGIC VECIOR(15 downto 0);
hi__muxsel
out
STDLOGIC;
clk1
in
STDLOGIC;
zbus
out
STDLOGIC VECIOR(13 downto 0);
led
out
STDLOGIC VECTOR(7 downto 0)
end ThreePhaseGen;
architecture
arch of ThreePhaseGen
is
167
type state-type
signal
(rst , si , offi , s2 , off2 , s3 , off3
is
state
:
);
state-type;
signal ti__clk
STDLOGIC;
signal oki
STD_LOGICVECTOR(30 downto 0);
signal ok2
SSTD_LOGICVECIOR(16
downto 0);
signal ok2s
STD_LOGICVECIOR(16
downto 0);
signal epOOwire
SITDLOGICVECIOR(15
downto 0);
signal ep20wire
STD_LOGICVECIOR(15
downto 0);
signal div
STD_LOGICVECTOR(23 downto 0);
signal count
STD_LOGICVECTOR(8
signal refcount
SITDLOGICVECTOR(8 downto 0);
signal ontime
SITDLOGICVECTOR(8 downto 0);
signal clkldiv
STDLOGIC;
signal reset
STDLOGIC;
signal disable
STDLOGIC;
signal phase3
STDLOGIC;
signal switch
STDLOGICVECIOR(2 downto 0);
downto 0);
begin
himuxsel
'0';
reset
epOOwire (0);
disable
epOOwire (1);
ontime
ep00wire(10 downto 2);
phase3
epOOwire (11);
ep20wire
("0000000" & count);
led
not ( "00000" & switch);
zbus
("00000" & (not switch (2)) & '0' & (not
switch (1))
& '0' & (not switch (0)) & "0000");
process
(clkl)
begin
if rising-edge(clkl)
then
168
if (reset = '1') then
state <= rst
elsif (disable = '0') then
case state is
when rst =>
state <= si;
count <= ontime;
refcount <= ontime;
when s1 =>
if count = 0 then
state <= offi
count <= std_
logic-vector (to-unsigned (5
,9));
else
state <= si;
count <= count -
"1";
end if;
when offI =>
if count = 0 then
state <= s2;
count <= refcount;
else
count <= count
-
state <= off;
end if;
when s2 =>
if count = 0 then
state <= off2
if phase3 = '1' then
count <= std.logicvector (to-unsigned (5 ,9));
else
count <= std-logicvector (to-unsigned (4 ,9));
end if;
else
state <= s2;
169
count <= count
-
'1';
end if;
when off2 =>
if count = 0 then
if phase3 = '1' then
state <= s3;
count <= refcount;
else
state <= rst
end if;
else
state <= off2
count <= count
-
'1';
end if;
when s3 =>
if count = 0 then
state <= off3;
count <= std-logic-vector(to-unsigned(4 ,9));
else
count <= count
-
state <= s3;
end if;
when off3 =>
if count = 0 then
state <= rst
else
state <= off3;
count <= count
end if;
when others =>
state <= rst
end case;
end if;
end if;
end process;
170
-
"1";
process (state)
begin
case
state is
when s1 =>
switch <= "001";
when s2 =>
switch <= "010"
when s3 =>
switch <= "100";
when others =>
switch <= "000";
end case;
end process;
Instantiate
okHI
:
the okHost and connect endpoints
okHost port map
(
-
hiin=>hiin , hi-out=>hiout , hiinout=>hiinout
ti
clk=>ti_clk , okl=>okl , ok2=>ok2 );
okWO
okWireOR
generic map (N=>i)
epOO
okWireIn
port map (okl=>okl,
port map (ok2=>ok2,
ok2s=>ok2s);
ep-addr=>x" 00" , ep-dataout=>ep00wire);
ep20
okWireOut
port map (okl=>okl,
ok2=>ok2s( 16 downto 0 ),
ep-addr=>x" 20" , ep-datain=>ep20wire);
end arch;
171
A.4.2
FrontPanel GUI Code
<?xml version=" 1.0" encoding='ISO-8859-1'?>
FPGA Interface for Solar DCR Experiment
FrontPanel GUI
<resource version=" 2.3.0.1 ">
<object
class="okPanel' name-"panell">
<title>Counters Example</title>
<size>230,170</size>
<!-
PLL22150 settings
These will only be visible when the attached device has
a 22150 PLL (XEM3001).
<object
class="okPLL22150">
<label>PLL1</ label>
<position>180,0</ position>
<size>40,15</ size>
<p>400</p>
<q>48</q>
<dividerl
source="vco">8</divider1>
<output0 source=" divibyn ">on</outputO>
<output1 source="ref">on</output1>
</object>
<!--
Three Phase Clock
Controls ->
<object class="okStaticBox">
<label>Three Phase Clock Controls</ label>
<posit ion>10,10</position>
<size>210,77</size>
172
</object>
<object
class="okDigitEntry">
<position>20,40</ position>
<size>72,30</ size>
<tooltip>Sets the on duration .</tooltip>
<minvalue>10</minvalue>
<maxvalue>500</ maxvalue>
<value>250</ value>
<endpoint>OxOO</ endpoint>
<bit>2</bit>
</object>
<object
class="okToggleCheck">
<label>_Reset</label>
<position>120,30</ position>
<size>60,20</ size>
<endpoint>OxOO</ endpoint>
<bit>O</bit>
<tooltip>Reset State Machine</tooltip>
</object>
<object
class="okToggleCheck">
<label>D</ label>
<position>120,60</ position>
<size>60,20</ size>
<endpoint>OxOO</ endpoint>
<bit>1</bit>
<tooltip>Momentarily
Disable
</object>
<object
class="okToggleCheck">
<label>3</ label>
<posit ion>180 ,60</ position>
<size>60,20</ size>
<endpoint>OxOO</ endpoint>
173
Switching</tooltip>
<bit>11</bit>
<tooltip>Enable Three-Phase Clock Generation</ tooltip>
</object>
Count Down States ->
<!-
<object
class=" okStaticBox">
<label>On Time Control</label>
<position>10,90</ position>
<size>210,70</size>
</object>
<!-
LEDs -- >
<object class="okLED'>
<posit i o n>15,125</ posit ion>
<size>25,25</size>
<label align="bottom">8</label>
<style>SQUAREk/ style>
<color>#ffO 0</ color>
<endpoint>0x20</endpoint>
<bit>8</ bit>
</ object>
<object class=okLED">
<posit ion>35 ,125</ position>
<size>25,25</ size>
<label align="bottom">7</label>
<style>SQUARE</ style>
<color>#00ffOO</ color>
<endpoint>0x20</ endpoint>
<bit>7</ bit>
</object>
<object class="okLED">
<posit ion>55 ,125</posit ion>
<size>25,25</ size>
<label align="bottom">6</label>
<style>SQUARE</ style>
<color>#00ffOO</ color>
<endpoint>0x20</endpoint>
174
<bit>6</ bit>
</object>
<object
class="okLED">
<position>75,125</ position>
<size>25 ,25</ size>
<label align="bottom">5</label>
<style>SQUARE</ style>
<color>#00ff00</ color>
<endpoint>0x20</endpoint>
<bit>5</ bit>
</object>
<object
class="okLED">
<position>95,125</ position>
<size>25,25</size>
<label align="bottom">4</label>
<style>SQUARE</ style>
<color>#00ffOO</ color>
<endpoint>0x20</endpoint>
<bit>4</bit>
</object>
<object
class="okLED">
<position>1 15,125</position>
<size>25,25</ size>
<label align="bottom">3</label>
<style>SQUARE</ style>
<color>#00ffOO</ color>
<endpoint>0x20</endpoint>
<bit>3</ bit>
</object>
<object
class="okLED">
<position>135,125</ position>
<size>25,25</size>
<label align="bottom">2</label>
<style>SQUARE</ style>
<color>#00ff0O</ color>
<endpoint>0x20</ endpoint>
175
<bit>2</ bit>
</object
<object
c I a s s ="okLED">
<posit ion>155,125</ position>
<size>25,25</size>
<label align="bottom">1</label>
<style>SQUARE</ style>
<color>#00ffO0</color>
<endpoint>0x20</ endpoint>
<bit>1</bit>
</object
<object
class='okLED'>
<position>1 75,125</position>
<size>25,25</ size>
<label align='bottom">0</label>
<style>SQUARE</ style>
<color>#00ffOO</ color>
<endpoint>0x20</endpoint>
<bit>0</bit>
</object>
</object>
</resource>
176
Appendix B
dDCR Current Divider Hardware
" Schematic Drawings
" PCB Layout
" Bill of Materials
" Software Interface
177
B.1
I~
U
I
lot
e
>
C
t
~
000~
0
~
80
t
0
~
II'~
~
~'.
~'LN!~I
<
I
Schematic Drawings
-..
+1
3
'I
<
-0
8
-J
z
II,~
CAI
U
H
&00
U
-
1~-09
i
-41
U
U
U
U
12
V2
0
C4
j
;zl
1
~'g~
'~~j'
U
0
U
U
'8
~
U
HU
+
U
HFHF-
1
Figure B-1: The Altium Designer® schematic of the dDCR current divider power
stage.
178
a A.N
~K2~
tvN
i
+1 -
2fldEII~
ILIA. 4 a A.0.
+I-
ANAJM
U
1
U)
-I
U
U
U
I'*
II,~
2
n
- -s
Zjii,;z
!
Figure B-2: The Altium Designer@ schematic of the dDCR current divider digital
control.
179
B.2
PCB Layout
3100.00 (mil)
0
(D0
0
0
0
Figure B-3: The Altium Designer® PCB layout of the dDCR current divider.
180
j
I
4 cl2U5
DCl
Q4
mU6
C1
DC
CIO
U7
05
C14
N
Fle
P13
9
DS ILI
I
_0
Adilk
U8
C30
l9
L)
-ti
C9
L
L
L2
L
E
0
9
P
P
-D
0
00
r--
0
c")
0
D4 P4
S4j
emme
C45
16
59 00.00 (miL
C4C
a)
Figure B-5: Bottom copper of the dDCR current divider.
182
B.3
Bill of Materials
Qty
Value
Device
Parts
2
47uF
CAPC2220(5750)255N
C8, C9
11
luF
CAPC0603(1608)100N
14
lO0nF
C10, C14, C18, C26, C27, C28,
C29, C30, C35, C40, C42
CAPC0603(1608)100_N
C11, C12, C13, C15, C16, C17, C19,
C20, C21, C31, C32, C33, C41, C43
4
10uF
CAPC0603(1608)100_N
C22, C23, C24, C25
1
22uF
TC7343-2917
C44
1
47uF
F Size Al Electrolytic
C45
2
33uF
CAPC1206(3216)190M
C46, C47
2
BLUE SiC LED
6-0805_L
D3, D4
4
MEU1S
MEU1S
DC1, DC2, DC3, DC4
1
SD2114SO40S5R0
D Schottky
DS
1
PJ-036AH-SMT
Power Supply Connector
Ji
4
10.OuH
WE-HCF-2013
L1, L2, L3, L4
2
HDR1X2
Header, 2-Pin
P7, P8
1
HDR1X5
Header, 5-Pin
PlO
1
1881558
Header, 2-Pin
P11
1
PCBlock_4
Header, 4-Pin
P12
1
PCBlock_2
Header, 2-Pin
P13
4
IRF9910
HEXFET Power MOSFET
Q4, Q5, Q6, Q7
2
470
J1-0603
R2, R4
4
10
RESC0603(1608)_L
R11, R12, R13, R14
1
EVQ-PE104K
Switch
S1
4
ADuM1100
ADuM1100
U4, U6, U8, U10
4
FAN3111
FAN3111
U5, U7, U9, U11
1
CYP-AX44-51-85064_N
PSoC
U13
Table B.1: dDCR Current Divider Prototype Bill of Materials
183
B.4
Software Interfaces
B.4.1
PSoC C Code
dDCR Current Divider Control
PWM 1
LED1
LEC
HFCLK_2
SWSPint1
Pin_2
>
24 MHz
8-bit (UDB)
Vs8
Vss
Debouner 1
SW
.0s4
Swint
VsS
Clock_2
The PWM outputs are used to modulate the current divide ratio. The
predetermined current divide ratios.
external switch generates an interrupt and cycle
through
Figure B-6: The Cypress PSoC@ top-level design of the dDCR current divider control.
#finclude <device .h>
uint8 count = 10u;
CYCODE const uint8 duty[] = {0,
20,
40, 60, 80, 100,
120, 140,
CY_SR(SwIntISR)
{
if (count < 10)
{
count++;
184
160, 180, 200};
} else {
count = 0;
}
PWM_1_WriteComparel (duty [count ] );
PWM_1_WriteCompare2( dut y [count ] );
}
int main()
{
SwIntStartEx(SwIntISR);
/*
Start all components */
PWM_1_Start () ;
PWM_1_WriteComparel (duty [count]);
PWM_1_WriteCompare2( duty [count ]);
CyGlobalIntEnable;
for (;;)
{
}
}
185
THIS PAGE INTENTIONALLY LEFT BLANK
186
Appendix C
Z-Source Circuit Breaker
Hardware
" Schematic Drawings
" PCB Layout
" Bill of Materials
" Software Interface
187
MANDU iOK2
_M3A
2.MAINOU
IL2
PADi
PAO13
2ad
IL2
To Load Resistor
PADi
PA02
)(-
MBP402
WIREPA04,1601
L2
L1
RK 16
6PAD
WIREPAD4,1601 6
PAD6
RKE16
1IBP402 0
0
01
U
02
P2
j
C6
WIPEPAD4,1601,6
CIBuF
i00uF
D
q:
T2
-t
0
WIREPAO4,1601,6
C
FAULT-OUT
ULA50E
*
0
c-t-
FC7
~OKI1
AUXV
P
200uFO:Ps_
PADS
PA07
00
0L2
N
0
PAD12
PAD11
a
20
FAULT
ILB4B3B
G
OUNT-HOLE5.5
'1
WOUNT-HOLE5.5
OUNT-HOLE4.
WOUNT-HOLE4.1
UNT-H0LE4.1
OUNT-HOLE4.1
K 6
Z-Source Breaker Demo
Arthur Chang, Brian Sennett, Steven Leeb
TITLE:
Inductors
DI
main-rev3.8
Power Section
Standoffs
REV:
Document Number:
3.0
Date: 7/22/2014
1:16:44
PM
Sheet:
1/3
CDq
.
....
. ....
1
0
(D
ciB
U$6
FAN3i111C
OUT
I IN+
(D
FAULTSI
+5U/1
IN-
D+
+
U$
to -CqN.
r,0
-B-
-
6-
0
23
'-_
P30
PO-4
PO.2
1uF
IC1B
WUAA-O
w 2 1P4-043
25
P8 .3
N5
24
+O
+5U/1
UD02
00
DI
wol
~~ ~
Q.
P13
XOU
74LS125N 240
U$2
2
)C
-
5 A3
(n
Z>
C
7
-UUT
u
-)
O -
M~~
5
C13i
t
e
C
iFP8.6
P2-2
P2-4 CY8C4125AXI-483
P2-5
P2_7
P2 7
o -pe
U3_k
C
'
UUT
aw.
Q.0I
B3
a
NC1 i63ENA
NC2
NC3
-6
7
-A
1
)C
00)
B21 A
A2
34
--U
050L
-A
A 2 1
LQ ai
-
FTDI-PXD-
U
GID
-VIN
325
FAULT_
2
1OuF
+IOUT
M a
XPES#
PO-7
P2-0
P2.1
5
19
luF
z
M
CO COCWN+VIN
(D
FTOI-TXD_
.uF
GND5 GND2/
G
D
3
CD
)
D nliniProg htea der
I
+5U/1
i~v
Bypass
IC
SPlace
for12 74LS125 buffer
close to power pin
i
O'2
Bypass for
deC.
C ontrol side
F
Si8630
Place close to
power pin
iC11
Po
uer
s ide
c.luF
1uF
0
C17
C8
C9
C16
luF 8.1uF B.1uF
iuF
Bypass for PSoC
Place close to power pins
D
(n
:>
U$5
2~ua
*O
L..lJI
Breaker Demo
Z-Source
Arthur Chang, Brian Sennett, Steven Leeb
TITLE:
main-rev3.0
Control Section
REU:
Document Number:
3.0
Date: 7/22/2014 1:16:44 PM
ISheet:
2/3
0
C)
CD
(D
P-.
D
IC2
Q3 Uccio
6
3M3UT
FTDI-TXD
TXD
RX
FTOI-RXD
(D
P9u
33nF
XTIN
O-te
14
COD
N
P14
27
15
27
V)
0)
-
N
C')
co
0
M3wff
211 XTOUT
PT
USSOP
USBOM1
TXDEN
TXLED
RXLED
M
U)
EEC:k
EESK
PWJRCTL
EEDATA
TEST
9=~l
PMlER
xi
+
Cr
No.
P18
AVCC
29AGND
470
CNM
GND
FT232BL
ci
C25
I.uF
0
(n
D
C24
Cf2
(D
iuF
21
22
0.1uF 0.1uF
C23
1uF
Bypass for FTOI chip
Place close to pouer pins
2-Source
Breaker Demo
Arthur Chang, Brian Sennett, Steven Leeb
0-a
TITLE:
main-rev3.0
FTOI USB-Serial
Document Number:
REV:
3.0
ISheet:
Date: 7/22/2014 i:i6:44 PM
..................................
11
.................
prww- --
-
--
--
--
-
-
-
-
:::
-:
-
I
-
3/3
-
-. I-'-
- -
-
I
C.2
PCB Layout
Figure C-4: The Eagle Cad® PCB layout of the Z-source breaker.
191
Figure C-5: Top copper of the Z-source breaker PCB layout.
192
Figure C-6: Bottom copper of the Z-source breaker PCB layout.
193
C.3
Bill of Materials
Qty
Value
Device
Parts
3
1O0uF
C-USC525X203-575X350
C1, C2, C6
1
200uF
CPOL-USE7.5-16
C7
7
0.luF
C-USC0805
C8, C9, C12, C18, C21, C22, C25
9
luF
C-USC0805
C10, C11, C13, C15, C16, C17, C19, C23, C24
1
33nF
C-USC0805
C14
1
10uF
C-USC1206
C20
2
MBR40250
BYT08P
D1, D2
2
MOUNT-HOLE5.5
MOUNT-HOLE5.5
H1, H2
4
MOUNT-HOLE4.1
MOUNT-HOLE4.1
H3, H4, H5, H6
1
74LS125N
74LS125N
IC1
1
FT232BL
FT232BL
IC2
2
RKE16
RKE16
L1, L2
LEDCHIPLED_0805
LED1
1
2
IL420
IL420
OK1, OK2
14
WIREPAD4,1601,6
WIREPAD4,1601,6
PAD1, PAD2, PAD3, PAD4, PAD5, PAD6, PAD7, PAD8,
PAD9, PAD10, PAD11, PAD12, PAD13, PAD14
1
IRLB4030
PMOSFETNTO22OBV
Q1
1
CSTCR6MOOG53Z
CSTCR6MOOG53Z
Q2
2
0.02
RKWP330
R1, R2
2
20
R-US_0207/10
R3, R4
1
0.82
RKH208-8
R5
1
620
R-US_0207/10
R6
1
250
R-USR0805
R10
1
200
R-USR0805
R11
2
240
R-USR0805
R12, R13
2
27
R-USR0805
R14, R15
1
4.7K
R-USR0805
R16
1
10K
R-US_R0805
R17
1
470
R-US_R0805
R18
1
1.5K
R-USR0805
R19
1
iM
R-USR0805
R24
MA05-1
SV1
1
2
CLA50E
CLA50E
T1, T2
1
CY8C4125AXI-483
CY8C4125AXI-483
U$1
1
S18630SO16W
S18630SO16W
U$2
1
MURATA-NTE
MURATA-NTE
U$3
1
OSTTC022162
OSTTC022162
U$5
1
FAN3111C
FAN3111C
U$6
1
MINI-USB-32005-201
MINI-USB-32005-201
Xl
Table C.1: Z-source Breaker Prototype Bill of Materials
194
C.4
Software Interfaces
C.4.1
PSoC C Code
Serial
Communication
SCR and MOSFET
Drive Logic
Timer Main
un
Clock_1 UL
>ckoek
i
UART_1
Timer Aux
7v un
----
Pin 2
Standard
Timer Fault
Ov
un
o Pin_3
cvv
_f
nterrupt
Figure C-7: The Cypress PSoC® top-level design of the Z-source breaker control.
#include <project .h>
uint8 serval(void);
int main()
{
void UART_1_Start (;
while (1)
{
195
uint8 serval = UART_1_UartGetByte(;
switch
(ser-val)
case
{
0:
TimerMainStop (;
TimerAuxStop ();
TimerFaultStop (;
break;
case
1:
TimerAuxStop (;
TimerFaultStop (;
TimerMainStart (;
break;
case
2:
TimerMainStop (;
TimerFaultStop (;
TimerAuxStart (;
break;
case
3:
TimerMainStop (;
TimerAuxStop ();
Timer_F ault__Start (;
break;
default:
TimerMainStop (;
TimerAuxStop ();
TimerFaultStop (;
break;
}
}
}
196
C.4.2
MATLAB Code
function s = open-ser(port)
106 WM Port Handling
portstr = int2str(port);
%Convert WM Port arg to string
ports=instrfind ;
% Close all open serial ports
if size(ports,1) > 0
disp( 'Closing, serial Uport openUfrom previous Lrun. ');
stopasync ( instrfind);
( instrfind);
delete ( instrfind);
fclose
end
% Determine Serial Port Path (Platform-Specific):
if ismac == 1
serialpath
elseif
=
'/dev/tty. usbserial';
isunix == 1
serialpath
elseif ispc =
=
'/dev/TTYUSBO';
1
%Create proper serial path with port arg
serial-path = strcat
('OOM',
portstr
);
else
disp('Cannot, configure, the serial, portpath. ');
return;
end
% Define the serial port and create a serial port object
s=serial (serial-path ,
'Parity',
'terminator
'BaudRate' , 9600,
'none',
' ,
'StopBits',
'DataBits',
1,
'LF' ,'timeout ' ,2);
set (s, 'Timeout ' ,1);
197
8,
%Open serial port defined above
fopen(s);
end
function varargout = zcontrol (varargin)
%ZCONTROL MATLAB code for zcontrol.fig
ZCONTROL,
by
itself ,
creates a new ZCONTROL or raises the
%
existing singleton*.
%
H = ZCONTROL returns the handle to a new ZCONTROL or the
%0
handle to the existing singleton*.
%
ZCONTROL('CALLBACK', hObject , eventData , handles,...) calls
%
the local function named CALLBACK in ZCONTROL.M with the
%0
given input arguments.
%
ZCONTROL('Property ', 'Value
%
or raises the existing singleton*.
%
left , property value pairs are applied to the GUI before
%/
zcontrolOpeningFcn gets called.
%0
name or invalid value makes property application stop.
%
All
%
*See GUI Options on GUIDE's Tools menu.
%
allows only one instance to run (singleton)'.
',...)
creates a new ZCONTROL
Starting from the
An unrecognized property
inputs are passed to zcontrolOpeningFcn via varargin.
% See also: GUIDE,
GUIDATA,
Choose "GUI
GUIHANDLES
% Edit the above text to modify the response to help zcontrol
% Last Modified by GUIDE v2.5 17-Jul-2014 13:01:46
% Begin initialization code - DO NOT EDIT
guiSingleton = 1;
198
'guiSingleton',
..
guiSingleton ,
..
.
mfilename ,
.
guiState = struct ( 'guiName' ,
'guiOpeningFcn' , @zcontrolOpeningFcn,
'guiOutputFcn',
'guiLayoutFcn'
'guiCallback '
4zcontrolOutputFcn,
,
[]
...
...
...
[
,
if nargin && ischar(varargin{1})
ate . guiCallback = str2func (varargin {1});
guiSt
end
if nargout
[varargout{1:nargout}]
= gui-mainfcn (guiState,
gui-mainfcn(guiState,
varargin {:});
varargin
{:});
else
end
% End initialization
%--
code
-
DO NOT EDIT
Executes just before zcontrol is made visible.
function zcontrolOpeningFcn(hObject,
eventdata,
handles,
varargin)
% This function has no output args, see OutputFcn.
% hObject
handle to figure
% eventdata
reserved -
% handles
structure with handles and user data (see GUIDATA)
% varargin
command line arguments to zcontrol (see VARARGIN)
to be defined in a future version of MATLAB
global s
s = openser(3);
% Choose default command line output for zcontrol
handles
.
output = hObject;
% Update handles structure
guidata (hObject , handles);
% UIWAIT makes zcontrol wait for user response (see UIRESUME)
199
% uiwait (handles. figurel );
%-
Outputs from this function are returned to the command line.
function varargout = zcontrolOutputFcn(hObject , eventdata , handles)
% varargout
cell array for returning output args (see
% hObject
handle to figure
% eventdata
reserved -
% handles
structure with handles and user data (see
VARARGOUT);
to be defined in a future version of MATLAB
GUIDATA)
% Get default command line output from handles structure
varargout{1} = handles.output;
%6-
Executes when selected object is changed in uipanell.
function uipanellSelectionChangeFen (hObject , eventdata , handles)
% hObject
handle to the selected object in uipanell
% eventdata
structure with the following fields (see ULBUTTONGROUP)
%/
EventName: string 'SelectionChanged ' (read only)
%
OldValue: handle of the previously selected object or empty if
none was selected
NewValue: handle of the currently selected object
% handles
structure with handles and user data (see GUIDATA)
global s
switch get(eventdata.NewValue,
case
'Tag')
'offBtn'
fprintf(s,
'%u', 0);
case 'mainBtn'
fprintf(s,
case
1);
'%u',
2);
'%u',
3);
'%u',
0);
'manualBtn'
fprintf(s,
'faultBtn
'
case
'%u',
fprintf(s,
pause(0.01);
fprintf(s,
end
200
%
-Executes
on button press in openSerBtn.
function openSerBtnCallback(hObject , eventdata , handles)
% hObject
handle to openSerBtn (see GCBO)
% eventdata
reserved -
% handles
structure with handles and user data (see GUIDATA)
to be defined in a future version of MATLAB
global s
s = openser(3);
201
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202
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