IC220 Set #14:
Controlling the Single Cycle Implementation
(Chapter Five)
1
ADMIN
•
Reading
– Sections 5.5, 5.10, 5.11
– Section 5.6 (first two pages)
2
Control
Selecting the
and controlling the
based on the
•
Outline:
1. Overview
2. Controlling the ALU
3. Controlling multiplexors and register writes
3
Part 1: Control Overview
Example #1: add $8, $17, $18
000000 10001 10010
op
rs
rt
Example #2: lw $2, 12($1)
100011 00001 00010
op
rs
rt
01000
rd
00000 100000
shamt funct
0000000000001100
16 bit offset
add $8, $17, $18
lw $1, 12($2)
A. What should the register file do?
B. What should the ALU do?
C. What should the muxes do?
4
Part 1 – Control Overview
PCSrc
0
M
u
x
Add
Add
4
Read
address
Instruction [25:21]
Instruction [20:16]
Instruction
[31:0]
Instruction
memory
Read
register 1
Instruction [15:11]
0
M
u
x
1
RegDst
Read
register 2
Write
register
Write
data
16
Instruction [15:0]
MemWrite
Read
data 1
ALUSrc
Read
data 2
Instruction [5:0]
32
MemtoReg
Zero
ALU ALU
result
0
M
u
x
1
Registers
Sign
extend
1
Shift
left 2
RegWrite
PC
ALU
result
Read
Address
data
1
M
u
x
0
Data
Write memory
data
ALU
control
MemRead
ALUOp
5
Recall: ALU Control and Symbol
PAT05F15.eps
ALU Control Lines
Function
0000
AND
0001
OR
0010
Add
0110
Subtract
0111
Set on less than
1100
NOR
6
Part 2: ALU Control Scheme
Instruction
OpCode
Instruction op
lw (35)
load word
000000
sw (43)
store word
000000
beq (4)
branch equal
000000
R-type (0)
add
100000
R-type (0)
subtract
100010
R-type (0)
AND
100100
R-type (0)
OR
100101
R-type (0)
Set on less than
101010
Funct Field
Desired ALU
action
ALU control
input
7
Part 2: ALU Control
•
Must describe hardware to compute 4-bit ALU control input given
1. Instruction type
00 = lw, sw
01 = beq,
10 = arithmetic
2. Function code (for arithmetic)
•
Describe it using a truth table:
8
Part 3: Main Control
•
•
•
Set the muxes and register write signals
– To get data to flow to the right places
– To store data in the appropriate places
7 signals:
– ALUSrc
– MemtoReg
– MemRead
– MemWrite
– PCSrc
– RegDst
– RegWrite
Control based on:
9
Part 3 – Main Control
0
M
u
x
Add
Add
4
Instruction [31–26]
PC
Read
address
Instruction
[31–0]
Instruction
memory
RegDst
Branch
MemRead
MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite
Control
Instruction [25–21]
Read
register 1
Instruction [20–16]
Read
register 2
0
M
u
Instruction [15–11] x
1
Instruction [15–0]
Write
register
Write
data
16
Read
data 1
Read
data 2
Registers
Sign
extend
Instruction [5–0]
ALU
result
1
Shift
left 2
32
Zero
0
M
u
x
1
ALU ALU
result
Address
Read
data
1
M
u
x
0
Data
Write memory
data
ALU
control
10
EX: 5-1 …
Example – Main Control for an ‘add’
0
M
u
x
Add
ALU
Add
result
4
Instruction [31–26]
PC
Read
address
Instruction
[31–0]
Instruction
memory
RegDst
Branch
MemRead
MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite
Control
Instruction [25–21]
Read
register 1
Instruction [20–16]
Read
register 2
0
M
u
Instruction [15–11] x
1
Instruction [15–0]
Write
data
16
Read
data 1
Read
data 2
Write
register
Registers
Sign
extend
1
Shift
left 2
32
Zero
ALU ALU
result
0
M
u
x
1
Address
Read
data
1
M
u
x
0
Data
Write memory
data
ALU
control
Instruction [5–0]
11
Our Simple Control Structure
•
All of the logic is combinational
•
We wait for everything to settle down, and the right thing to be done
– ALU might not produce “right answer” right away
PAT05F17.eps
– we use write signals along with clock to determine when to write
•
Cycle time determined by length of the longest path
State
element
1
Combinational logic
State
element
2
Clock cycle
We are ignoring some details like setup and hold times
12
Performance
•
Calculate cycle time assuming negligible delays except:
Memory (200ps), ALU and adders (100ps),
Register file access – read or write (50ps)
PCSrc
0
M
u
x
Add
Add
4
RegWrite
Read
address
PC
Instruction [25:21]
Read
register 1
Instruction [20:16]
Read
register 2
Instruction
[31:0]
Instruction
memory
Instruction [15:11]
0
M
u
x
1
RegDst
Instruction [15:0]
Write
data
16
ALUSrc
Read
data 2
0
M
u
x
1
Registers
Sign
extend
Instruction [5:0]
1
MemWrite
Read
data 1
Write
register
ALU
result
Shift
left 2
32
MemtoReg
Zero
ALU ALU
result
Address
Read
data
1
M
u
x
0
Data
Write memory
data
ALU
control
MemRead
13
ALUOp
Performance Calculation
Instruction
Class
Functional Units used by the instruction class
R-type
PAT05F15.eps
lw
sw
beq
Memory (200ps)
ALU and adders (100ps)
Register file access – read or write (50ps)
Final Cycle Time?
14
Evaluation – Single Cycle Approach
•
Good:
•
Bad:
15
Adding Jump?
0
M
u
x
Add
Add
4
Instruction [31–26]
PC
Read
address
Instruction
[31–0]
Instruction
memory
RegDst
Branch
MemRead
MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite
Control
Instruction [25–21]
Read
register 1
Instruction [20–16]
Read
register 2
0
M
u
Instruction [15–11] x
1
Instruction [15–0]
Write
register
Write
data
16
Read
data 1
Read
data 2
Registers
Sign
extend
Instruction [5–0]
ALU
result
1
Shift
left 2
32
Zero
0
M
u
x
1
ALU ALU
result
Address
Read
data
1
M
u
x
0
Data
Write memory
data
ALU
control
16