Berkeley
Amplifiers Power Combining
Prof. Ali M. Niknejad
U.C. Berkeley
c 2014 by Ali M. Niknejad
Copyright Niknejad
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Power Combining
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How Big?
The amount of power that we can extract from a PA device is
limited by the output imepdance of the device. As the device
is made larger to handle a higher DC current (without
compromising the fT ), the lower the output impedance.
For a “current source” style of PA, eventually the device is so
large that power is lost in the device rather than the load.
This is the attraction of a switching PA.
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Gain vs. Output Power Tradeoff
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Power Devices (cont)
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Power Combining (cont)
Lossy Power Combiner
But for a non-switching PA we must perform some power
combining to use more than one device. This way we can
transform the load into a higher impedance seen by each PA.
The power combining networks are lossy and large. We’ll
come back to them later.
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Can we “wire” PAs together?
Note that we cannot simply “wire” PAs together since the
impedance seen by each PA increases by N if we connect N in
parallel:
VL
RPA =
= NRL
IL /N
This means that each PA delivers less power for a fixed swing
PPA =
2
Vswing
2RPA
There is also “load pulling” effects if the sub-PAs are not
perfectly in phase
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Wilkinson Power Combiner
L
λ/4
Input 1
Output
Z1
Output
C
R
Input 1
2C
R
Input 2
L
Input 2
C
Z1
Theoretically we cannot build a lossless 3-port device with
isolation and power combining.
The Wilkinson uses a resistor that is normally “open
circuited” (even mode) and does not generate loss.
Effective for high frequency designs or using LC circuit at low
frequency.
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Outphasing LINC Amplifier
A0 cos(ωt + φ1 (t))
vi (t) = A(t) cos(ωt + φ(t))
PA
AM
to
PM
+
A0 cos(ωt + φ2 (t))
vo(t) = B(t) cos(ωt + φ(t))
PA
LINC = LInear amplifier from Non-Linear Components
Decompose the AM/PM signal into two PM signals
The two PM signals can get amplified by two non-linear PA’s.
These can be saturated and efficient amplifiers.
By combining the two signals, the amplitude modulation is
restored at the antenna.
How to combine signals? Simple current mode will present a
time-varying load to each PA. Coupler or isolator will waste
power.
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Outphasing Math
cos(A) + cos(B) = 2 cos
A+B
2
cos
A−B
2
cos(ωt + ϕ) + cos(ωt − ϕ) = 2 cos (ϕ) cos (ωt)
cos ωt + cos−1 A(t) + cos ωt − cos−1 A(t) =
2 cos cos−1 A(t) cos (ωt)
cos ωt + cos−1 A(t) + cos ωt − cos−1 A(t) = 2A(t) cos (ωt)
In theory all we need to do is to compute the inverse cosine of
the AM waveform to generate our outphasing signals
In practice, we can use a DSP to calculate these signals since
the envelope rate is at the modulation rate and digital
techniques work well.
Power combining is the main difficulty.
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How to add to “Power” Vectors?
Adding two vectors on paper is easy, but how do we actually
combine the two PA?s?
Main issue is that the impedance seen by each PA varies
according to the output of the other PA. This is known as
load pulling.
This causes code dependent load variation, which changes the
actual output power, rendering the PA non-linear.
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Active Load Modulation
Zin = Vx /Ix
Vx = (Ix + Iy )RL = Ix (1 + αe jβ )RL
Zin = RL (1 + α cos(β) + jα sin(β))
Note that the second amplifier can modulate the load seen by
the first, both in terms of the magnitude and phase.
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Doherty Amplifier Concept
Invented by W.H. Doherty in 1936
Good power efficiency over a wide
range of output power
Must efficiently combine power
without increasing Vs wing
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Doherty Amplifier Block Diagram
Quarter wave line used as an impedance inverter. Can be
realized with LC equivalent.
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Doherty Details
Small signal region:
auxiliary amplifier is
off
When the input
crosses the threshold,
the action of the
auxiliary amplifier is
to dynamically lower
the load seen by the
main PA
Finally, both
amplifiers operate at
the peak power point
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Doherty Amplifier Operation
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Lumped Doherty Implementation
Can use lumped elements to
realize 90◦ phase shift
The CLC line is an
impedance inverter that also
provides VDD for the aux
amp
The LCL line is embedded
into the matching network
and provides 90◦ phase shift
Simulations show an
improved efficiency
Source: Zhao, M. Iwamoto, D.
Kimball, L. Larson, P.
Asbeck,University of California,
San Diego
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LC Matching Networks
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LC Matching Networks
(a)
(b)
RS < RL
RS <Matching
RL
networks are
needed Lto drive output
C
power to the load, which has
a fixed impedance.
Large output
RL
C powers require
a large transformation ratio,
and low voltage operation
means high currents in the
CMOS stage
(d)(sensitive to
series resistance).
30 dBm of output power
requires a matching ratio of
100 !
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L
PL = m
PL < m
RL
(e)
2
V2
V
sw
≤ m DD
2RL
2RL
1V2
= m × 10mW
2 · 50Ω
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LC Matching Network Loss
Pin = PL + Pdiss
The power loss of
integrated matching
networks is important.
IL =
The insertion loss can be
derived by making some
simple approximations
The final result implies
that we should minimize
our circuit Q factor and
maximize the component
Qc
1
IL =
1 + QQc
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PL
PL
1
=
=
Pin
PL + Pdiss
1 + PPdiss
L
1
1 vs2
L
Wm = Lis2 =
4
4 4RS2
ω0 ×Wm =
PL =
2
1 vs
4 4R
S
ω0 L
v2
= 12 s Q = 12 PL ×
RS
8RS
vL2
vs2
v2
=
= s
2RS
4 · 2 · RS
8RS
ω0 (Wm + We ) = Q × PL
Pdiss =
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PL · Q
Qc
Multistage Matching
Rhi
Cn
Rii
Ln
Q=
Ci
Ri2
Li
C2
L2
Ri1
C1
Rlo
L1
ω(Ws1 + Ws2 )
ωWs1
ωWs2
Q1 + Q2
=
+
=
Pd1 + Pd2
2Pd
2Pd
2
s
Q=
1
2
Ri
−1+
RL
s
Ri,opt =
!
RS
−1
Ri
Ri1
Ri2
Ri3
Rhi
=
= ··· =
= 1 + Q2
=
Rlo
Ri1
Ri2
Rin
Qopt
s
Q=
Ri1 Ri2 Ri3
Rhi
Rhi
·
·
·· · ··
=
= (1 + Q 2 )N
Rlo Ri1 Ri2
Rin
Rlo
p
RL RS
vs
u
u R
S
=t
− 1 ≈ m1/4
RL
Rhi
Rlo
1/N
−1
From two-stage Q, we generalize to multi-stage design
Since the Q of each stage is lowered, the insertion can improve
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Approximate Insertion Loss
Pdiss =
IL =
IL =
1+
N
Qu
NQPL
Qu
1
1 + N QQu
r
1
Rhi
Rlo
1/N
−1
N
1
2
3
4
5
6
Q
9.95
3
1.91
1.47
1.23
1.07
IL (dB)
−1.24
−0.79
−0.76
−0.78
−0.81
−0.85
Suppose a power amplifier delivering 100 W of power has an
optimal load resistance of .5Ω, but needs to drive a 50Ω
antenna.
Design a matching network assuming that the component Qc
of 30 are available (on-chip ∼ 10 − 15 for thick metal).
First note that a matching factor of m = 50/.5 = 100 is
needed.
Table above shows that 3 stages is optimum
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Efficiency Loss of Matching Network
Power Enhancement Ratio (PER)
source: Aoki, IEEE MTT-S
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Technology Scaling
Example Class A design
65nm ⇒ Vpeak = 2V
Pout,50Ω = 10mW
Required Pout = 100mW
Rin = 5Ω
PER = 50/5 = 10
Q of 5 ⇒ η = 35%
Q of 10 ⇒ η = 70%
...These numbers are for the
matching network alone !
Impedance matching is the
limit for low voltage
operation
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Quarter Wave Transformer
Rs
Z0 =
Vs
RL Rs
RL
λ/4
Pin =
|V + |2 2α`
(e
− |ρ(λ/4)|2 e −2α` )
2Z0
IL =
+ 2
PL =
|ρ(λ/4)| = |ρL |e −2αλ/4
|V |
(1 − |ρL |2 )
2Z0
1 − |ρL |2
PL
= 2αλ/4
Pin
e
− |ρ(λ/4)|e −2αλ/4
Quarter wave line
√ is a nice way to impedance match source
and load Z0 = ZL ZS (source/load must be real). T-line
comes for free since we can use the board trace at high
frequency.
How does this vary with matching ratio?
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T-Line Loss
m=
IL =
Rhi
≥1
Rlo
1
Q = 200
0.9
1
cosh(2αλ/4) +
1+m
√
2 m
sinh(2αλ/4)
αλ
β
π
=
λ2 =
2
2Q
2Q
1
IL(Q, m) =
π
√ sinh( π )
cosh( 2Q
) + 21+m
2Q
m
2αλ/4 =
IL
Q = 50
0.8
Q = 20
0.7
Q = 10
0.6
10
20
m
30
40
For FR4 and other lossy dielectrics, the IL can be quite high.
Multi-section T-line helps (lower Q) but area is a big
constraint.
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50
Transformer Matching
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Transformer Matching
M
=k
N=
L2
r
L1
L2
ωL2
r2 + RL
PL
IL =
PL + Pdiss
RL
=
2
r1 + r2 + RL + LM2 r1 +
QL =
≈
RL
r1 + r2 + RL +
r1 (r2 +RL )2
ω2 M 2
r1
N 2 Q22
Simple model of transformer as coupled inductors with series
loss.
Key result: loss is nearly independent of the matching ratio!
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Simbürger PA Interstage Drive
Simburger and co-authors demonstrated that on-chip
transformer can be used to drive large bipolar PA devices
Output power 5W, 55% PAE
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Simbürger Transformer
Siemens team showed that on-chip transformers were useful
for PA interstage matching.
Can they be used for the output stage as well?
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Planar Transformer Layout
Moderately high k factor transformers can be realized using
two metal layers
Different layout styles offer an asymmetric primary/secondary,
a symmetric prim/sec, and a fully balanced and symmetric
prim/sec
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Transformer Turns Ratio
With a planar layout, turns ratio can be obtained from
omitting turns on the secondary or by connecting secondary
turns in parallel
Parallel connection offers lower loss on secondary
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High Turns 3D Ratio Transformers
A 3D layout allows much more flexibility.
High turns ratio and higher coupling factor can be
implemented in a simple way
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Balun Layout
+ V3 −
+
V1
−
+
V2
−
+
V3
−
+ V2 −
Symmetric structures can be used to build baluns.
Baluns are a natural fit in fully differential circuits.
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+
V1
−
Lumped Modeling of Transformer
Symmetric 2π model
RL network models
frequency-dependent loss
Winding capacitance for
SRF
Asymmetric substrate
network
Ref: [Chow4], [Mohan],
[Cao]
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Comparison of Results
Necessary to match both y , z parameters instead of
s-parameters only
Good match up to high frequencies
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Transformers Comparison
“Microwave Performance of Monolithic Silicon Passive
Transformers”
Mounir. Y. Bohsali and Ali. M. Niknejad
Paper published at RFIC 2004:
Compare various transformer layouts
Define metric that takes into account bandwidth
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Shunt versus Planar
Planar versus shunt have similar behavior below resonance
with 2-3 dB of loss.
Series structure has much lower resonance frequency.
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Transformer Bandwidth
Define a new metric: bandwidth over which gain is within 1
dB of “optimal” gain (for a bi-conj. match)
Planar structure has very good bandwidth (50-150%), and
other structures are worse, but series structure is significantly
worse.
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Baluns
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Transmission Line Balun
+
+
V1
V2
−
−
+
V2
−
+
V1
−
Turn parasitic coupling capacitance into a distributed
broadband transmission line!
Excite the differential mode rather than the odd mode.
L
i1
+
vs
−
−
i1
+
vs
−
R
vs
+
L
i1
i1
+
vs
−
L
R
k≈1
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R
L
R
k≈1
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Broadband Inverter
RS I1
+
vs
−
L
I2
RS
+
V2
−
+
V1
−
+
vs
−
L
RL
RL
V1 = (cosh γ` + sinh γ`)V2 = e γ` V2
vL = −V2 = −e γ` V1
The voltage at the load is inverted if the length of the line is
small (∼1/10 wavelength)
Note that line excited with both odd and even mode at source
but higher Z0 and loss of line rejects even mode.
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LC Coupler
2C
2C
L
L
L
Lumped 180◦ coupler
C
2C
C
L
Low bandwidth (20%)
Element values can be an issue
2C
√
1
= ωL = 2Z0
ωC
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LC Balun
Essentially a bridge with
phase lead and lag networks.
balanced
Bandwidth: Depends on Q
of match since this is just a
high-pass and low-pass
matching network.
p
Zc = Ri RL
Zc
ω
1
C=
ωZc
L=
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Transmission Line Balun
RS
+
vs
−
is
I1
I2
+
V1
−
+
V2
−
I3
I4
+
V3
−
+
V4
−
2RS
vL
2RS
This works as a balun over a very broad band. If length is
quarter wavelength, the even mode is rejected at center
frequency.
2
vL
2
= jk` = 2e −jk`
G=
=
Z
0
vs
e
cos k` + j 2Rs sin k`
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Marchand Balun
unbalanced
open
balanced
Improved bandwidth
Less sensitivity to even-mode impedance
Requires two quarter wave structures.
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Transformer Combiners
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Cal Tech DAT
VDD
+
Vout
−
VDD
VDD
VDD
−Vout
−Vin
+Vout
+Vin
−Vin
+Vin
−Vin
+Vin
−Vin
+Vin
Use virtual grounds wisely to turn 1:1 coupled lines into a
transformer loop.
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Transformer Matching / Loss
The insertion loss of a
transformer can be
calculated from the
maximum power gain
(bi-conjugate match)
2<(Z11 )<(Z22 ) − <(Z12 Z21 )
|Z12 Z21 |
Rp + jωLp
jωM
Z=
jωM
Rs + jωLs
p
Y21 K − K2 − 1
Gmax =
Y12
K=
For a simple transformer,
the maximum gain is a
function of only the winding
Q factors and the magnetic
coupling factor (k)
It’s independent of the
matching ratio!
2Rp Rs + ω 2 M 2
ω2M 2
2Rp Rs
2
= 2 2 +1= 2
+1
ω M
k Qp Qs
K=
s
2
1
Gmax (Q, k) = 1 +
−2
2
Qp Qs k
Qp2 Qs2 k 4 +
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1
Qp Qs k 2
Transformers for Power Combining
Transformer Insertion Loss
1
0.9
Q = 20
Q = 15
0.8
Q=10
0.7
0.6
0.6
0.7
0.8
0.9
1
Notice that relatively low insertion loss is possible with
moderate on-chip Q and K factors, thus allowing
fully-integrated transformers
Connecting 1:1 transformers in series and shunt, we can
perform efficient power combining independent of the number
of sections [Caltech DAT architecture]
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Transformer Power Combining Layout
− Vout +
Very simple layout
Don’t get DAT benefit ⇒ have extra “leads” that waste power
But can turn off individual stages for power back-off
Can easily scale power by adding more stages: design core
driver stage
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Fully Integrated Dual Mode CMOS PA
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Power Combining and Control
Use transformer to perform
efficient power combining
At moderate back-off (6
dB), efficiency close to peak
level
efficinety (%)
Can also use structure for
efficient power back-off to
improve average power
efficiency
relative output power (dB)
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Power Control and Efficiency Enhancement
η=
1 VRF IRF
Pout
=
Pdc
2 VDC · IDC
At power back-off, to
improve efficiency you must
do one or more of the
following
Reduce DC current
Reduce supply
Modulate load
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Load Modulation
Zm,j
=
=
Vpa,j
− RPA,j
ip,j
P
2·R
RL + N
m
· Vpa,j
PA,i
i=1 i
− RPA,j
PN
mj · i=1 mi · Vpa,i
In general there is no isolation in the transformer so the load
current of one primary will “pull” the impedance of another
winding.
It’s only under the special circumstance that all windings are
driven in phase that we obtain isolation.
RL
Rm =
N · m2
2
Vpa
2
2
Po = N · m ·
2RL
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Efficiency at Back-Off
ηB =
π Vp
4 VDD
g m RL
· Vi
4
= 4Vp = gm RL · Vi
Vout,max
efficinety (%)
Vp,max =
gm RL Vi
1
·
= gm RL · Vi
2
2
4
gm RL Vi
Vout,two = 2Vp =
2
Vp,two =
relative output power (dB)
When all four stages are on, each PA see 1/4 of the load.
Suppose 2 stages are turned off. Then the PAs see 1/2 of the load.
The voltage swing at the output drops, but the voltage on each
primary remains the same!
For Class B operation, we can theoretically achieve the same
efficiency at back-off.
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Power Back-Off Mode
R=
1
RL
3
1
Vp,three = gm · RL · Vi
3
3
Vi,three = Vi,max
4
1
3
1
Vp,three = gm · RL · Vi = gm RL · Vi
3
4
4
3
Vout,three = 3Vp = Vout,max
4
Say we back-off the input by 3/4. If we turn off one amplifier, the
load seen by each amplifier is now 1/3, but the output voltage is
still at the peak optimal value
The overall efficiency is therefore at the peak value.
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Example Linear PA with Transformer Power Combining
“A 1.2V, 2.4GHz Fully Integrated Linear CMOS PA with
Efficiency Enhancement”
CICC 2006
Authors: Gang Liu, Tsu-Jae King Liu, A. M. Niknejad
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Simplified 4-Way Combiner Schematic
Combing power from 4 unit amplifiers, center tuned at 2.4
GHz
Output matching tuned by switched cap at back-off
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Schematic of Each Unit Amplifier
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Cascode Layout
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Die Microphotograph
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Transformer and Cap Array
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Single-Tone Test
Freq = 2.4-GHz, Peak Power Mode
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Two-Tones Test
Freq = 2.4-GHz, 1-kHz tone spacing, Peak Power Mode
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Simulateed Efficiency at Back-Off
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Measured Efficiency at Back-Off
Note: at 2.5-dB back-off, one unit amplifier was turned off.
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Measurements with EDGE Signals
Freq = 2.4-GHz, Peak Power Mode
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Measurements with 802.11g Signals
Pout = 14.5-dBm EVM = 4.48%
Freq = 2.4-GHz, Peak Power Mode
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EVM vs Output Power
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Table of Performance
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Example 5.8 GHz WiFi PA
“A 5.8 GHz Linear Power Amplifier in a Standard 90nm
CMOS Process using a 1V Power Supply”
RFIC 2007
Authors: Peter Haldi, Debopriyo Chowdhury, Gang Liu, Ali M.
Niknejad
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New Transformer Network
Vdd
Vdd
Vdd
Vdd
Cout Rload
Figure “8” style layout minimized the impact of lead
inductance
Lateral coupling used since top metal layer is most conductive
and most distant from substrate
Very good isolation characteristic due to flux inversion (for
example it can be used as a stand-alone inductor low
magnetic coupling)
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Improved Layout for Windings
Vdd
Vdd
Vdd
Vdd
Cout Rload
V+
Cin
V-
V-
Cin
V+
V+
Cin
V-
V-
Cin
V+
Using two primary windings
Improved coupling
Lower loss (current crowding at edge of conductors)
More symmetric primary/secondary for optimal power transfer
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Prototype PA in Digital CMOS
Vdd
Vdd
Vdd
Vdd
gnd
out
gnd
gnd
+ input –
gnd
Four stage differential design
Single-ended 50Ω output
Thin oxide 90nm transistors
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Measured Output Power
33
measured
simulation
28
Efficiency [%]
23
18
13
8
3
12
14
16
18
20
Output Power [dBm]
22
24
26
Peak power is 24 dBm. Good match to simulation up to 1dB
compression point.
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Measured Efficiency
26
measured
Output Power [dBm]
24
simulation
22
20
18
16
14
12
4
6
8
10
12
14
16
Input Power [dBm]
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18
20
PA Linearity
IM3 = 28 dBc at output power of 20.5 dBm (200 MHz)
IM3 has tone spacing dependence due to lack of good bypass
(class AB stage). Verified with packaged version.
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Output Power vs Frequency
Frequency of Interest
80
70
24.4
Efficiency [%]
Output Power [dBm]
24.6
24.2
0.9 dB
24.0
60
50
40
30
20
23.8
10
23.6
1
5
5.1
5.2
5.3
5.4
5.5
5.6
5.7
2
3
5.8
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4
5
6
7
Frequency [GHz]
Frequency [GHz]
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8
9
10
CMOS “Digital” Prorotype
Process
Type
Freq
η
Size ( mm2 )
Ref.
0.35 µm BiCMOS
slab
2.4 GHz
70.5%
0.8x0.8
[1]
0.18 µm CMOS
slab
2.4 GHz
83%
0.8x0.5
[5]
RF GaAs
slab
2 GHz
87.7%
1.2x1.2
[4]
RF 0.20 µm SiGe
slab
21-26 GHz
77.6%
0.4x0.2
[3]
RF 0.13 µm CMOS
loop
2.4 GHz
80%
1.5x0.25
[2]
0.09 µm CMOS
loop
5.35 GHz
75%
0.65x0.15
this work
Table 1: Comparison between state-of-the-art power combining networks.
New transformer layout has simulated efficiency of 75%
State-of-the-art performance of 5 GHz linear PA
24 dBm with 27% efficiency
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Advanced IC’s for Comm
Example: Two-Stage WiMAX/LTE CMOS PA
VBIAS1
VBIAS2
POWER
COMBINER
I1
POUT
MB1
M3 M4
M1 M2
I2
P1
VDD
P2
VPMOS
M7 M8
PIN
Cb
VPMOS
M5 M6
VDD
INTER-STAGE
SPLITTER
OUTPUT STAGE 2
(IDENTICAL TO STAGE 1
SHOWN ABOVE)
INPUT
XFMR
Ref: [Chow2]
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Advanced IC’s for Comm
WiMax/LTE PA Die Photo
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Advanced IC’s for Comm
Output Stage Design
Thick-oxide CG stage
(VDD = 3.3V)
Dynamic gate biasing
Capacitive divider
Differential ⇒ does not
affect small signal gain
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Optimal Class AB Biasing
Magnitude of S21 (dB)
30
28
Increasing output
stage gate bias
26
24
22
20
18
-20
-15
-10
-5
0
Input Power (dBm)
5
10
Ideal clipping is better than soft saturation of Class AB
Class AB is more linear since we can tune the PA so that gain
peaking compensates for gain compression
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Large-Signal CW Measurements
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Meeting the WiMAX Mask
Average Pout = 22.76 dBm
Average drain efficiency = 15%, Average PAE = 12%
Power of 2nd, 3rd and higher harmonics also meet FCC mask
⇒ possible to eliminate harmonic filter
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Back-Off Mode Implementation
Bottom stage powered-down for low-power mode
Vctrl = 0 in high-power mode and 2 · VDD in low-power mode
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Low Power Mode
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Common-Mode Stability
VDD
LDD
Lpr
Ls
Cb
Lbias
R1
RL
M1
Cb
R1
Lbias
M2
Cc
Cc
LGND
Pseudo-differential architecture ⇒ common-mode oscillations
possible
Need to consider ground and supply inductances, bypass
network
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Equivalent Circuit for Common Mode
ZIN =
If (1/ωCgd ) (ωL):
ZIN =
1
j ωL −
Niknejad
1 + jωgm LD
1
gm LD
−
]
Cgd
(1 + ωgm LD ) jωCgd
2
1
ωCgd
[
Advanced IC’s for Comm
Stability Analysis
Rg
Vi
I1
Cgs
Cgd
Vgs
I3
gm Vgs
Lp
ro
I2
Cb
R1
Lg
For oscillation, [A] is singular [Chow3]



Vi
I1
 0 
 I2



 Vi  = [A] ×  I3



 Vi 
 Vgs
0
I4
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I4
Lv






Advanced IC’s for Comm
Stabilizing the PA
Resistor in series with gate
Resistor in series with bypass capacitor
Staggered-RC bypass network
Series RC -pair
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Series RC Pair
Transistors have higher gain at lower frequency, transformers
are wideband
RC network ⇒ loss around 35GHz without impacting 60GHz
Ref: [Kom]
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References
Chow2 Chowdhury, D.; Hull, C.D.; Degani, O.B.; Goyal, P.; Yanjie Wang; Niknejad, A.M., “A single-chip highly
linear 2.4GHz 30dBm power amplifier in 90nm CMOS,” Solid-State Circuits Conference - Digest of
Technical Papers, 2009. ISSCC 2009. IEEE International , vol., no., pp.378,379,379a, 8-12 Feb. 2009
Chow3 Chowdhury, D.; Reynaert, P.; Niknejad, A.M., “Transformer-Coupled Power Amplifier Stability and Power
Back-Off Analysis,” Circuits and Systems II: Express Briefs, IEEE Transactions on, vol.55, no.6,
pp.507,511, June 2008
Chow4 Chowdhury, D.; Reynaert, P.; Niknejad, A.M., “Design Considerations for 60 GHz Transformer-Coupled
CMOS Power Amplifiers,” Solid-State Circuits, IEEE Journal of, vol.44, no.10, pp.2733,2744, Oct. 2009
Mohan Mohan, S.S.; Yue, C.P.; del Mar Hershenson, M.; Wong, S.S.; Lee, T.H., “Modeling and characterization
of on-chip transformers,” Electron Devices Meeting, 1998. IEDM ’98. Technical Digest., International ,
vol., no., pp.531,534, 6-9 Dec. 1998
Cao Yu Cao; Groves, R.A.; Xuejue Huang; Zamdmer, N.D.; Plouchart, J.-O.; Wachnik, R.A.; Tsu-Jae King;
Chenming Hu, “Frequency-independent equivalent-circuit model for on-chip spiral inductors,” Solid-State
Circuits, IEEE Journal of, vol.38, no.3, pp.419,426, Mar 2003
Aoki Aoki, I.; Kee, S.D.; Rutledge, D.B.; Hajimiri, A., “Distributed active transformer-a new power-combining
and impedance-transformation technique,” Microwave Theory and Techniques, IEEE Transactions on,
vol.50, no.1, pp.316,331, Jan 2002
Kom Komijani, A.; Hajimiri, A., “A Wideband 77-GHz, 17.5-dBm Fully Integrated Power Amplifier in Silicon,”
Solid-State Circuits, IEEE Journal of, vol.41, no.8, pp.1749,1756, Aug. 2006
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Advanced IC’s for Comm