(5 pts) Exercise 4-1 (Single-cyc impl.)
First row covered in class
Fill in the needed control value (0 or 1) for each case
Inst.
MemtoReg
MemRead
MemWrite
Branch
ALUOp
1
ALUOp
0
1
0
0
0
1
0
1
1
1
0
0
0
0
1
X
0
0
1
0
0
0
0
X
0
0
0
1
0
1
RegDst
ALUSrc
1
0
0
0
1
X
X
Rformat
RegWrite
lw
sw
beq
TRUTH TABLE  Now can implement with gates
(5 pts) Exercise 4-2 (Single-cyc impl.)
Fill in the correct signal name by looking back at the datapath diagram.
Possibilities: ALUSrc, MemtoReg, MemRead, MemWrite, Branch, RegDst, RegWrite
Signal Name
Effect when deasserted
Effect when asserted
The register destination number for the write
register comes from the rt field (bits 20-26)
The register destination number for the write register
comes from the rd field (bits 15-11)
None
The register on the Write register input is written
with the value on the Write data input
The second ALU operand comes from the second
register file output (Read data 2)
The second ALU operand is sign-extended, lower 16
bits of the instruction
Branch
The PC is replaced by the output of the adder that
computes the value of PC+4
The PC is replaced by the output of the adder that
computes the value of branch target
(provided that “Zero” signal is true)
MemRead
None
Data memory contents designated by the address
input are put on the Read Data output
None
Data memory contents designated by the address
input are replaced by the value on the Write
Data input
The value fed to the register Write data input
comes from ALU
The value fed to the register Write data input comes
from the data memory
RegDst
RegWrite
ALUSrc
MemWrite
MemtoReg
(15 pts) Exercise 4-5
A “stuck-at-0” fault is a defect that can occur during manufacturing, where a particular
signal becomes hardwired to zero. Considering the single-cycle implementation shown in
Figure 4.17 on page 265, describe the effect that a stuck-at-0 fault would have for each of
the following signals. Which instructions, if any, will not work correctly? Explain why. The
first is done for you as an example. Consider these instructions: R-type, lw, sw, beq.
NOTE – explain specifically what goes wrong in each case – do NOT just say “MemRead is
supposed to one for that instruction.”
–
–
ALUSrc = 0. lw and sw would not work, because the immediate value
from the instruction couldn’t be provided to the ALU as needed.
MemRead = 0
lw will not execute correctly, can’t load from the memory
–
MemWrite = 0
sw can’t write to the memory
–
ALUop1 = 0
All R-format instructions except add will not work
properly because the ALU will perform addition
instead of the required ALU operation from the
function field.
–
ALUop0 = 0
beq instruction will not work because the ALU will
perform addition instead of the subtraction needed.
–
RegWrite = 0
All R-type instructions, and lw, will not work because
they won’t be able to write their results back into the
register file.
(blank space)
(practice) Practice Exercise
Consider a new instruction “swai” (store word and auto-increment). This
instruction first performs a normal “sw” instruction and then increments
the “rs” register by 4 (so the original “rs” value is used for address
computation). More formally, it does this:
Mem[ Regs[rs] + SignExtImm] = Regs[rt]
Regs[rs] = Regs[rs] + 4
Example: swai $t0, -12($s0) will store the value of $t0 in Mem[$s0-12], and
also increase the value of $s0 by 4.
We wish to add this instruction to our single-cycle implementation. To
make this happen, 1.) add any necessary hardware (gates, adders, wires,
etc.) to the single-cycle datapath shown below and 2.) modify the control
chart below (add a new row and any new signals, if necessary).
Instr
RegDst
ALUSrc
MemtoReg
RegWrite
MemRead
MemWrite
Branch
ALUOp1
ALUOp0
R-format
1
0
0
1
0
0
0
1
0
lw
0
1
1
1
1
0
0
0
0
sw
X
1
X
0
0
1
0
0
0
beq
X
0
X
0
0
0
1
0
1
(15 pts) Exercise 4-7
•Consider the jr instruction (jump register), which is described as follows:
We wish to add this instruction to our single-cycle implementation. To
make this happen, 1.) add any necessary hardware (gates, adders, wires,
etc.) to the single-cycle datapath shown below and 2.) modify the control
chart below (add a new row and any new signals, if necessary).
Note: ‘jr $s0’ states that the next PC value should come from register $s0.
It is NOT the same as instructions like ‘j Loop’, whose datapath and
control is described on page 270 (though reading about that may help with
the general idea)
Instr
RegDst
ALUSrc
MemtoRegMemMemBranch
ALUOp1 ALUOp0
jumpreg
Reg
Write
Read
Write
0
R-format
1
0
0
1
0
0
0
1
0
0
lw
0
1
1
1
1
0
0
0
0
0
sw
X
1
X
0
0
1
0
0
0
beq
jr
X
0
X
0
0
0
1
0
1
0
X
X
X
0
0 or X
0
X
X
X
1
(RegWrite=0, MemWrite=0 so that don’t do extraneous writes. Others signals don’t matter here.)
Some students tried to make the mux up top 3-way instead of using two separate muxes. That
doesn’t work (at least w/o more logic) because of the need to have the original mux control
determined by branch AND Zero (the AND gate).
(15 pts) Exercise 4-8
•Do the same as previous exercise, but for the lui instruction:
You can find more info on this instruction in Section 2.10.
Again, table/figure below for you to modify. There are multiple ways to
solve this problem; provide some brief text explaining how your solution
works. Make sure that the other instructions continue to work.
Instr
RegDst
ALUSrc
MemtoReg
RegWrite
MemRead
MemWrite
Branch
ALUOp1
ALUOp0
R-format
1
0
0
1
0
0
0
1
0
0
lw
0
1
1
1
1
0
0
0
sw
X
1
X
0
0
1
0
0
0
do_lui
0
0
X
beq
X
0
X
0
0
0
1
0
1
X
0
X
X
0 or X
0
0
X
X
1
lui
1
lui just needs to shift the immediate value by 16 bits. Once we have that value, we need some way
to provide that value to the writeback path (so it can be stored in the register file). The new mux
provides this capability. NOTE: lui is NOT accessing memory. See notes and/or textbook.
Note: below we add a new mux. It would also have worked to instead add a new input (labeled “2”) to the existing mux
that is controlled by MemToReg, then set that control signal to “2” for the lui instruction in the table shown on the previous
slide.
(10 pts) REVIEW
•
•
For monkey: ‘a’ passed in $f12, ‘b’ passed in $a0.
(return value in $f0)
For lemur: ‘x’ passed in $a0, ‘y’ passed in $a1
Given this protoype:
(return value in $f0)
float lemur (int x, int y);
monkey:
Write the MIPS code to define the
following
function
addi
$sp, $sp, -8
float monkey(float a, int b)
sw $ra, 4($sp)
swc1 $f12, 0($sp) # save ‘a’ for later
{ return a + lemur(97,b); }
# Set-up to call lemur
move $a1, $a0 # copy ‘b’ into 2nd argument
li $a0, 97
# first argument = 97
jal lemur
# result now in $f0
# reload stored values and fix up stack
lw $ra, 0($sp)
lwc1 $f12, 4($sp)
# reload a
addi $sp, $sp, 8
# add lemur result to ‘a’, put in $f0
add.s $f0, $f0, $f12
jr $ra