IC220 Set #19:
Laundry, Co-dependency, and other Hazards
of Modern (Architecture) Life
Return to Chapter 4
1
Midnight Laundry
Time
6 PM
7
8
9
10
11
12
1
2 AM
Task
order
A
B
C
D
2
Smarty Laundry
Time
6 PM
7
8
9
10
11
12
1
2 AM
6 PM
7
8
9
10
11
12
1
2 AM
Task
order
A
B
C
D
Time
Task
order
A
B
C
D
3
Pipelining
•
Improve performance by increasing instruction throughput
Program
execution
Time
order
(in instructions)
200
lw $1, 100($0) Instruction
fetch Reg
lw $2, 200($0)
400
600
Data
access
ALU
800
1000
1200
1400
ALU
Data
access
1600
1800
Reg
Instruction Reg
fetch
800 ps
lw $3, 300($0)
Reg
Instruction
fetch
800 ps
800 ps
Program
execution
Time
order
(in instructions)
lw $1, 100($0)
200
Instruction
fetch
400
Reg
lw $2, 200($0) 200 ps Instruction
fetch
lw $3, 300($0)
600
ALU
Reg
Instruction
200 ps fetch
800
Data
access
ALU
Reg
1000
1200
1400
Reg
Data
access
ALU
Reg
Data
access
Reg
200 ps 200 ps 200 ps 200 ps 200 ps
Ideal speedup is number of stages in the pipeline. Do we achieve this?
4
Basic Idea
IF: Instruction fetch
ID: Instruction decode/
register file read
EX: Execute/
address calculation
MEM: Memory access
WB: Write back
Add
4
ADD
Add
result
Shift
left 2
0
M
u
x
1
Read
register 1
Address
PC
Read
data 1
Read
register 2
Registers
Write
Read
register
data 2
Instruction
Instruction
memory
Write
data
Zero
0
M
u
x
1
ALU ALU
result
Address
Read
data
Data
Memory
1
M
u
x
0
Write
data
16
Sign
extend
32
5
Pipelined Datapath
IF/ID
ID/EX
EX/MEM
MEM/WB
Add
Add Add
result
4
Shift
left 2
PC
Address
Instruction
memory
Instruction
0
M
u
x
1
Read
register 1
Read
data 1
Read
register 2
Registers
Read
Write
data 2
register
Write
data
0
M
u
x
1
Zero
ALU ALU
result
Read
data
Address
Data
memory
0
M
u
x
1
Write
data
16
32
Sign
extend
6
Pipeline Diagrams
Clock cycle:
Time
200
1
2
IF
$s0, $t0,
add $s0,add
$s1,
$s2$t1
400
600
3
EX
ID
200
Time
IF
sub $a1, $s2, $a3
add $s0, $t0, $t1
600
EX
ID
IF
6
7
800
400
600
EX
ID
1000
WB
MEM
200
add $s0, $t0, $t1
1000
5
WB
MEM
400
Time
add $t0, $t1, $t2
800
4
800
MEM
1
WB
Assumptions:
• Reads to memory or register file in 2nd half of clock cycle
• Writes to memory or register file in 1st half of clock cycle
What could go wrong?
7
Problem: Dependencies
•
Problem with starting next instruction before first is finished
Clock cycle:
Time
subadd
$s0,
$s2
$s0,$s1,
$t0, $t1
1
200
IF
2
400
200
Time
600
EX
ID
and $a1, $s0, $a3
add $s0, $t0, $t1
3
IF
800
5
600
EX
200
1000
6
7
8
WB
MEM
400
ID
Time
4
800
WB
MEM
400
1000
600
800
1000
add $t0, $t1, $s0
add $s0, $t0, $t1
or
$t2, $s0, $s0
IF
Time
add $s0, $t0, $t1
ID
IF
200
EX
ID
400 MEM 600
EX
WB
800
WB
MEM
Dependencies that “go backward in time” are ____________________
Will the “or” instruction work properly?
8
Solution: Forwarding
Use temporary results, don’t wait for them to be written
Clock cycle:
Time
sub add
$s0,
$s2
$s0,$s1,
$t0, $t1
1
2
200
IF
400
3
EX
ID
200
Time
and $a1, $s0, $a3
add $s0, $t0, $t1
600
IF
4
800
600
EX
ID
1000
200
6
7
8
WB
MEM
400
Time
5
800
WB
MEM
400
1000
600
800
1000
add $t0, $t1, $s0
IF
Time
add $s0, $t0, $t1
or
$t2, $s0, $s0
ID
200
IF
add $s0, $t0, $t1
EX
WB
400 MEM 600
EX
ID
800
WB
MEM
Where do we need this?
Will this deal with all hazards?
9
Problem?
Clock cycle:
Time
lw $t0,add
0($s1)
$s0, $t0, $t1
1
200
IF
2
400
add $s0, $t0, $t1
600
EX
ID
200
Time
sub $a1, $t0, $a3
3
IF
800
4
600
EX
ID
200
Time
6
7
WB
MEM
400
1000
5
800
WB
MEM
400
1000
600
800
10
add $a2, $t0, $t2
add $s0, $t0, $t1
IF
ID
EX
MEM
WB
Forwarding not enough…
When an instruction tries to ___________
a register following a ____________
to the same register.
10
Solution: “Stall” later instruction until result is ready
Clock cycle:
1
2
3
4
5
6
7
lw $t0, 0($s1)
sub $a1, $t0, $a3
add $a2, $t0, $t2
Why does the stall start after ID stage?
11
Assumptions
•
For exercises/exams/everything assume…
– The MIPS 5-stage pipeline
– That we have forwarding
…unless told otherwise
12
Exercise #1 – Pipeline diagrams
•
Draw a pipeline stage diagram for the following sequence of instructions.
Start at cycle #1.
You don’t need fancy pictures – just text for each stage: ID, MEM, etc.
add $s1, $s3, $s4
lw $v0, 0($a0)
sub $t0, $t1, $t2
•
What is the total number of cycles needed to complete this sequence?
•
What is the ALU doing during cycle #4?
•
When does the sub instruction writeback its result?
•
When does the lw instruction access memory?
13
Exercise #2 – Data hazards
•
Consider this code:
1. add $s1, $s3, $s4
2. add $v0, $s1, $s3
3. sub $t0, $v0, $t2
4. and $a0, $v0, $s1
1. Draw lines showing all the data dependencies in this code
2. Which of these dependencies do not need forwarding to avoid stalling?
14
Exercise #3 – Data hazards
•
Draw a pipeline diagram for this code. Show stalls where needed.
1. add $s1, $s3, $s4
2. lw $v0, 0($s1)
3. sub $v0, $v0, $s1
15
Exercise #4 – More Data hazards
•
HW: 4-81 to 4-82
Draw a pipeline diagram for this code. Show stalls where needed.
1.
2.
3.
4.
lw
lw
sw
sw
$s1,
$v0,
$v0,
$t0,
0($t0)
0($s1)
4($s1)
0($t1)
16
The Pipeline Paradox
• Pipelining does not ________________ the execution time of
any ______________ instruction
• But by _____________________ instruction execution, it can
greatly improve performance by
________________ the
________________
17
Structural Hazards
•
Occur when the hardware can’t support the combination of
instructions that we want to execute in the same clock cycle
•
MIPS instruction set designed to reduce this problem
•
But could occur if:
18
Control Hazards
•
What might be a problem with pipelining the following code?
Else:
•
beq
lw
sw
add
$a0,
$v0,
$v0,
$a1,
$a1, Else
0($s1)
4($s1)
$a2, $a3
What other kinds of instructions would cause this problem?
19
Control Hazard Strategy #1: Predict not taken
•
What if we are wrong?
•
Assume branch target and decision known at end of ID cycle. Show a
pipeline diagram for when branch is taken.
beq $a0, $a1, Else
lw $v0, 0($s1)
sw $v0, 4($s1)
Else: add $a1, $a2, $a3
20
Control Hazard Strategies
1. Predict not taken
One cycle penalty when we are wrong – not so bad
Penalty gets bigger with longer pipelines – bigger problem
2.
3.
21
Branch Prediction
Taken
Not taken
Predict taken
Predict taken
Taken
Not taken
Taken
Not taken
Predict not taken
Predict not taken
Taken
Not taken
With more sophistication can get 90-95% accuracy
Good prediction key to enabling more advanced pipelining techniques!
22
Code Scheduling to Improve Performance
•
Can we avoid stalls by rescheduling?
lw
add
lw
add
•
$t0,
$t2,
$t3,
$t4,
0($t1)
$t0, $t2
4($t1)
$t3, $t4
Dynamic Pipeline Scheduling
– Hardware chooses which instructions to execute next
– Will execute instructions out of order (e.g., doesn’t wait for a
dependency to be resolved, but rather keeps going!)
– Speculates on branches and keeps the pipeline full
(may need to rollback if prediction incorrect)
23
Dynamic Pipeline Scheduling
•
•
Let hardware choose which instruction to execute next
(might execute instructions out of program order)
Why might hardware do better job than programmer/compiler?
Example #1
lw $t0, 0($t1)
add $t2, $t0, $t2
lw $t3, 4($t1)
add $t4, $t3, $t4
Example #2
sw $s0, 0($s3)
lw $t0, 0($t1)
add $t2, $t0, $t2
24
Exercise #1
•
Can you rewrite this code to eliminate stalls?
1.
2.
3.
4.
lw
lw
sw
add
$s1,
$v0,
$v0,
$t0,
0($t0)
0($s1)
4($s1)
$t1, $t2
25
Exercise #2
•
HW: 4-86 to 4-87
Show a pipeline diagram for the following code, assuming:
– The branch is predicted not taken
– The branch actually is taken
lw
beq
sub
Label2: add
$t1,
$s1,
$v0,
$t0,
0($t0)
$s2, Label2
$v1, $v2
$t1, $t2
26
Exercise #3 – Stretch
•
This diagram (from before) has a serious bug. What is it?
IF/ID
ID/EX
EX/MEM
MEM/WB
Add
Add Add
result
4
Shift
left 2
PC
Address
Instruction
memory
Instruction
0
M
u
x
1
Read
register 1
Read
data 1
Read
register 2
Registers
Read
Write
data 2
register
Write
data
0
M
u
x
1
Zero
ALU ALU
result
Read
data
Address
Data
memory
0
M
u
x
1
Write
data
16
32
Sign
extend
27
Implementing Pipelining
•
What makes it easy?
– all instructions are the same length
– just a few instruction formats
– memory operands appear only in loads and stores
•
What makes it hard?
– data hazards
– structural hazards
– control hazards
•
What make it really hard?
– exception handling
– Improving performance with out-of-order execution, etc.
28
Pipeline Control
•
Generate control signal during the ________ stage
•
_________ control signals along just like the __________
Instruction
R-format
lw
sw
beq
Execution/Address Calculation Memory access stage
stage control lines
control lines
Reg
ALU
ALU
ALU
Mem
Mem
Dst
Op1
Op0
Src Branch Read Write
1
1
0
0
0
0
0
0
0
0
1
0
1
0
X
0
0
1
0
0
1
X
0
1
0
1
0
0
Write-back
stage control
lines
Reg Mem to
write
Reg
1
0
1
1
0
X
0
X
WB
Instruction
IF/ID
Control
M
WB
EX
M
WB
ID/EX
EX/MEM
MEM/WB
29