AN ABSTRACT
OF
THE
THESIS
OF
James Chester Looney for the Electrical Engineer
(Name)
(Degree)
Date thesis is presented
Title
/ Ii:\ w
L
! 'i ^ -
The GALAXY Memory^ystem
Abstract approved
Redacted for privacy
(Major professor)
The GALAXY computer is a large, high speed, general
purpose, digital computer intended to be used for solving
scientific problems.
It requires a random access memory
system of 16,384 words of 59 bits each with a cycle time
of one microsecond or less.
A memory system capable of
meeting these requirements has been designed for ferrite
core storage elements and transistor active elements.
It consists of four sections of 4,096 words each, with
the initial installation consisting of two sections.
section has
its
own
associated current drivers
and
Each
sense
amplifiers while the memory register, decode circuits,
and timing unit are used in common by the whole system.
An experimental investigation of the memory system
gave evidence that the requirements could be met by using
presently available commercial components.
A linear
selection system was selected and investigated by using a
64 core word line and a 4,096 sense line to simulate a
core stack.
The experimental results showed that a
minimum cycle time of 700 nanoseconds could be obtained.
The results of an investigation of the system com
ponents were used to select the type of cores and plane
configuration.
Ferroxcube type 6F2 cores were used with
a word line configuration of two turns per core and a
sense line configuration of one turn per core.
Distri
buted capacitance was added to the sense line to achieve
a purely resistive characteristic impedance and thus sub
stantially reduce the post-write disturb voltage.
The investigation and design of the associated elec
tronic circuits are also discussed.
THE
GALAXY MEMORY SYSTEM
by
JAMES
CHESTER LOONEY
A
THESIS
submitted to
OREGON STATE
UNIVERSITY
in partial fulfillment of
the requirements for the
degree of
ELECTRICAL ENGINEER
June
1963
APPROVED:
Redacted for privacy
/rofessor of Electrical Engineering
Head of Department Electrical Engineering
Redacted for privacy
Chairman of School Graduate Committee
Redacted for privacy
Dean of Graduate
Date thesis is presented
Typed by Norma Hansen
School
rig u £ / J- ^3
ACKNOWLEDGMENT
The author wishes to express his sincere
appreciation to the group working on the GALAXY
computer at Oregon State University.
W. G.
Magnuson in particular, has contributed substan
tially to the work discussed in this paper.
TABLE
OF
CONTENTS
Page
SYSTEM DESIGN
1
Introduction
1
General Description
Memory Cycle
Experimental Investigation
2
5
10
Results
11
SYSTEM COMPONENTS
......
17
Cores
17
Core Planes
23
Decoding and Word Selection Circuits
Timing Unit
....
27
30
Current Drivers and Switch
32
Sense Amplifier
Memory Register
36
38
CONCLUSIONS
39
BIBLIOGRAPHY
41
LIST OF
ILLUSTRATIONS
Figure
1.
2.
Page
Block Diagram of GALAXY Memory System . „ .
4
Outputs of Timing Unit During Memory
Cycle
7
3.
Driver Current Waveforms
.........
15
4.
Signal Waveforms
„ . .
16
5„
Switching Characteristics of Ferroxcube 6F2
30 mil Core
22
6.
Word Line Selection Circuits
29
7.
Timing Unit Block Diagram
.
31
8.
Current Driver and Bilateral Switch ....
33
9.
Sense Amplifier and Memory Register ....
37
THE
GALAXY MEMORY SYSTEM
SYSTEM DESIGN
Introduction
The GALAXY computer is a large, high speed, gen
eral purpose, digital computer intended to be used for
solving scientific problems.
It requires a memory
system with a storage capacity for a large number of
words which are randomly accessible in a very short
period of time.
The design of a suitable memory sys
tem to be used in the GALAXY computer is the subject
of this paper.
The design of the GALAXY memory was based on the
following philosophies:
(1) Components presently available from commercial
sources should be used so that construction could
be started in a reasonable length of time.
(2) The cycle time should be as short as possible
consistent with high reliability and reasonable
economy.
(3) The initial capacity will be one-half of the
final capacity.
The type of storage elements and active elements to be
used in the memory system was determined by an investi
gation of the present state of the art and the above
considerations.
Small ferrite cores were selected for
the storage elements and transistors were chosen for
the active elements in the associated electronic cir
cuits .
General Description
The GALAXY memory system consists of a ferrite
core stack and associated driver,
circuits.
timing,
and sensing
The original specifications were:
ity of 16,384 words of at least 59 bits each,
cycle time of one microsecond,
time of 300 nanoseconds.
A capac
a maximum
and a maximum access
It was evident early in the
investigation that these specifications could best be
met by using a word-organized ferrite core stack con
figuration with four sections of 4,096 words each.
The four sections are independent and each has its own
drivers and sensing circuits.
The initial GALAXY in
stallation will have two sections and since the sections
are independent,
the last two sections do not have to
3
be identical to the first two.
For example, at the
time of installation of the last two sections the
technology may be such that much faster operation is
possible.
A block diagram of the memory system is shown in
Figure 1.
The basic storage section is the ferrite
core matrix.
Everything else can be considered as
auxiliary circuits for communicating with the core
matrix.
There are two fundamental paths for communica
tion with this matrix, an information path, and a con
trol path.
The information path consists of the
memory register,
sense amplifiers,
and digit drivers.
Stored words are obtained from the core matrix via the
sense amplifiers and the memory register.
Words are
stored in the core matrix via the memory register and
the digit drivers.
The memory control consists of word selection
circuits and timing circuits.
The selection of the
desired word is accomplished by the decode circuits
which use the signals on the address busses to energize
a particular combination driver circuit.
Once the
desired word is selected the timing circuits are
Control <Tr^ismit Complete
qycle Complete
Inhibit
Information
Figure 1.
Block Diagram of GALAXY Memory System.
actuated and they control the operation of the memory
during its cycle.
Memory Cycle
The memory cycle is divided into two parts, a read
portion and a write portion.
This is necessary because
the process of reading a word out of the core matrix
simultaneously erases the stored word.
Thus it is
necessary to rewrite the same word back into the core
matrix when it is to be retained.
There are two operations that the memory performs,
a read function in which a word previously stored in
the cores is delivered to the computer and a store
function in which the computer stores a word in the
cores.
Both of these operations require a full cycle
of the memory system.
The read operation will be des
cribed first in detail and the store operation will
follow.
The read operation is initiated by the computer
control circuits by supplying address signals on the
address busses and a start signal called CORE READ-WRITE
to the timing unit.
Once the start signal has been
6
applied,
the memory system proceeds under its own con
trol and the memory is independent of the rest of the
computer until the end of the cycle.
Figure 2 shows
the outputs of the timing unit beginning with the re
ceipt of the start signal.
At the receipt of the start
signal, the timing unit turns on the read driver and
the bilateral switch.
A drive of one ampere-turn from
the read driver forces all of the cores in the selected
word to the reset or zero state and any cores that were
initially in the one state produce output voltages that
are amplified in the sense amplifiers.
The outputs of
the sense amplifiers are gated into the memory register
by a strobe signal from the timing unit.
The strobe
signal only appears during the expected output from
the sense amplifiers and thus improves the signal-to-
noise ratio because any noise signals that occur during
the rest of the memory cycle cannot reach the memory
register.
As soon as the memory register has been set by
the outputs of the sense amplifiers, the timing unit
gives a Transmit Complete signal to the computer.
This
allows the word in the memory register to be used by
TIME
100
200
300
IN NANOSECONDS
400
500
600
700
800
900
1000
Read
Driver
Sense
Probe
Bilateral
Switch
Write
Driver
Digit
Driver
Transmit
Complete
Cycle
Complete
Figure 2.
Output of Timing Unit
During Memory Cycle.
-j
8
the computer as soon as possible while the memory
simultaneously rewrites the word back into the cores.
The word in the cores has been erased in the
process of read out so it is necessary to rewrite the
word back into the cores.
The timing unit starts the
rewrite process by sending signals to the write and
digit drivers.
There is a digit driver for each bit
of a word and only those digit drivers which corres
pond to bit positions containing a one in the memory
register are energized.
The energized digit drivers
put a digit current in their corresponding sense lines
and the coincidence of the digit current and the
current due to the write driver resets the cores to
their
initial
states.
The write driver puts a current of opposite
polarity to the read driver current through the word
line.
The sum of the ampere-turns of drive due to the
write and digit currents is somewhat less than the
read drive on the cores but it is enough to switch
the cores.
The write or digit drive alone will not
change the state of the cores.
In general the digit
and write drive will not be equal because,
for any
particular word, the write drive will appear only once
between read drives while the digit drive may appear
a large number of times.
state of the cores,
In order to not affect the
the magnitude of the digit drive
has to be less than the write drive.
At the end of the cycle,
the timing unit supplies
a signal called Cycle Complete to computer to indicate
that the memory is available for another operation.
The store operation is different from the read
operation in the following respects.
The word to be
stored is put in the memory register and the address
is put on the address busses before the start signal
is applied to the timing unit.
Also,
a signal is
applied to the inhibit gates in the outputs of the
sense amplifiers.
The timing unit then controls the
memory cycle in the same manner as for the read opera
tion.
The difference in operation occurs during the
read portion of the cycle in that the word read out is
lost due to the inhibit gates in the outputs of the
sense amplifiers.
cycle,
During the write portion of the
the word that was put in the memory register
is stored in the cores in place of the word that was
10
lost during the read out.
Experimental Investigation
An experimental investigation of the memory system
has been carried on to determine whether or not the
specifications for the memory system could be met.
A
64 x 64 core plane was used with all the cores connected
in series as an equivalent 4,096 core sense line and
one row of 64 cores in another 64 x 64 core plane was
used as
a word line.
The experimental system was essentially the same
as that shown in the block diagram of Figure 1.
The
main difference was that the decode circuits were not
included.
The timing unit consisted of a pulse genera
tor driving a delay line with multiple taps.
Outputs
from the taps on the delay line were then used to
trigger the pulse generators that determined the pulse
lengths of the driver circuits.
The result was a very
flexible timing system in that the pulse lengths and
starting times of the various portions of the cycle
were independently adjustable.
Most of the other
circuits used in the investigation were in their final
11
form and they are described later.
Results
In general,
the results of the experimental in
vestigation showed that the specifications for the
memory system could be met.
It was found that the cycle
time could be reduced to less than one microsecond.
The minimum cycle time is of interest because it de
termines the highest repetition rate at which the
memory is capable of being operated.
The minimum
cycle time is composed of several items:
read current pulse length,
the cores,
(3)
(1) the
(2) the switching time of
the total propagation time of the
sense line, (4) the digit current pulse length, and
(5) the post-write disturb voltage.
The contribution
to the minimum cycle time of each item will be dis
cussed in the above order.
The read current pulse length is determined by
the characteristics of the cores and is approximately
equal to the switching time of the cores.
The cores
used in this system had a switching time of 100
nanoseconds for one ampere-turn of drive and so a
12
100 nanosecond pulse was used for the read current pulse
length.
An investigation of sense line configurations
showed that a 4,096 bit line with a resistive charac
teristic impedance was best for this application.
The
sense line used was 35 feet long and had a total propa
gation time of 50 nanoseconds.
This results in a
variation in time of arrival of a signal at the sense
amplifier input.
Consequently, the minimum cycle time
is lengthened by 50 nanoseconds.
The digit current pulse length also affects the
minimum cycle time directly since the next read
operation cannot begin until the sense line has re
covered from the digit pulse.
The length of the digit
pulse is determined by the core characteristics in a
manner which will be discussed later.
However,
in
the experimental system, a pulse length of 100 nano
seconds was
used.
The post-write disturb voltage probably has the
largest influence of the five items in determining the
minimum cycle time of the memory.
This is a voltage
that remains on the sense line after the termination of
13
the digit pulse.
Unfortunately,
the amplitude of the
post-write disturb voltage is usually very much larger
than the amplitude of the signal on the sense line
caused by the read current.
Figure 2 shows that the basic cycle to the end of
the write pulse is completed in less than 400 nano
seconds, however the post-write disturb voltage may be
larger than the read output for as long as 10 micro
seconds.
In the GALAXY memory system,
the limitation
due to the post-write disturb has been greatly reduced
by adding distributed shunt capacitance to the sense
line so that it has a
pendance.
resistive characteristic im-
This results in a post-write disturb period
of approximately 250 nanoseconds and a minimum cycle
time of about 700 nanoseconds.
made for the address decode,
After an allowance is
the total minimum cycle
time should still be less than one microsecond.
One of the principal reasons for the experimental
investigation of the memory system was to determine
the feasibility of obtaining the necessary current
pulses to drive the cores.
cores in 100 nanoseconds,
In order to switch the
a drive of one ampere-turn
14
is required for 100 nanoseconds.
It is difficult to ob
tain a 100 nanosecond, one ampere pulse from the best
transistors presently available so the current require
ments were reduced by using a winding configuration of two
turns per cor for the word line.
Thus the read driver
current requirement is 500 ma for 100 nanoseconds with a
repetition rate of one megacycle.
The sum of the write driver and digit driver outputs
have to be approximately equal to one amper-turn in order
to reset the cores in 100 nanoseconds.
This is accom
plished by having the write driver supply 300 ma into the
two-turns-per-core word line while the digit driver simul
taneously supplies 400 ma into the one-turn-per-core sense
line .
The actual waveforms obtained from the current driv
ers in the experimental memory system are shown in Figure
3.
Notice
that the write current lasts about 50 nanosec
onds longer than the digit current.
This is necessary so
that the two currents will be coincident for 100 nanosec
onds even though the digit current may have had to propa
gate down the entire length of the sense line.
Figure 4 shows signal waveforms in the memory system
during a complete cycle.
The outputs of the selected
15
Figure 3
Driver Current Waveforms
Top Trace - Digit Current
Bottom
Trace
-
Read
and
Write Current
Vertical Scale - 200 ma/cm
Horizontal Scale - 100 ns/cm
(b)
(a)
Figure 4.
Signal Waveforms
Top Traces - Memory Register Output, 2 volts/cm
Middle Traces - Sense Amplifier Output, 2 volts/cm
Bottom Traces - Switched Core Output, 200 mv/cm
(a)
"1" read-out
(b)
"0" read-out
Horizontal Scale - 100 ns/cm
en
17
core,
the sense amplifier, and the memory register are
shown for a
"0".
read out of both a
stored
"1"
and a
stored
Note that the "1" is available from the memory re
gister approximately 150 nanoseconds after the beginning
of the cycle.
the memory,
This period represents the access time of
the time at which a stored word is first ac
cessible to the computer during a read operation.
The
computer is notified that the word is available by a sig
nal from the timing unit called Transmit Complete.
SYSTEM COMPONENTS
Cores
A thorough investigation of the state of the art in
dicated that at the present time small ferrite cores were
the only practical storage component for a large, fast,
random-access memory (2, p. 5).
Consequently, a major
effort was expended in evaluating the characteristics of
the newest and fastest cores available at the present
time (3).
The switching properties of 13 different types
of cores were investigated with current pulse widths rang
ing from 100 nanoseconds to one microsecond.
The cores
were tested in groups of five connected in series with a
winding arrangement of two turns per core.
The
18
measurements were quite consistent and reproducible and
are presented in Table I where the values listed have all
been normalized to one turn and one core.
Although Table
I gives only the results for the 100 nanosecond pulses,
current pulse widths of 100, 200, 300, 500, and 1000 nano
seconds were used in the
tests.
The digit current threshold, I
was taken as the
amplitude of the digit current need to cause the output to
increase 10 percent above the shuttle voltage.
The shut
tle voltage is that voltage induced in the sense winding
when the core does not switch upon applying the read cur
rent pulse.
There were approximately 1200 digit pulses
of 100 nanosecond pulse width between each read pulse for
these tests, however,
the threshold was found to be inde
pendent of pulse width as long as there were many pulses
for each read pulse.
IWT, the write current threshold, was determined in
the same way as the digit current threshold with the ex
ception that the core was reset or read out between each
write current pulse.
The quantity labeled IR in Table I is the current
required for full switching when the pulse width is 100
nanoseconds.
The risetime of the read pulse was
w
H"
pq
a)
O
in
o
o
kO
H
o
o
o
H
o
O
H
CN
O
o
O
m
n
O
o
H
o
in
O
O
H
H
o
m
O
O
CO
o
i£>
H
H
I
o
CN
H
n
o
H
o
<sf o
o
t
o
in
H
o
in
O
o
H
CN
"^
CO n
O
O
H
u
o
u
u
O
O
r^
o
r-
0)00
<
X O
o
CO CN
O
O
in
O
in
O
in
o
o
o
o
H
o
o
o
CN
CO
0
C
03
o
o
H
Sh
-P
-P
c
0)
u
u
O
H
u
H
CD
03
CN
H
a)
u
£
0
03
rC
o
CD
H
03
CN
a)
Eh
-p
^
03
H
£
•P
tn
•H
•H
Q
Q
Eh
Sh
H
II
-P
0
<
U
-P
G
<D
I
H
o
g
m
Eh
X
h
i
a)
a,
1^
o
o
co co co co co
o
o
o
•*$
o
O
o
en
r-m o
oooi^^ujHco^ojmm^^
O
O
<tf
H
O
in
O
O
in
H
H
o
O
n
O
O
H
H
HOOOOHOOOOOOO
o
o
CO
CN
^roini^^mminkDootM
O
in
o
o
o
H
>
"-^
^
Eh
fO
H
Eh
Q
H
SSoco^iniom
•
cji a
u
N
u
u
o
O
in
OOOOOPufXO
u
u
<D g
X
ass
O
in
u
4-1
O
m
U
(N CM
U
O
m
a,
~" o
r-kDinoorHinrHiH
CM CM
H
I
I
I
g
eh
03
H
•H
a
rG
T3
QJ H
N
•H
03
-P
a
o
CO 0)
tJ
CD -H
M
0
u
0)
03
3
Cn
-P
0)
C
i-i
u
rd
0)
ps
o
o
cn
M
•p
m
0)
ft
Eh
a)
§•
-p
•H
0)
a
-P
w
o
o
0)
u
•H
0)
P
in
>
rd
•P
•P
C
d)
U
u
-p
H
U
rG
ed
19
20
approximately 1 nanosecond and that of the digit and
write currents about 18 nanoseconds.
For full switching,
the core induces a "one"
voltage in the sense winding.
This is called E
Table I where the peak voltage is given.
in
The read
current for these measurements was 1.5 amperes.
Since the memory cycle was specified to be one
microsecond or less, the switching characteristics
with pulse widths of 100 nanoseconds were of most
interest.
It was decided that the fully switched type of
core operation was to be preferred over the partially
switched version.
Although full switching does have
the disadvantage of producing more heating in the
cores, it has the advantage of less stringent require
ments on current levels and driver circuits.
To obtain full switching, the sum of the write
and digit drives must fully set the core.
Only one
core was found to meet this requirement for 100
nanosecond pulses,
the Ferroxcube 6F2 30-mil core.
At
an ambient temperature of 70°F it has a digit threshhold of 450 milliampere-turns (ma-turns), a write
21
threshold of 650 ma-turns, and it will switch fully
with 1100 ma-turns using 100 nanosecond pulses.
The
switching characteristics of the Ferroxcube 6F2 core
are shown in Figure 5.
The operating characteristics of the cores above
ambient temperature are also important.
Heating effects
due to external equipment and the power dissipated by
the cores will both tend to raise the temperature of
the core stack.
The maximum possible power dissipated
in the core stack is simple to calculate since it can
only be due to the outputs of the current drivers.
The
results of such a calculation for a 4,096 word stack
in the GALAXY memory system gives 1.5 watts maximum
dissipation for operation at one megacycle.
As temperature increases, the following changes
take place in the core characteristics:
The digit
threshold current decreases at the rate of 2.8 ma/°C;
the write current threshold increases at the rate of
about 5 ma/°C; and the knee of the write current curve
becomes progressively more rounded with increasing
temperatures.
The shuttle voltage, which is the
voltage induced in the sense winding when reading a
CO
rt
O
22
I
CD
H
l-i
0
^
Hi
0
en
Ho
cn
CD
H
CD
3
^
PJ
HH
H
H-
3
K
H- DJ
H
n
rt
n
cd
0
i-i
l-i HCD CQ
•
rt
3
H-
3
pj
o
rt
3
H
H
CD
o
d
rt
CD
if
O
u>
U3
CTi tf
hr) p.
M 3
CD
£tf H$
O
•
Ul
H
CD
H
H-
H
O
O
O
o
00
o
CTi
O
O
o
O
4^
o
o
ua
c
to
*1
H-
3
cn
,_,
CO
cn
CO
3
13
3
3
CO
H
O
O
NJ
O
O
tf f"
,—.
LO
0
,-»
o
o
&
CD
Cn
O
O
.—.
^—.
H
O
O
O
o
o
to
o
o
in millivolts
13*
13
02
rt
CD
M
CD
H
CO
T1
Digit Threshold Current
o
o
Output Voltage E
23
zero,
increases slightly with temperature about
1 mv/°C, but the read out voltage for full switching
remains fixed at about 300 mv.
To select the nominal operating current levels,
the maximum temperature at which the memory is to be
operated must be specified.
Fifty degrees Centigrade
was selected as an upper limit for ambient temperature
and experiments with the Ferroxcube 6F2 cores deter
mined the following current specifications:
ID (max) = 400 ma for 100 ns
Iw (max) = 600 ma for 150 ns
IR (min) = 1000 ma for 100 ns
When operating at 50°C the shuttle voltage will be
about 35 millivolts and the output voltage for a "1"
will be about 150 millivolts.
Core
Planes
Ferrite core memories usually consist of a
number of planes of cores wired together to form a
stack.
The manner
in which the cores
are wired into
the planes and the planes into stacks is a major factor
in determining whether or not the system requirements
24
can be met.
The type of wiring configuration selected
for the GALAXY memory stack is a linear selection system
with a two-turns-per-core word line and a single-turnper-core sense line.
This type of configuration was
chosen as a result of an investigation of the more
important factors such as cost, speed, signal to
noise ratio, and power requirements (3).
All of the above factors are affected appreciably
by one circuit in particular,
the sense line.
The in
dependent parameter of the sense line is the circuit
configuration.
The dependent parameters are:
to noise ratio,
propagation time,
signal
characteristic im-
pendance, power dissipation, and ease of wiring.
These will be discussed briefly below.
The signal to noise ratio is adversely affected
by capacitive and inductive coupling with the word
line, partially excited cores,
disturb voltage.
and the post-write
Unfortunately, there is no wiring
configuration that will minimize all of these items
simultaneously.
Consequently, the ones that cause the
most trouble receive the most attention.
These are
the post-write disturb voltage and the word line
25
coupling.
The propagation time is directly proportional to
the length of the sense line and directly proportional
to the square root of the product of the unit inductance
and capitance of the line.
The inductance can be re
duced by increasing the spacing between the cores but
this increases the length because the number of cores
is fixed.
The capacitance can be varied by changing
the position of a ground plane but this also affects
the characteristic impedance of the line.
The characteristic impedance is approximately
Zo =/L
It is desirable to minimize the characteristic im
pedance to reduce the voltage swing on the digit
current drivers.
It is also desirable to have a purely
resistive characteristic impedance to minimize the
post-write disturb voltage.
If the inductance is reduced, the line length will
be increased and this will also increase the coupling
from the word line.
If the capacitance is increased,
the propagation time will be increased.
Thus there is
26
no simple optimizing procedure.
The largest single gain in performance was ob
tained by adding capacitance to the sense line to
achieve a purely resistive characteristic impedance.
This reduced the period of the post-write disturb
voltage by an order of magnitude.
Measurements were made on a 4,096 core sense line
that was wired in the form of a 64 x 64 plane.
Numer
ous configurations were investigated (3) and the one
that gave the best results was a single wire with
added distributed shunt capacitance.
The line had a
characteristic impedance of 180 ohms and a propagation
time of 50 nanoseconds.
The word line configuration was selected mainly
on the basis of what was available for read and write
current driver transistors.
The required drive on
the cores is one ampere-turn and since the current
drivers were not capable of providing a one ampere,
100 nanosecond pulse,
Measurements
on a
two turns are used.
64 core word
line of two turns
indicated that there would be 18 volts across the line
during the switching time for a current pulse of 500
27
milliamperes.
This corresponds to the read driver
output and it has a duty cycle of approximately 10
percent.
The average power output of the read driver
is then equal to 900 milliwatts.
Decoding and Word Selection Circuits
The GALAXY memory system includes a ferrite core
matrix with a total capacity of 16,384 words.
This
requires a 14-bit address in order to select one word
out of 16,384 and another bit has been included in
the address to allow the selection of half words.
The
two most significant bits of the address are used to
select one out of four memory banks and the next 12 bits
are used to select one word out of the 4,096 words in
each section.
The least significant bit is used to
designate a particular half of the selected word if
desired.
Of the 12 bits used to select one word out
of 4096,
six bits are used to select one out of 64 X
lines and the other six bits are used to select one
out of 64 Y
lines.
A two-stage diode sectional matrix is used to
convert six address bits into 64 outputs.
Each matrix
28
requires 175 diodes and there are two matrices, one for
the X lines and one for the Y lines.
connected to all four memory banks.
Each matrix is
The connection
points are the inputs of the current drivers and
switches which are effectively in series with the X
and Y lines.
Each memory bank has its own set of
drivers and switches and their outputs are connected
to the corresponding X and Y lines of the core matrices.
For example, the line X]_ from the output of the decod
ing matrix is connected to the inputs of the four X,
current drivers.
The outputs of the four X^ drivers
are connected to the X-^ lines of their corresponding
core matrix.
Figure 6 shows the connections for the
selection of a particular word in one plane of one
bank.
, The selection of the desired memory section from
the four available is accomplished by a bank decode
circuit using transistors.
The bank decode outputs
select the addressed memory bank by gating the outputs
of the timing unit to only that bank.
The final stage of decoding is incorporated in
the wiring of the 4,096 word memory bank as shown in
Read
Read
Driver
X^ decodeoooooooooooo
ooooo
^
Y]_ Line
Write
Write
Driver
Read
& Write
Bilateral
Switch
Y^ decode
T
Figure 6.
Word Line Selection Circuits.
30
Figure 6.
The output of a selected X current driver
and a selected Y switch determine one particular word
out of 4,096 words.
The plane shown in Figure 6 would
be the bottom plane and there would be 63 more stacked
above it.
Timing Unit
The timing unit is the control for the memory
during the memory cycle.
To accomplish this, it has
to deliver a variety of timing pulses of proper se
quence,
duration,
in the memory.
and magnitude to different sections
The timing sequence and duration of
the pulses required from the timing unit are shown in
Figure 2.
A block diagram of the timing unit is shown in
Figure 7.
A pulse from a blocking oscillator is
applied to an 80 section lumped-constant delay line.
The signals from taps on the delay line are used to
trigger monostable multivibrators which give the
proper length pulses for the various functions.
The
outputs of the multivibrators are connected to tran
sistor gates which are operated by the outputs of the
Outputs
To
Bank
1
Outputs
To
Bank
2
From
Memory
Outputs
To
Bank
Bank
3
Decode
Outputs
To
Bank
Cycle
Complete
Block
Core
Read-
Write
ing
-HOscilla-
£Si
80 Section LC
Delay
Line
(500 ns)
se
Generator
Figure 7.
Timing Unit Block Diagram.
u>
4
32
memory bank decode circuit.
Since there can only be
one output from the bank decode circuit, the outputs
of the timing unit are connected to only the selected
memory bank.
Current Drivers and Switch
There are three types of current drivers and a
bilateral switch needed for the operation of the
memory system.
The way in which these circuits are
used has already been discussed so this section will
be limited to information about the circuits themselves.
' The read driver and write driver circuits are
almost identical except for the polarity of output
and the change in polarity is obtained by means of a
pulse inverting transformer.
Both of these drivers
are operated in the class A mode so that they will
appear as
current sources to the word line.
The
amount of current that is delivered is determined by
the size of a resistor in the emitter of the output
transistor.
Figure 8 shows a schematic of the circuit for the
read or write driver.
Complementary symmetry circuits
-21
33
180
r-Wv—
h^wJ—r
0.1
300
Word
Line
\
Decode
300
Timing
(a) Read or Write Driver
+6
180
470
Hs»- To
-/VW-
Timing
AAA
£
360
300
Sense
Line
•240
Memor
y-72
Register
(b) Digit Driver
+ 10
Decode
fc*-J
Timing
(c) Bilateral Switch
Figure 8.
Current Drivers and
Bilateral Switch.
34
are used so that all three stages are normally off.
Since no more than one read or write driver is used
for a memory operation, the total average power dis
sipated is very low.
The first stage of the driver is actually a tran
sistor gate that is operated by the decode and timing
signals.
The decode input is a dc level which is too
low to turn on the transistor until the timing signal
is applied.
However,
if the decode signal is not
present, the timing signal cannot turn on the tran
sistor.
The digit current driver is somewhat different
than the read and write drivers.
The difference is
due to the vastly different impedance of the sense
line as compared to the word line.
The digit driver
has to deliver 400 ma of current into the 180 ohm
sense line and this requires a 72 volt swing.
This
is a considerably more exacting requirement than that
of the read amplifier which delivers 500 ma into a
maximum of 36 ohms or 18 volts.
However,
the fact that
the sense line is a constant resistance of 180 ohms is
an advantage in that the digit driver can be operated
35
in the saturated mode and still provide a constant
current.
This is not possible with the read and
write drivers because the impedance of the word line
depends on how many cores might be switching.
The bilateral switch is connected to the opposite
end of the word line from the read and write drivers.
Its function is to provide a low impedance path to
ground for either polarity current.
This is accomp
lished by two saturated transistors connected in
parallel,
one with grounded emitter and the other with
grounded collector.
A blocking oscillator drives the
output transistors and it in turn is triggered by the
first transistor stage which is operated by the decode
and timing pulses.
As can be seen in Figure 8, series
diodes are included in the output line to protect the
transistors when they are turned off.
A
number of variations of driver circuits have
been investigated (3) and with the present state of the
transistor art, it is just barely possible to fulfill
the current driver requirements.
However, by the time
construction begins on the computer, better devices may
be available.
36
Sense Amplifier
The sense amplifier is used to amplify the small
information signal that is obtained from the cores so
that it may be transmitted to the computer.
The re
quirements for the sense amplifier are as follows:
Input signal:
100 mv across 180 ohms,
Output signal:
In addition,
50 ns pulse,
2 volts across 1000 ohms,
pulse.
50 ns
the sense amplifier must be able to with
stand a negative 70 volt digit pulse at its input just
previous to the information signal without any adverse
effects.
This requirement rules out the possibility of
using any reactive elements in the first stage.
Although the design of the sense amplifier is not
considered final,
it presently consists of an emitter
coupled first stage and an output stage and is shown
in Figure 9.
The output stage has provisions for an
inhibit input and a timing strobe signal.
A forward
biased diode is used in series with the input to de
couple the sense amplifier from the sense line during
the time that the negative 70 volt pulse from the digit
driver is applied.
The voltage at the input of the
>. To
Digit
Driver
-4,
Sense
_Line _
^~<
180
-\_r
To
Digit
Driver
+6
Figure 9,
Inhibit
Strobe
Computer
Sense Amplifier and Memory Register,
co
38
first transistor during the digit pulse is thereby
reduced from 70 volts to approximately 0.6 volts which
is the forward voltage across the diode.
The output stage bias is set so that neither a
"1" output from the first stage nor the strobe signal
alone can turn it on.
The sum of the two signals will
turn on the output stage unless the inhibit signal is
present.
The inhibit signal reduces the bias so that
the output stage cannot be turned on under any circum
stances .
The output of the sense amplifier is connected to
the SET input of the memory register.
The signal
waveforms obtained at the sense amplifier output in
the experimental system are shown in Figure 4.
Memory Register
The memory register is used to store information
while
puter.
in transit between the
core
stack and
the
com
The basic element of the memory register is a
bistable multivibrator and the circuit is identical to
those used in the registers in the B section of the
computer.
39
All of the inputs and outputs of the memory
register have transistor gates in series to control the
path of information flow.
One of the inputs of each bit
is permanently connected to the corresponding digit
driver.
The memory register is cleared by the computer
control at the beginning of each memory cycle at the
same time that the address bus register is filled.
This is accomplished by inserting a word which is all
zeros.
If the clear operation is omitted,
logical
operations can be performed by inserting more than one
word.
CONCLUSIONS
The design of a large,
fast,
random access
memory system for use in the GALAXY computer is
essentially complete.
Theoretical and experimental
investigations have shown that the original specifi
cations can be met at the present time.
Investiga
tions will continue until construction is started so
that the latest advances in solid state technology may
be included.
40
A feature of the memory system design will allow
an addition of another 8,192 words at some later time
with entirely different and presumably faster circuits.
41
BIBLIOGRAPHY
1.
Haynes, John L. and Robert C. Minnick. Magnetic
Core Access Switches. Menlo Park, California,
Stanford Research Institute, May 1961.
(SRI
Project 3184.
Contract AF30(602)-2227) (RADCTR-61-117B.
Technical Supplement to RADC-TR61-117A)
2.
Miller, Steve W. Fundamental Investigation of
Digital Computer Storage and Access Techniques.
Menlo Park, California, Stanford Research Insti
tute, May 1961.
(SRI Project 3184.
Contract
AF30(602)-2227)
3.
(RADC-TR-61-117A.
ASTIA 260117)
Oregon State University.
Galaxy Computer.
II.
Electrical Engineering Section Progress Report.
Corvallis, November 1962.
N. p.