ALCT2000 Users Manual
(Version 1.0)
Martin von der Mey
Jay Hauser
University of California at Los Angeles
July 8, 2000
1
1 Introduction: ALCT2000 and LCT99-mod
The ALCT2000 system consists of two boards, the ALCT2000 board (see Figure 1) and the
LCT99-mod board (see Figure 2).
The master specication documents (very detailed) are located at (for ALCT2000)
ftp://cos.physics.ucla.edu/pub/cms/alct2000/documentation/alct 2000 spec.PDF, and (for LCT99)
ftp://www-collider.physics.ucla.edu/pub/cms/lct99/documentation/lct99 spec.ps. The user may nd them helpful
in case of detailed questions or if the user makes an unusual choice of conguration (not
recommended). This Users Manual defers to those documents in case of any conict. Updates
(if any) will be posted at the UCLA-CMS trigger web site,
http://www-collider.physics.ucla.edu/cms/trigger/ .
A good source for DAQ and other conguration information are the various instructional
les written by Lisa Gorn that can be found on the web in directory http://www.phys.u.edu/ gorn/.
The ALCT2000 board is mounted directly at the muon chamber and gets as input,
discriminator pulses from the anodes. It processes this information using pattern nding
logic and communicates the result to the LCT99-mod board. It also has test pulse and other
control features (threshold, delay) used in testing and operating the front end anode (AFEB)
boards.
The LCT99-mod board serves as an interface module between the ALCT2000 board
and the DAQ system. Originally LCT99 boards were used directly for triggering purposes.
Since these boards mainly consist of a large programmable chip with many inputs, modifying mostly the software in the programmable chip allowed us to use LCT99-mod to read
out ALCT2000 without building a new board. Some slight hardware modications were
necessary, for example, to allow external triggering of ALCT2000. In the nal system, the
functions of the LCT99-mod board as well as the Trigger Motherboard (TMB) will be included in the CLCT/TMB combination board.
2 Initial Handling, Power Supply
The ALCT2000 and LCT99-mod boards are large and moderately fragile, so must be handled
with care not to bend them or disturb the special wires. It is imperative to apply only the
correct voltages to power the boards. Also, the initial switch and jumper settings on both
boards are probably what is desired, so do not change them without good reason.
The LCT99-mod board sits in a 9U VME-crate having a J1 backplane but otherwise no
J2 or J3 or other backplanes. LCT99-mod is powered from the standard J1 backplane.
The ALCT2000 board has a special power connector which attaches to a cable from
the on-chamber low-voltage distribution board. It has to be supplied with three dierent
voltages: 5.5 V, 4.3 V and -3.3 V. These voltages should be set to within 0.05 V of their correct
values. The power supply voltages should be checked rst before any boards are plugged in,
and then again later after all boards are plugged in. If there is a large overvoltage situation,
fuses on the ALCT2000 board will blow out. These fuses are located on the bottom side
of the board (away from the input connectors), which is somewhat inconvenient. There are
LEDs to indicate rough power supply status and accessible test points to read the voltage
on the board.
2
3 Default Hardware Settings for ALCT2000
The ALCT board has a variety of switches and jumpers which should be set to the appropriate positions, otherwise the board may not function in the correct mode and diagnosis
can be very dicult. The locations of rotary switches, DIP on/o switches, and jumpers
(shunts) on the board are indicated in Figure 1.
SW1
SW2
SW3
SW4
SW5
SW6
SW7
SW8
SW9
up
up
up
right
right
left
left
left
down
Table 1: Names and default settings of the shunts on the ALCT2000 board.
The settings of these switches will be described in order of their designated switch number.
Switches SW1-SW9 are 3-pin shunts. All are connected by 2-pin jumpers. Their settings
can be found in Table 1. The settings listed in Table 1 (left, right, up and down) corespond
to a view of the board as in Figure 1.
Then there is a single hexadecimal (0-F) rotary switch designated as SW10. This switch
has the default setting at 1.
1
2
3
4
5
6
7
8
9
10
11
12
ON
ON
OFF
ON
ON
ON
ON
ON
ON
ON
ON
OFF
Table 2: Names and settings of the SW11 On/O DIP switches on the ALCT2000 board.
Finally there is a DIP switch designated as SW11 that contains 12 On/O settings. The
12 default On/O settings are listed in Table 2.
3
STAT L1A WIN (Time window for Level 1 Accept signal)
STAT HALT (ALCT Halted)
STAT PRETRIG (Pretrigger found)
STAT INVPAT (Invalid Pattern: pretriggered but no valid pattern found)
STAT TMB (Sending a muon trigger to Trigger Motherboard)
STAT L1A (Level 1 Accept received)
STAT DAQMB (Sending a muon trigger to DAQ Motherboard
STAT SEQ BUSY (Sequencer Busy after pretrigger and Level 1 Accept)
Table 3: Names of the oscilloscope test points on the ALCT2000 board.
For purposes of debugging with an oscilloscope, there are several useful test points on the
ALCT2000 board. The most important names for the test signals at the ALCT2000 board
can be found in Table 3.
4 Default Hardware Settings for LCT99-mod
The LCT99-mod board has a wide range of functionality, and many settings can be set using
software as well as hardware. The hardware settings are set using a variety of switches and
jumpers. The switches and jumpers should be set to the appropriate positions, otherwise
the board may not function in the correct mode and diagnosis can be very dicult. The
locations of rotary switches, DIP on/o switches, and jumpers (shunts) on the board are
indicated in Figure 2.
The LCT99-mod board has 14 rotary hexadecimal (0-F settings) switches on the board.
These are named rather than numbered. The names and default settings can be found in
Table 4
The LCT99-mod board has 2 DIP switches, labelled as DIP10 and DIP8 in Figure 2.
The names and settings for the 8 switches of DIP8 can be found in Table 5. The names and
settings for 10 switches of DIP10 can be found in Table 6.
The LCT99-mod has 32 shunts, labelled as SH0-SH31. Most of these are 3-pin shunts,
congured by 2-pin jumpers. Their names and settings can be found in Table 7. The settings
left and right correspond to viewing the board according to the shunt labels written on the
board or the shunt labels shown in Figure 2.
5 ALCT2000 Cable Connections
The ALCT2000 and LCT99-mod boards are connected by two 8m long \Skewclear" cables
with SCSI-type connectors. These high-performance cables are required because the Channel
Link chip set used for data transmission sends and receives signals at seven times the input
40 MHz frequency, i.e. 280 MHz. Ordinary twisted-pair or twisted-at cables give frequent
data errors at these frequencies.
4
CSC ID
Board ID
FIFO mode
FIFO time bins
FIFO Pretrig Tbins
BXN Oset
Drift Delay
L1A Window
L1A Delay MSB
L1A Delay LSB
L1A Count Oset
Pattern Threshold
Plane Threshold
FEB Clock Delay
6
0
0
D
1
0
3
2
7
C
0
2
4
8
Table 4: Names and settings of the hexadecimal (0-F) rotary switches on the LCT99-mod
board.
1.
2.
3.
4.
5.
6.
7.
8.
/ENX
L1A
HALT
RESU
INTP
/FCK
(no name)
(no name)
ON
ON
ON
ON
ON
ON
ON
ON
Table 5: Names and settings of DIP8 switches on the LCT99-mod board.
5
1. /PD0
2. /PD1
3. /PD2
4. /PD3
5. /PD4
6. /PD5
7. /PD6
8. /PD7
9. /PD8
10. /PD9
OFF
OFF
ON
ON
ON
ON
ON
ON
OFF
ON
Table 6: Names and settings of DIP10 switches on the LCT99-mod board.
SH0-SH14
SH15
SH16
SH17
SH18
SH19
SH20-24
SH25-28
SH29-31
left choice
unconnected
unconnected
connected (2-pin-shunt)
right
right
right
left
left
Table 7: Names and settings of the shunts on the LCT99-mod board.
6
Besides the power connector and the Skewclear connectors already mentioned, the ALCT2000
board has two additional 20-pin-connectors used for conguration of the programmable logic
from a computer. The two connectors are labeled with JTAG and ALTERA. (Both of these
actually program the board using a protocol for communicating with chips known as JTAG.
A serial chain links all of the programmable chips on the ALCT2000.)
Normally, the ALCT2000 programmable logic is congured automatically to some acceptable default state upon power-up from ash-RAM chips. One often wants to use a
slightly dierent conguration from that stored in the ash RAMs, and for this purpose,
the JTAG connector receives dierential LVDS signals from a small Carnegie-Mellon/PNPIdesigned box, which translates TTL-level signals from a computer parallel port to LVDS
levels. This connection is often used to change conguration under software control via an
ALCT conguration le.
The Altera connector receives TTL-level signals, and is connected to a PC equipped with
an Altera ByteBlaster interface. This is only used on infrequent occasions if the ALCT2000
board needs serious re-programming.
6 LCT99-mod Cable Connections
As previously mentioned, the LCT99-mod and ALCT2000 boards are connected by two
8m Skewclear cables. These run from the LCT99-mod FEB0 and FEB4 connectors to the
ALCT2000 SCSI-type connectors as indicated in Figure 1.
There are also some small front-panel connections to the FAST site DAQ system. The
middle pair (pins 5,6) of the ECL IN connector brings the external trigger signal from
the scintillators to LCT99-mod through a NIM/ECL converter unit. On the ECL OUT
connector, the 3rd row from the top (pins 11,12) is used to bring out a fake Level 1 Accept
signal (that is delayed 3.0 us from the external trigger signal) to the NIM logic. The 5th row
from the top (pins 7,8) brings out a clock signal to a TDC channel to measure the phase of
the 40 MHz clock with respect to the scintillator trigger.
LCT99-mod must also be connected via three rear standard cables to the CCB (Clock and
Control Board), TMB (Trigger MotherBoard) and DMB (DAQ Mother Board) as follows.
Using a connector at the rear of the LCT99-mod board the LCT99-mod-board sends
anode trigger data to the TMB (Trigger Mother Board). The communication is using LVDS
Channel Links. For the description of the data format, see
http://www-collider.physics.ucla.edu/cms/trigger/ . For information about the Trigger MotherBoard, see
http://bonner-ntserver.rice.edu/motherboard/, in particular
http://bonner-ntserver.rice.edu/motherboard/tmb.htm .
A second connector at the rear of the LCT99-mod board connects it with the Data Aquisition
MotherBoard (DAQMB). The LCT99-mod module sends 2 LCT data words, Active-FEB bits,
and wire group FIFO dump data using the rear connector to the DAQMB. The DAQMB module
stores the LCT data it receives in a FIFO for every 25 ns clock cycle. The DAQMB transmits its
own output data over an optical link to a PCI card, which connects to a computer. For detailed
description see the Ohio State electronics page at
http://mills.mps.ohio-state.edu/ ling/elec/ .
7
A third connector on the rear of the LCT99-mod board connects it with the CCB (Clock and
Control Board). The LCT99-mod-board receives over this connector the 40 MHz system-clock, the
Level 1 Accept bit, and Bunch Crossing (BX) control bits. The BX-0-bit starts the LCT99-mod
Bunch Crossing Counter and Event Counter, and The BX-Reset-bit stops them and loads them
with the preset values. The preset values compensate for dierent processing times of Cathode and
Anode LCT99-mod modules. Detailed information on the CCB may be found at
http://bonner-ntserver.rice.edu/motherboard/Archive/CCB spec.pdf
7 ALCT2000 Software Conguration
As mentioned previously, the ALCT2000 programmable logic is normally congured automatically
to some acceptable default state upon power-up from ash-RAM chips. One often wants to use a
slightly dierent conguration from that stored in the ash RAMs, and for this purpose, the JTAG
connector receives dierential LVDS signals from a small Carnegie-Mellon/PNPI-designed box,
which translates TTL-level signals from a computer parallel port to LVDS levels. This connection
is often used to change conguration under software control via an ALCT conguration le.
At present, ALCT conguration les are found in the FAST site computers in the
/home/fast/data/afeb cong area. File afeb cong 0029 is currently recommended for the
default mode of operation, i.e. external triggering by scintillators and the NIM logic that controls
TDCs, etc. This le is a text le containing all of the parameters that can be set using the JTAG
conguration cable. If the trigger logic is changed, it is likely that the ALCT conguration le will
need to be revised, especially to adjust timing.
The digital part of ALCT2000 consists of 5 chips : one Concentrator chip and 4 LCT chips
(LCT0 to LCT3). A decision of whether a muon has crossed the muon-chamber or not (patternnding) is taken in these chips. The LCT chips handle 96 wire groups with some overlap for muons
crossing boundaries, and the Concentrator chip coordinates control signals and chooses muon LCTs
from those presented to it by the LCT chips (in the case of multiple LCTs). These chips have a
large functionality and a large number of operation modes. The dierent operation modes can be
selected using the JTAG chain.
The analog part of ALCT2000 consists of the slow control chip and a pulse generator circuit.
The slow control chip controls the thresholds for the front-end AFEB discriminator chips, as well
as the time delay for the LVDS-to-TTL converter/time delay chips on the ALCT2000 board. The
pulse generator circuit can be used to generate variable-height input pulses for the ALCT2000
board for testing purposes, either by pulsing through the AFEB preamplier/discriminator chips,
or by pulsing a test strip in one of six CSC layers, which couple capacitively to the wires.
8 LCT99-mod Software Conguration
LCT99-mod is a programmable module that, like ALCT2000, boots up from its ash-RAM chips.
It is possible to re-program the board from a front-panel Altera Byteblaster connector. However,
due to the simplicity of this module, usually no modication of the default conguration needs to
be made.
8
ID
PRTRG
L1A OK
NO L1A
INVPAT
HALT
FEB0
FEB1
FEB2
FEB3
FEB4
1ST 6
1ST 5
1ST 4
2ND 6
2ND 5
2ND 4
TCK
CFD
FUNCTION
Pretrigger: sucient hits in a pattern to pre-trigger.
Level 1 Accept arrived in the L1A window.
Level 1 Accept did not aarived in the L1A window.
Invalid Pattern: No valid pattern remains after drift delay.
Sequencer halted.
FEB0 hit.
FEB1 hit.
FEB2 hit.
FEB3 hit.
(FEB4 hit-not valid for ALCT2000).
1st best muon has 6 layers hit.
1st best muon has 5 layers hit.
1st best muon has 4 layers hit.
2nd best muon has 6 layers hit.
2nd best muon has 5 layers hit.
2nd best muon has 4 layers hit.
JTAG clock during initialization.
Altera Conguration done.
Table 8: Names and meaning of the LEDs on the LCT99-mod front-panel.
9 Front Panel LED Indicators and Timing Settings
A way to notice some problems while installing the ALCT-System are the Front-panel LEDs on
the LCT99-mod. These indicate the status of the LCT99-mod sequencer logic. The lights ash on
response to a pre-trigger state. The dierent LEDs and their functions are described in Table 8.
When the system is in good shape the LEDs for PRTRG, L1OK, FEB0-FEB3 and CFD should be
ON or ashing.
One of the main problems in setting up the system is getting all signals in the right timing to
each other. For this reason, we show and explain next the measured signal curves for the main
signals for a running system that was set up properly.
We compare the measured signals with the time window for the Level 1 Accept signal to arrive
(STAT L1A WIN) as reference. The following plots are from an oscilloscope connected to the
ALCT2000 test points mentioned earlier.
Figure 3 shows the Level 1 Accept signal at the bottom compared to the Level 1 Accept Window
(STAT L1A WIN) at the top. For getting any output of the ALCT-System the Level 1 Accept
signal has to be timed within the Level 1 Accept window. The Level 1 Accept window is 100 ns
wide. The Level 1 Accept signal is 25 ns wide.
Figure 4 shows at the bottom the Pretrigger signal compared to the Level 1 Accept Window
signal. The Pretrigger signal is timed 3 s before the Level 1 Accept Window signal.
Figure 5 shows at the bottom the signal going to the Trigger MotherBoard in comparison to
the Level 1 Accept Window. The TMB-Signal arrives 3 s before the Level 1 Accept Window.
Figure 6 shows at the bottom the DAQ Motherboard signal (STAT DAQMB) as measured
at the ALCT2000 board. The pulse begins at the same time with the Level 1 Accept Window
9
(STAT L1A WIN) and remains for 20 s.
Figure 7 shows at the bottom the busy-signal coming from the sequencer as compared to the
Level 1 Accept Window signal. The signal begins 3 s before the Level 1 Accept Window signal
and rests for 23 s.
10
Config.
JTAG
To
FEB4
Altera
SW6 SW4
To
FEB0
SW9
Power
In
SW10
SW7 SW5
SW8
SW11
Test
Points
AFEB1
SW3
SW1
SW2
AFEB24
Figure 1: Picture of the 384-channel ALCT2000 board. The locations of rotary switches,
DIP on/o switches, and jumpers (shunts) on the board have been indicated.
11
P13
SW
13
A1
P19
U4
U10
P20
SH7
SH6
P21
U7
J8
ECL
Out
1
P23
U9
P24
U8
U6
SH9
SH8
P25
U29
SH19
SH18
U20
1
J7
To CCB
1
J6
To TMB
1
J5
To DAQMB
SH10
SH31
1
J9
1
U16
U5
P18
U21 U22 U28 U33
J10
X1
SH11
SH30
1
J4
SH16
SH17
SH15
P17
P22
FEB4
JTAG
In
ECL
In
U26
SH12
SH29
SH5
SH4
U25
U27
P15
P16
LED19
LED20
LED21
U17
U2
U3
P12
VME
J1
I/O
U34
32
U19
P34
U35
SH14
SH13
U18
U1
U0
8
DCBAZ
CSC ID
DIP8
FEB3
1
J3
Board ID
1
J2
FIFO mode
FEB2
FIFO time bins
10 1
U36
FEB Clock Delay
1
J1
BXN Offset
FEB1
FIFO Pretrig Tbins
DIP10
P33
SH3
SH2
Drift Delay
1
J0
L1A Window
1
FEB0
/ FCK
INJP
RESU
HALT
IL1A
/ ENX
P11
SH1
SH0
1
SW SW SW SW SW SW SW SW SW SW SW SW SW
1
2
3
4
0
5
6
7
8
9 10 11 12
/PD9
/PD8
/PD7
/PD6
/PD5
/PD4
/PD3
/PD2
/PD1
/PD0
U32
RN31
L1A Delay LSB
U24
L1A Delay MSB
RN15
L1A Count Offset
U23
Pattern Threshold
RN14
Plane Threshold
LED1
LED2
LED3
LED4
LED5
LED6
LED7
LED8
LED9
LED10
LED11
LED12
LED13
LED14
LED15
LED16
LED17
LED18
U31
SH20
SH21
SH22
SH23
SH24
U30
SH26
SH27
SH28
SH25
UCLA LCT99 Module
6-July-2000
Figure 2: Diagram of the LCT99-mod board used for reading out ALCT2000. The locations
of connectors, rotary switches, DIP on/o switches, and jumpers (shunts) on the board are
indicated.
12
Figure 3: The curve at the bottom represents the Level 1 Accept signal (STAT L1A). The
curve at the top shows the measured curve for the Level 1 Accept Window (STAT L1A WIN).
13
Figure 4: The curve at the bottom represents the Pretrigger signal (STAT PRETRIG). The
curve at the top shows the measured curve for the Level 1 Accept Window (STAT L1A WIN).
14
Figure 5: The curve at the bottom represents the Trigger Motherboard signal (STAT TMB).
The curve at the top shows the measured curve for the Level 1 Accept Window
(STAT L1A WIN).
15
Figure 6: The curve at the bottom represents the Bunch Crossing Signal. The curve at the
top shows the measured curve for the Level 1 Accept Window (STAT L1A WIN).
16
Figure 7: The curve at the bottom represents the Sequencer Busy signal (STAT SEQ BUSY).
The curve at the top shows the measured curve for the Level 1 Accept Window
(STAT L1A WIN).
17