Design of a Very High Frequency Resonant Boost
DC-DC Converter
by
Justin Burkhart
B.S., University of Massachusetts (2006)
Submitted to the Department of Electrical Engineering and Computer Science
in partial fulfillment of the requirements for the degree of
Master of Science
MA5SACHUSETTS INSTITUTE,
OF TECHNOLOGY
at the
JUL 12 2010
MASSACHUSETTS INSTITUTE OF TECHNOLOGY
LIBRARIES
June 2010
@ Massachusetts Institute of Technology, MMX. All rights reserved.
A
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Departm
t of Electrical Engineering and Computer Science
May 21, 2010
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Certified by
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David Perreault
Associate Professor of Electrical Engineering
Thesis Supervisor
A7
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Accepted by
Terry P. Orlando
Chairman, Department Committee on Graduate Students
Design of a Very High Frequency Resonant Boost DC-DC Converter
by
Justin Burkhart
Submitted to the Department of Electrical Engineering and Computer Science
on May 21, 2010, in partial fulfillment of the
requirements for the degree of
Master of Science
Abstract
T
resonant boost
of a very high frequency DC-DC
development
the
explores
thesis The topology examined features low parts count and fast transient response
HIS
converter.
but suffers from higher device stresses compared to other topologies that use a larger number
of passive components.
A new design methodology for the proposed converter topology is developed. This design
procedure - unlike previous design methodologies for similar topologies - is based on direct
analysis of the topology and does not rely on lengthy time-domain simulation sweeps across
circuit parameters to identify good designs.
Additionally, a method to design semiconductor devices that are suitable for use in the proposed VHF power converter is presented. When the main semiconductor switch is fabricated
in a integrated power process where the designer has control over the device layout, large
performance gains can be achieved by considering parasitics and loss mechanisms that are
important to operation at VHF when designing the device. A method to find the optimal
device for a particular converter design is presented.
The new design methodology is combined with the device optimization technique to enable
the designer to rapidly find the optimal combination of converter and device design for a
given specification.
To validate the proposed converter topology, design methodology, and device optimization,
a 75 MHz prototype converter is designed and experimentally demonstrated. The performance of the prototype closely matches that predicted by the design procedure, and achieves
good efficiency over a wide input voltage range.
Thesis Supervisor: David Perreault
Title: Associate Professor of Electrical Engineering
Acknowledgements
I would like to thank my advisor Professor Dave Perreault for sharing his extensive knowledge with me over the past two years. I am thankful for the guidance and support that he
has given me throughout this project. I have learned far more than I expected to when I
first began here, and that is largely due to him.
To all of my friends in Dave's group, its been a pleasure spending the past two year here
with all of you. Its hard to believe how fast the time has gone by.
Tony Sagneri has been a continuous source of help to me throughout this whole project.
His willingness to drop what he was doing to help me whenever I was stuck on a problem
has been of tremendous value to me.
My thanks goes to Irwin and Joan Jacobs for their generosity in supporting my education,
and to Texas Instruments for supporting my research. Specifically I'd like to thank Roman
Korsunsky for all of his support through out the course of this project, and especially for
the help getting my chip fabricated.
I'd like to express my thanks and gratitude to my Parents. You've been a constant source
of encouragement throughout my whole life, and I'm sure that I wouldn't be here today
without your love and support.
Most importantly, I'd like to thank my wife Jennifer for always being there for me. Your
support throughout our time here means a lot to me. I couldn't of made through without
you by my side. I love you.
-5
Contents
1
1.1
2
2.2
2.3
4
Thesis Contribution and Organization
. . . . . . . . . . . . . . . . . . . . .
20
23
VHF Converter Architecture
2.1
3
17
Introduction
The Class-E Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
2.1.1
Design Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
2.1.2
Drawbacks of the Class-E Inverter
. . . . . . . . . . . . . . . . . . .
28
Class-E DC/DC converter . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
2.2.1
Problems with Hard-Switched Rectifiers . . . . . . . . . . . . . . . .
31
2.2.2
Resonant Rectifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
2.2.3
DC-DC Converter Topology . . . . . . . . . . . . . . . . . . . . . . .
35
2.2.4
Converter Control
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
36
2.2.5
Resonant Input Inductor . . . . . . . . . . . . . . . . . . . . . . . . .
38
2.2.6
Mitigation of Frequency Dependent Loss Mechanisms
. . . . . . . .
39
Relation to Other Converters . . . . . . . . . . . . . . . . . . . . . . . . . .
40
Design Methodology
43
3.1
Inverter Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
45
3.2
Rectifier Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55
65
Semiconductor Devices
4.1
Device Model and Loss Mechanisms
. . . . . . . . . . . . . . . . . . . . . .
65
4.2
Device Layout Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . .
67
4.2.1
Layout of a LDMOS Transistor . . . . . . . . . . . . . . . . . . . . .
68
4.2.2
Scaling of Device Parasitics....... . . .
69
-7-
. . . . . . . . . . ...
Contents
5
5.2
5.3
A
Semiconductor Optimization
. . . . . . . . . . . . . . . . . . . . .
4.2.4
Design of an Interconnect Network . . . . . . . . . . . . . . . . . .
Converter Design
5.1
6
4.2.3
Device Modeling
. . . . . . . . . . .
5.1.1
MOSFET Model . . . . . . .
5.1.2
Parasitic Capacitances . . . .
5.1.3
On Resistance
5.1.4
Compensation for Non-Linear Device Capacitance
Design Example
. . . . . . . .
. . . . . . . . . . .
5.2.1
Select ws . . . . . . . . . . . .
5.2.2
Select #1
5.2.3
Select w . . . . . . . . . . ..
5.2.4
Simulation Results . . . . . .
. . . . . . . . . . .
Experimental Results.
. . . . . . . .
Conclusion
101
103
SPICE Code
A .1 Chapter 2 . . . . . . . . . . . . . . . . . . . .
103
A.1.1
SPICE Code to Generate Figure 2.2
103
A.1.2
SPICE Code to Generate Figure 2.7
104
A.1.3
SPICE Code to Generate Figure 2.8
105
A.1.4 SPICE Code to Generate Figure 2.11
106
A.1.5
SPICE Code to Generate Figure 2.14
107
A.1.6
SPICE Code to Generate Figure 2.17
108
A.1.7
SPICE Code to Generate Figure 2.21
109
A .2 Chapter 5 . . . . . . . . . . . . . . . . . . . .
110
A.2.1
SPICE Code to Generate Figure 5.19
110
A.2.2
SPICE Code to Generate Figure 5.20
111
-8-
Contents
B
121
Design Methodology MATLAB Scripts
...............
B.1 MATLAB Code to Generate Figures 3.4 and 3.7 ....
C
D
E
131
Device Layout Optimization MATLAB Scripts
C.1
121
MATLAB Code to Generate Figures 4.3 - 4.6 .....................
131
C.2 MATLAB Code to Generate Figures 4.11 and 4.12 ..................
137
C.3 MATLAB Code to Generate Figure 4.15 ....................
141
Design Example MATLAB Scripts
145
D.1
MATLAB Script to generate Figure 5.10 ......
...................
145
D.2
MATLAB Script to generate Figures 5.11, 5.12, and 5.13 ..........
149
D.3
MATLAB Script to generate Figures 5.15, 5.16, and 5.17 ..........
153
Experimental Prototype Design
159
Bibliography
163
-9-
List of Figures
1.1
Schematic of a linear regulator circuit. . . . . . . . . . . . . . . . . . . . . .
17
1.2
Schematic of a buck converter . . . . . . . . . . . . . . . . . . . . . . . . . .
18
1.3
Buck converter waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
1.4
Notional switch waveforms during commutation . . . . . . . . . . . . . . . .
20
2.1
Schematic of the Class-E Inverter . . . . . . . . . . . . . . . . . . . . . . . .
24
2.2
Simulated waveforms from a SPICE simulation of an ideal class-e Inverter
operating with a switching frequency of 100 MHz and an input voltage of 12
Volts. Component values are: LF = 10uH, CE = 67.7pF, CR = 105pF, LR
= 34.1nH, and RLOAD=5 Ohms. Simulation script is included in Appendix A. 25
2.3
Diagram showing the switching times of the class-e inverter . . . . . . . . .
25
2.4
Schematic of a class-e inverter with ideal components used for analysis.
. .
26
2.5
Plot showing the relation between the quality factor and resonant frequency
of the load leg of a class-e inverter . . . . . . . . . . . . . . . . . . . . . . .
28
Class-e inverter component values plotted versus the resonant frequency of
the load leg of the inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29
Simulated class-e inverter waveforms using component values resulting from
the design procedure. The inverter is designed for a switching frequency of
100 MHz and an input voltage of 5 Volts. Simulation script is included in
A ppendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29
Simulated waveforms of a class-e inverter showing how VD(t) varies with
an increased load resistance. Component values are: LF = 10uH, CE =
67.7pF, CR = 105pF, LR = 34.1nH, and RLOAD is varied from 5 to 10 Ohms.
Simulation script is included in Appendix A. . . . . . . . . . . . . . . . . .
30
Block diagram of a resonant DC/DC converter
. . . . . . . . . . . . . . . .
31
. . . . . . . . . . . . .
32
2.11 Simulated waveforms of the hard-switched rectifier circuits of Figure 2.10
showing the effect that including parasitics has on operation at VHF. Simulation performed with VAC = 10 Volts, IDC = 1 Amp, LPAR = 3 nH, and
CPAR = 30 pF. Simulation script is included in Appendix A. . . . . . . . .
32
2.6
2.7
2.8
2.9
2.10 Hard-switched rectifier circuits.. . . . . . . . . .
-
10 -
List of Figures
2.12 Schematic of a series loaded resonant rectifier circuit. Note that the AC
voltage source must pass the dc load current. . . . . . . . . . . . . . . . . .
33
2.13 Schematic of a series loaded resonant rectifier circuit with extra capacitance
for converter tuning and dominant parasitic components included . . . . . .
34
2.14 Simulated waveforms from the resonant rectifier of Figure 2.13 both with and
without parasitics included. Simulation script is included in Appendix A. .
34
2.15 Schematic of a resonant boost DC/DC converter made by joining together a
class-e inverter and a series loaded resonant rectifier. . . . . . . . . . . . . .
35
2.16 Simulated waveforms from the boost converter of Figure 2.15 operating at
100 MHz with an input voltage of 12 Volts and an output voltage of 30 Volts. 36
2.17 Simulated converter waveforms showing the effect of decreasing the load resistance by a factor of two. Simulation script is included in Appendix A. . .
37
2.18 Block diagram of the boost converter control system . . . . . . . . . . . . .
37
2.19 Simulated waveforms of the start-up transient from two converter designs,
both designed to operate with an input voltage of 12 Volts, an output voltage
of 30 Volts, and a switching frequency of 100 MHz. One design uses LF=3
pH and is labeled "Choke Inductor", and the other design uses LF=40 nH
and is labeled "Resonant Inductor" . . . . . . . . . . . . . . . . . . . . . . .
38
2.20 Schematic of the converter circuit used to gain a qualitative understanding
of the effects of reducing the size of LF . . - . . . - - .
- - - - - - . .. .
39
2.21 Simulated converter waveforms showing the error in equation (2.20) for a 100
MHz converter with an input voltage of 12 Volts, an output Voltage of 30
Volts, and LF=40 pH. Simulation script is included in Appendix A . . . . .
40
3.1
Schematic of the proposed DC-DC converter topology showing parasitic capacitances that limit the available design space. . . . . . . . . . . . . . . . .
43
Schematic of the inverter used for analysis. The rectifier is modeled as a
sinusoidal current source labeled IRECT . - . . . .
- -.
. . . . . . . . . . .
45
3.3
Sample illustrative waveforms for the inverter circuit of Figure 3.2. . . . . .
45
3.4
Closed form solution to the inverter. Solution assumes an input and output
voltage of 12 and 30 Volts and an output power of 7 Watts. #1 is the rectifier's
current phase, as specified in (3.1). . . . . . . . . . . . . . . . . . . . . . . .
54
Schematic of the rectifier used for analysis. The inverter is modeled as a
sinusoidal voltage source labeled VAC . . . . .
- - - - - - - -.
-. .
. .
55
Sample illustrative waveforms for the rectifier circuit of Figure 3.5. . . . . .
55
3.2
3.5
3.6
-
11 -
List of Figures
3.7
Numerical solution to the rectifier. Solution assumes an input and output
voltage of 12 and 30 Volts and an output power of 7 Watts. #1 is phase of
the fundumental component of IR (t). . . . . . . .
. - -.
. - - - - .
.
63
4.1
MOSFET model that is preferred for VHF converter design. . . . . . . . . .
66
4.2
Drawings showing the top view and cross section layout of a LDMOS transistor cell. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
68
Plots showing how the major intrinsic parasitic components of the LDMOS
transistor vary with device and finger size. . . . . . . . . . . . . . . . . . . .
71
4.3
4.4
Plot of the gate time-constant for intrinsic parasitics vs device and finger size. 71
4.5
Predicted converter loss vs device and finger size for a converter that boosts
12 Volts to 30 Volts with a switching frequency of 75 MHz, an output power
of 15 Watts, an inverter resonant frequency of 63.75 MHz, and the rectifier's
current phase set to -1 radian . . . . . . . . . . . . . . . . . . . . . . . . . .
72
Predicted converter loss vs device and finger size for a converter that boosts
12 Volts to 30 Volts with a switching frequency of 75 MHz, an output power
of 7 Watts, an inverter resonant frequency of 63.75 MHz, and the rectifier's
current phase set to -1 radian .. . . . . . . . . . . . . . . . .I . . . . . . . . .
72
Schematic of the proposed DC-DC converter topology showing parasitic capacitances that limit the available design space. . . . . . . . . . . . . . . . .
73
Drawings of a LDMOS transistor broken down into 16 fingers and arranged
into various different aspect ratios. . . . . . . . . . . . . . . . . . . . . . . .
74
Drawing showing the scheme used to connect the LDMOS finger gates. . . .
75
4.10 Schematic of the LDMOS gate model for a single finger. . . . . . . . . . . .
76
4.11 Plots showing the gate resistance and capacitance vs. the width of the metal
used to connect the gates. ........
............................
76
4.12 Plots calculating the loss of a 75 MHz resonant gate driver and gate timeconstant using the parasitic values from Figure 4.11. . . . . . . . . . . . . .
77
4.13 Drawing showing the scheme used to connect the LDMOS drain and source
term inals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
78
4.14 Schematic of the LDMOS drain-to-source interconnection model for a single
row of fingers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
78
4.15 Predicted drain-to-source resistance vs. taper angle for two, three, and four
rows of fingers. The device has 100 fingers each with a width of 450 pm. . .
79
4.16 Photograph of the designed LDMOS transistor layout. . . . . . . . . . . . .
80
MOSFET model that is preferred for VHF converter design. . . . . . . . . .
82
4.6
4.7
4.8
4.9
5.1
-
12 -
List of Figures
5.2
Schematic of the test setup used to measure the device parasitic capacitances. 82
5.3
Photograph of the PCB used to measure the device capacitances
. . . . . .
83
5.4
Measured Coss data. The model of equation (5.1) is also plotted to show
the good fit. Model parameters are: Cj 0 =121 pF, V3 = 1.2701 Volts, and M
= 0.4123. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
84
5.5
M easured CIss data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
84
5.6
Measured reverse biased junction capacitance of S310 Schottky diode manufactured by Fairchild. The model of equation (5.1) is also plotted to show
the good fit. Model parameters are: Cj,=267 pF, V3 = 0.365 Volts, and M
= 0.421. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
85
.
86
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
86
Plots showing equation (5.6) graphically with the fitting parameters for the
LDMOS capacitance Coss and for the diode's junction capacitance. ....
88
5.10 Output from the combined design methodology and device optimization procedure for a converter with an input voltage of 12 Volts, an output voltage
of 30 Volts, and an output power of 7 Watts. The MATLAB script used to
generate this figure is included in Appendix D.1 . . . . . . . . . . . . . . . .
89
5.11 Plots generated from the design methodology to show the inverter's passive
component sizes as a function of the rectifier's current phase, 41 and the
resonant frequency of the inverter. Solution is for a converter with an input
voltage of 12 Volts, an output voltage of 30 Volts, an output power of 7
Watts, and a switching frequency of 75 MHz. . . . . . . . . . . . . . . . . .
90
5.12 Plots generated from the design methodology to show the rectifier's passive
component sizes as a function of the rectifier's current phase, 41 and the
resonant frequency of the inverter. Solution is for a converter with an input
voltage of 12 Volts, an output voltage of 30 Volts, an output power of 7
Watts, and a switching frequency of 75 MHz. Due to the diode's parasitic
junction capacitance, the design space is limited as shown by the grey area.
90
5.13 Plots generated from the combined design methodology and device optimization to show the converter's predicted efficiency and the optimal device size
(for each design point). Solution is for a converter with an input voltage of
12 Volts, an output voltage of 30 Volts, an output power of 7 Watts, and a
switching frequency of 75 MHz. . . . . . . . . . . . . . . . . . . . . . . . . .
91
5.14 Plot showing the slope of VC(t) as a function of the rectifier's current phase,
#1and the resonant frequency of the inverter for a converter with an input
voltage of 12 Volts, an output voltage of 30 Volts, an output power of 7
Watts, and a switching frequency of 75 MHz. . . . . . . . . . . . . . . . . .
91
5.7
Schematic of the setup used to measure RDS-ON.
5.8
M easured RDS-ON data.
5.9
-
13 -
. . . . . .
. ...
-.
List of Figures
5.15 Plots generated from the design methodology to show the inverter's passive
component sizes as a function of the resonant frequency of the inverter. Solution is for a converter with an input voltage of 12 Volts, an output voltage
of 30 Volts, an output power of 7 Watts, a switching frequency of 75 MHz,
and the rectifier's current phase of #1=-1 radian. . . . . . . . . . . . . . . .
93
5.16 Plots generated from the design methodology to show the rectifier's passive
component sizes as a function of the resonant frequency of the inverter. Solution is for a converter with an input voltage of 12 Volts, an output voltage
of 30 Volts, an output power of 7 Watts, a switching frequency of 75 MHz,
and the rectifier's current phase of #1=-1 radian. . . . . . . . . . . . . . . .
93
5.17 Plots generated from the combined design methodology and device optimization to show the converter's predicted efficiency and the optimal device size
(for each design point). Solution is for a converter with an input voltage of 12
Volts, an output voltage of 30 Volts, an output power of 7 Watts, a switching
frequency of 75 MHz, and the rectifier's current phase of
#1=-1
radian. . . .
94
5.18 Plot showing the peak energy stored in the inverter in a cycle normalized
to the energy delivered to the load in a cycle as a function of the resonant
frequency of the inverter for a converter with an input voltage of 12 Volts,
an output voltage of 30 Volts, an output power of 7 Watts, and a switching
frequency of 75 MHz, and the rectifier's current phase of
#1=-1
radian. . . .
95
5.19 Simulation results for a converter with an input voltage of 12 Volts, an output
voltage of 30 Volts, an output power of 7 Watts, and a switching frequency
of 75 MHz, the rectifier's current phase of #1=-1 radian, and the inverter's
resonant frequency set to 85% of the switching frequency. The figure shows
the simulation result with the component values predicted by the design
methodology and with corrected component values (shown in Table 5.4) . .
97
5.20 Simulation results of a converter with an input voltage of 12 Volts, an output
voltage of 30 Volts, an output power of 7 Watts, and a switching frequency of
75 MHz and a duty ratio of 50%, the rectifier's current phase of #1=-1 radian,
and the inverter's resonant frequency set to 85% of the switching frequency.
Simulation uses more exact models for each of the circuit components in
preparation for building a prototype. Appendex A.2.2 contains SPICE code
detailing this simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
98
5.21 Schematic of the experimental implementation. The inductors are from the
midi-spring family from Coilcraft, and the diode is an S310 Schottky diode
from Comchip Technology. The MOSFET is a custom LDMOS device fabricated from an integrated power process. The converter operates at 75 MHz
with a 50% duty cycle. The device characteristics of S1 are shown in Figures
5.4, 5.5, and 5.8............
. .. . .. . . .. . .. . .. .
. . .
. .
98
5.22 Photograph of the converter PCB. . . . . . . . . . . . . . . . . . . . . . . .
99
List of Figures
5.23 Measured converter waveforms compared to simulated waveforms in SPICE.
99
5.24 Measured converter waveforms over the input voltage range. . . . . . . . . .
100
5.25 Measured efficiency (not including gate drive loss) versus input voltage for
two specified output power levels. Output power is controlled by on-off modulating the converter with a PWM signal at 1 MHz. . . . . . . . . . . . . .
100
E.1
Experimental schematic of the power stage. . . . . . . . . . . . . . . . . . .
159
E.2 Experimental schematic of the gate drive circuit. . . . . . . . . . . . . . . .
159
E.3 PCB top metal layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
160
E.4 PCB first inner metal layout.
. . . . . . . . . . . . . . . . . . . . . . . . . .
161
E.5 PCB second inner metal layout. . . . . . . . . . . . . . . . . . . . . . . . . .
161
E.6 PCB bottom metal layout . . . . . . . . . . . . . . . . . . . . . . . . . . . .
162
E.7 PCB holes and vias layout.
162
. . . . . . . . . . . . . . . . . . . . . . . . . . .
-
15
-
List of Tables
1.1
Summary of buck converter loss mechanisms . . . . . . . . . . . . . . . . . .
20
4.1
Overall size of a LDMOS transistor composed of 100 fingers each with a
width of 450 pm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
74
5.1
Target converter specifications..... . .
. . . . . . . . . . . . . . . . . .
81
5.2
Parameters to fit equation (5.1) to measured the junction capacitance data
for the S310 diode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
83
5.3
Parameters to fit equation (5.1) to measured the Coss data. . . . . . . . . .
85
5.4
Component values as predicted by the design methodology for a converter
with an input voltage of 12 Volts, an output voltage of 30 Volts, an output
power of 7 Watts, and a switching frequency of 75 MHz, the rectifier's current
phase of #1=-1 radian, and the inverter's resonant frequency set to 85% of
the switching frequency. The table also show component values that result
from correcting the error in the design methodology (due to the sinusoidal
current approximation) in SPICE. . . . . . . . . . . . . . . . . . . . . . . .
96
Converter Bill of Material . . . . . . . . . . . . . . . . . . . . . . . . . . . .
160
E.1
-
16 -
Chapter 1
Introduction
P
In battery operated
of nearly every electrical system.
a vital partsupply
OWER conversion
the constant voltage that electronics require as
powerisconverters
applications,
the battery voltage drops from discharge. Systems that need multiple DC supply voltages
require the use of a power converter to convert one DC voltage to another.
VIN
Control
VoUT
Figure 1.1: Schematic of a linear regulator circuit.
A linear regulator shown in Figure 1.1 is a simple way to convert one DC voltage to another,
but it has two major problems. First, the output voltage must always be less than the input.
Consider a system that is powered by a Lithium-Ion battery. Fully charged, the battery
supplies 4.3 Volts, but when discharged it only supplies 3 Volts. Many electronic systems
require a supply voltage of 3.3 Volts. Thus, if a linear regulator is used the system cannot
be operated throughout the entire discharge cycle. The second major drawback of using a
linear regulator is efficiency. Since the load current must pass through the regulation device,
the converter consumes a power equal to the load current times the change in voltage. This
leads to a best-case efficiency of:
VOUT
VIN
When the the conversion ratio is large this efficiency is not acceptable. Thus, there is a need
for conversion technology that can efficiently convert from one DC voltage to another, and
be able to convert up and down. Both of these needs are met by switching power converters.
Figure 1.2 shows the schematic of a buck converter. This converter achieves 100% efficiency
with ideal components.
-
17 -
MM
I
Introduction
Ideal
Switch
Lossless
Filter
+ VDS -
-
+1
+
I"
+
+
-rVIN
Vx
-_
VIN
:
~--------..
VouT
RLOAD
VxRLOAD
N +
--
VNIxVo~
Ideal Converter
Real Implimentation
Figure 1.2: Schematic of a buck converter
VVOUT
3.1.56
2.5
- -1.54
I0i
2.
.
-i
--
I
.1.52
.
r
4
.1.5
.
-
-'
I
--
-
-
5
10
15
20
Time (ps)
25
1.44
30
0
FC=0.1F
---
F =0.3F
Fc=0.5F
.
0
-
10
20
30
Time (ps)
Figure 1.3: Buck converter waveforms
The converter operates by controlling the switch to generate a square wave, shown at V, in
Figure 1.3. This square wave is filtered using a lossless LC filter to produce a DC output
equal to the average value of the square wave, and the output voltage is controlled by
varying the duty cycle of the square wave. The output voltage of the converter contains
some ripple components in addition to the desired DC voltage. The ripple is reduced by
lowering the cutoff frequency (FC in Figure 1.3) of the LC filter relative to the switching
frequency, increasing the size of the inductor and capacitor.
In many state-of-the-art systems, miniaturization is a dominant constraining factor that designers are being forced to address. Since these systems typically include a power conversion
circuit, the same miniaturization constraints are also applied to the power converter. The
size of a typical power converter is dominated by passive components. For a given ripple
requirement and circuit design, the main way to reduce the size of the passive components
is to increase the switching frequency of the converter [1].
-
18 -
As shown in Figure 1.2, in a practical circuit the ideal switch is implemented using a
transistor and a diode. Inclusion of these non-ideal components spurs a number of loss
mechanisms, lowering the converter efficiency. When the transistor is on, its channel has
finite resistance resulting in a conduction loss.
PCOND
ISRDS-ON
(1.2)
Similarly, the when the diode is on it has a finite forward voltage, resulting in loss.
PDIODE =
(IDIODE) VFWD
(1.3)
The transistors gate is capacitive, and each time the transistor is turned on and off the
capacitor is charged and discharged to ground, resulting in loss.
PGATE
CISSV2Fs
(1.4)
Additionally, each time the switch commutates there is a period of time in which the switch
has high voltage across it and high current through it resulting in switching loss. This is
illustrated in Figure 1.4 for the off-to-on switch transition. Prior to the switch turning on,
the diode is carrying all of the inductor current. When the switch is turned on, the inductor
current must fully transfer to the switch prior to the voltage across the switch falling. The
area of this overlap is the energy lost per switching transition.
1
(t2
2
PSW-OVERLAP
-
to)IDSVINFs
(1.5)
Since the switch has a parasitic capacitor between its drain and source terminals, there is
a capacitive discharge loss similar to the gating loss of the transistor, ideally:
PSW-CAP
COSSV2NFs
(1.6)
The final loss mechanism considered for the buck converter is loss the magnetic material
used by the inductor in the converter's output filter. This is traditionally estimated using
a "Steinmentz" loss model:
PMAG oc kfaB' C
where k, a, and
core [2, Ch. 20].
(1.7)
3 are a constants and BAC is the sinusoidal AC flux density in the inductor
-
19 -
Introduction
VIN
VDS
IDS
Time
VIN 1DS
to
ti
t2
Time
Figure 1.4: Notional switch waveforms during commutation
Mechanism
Conduction
Switching
Gating
Magnetic
Loss
IDSRDS-ON
(kIDSVIN + COSSVIN) Fs
C1ssV Fs
oc kf&Bfc
Frequency Dependance
Independant
oc F,
oc F,
oc F,
Table 1.1: Summary of buck converter loss mechanisms
Table 1.1 summarizes the loss mechanisms in the buck converter. From this table one can
see that all but one of the converter's loss mechanisms grow with switching frequency. While
it is desirable to increase the converter switching frequency to reduce the size of the passive
components, this cannot be done arbitrarily as efficiency will degrade.
1.1
Thesis Contribution and Organization
This thesis explores methods to achieve a drastic increase in switching frequency. Chapter
2 presents the background information on the strategy that is used to overcome switching
losses, and proposes a boost converter topology. While the proposed circuit is topologically
equivalent to previous converters, [3] and [4], different component selection choices and a
different control method differentiate this work.
Chapter 3 introduces a new design methodology for the proposed converter topology. This
design procedure - unlike previous design methodologies for similar topologies [3], [5] - is
-
20 -
1.1
Thesis Contribution and Organization
based on direct analysis of the topology and does not rely on lengthy time-domain simulation
sweeps across circuit parameters to identify desirable design points.
In Chapter 4, the design of semiconductor devices suitable for use in the proposed VHF
power converter is presented. When the main semiconductor switch is built from an integrated power process where the designer has control over the device layout, large performance gains can be achieved by considering parasitics and loss mechanisms that are
important at VHF when designing the device. A procedure to find the optimal device
design for a particular converter design is developed.
Combination of the design methodology of Chapter 3 and device optimization of Chapter
4 is completed in Chapter 5. This combined approach is used to design a converter that
represents the combination of optimal design and optimal device (rather than optimal device
for some design). Experimental results are presented to validate the approach.
The thesis is concluded in Chapter 6 providing an overview of the contributions of this work
and offering suggested future research areas.
-
21 -
Chapter 2
VHF Converter Architecture
C
of
that limit the switching frequency
dependent losses
frequency
the
ONSIDERING
conventional power converters, specialized techniques must be used to overcome these
losses in order to realize converters with Very High Frequency (VHF, 30-300 MHz) operation. In this chapter, the class-e inverter is presented as a circuit topology that was specially
designed to overcome each of the major frequency dependent losses. since we are after a
DC/DC converter and not an inverter, it is then shown how to transform and rectify the
output of the inverter to a DC voltage. While this converter circuit is able to achieve high
efficiency at VHF switching frequencies, it has a number of problems that limit its usefulness. Solutions to these problems are presented, resulting in a VHF converter architecture
suitable for practical use.
2.1
The Class-E Inverter
The class-e inverter, shown in Figure 2.1, was introduced in 1975 as a means to invert a
DC voltage to an RF AC signal with high efficiency [6]. In this circuit LF is assumed to
be a large choke inductor that delivers only DC current. In a conventional power converter
circuit, switching action generates a square wave resulting in switching losses from capacitive
discharge and overlap loss. The class-e inverter uses resonance to synthesize a specialized
switching waveform that circumvents these traditional switching losses [7]. When the switch
is opened, the circuit elements CE, LR, CR, and RLOAD resonate with each other. These
elements are tuned specifically such that the voltage across the switch will naturally ring up
and then back to zero at some known later time, giving an opportunity to turn the switch
on without switching loss. An example of this switching waveform is shown in Figure 2.2
from a SPICE simulation of a class-e inverter.
23
-
VHF Converter Architecture
LF
VD(t)
LR
CR
\fRM
RLOAD
Figure 2.1: Schematic of the Class-E Inverter
2.1.1
Design Procedure
A class-e inverter is designed by first assuming that LR, CR, and RLOAD form a resonant
network of sufficient quality factor Q such that the current through them is purely sinusoidal
at the switching frequency.
IR(t) = 'AC Sin(wst + 01)
(2.1)
The resonant frequency of LR and CR is set slightly below the switching frequency such
that the network looks inductive. With these assumptions in mind, the circuit schematic is
redrawn with LR and CR replaced by an inductor that represents their equivalent impedance
at the switching frequency and an ideal band-pass-filter to force the purely sinusoidal current, as shown in Figure 2.4. The duty cycle of the inverter switch is assumed to be 50%,
and in the time period with the switch off (shown in Figure 2.3 the voltage VD(t) is found
by integrating the current in CE.
VD(t) =
1 IDC ' t + 1AC lcos(wst + 01) - cos(0i)]
CE
WsCE
(2.2)
To avoid switching losses, VD(t) is set equal to zero at the switching turn on instant (wst
7r). Additionally, the slope of VD(t) is also set equal to zero at the switching instant both to
provide immunity to switching jitter and so that there is no current in CE resulting in the
least amount of ringing in the circuit. These are known as the so-called "Class-E" switching
conditions. Applying these constraints to (2.2) results with the following relationships:
2
7rIDC
AC coS(0
IDC= -AC
-
24 -
1)
sin(01)
(2.3)
(2.4)
The Class-E Inverter
2.1
VR
- -..
o
-20
2-4
8-0
2
0
4
6
10
Time (ns)
8
12
14
16
18
2
16
18
20
41
2 - -
40 2
-.. -.
..
4
6
10
Time (ns)
8
--.
2
1O
..
-.
....
14
16
....
18
20
Figure 2.2: Simulated waveforms from a SPICE simulation of an ideal class-e Inverter operating
with a switching frequency of 100 MHz and an input voltage of 12 Volts. Component values are:
LF = 10uH, CE = 67.7pF, CR = 105pF, LR = 34.1nH, and RLOAD=
5
Ohms. Simulation script is
included in Appendix A.
21s wtt
Fgr 23 Diara
Figure 2.3: Diagram showing the switching times of the class-e inverter
-
25 -
VHF Converter Architecture
Ideal
BPF
LF
VD(t)
LEQ
VRM
IRM
VINL
LOAD
CE
S
Figure 2.4: Schematic of a class-e inverter with ideal components used for analysis.
#1:
These two equations are used to solve for
41=tan-
-
(2.5)
For analysis the circuit is assumed to be lossless, and since average power is only delivered
from the source by DC current:
(2.6)
IDC = POUT
VIN
where POUT is the average power delivered to the load resistor. IAC is found by substituting
(2.6) into equation (2.4):
IAC -
(2.7)
POUT
VIN sin(0 1)
Periodic-steady-state demands that the average value of VD(t) must be equal to the input
voltage. Combining this result with equations (2.3) and (2.4) enables CE to be found:
CE =
POUT
V2N7T~s
(2.8)
The value of RLOAD is found by noting that it carries that same current as LEQ.
RLOAD
-
2V2N
sin2(01)
(2.9)
IN
POUT
The fundamental component of VD(t) is found from the Fourier integral:
VD (t)UND= 1.64VIN sin(wst +
-
26 -
4)
(2.10)
2.1
The Class-E Inverter
where
#
tan-
2
-
(2.11)
)
7r
Because of the ideal band-pass-filter, the current IR(t) in LEQ is driven only by the fundamental component of VD(t). The phase-shift between IR(t) and the fundamental component
of VD (t) is found from the equivalent series impedance of LEQ and RLOAD. LEQiS found by
constraining this phase-shift to value constrained by the inverter design.
LEg = tan(# -
(2.12)
#1)RLOAD
The only remaining task is to determine the values of LR and CR from LEQ. This is done by
setting the series impedance of LR and CR equal to the impedance of LEQ at the switching
frequency.
jwsLEQ
=
=
where
(wsLR
jZR (WS/Wr)
1
Or =
O(.R)
-
LRCR
and
LR
R2
ZR
(.4
Since there are two free variables and only one constraint, Or is kept as a free variable. The
inverter design could utilize this free variable to constrain another aspect of the design if
desired (such as a specific load resistance, etc.). The choice of Or has implication on the
accuracy of the design procedure as well. For the sinusoidal current approximation to be
valid, LR, CR, and RLOAD must form a high Q network. The quality factor of a series RLC
circuit is:
ZR
RLOAD
tan(# -
(2.15)
(LOr/Os)
#1)
2
-
1
(.5
(rLws)
Figure 2.5 presents this relation graphically. Increasing the resonant frequency of the network relative to the switching frequency has the effect of increasing the quality factor, but
there are negative implications of choosing Or to close to ws. Figure 2.6 plots the value of
LR and CR versus Or for a 100 MHz inverter with an input voltage of 5 Volts and an output
power of 1 Watt. From this figure it is seen that the components approach extreme values
-
27 -
VHF Converter Architecture
as wr approaches ws. Additionally, the tolerance of the component values becomes very sensitive as the slope of the impedance is very steep versus frequency when operating close to
resonance. Figure 2.7 shows simulated waveforms using predicted component values from
the design solution for the inverter specification previously mentioned and Wr = 0.9 - Ws.
The inaccuracy of the design solution can be observed in the waveforms as VD(t) does not
achieve perfect zero-voltage-switching. Additionally, both simulated and calculated values
of IR(t) are plotted together so the differences can be observed. While not perfect, the
design procedure does result with a solution that is quite near to the actual solution. The
designer can easily account for this error when simulating the inverter in SPICE.
13
10.
S10'
:::..:
Figure 2.5: Plot showing the relation between the quality factor and resonant frequency of the
load leg of a class-e inverter
2.1L2
Drawbacks of the Class-E Inverter
While the class-e inverter successfully mitigates switching losses, it has numerous qualities
that reduce its usefulness in a practical DC/DC converter circuit. First and foremost the
inverter is unable to operate over a wide load range. The quality factor of the output RLC
leg of the inverter is set by the load resistance. Thus, the phase shift of load leg is also set
by the load resistance since:
Since this phase shift is constrained by the inverter design, the circuit can only be tuned
properly for a single load resistance. This phenomena is shown in Figure 2.8 where the load
resistance is varied by only a factor of two. Clearly this is an unacceptable condition for a
DC/DC converter.
-
28 -
2.1
The Class-E Inverter
..
...........
.....I..
...
.........: ......
...............
........
..............
..........
...
......... ............
............
.......
...........
......... ......
................. ............
..
. . . . . . . .... . . . . . .
. . . . . .. . . . . . .
.......... ..... . ......
............ .....
..... .
......... . ......
............... .....
...... .. .
. . . . . . . . . .:. . . . . . . . . . . . . . . . . . . . . . ...
...... .
.
.
.
.
.
...
.
.
.
.
.
.
.
....
. . . . . . . . . .... . . . .
. . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.....................
...............
.....................
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .... . . . . . . . . . . . . . . . . .
. . .. . . . . . . . . . . . . . . . . . . . . . .
.......... .........
......
. . . . . . . . . . .. . . . . . . . . . . . . . . .. .. .... . . . . . . . .
..
..
.
. ...
....
..
... ..
..
... . . . . . . .. .
......
................
. . . . . . .... . .
......
:- ............
......
.
*.. ........
..
..
..
........
..
. .*....
....
..
..
...
..
.
..
...........
..
..
..
..
...
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
...
..
..
..
..
..
..
..
..
..
.....
..........
1011
0.5
0.6
0.7
0.8
..........
0.9
0.8
0.7
1
W SWR
S
R
Figure 2.6: Class-e inverter component values plotted versus the resonant frequency of the load
leg of the inverter
V D(t)
0
10
Time (ns)
I (t)
0.
E
C
U
10
Time (ns)
Figure 2.7: Simulated class-e inverter waveforms using component values resulting from the design
procedure. The inverter is designed for a switching frequency of 100 MHz and an input voltage of 5
Volts. Simulation script is included in Appendix A.
-
29 -
VHF Converter Architecture
40
5-
Designed Load
---
Decreased Load
~30Increased Load
Resistance
-
20
.
0
0
-.
.
. -..
.
.
..
.
5
..-.
10
.
15
20
Time (ns)
Figure 2.8: Simulated waveforms of a class-e inverter showing how VD(t) varies with an increased
load resistance. Component values are: Lp = 10uH, CE = 67.7pF, CR = 105pF, LR = 34.1nH, and
RLOAD is varied from 5 to 10 Ohms. Simulation script is included in Appendix A.
Furthermore, in a practical design the capacitor CE is partially made up by a parasitic
capacitor from the switching device Si. Equation (2.8) can be rearranged to show the
following:
POUT= CEIN7ws
(2.17)
This shows that the output power is directly proportional to the capacitance of CE. Since
this capacitor is partially a parasitic whose value is fixed for a given device, there is a
minimum power that the inverter can be designed for.
Finally, the inverter circuit requires a large choke inductor. In the quest for a highly integrated DC-DC converter, the requirement for a large inductor is an unattractive prospect,
especially if fast dynamic response is sought.
2.2
Class-E DC/DC converter
The class-e inverter is made into a DC/DC converter by replacing the load resistor with a
rectifier circuit, as shown in the block diagram of Figure 2.9. Since voltage transformation
-30
-
2.2
Class-E DC/DC converter
is done at AC, large conversion ratios can be obtained without extreme duty cycles through
the use of a passive transformation network between the inverter and the rectifier [8].
VIN
-RLOAD
Figure 2.9: Block diagram of a resonant DC/DC converter
2.2.1
Problems with Hard-Switched Rectifiers
Common hard-switched rectifiers generate a square wave and are not suitable for use in VHF
applications. With the very high switching frequency, the harmonics that are generated from
the switching waveform easily excite resonances among the parasitics in the circuit leading
to oscillations and additional loss. Figure 2.10(a) shows an ideal hard-switched half-wave
rectifier circuit driven by a sinusoidal voltage source and loaded by a DC current. When
the input sinusoid is positive, D1 is on and carries IDC, and in the second half of the period
when the input sinusoid is negative D 2 is on and carries IDC - When the input voltage crosses
zero, the current must commutate from one diode to the other, resulting in a current square
wave. This is troublesome when parasitics are included in the analysis. The dominant
parasitics are the junction capacitance of diodes and the series package inductance, shown
in Figure 2.10(b). Figure 2.11 shows simulated waveforms of an ideal half-wave rectifier and
of a rectifier with parasitics included operating at 100 MHz. With a junction capacitance
of 30 pF and a series inductance of 3 nH, the ringing harmonic currents become dominant.
This leads to substantial loss since the rectifiers operation is disrupted and the additional
harmonic currents do not contribute to delivering power to the load. Additionally, finite
commutation time of the diodes brings about the same switching losses that the inverter
circuit was specifically designed to avoid.
2.2.2
Resonant Rectifiers
The primary problem facing a hard-switched rectifier for operation at VHF speeds is the
parasitic resonant that occurs between the diode's junction capacitance and the parasitic
package inductance. In a resonant rectifier, this resonance is used as an advantage rather
than a hinderance. The series loaded resonant rectifier of [9], shown in Figure 2.12, is
-
31 -
.
..............
.............................
VHF Converter Architecture
CPAR
'DC
VAC
(a) Schematic of an ideal hard-switched (b) Schematic of a hard-switched half-wave
rectifier including dominant parasitic comhalf-wave rectifier.
ponents.
Figure 2.10: Hard-switched rectifier circuits
VD(t)
0
Time (ns)
IDI(t)
0.
Time (ns)
ID2(t)
0
5
10
20
Time (ns)
15
25
30
35
40
Figure 2.11: Simulated waveforms of the hard-switched rectifier circuits of Figure 2.10 showing
the effect that including parasitics has on operation at VHF. Simulation performed with VAC = 10
Volts, IDC = 1 Amp, LPAR = 3 nH, and CPAR = 30 pF. Simulation script is included in Appendix
A.
-
32
-
2.2
Class-E DC/DC converter
designed specifically to do this by adding an inductor in series with the diode to control
the frequency at which the resonance occurs. To gain a qualitative understanding of how
this rectifier operates, it is assumed that the current IR(t) is sinusoidal, and CFILT is large
enough such that VOUT is a DC voltage relative to a switching cycle. When the diode
turns on, the voltage VD(t) is held at VOUT, and all of the current IR(t) passes through
the diode. The diode turns off when IR(t) crosses zero. At this point IR(t) switches to
being carried through the diode's parasitic capacitor CPAR . This transition of current
from the diode to the capacitor happens without ringing since the current was at zero
during the transition. The current IR(t) then charges and discharges CR until the voltage
VD(t) reaches VOUT again, turning the diode on and causing the cycle to repeat. At
this point, the current in CPAR must transition to the diode, but since this capacitance is
physically the same piece of silicon as the diode, this transition occurs without ringing as
there is essentially no inductance between them.
---
LR
PAR
LPAR
------------.
D,
VAC
CFILT
Figure 2.12:
Schematic of a series loaded resonant rectifier circuit. Note that the AC voltage
source must pass the dc load current.
When using this rectifier circuit with a resonant inverter to build a DC-DC converter, the
diode's junction capacitance might not be the needed impedance for proper inverter tuning.
An external capacitor can be added in parallel with the diode to fix this problem, shown in
Figure 2.13. In doing so, however, the parasitic inductance between this external capacitor
and the diode introduces some ringing into the resonant rectifier circuit when the diode
turns on. While this is exactly the behavior that the circuit sought to avoid, the outcome
in many cases is tolerable as diode's junction capacitance is still being absorbed by the
topology. Simulated waveforms comparing of an ideal resonant rectifier, and a rectifier
containing the same parasitics of the previously described hard-switched rectifier are shown
in Figure 2.14. Resonant boost converter using this rectifier topology have been successfully
demonstrated with switching frequencies up to 110 MHz in [10], [11], [12], and [13].
-
33
-
. .............................
...........
. . ..........................................
VHF Converter Architecture
VAC
Figure 2.13: Schematic of a series loaded resonant rectifier circuit with extra capacitance for
converter tuning and dominant parasitic components included
VD(t)
Time (ns)
ID(t)
-0.1
-
0
5
10
15
20
Time (ns)
25
30
35
40
Figure 2.14: Simulated waveforms from the resonant rectifier of Figure 2.13 both with and without
parasitics included. Simulation script is included in Appendix A.
-
34 -
2.2
2.2.3
Class-E DC/DC converter
DC-DC Converter Topology
Figure 2.15 shows the a schematic of a resonant boost DC-DC converter that is formed by
joining together a class-e inverter and a series loaded resonant rectifier. Figure 2.16 presents
waveforms from a SPICE simulation of this converter with ideal components. Aside from
the output filter capacitor, the dc-dc converter only requires adding a single diode to the
class-e inverter circuit, as the output tank of the inverter and the input tank of the rectifier
are shared. Also, LR and CR are rearranged relative to the class-e inverter circuit to provide
a DC link from input to output. The constrains the converter topology to boost applications
only due to the diode's polarity. Note that in this topology there is some direct transfer of
energy at DC from the input to the output (unlike the case where all energy flow is mediated
through AC waveforms). From simple conservation of energy arguments, it is shown that
the ratio of AC to DC power transfer is set by the conversion ratio:
PAC
LF
(2.18)
VIN
VD(t)
LR
D,
VRt
VOUT
IR~
IF(t)
VIN
1
_VouT
PDC
S,
CR
E
CFILT
LOAD
Figure 2.15: Schematic of a resonant boost DC/DC converter made by joining together a class-e
inverter and a series loaded resonant rectifier.
Designing this general type of converter has traditionally be accomplished by repeatedly
performing time-domain simulations in SPICE sweeping the available parameters in the
circuit until the desired waveforms are achieved [3] and [5]. Since there are closed-form
equations describing the class-e inverter alone, typically design starts with an inverter circuit. The inverter design requires a specific current IR(t), and the rectifier has to be designed
to provide this current when driven by the inverter. The non-linear nature of the rectifier
has traditionally made it difficult to derive a set of closed-form design equations, and its
design is usually accomplished in SPICE. By sweeping over values of Wr and ZR it is readily
observed that Wr roughly controls the phase of IR(t), and ZR controls the amplitude. Thus,
the designer has two control knobs to dial the current to the desired amplitude and phase.
In Chapter 3 a new design methodology for this converter circuit is presented that is based
-
35
VHF Converter Architecture
CU
5
0
10
15
20
Time (ns)
---- .........
..... --.-...-....
-.
--.
4 0 ..-
..
- - V (tW
- -- - -
>
-
-VR(t
%
0
5
10
Time (ns)
15
20
Figure 2.16: Simulated waveforms from the boost converter of Figure 2.15 operating at 100 MHz
with an input voltage of 12 Volts and an output voltage of 30 Volts.
on direct analysis of the topology and does not require SPICE simulation sweeps across
parameters to determine good designs.
2.2.4
Converter Control
Since this boost converter topology is based on a class-e inverter circuit, it inherits all the
associated problems that were previously presented.. Most notably, the converter operation
is dependant on the value of the resistor loading the converter. As with the class-e inverter,
the converter is only tuned properly and operates with zero-voltage-switching for a specific
load resistance. Additionally, as load resistor set the Q of the transformation network,
output voltage is dependent on its value. Figure 2.17 shows this undesirable phenomena by
presenting converter waveforms with the ideal load resistance and also with the resistance
varied by up to a factor of two.
A control scheme has been designed that allows the converter to operate over a wide load
range without losing proper tuning [14], [15], and [16]. This is accomplished by modulating
-
36 -
2.2
Class-E DC/DC converter
V D(t)
CA_
-.
.......
. ... ... .. ..
2
4
10
Time (ns)
V R(t)
8
6
20
18
16
14
12
Designed Load
-Decreased Load
Resistance
An
..........
. ....
.....
............
. .. . .. .
. . .. .. .
. . .. .. ..
%
.............. ...............
. .. .. ..
%
. ...
10
Time (ns)
8
6
. .. .. . .. .. ...
I . .........
.... .....
%
%
4
. .. .. . ..
%
............
2
.. .. .
.......
12
..... .
... ................
14
..........
18
16
20
Figure 2.17: Simulated converter waveforms showing the effect of decreasing the load resistance
by a factor of two. Simulation script is included in Appendix A.
the converter on and off at a frequency far below the switching frequency to regulate the
average output power. While the converter is on, so long as the output voltage is close to
the designed value, the converter operates with the designed maximum power value and is
tuned correctly. A capacitor is added in parallel with the load to filter modulation harmonic
content, and a feedback controller closes the loop. Figure 2.18 shows a block diagram of
this system. This control scheme has been successfully demonstrated in [14], [15], [16], [5],
[3], [10], [12], [11], and [13].
]Enab
Controller
Enab
GateVHF
Dr ver
erg
Converter
vREF +
CFILT
RLOAD
Feedback
Figure 2.18: Block diagram of the boost converter control system
This scheme successfully enables the converter to efficiently operate over a wide load range.
The speed at which the convertei can be modulated sets the size of the output filtering
components. The ability to modulate on and off quickly is in part limited by the inclusion
of a large choke inductor in the inverter circuit [3]. This choke inductor causes the inverter
to take a long time to reach steady-state. Figure 2.19 demonstrates this by simulating the
-
37 -
VHF Converter Architecture
start-up transient of a 100 MHz converter boosting 12 to 30 Volts with LF=3[tH and 40 nH.
This -two order magnitude reduction in inductance results in a dramatically faster start-up
transient. The converter does not reach efficient operation until steady-state is achieved,
and when designing an on/off control loop, the minimum on time must be a significant
fraction larger than the start-up transient such that efficiency is not significantly degraded.
vD(t)
~40,~20-4!~
%
0
100
200
300
400
700
em i
-_M
flpU
800
900
10
111110
.1
800
900
. 1
4
1
U
600
ID(t)
3
2r
500
Time (ns)
0,
0
100
200
300
400
500
Time (ns)
600
700
1000
Figure 2.19: Simulated waveforms of the start-up transient from two converter designs, both
designed to operate with an input voltage of 12 Volts, an output voltage of 30 Volts, and a switching
frequency of 100 MHz. One design uses LF=3 pH and is labeled "Choke Inductor", and the other
design uses LF=40 nH and is labeled "Resonant Inductor"
2.2.5
Resonant Input Inductor
The size of inductor LF can be reduced without significantly changing the converter operation [17]. As the size of LF is reduced it begins to resonate'with the other passive
components in the circuit and carries both AC and DC current. Since the design procedure
for the class-e inverter presented earlier in the chapter assumed that LF carries only DC
current, the other component values must be adjusted to account for the added AC current.
To gain a qualitative understanding of the effect that making LF resonant has on the circuit
in steady-state, it is assumed that it only resonates with CE. The schematic of Figure
2.20 shows this by splitting LF into two inductors: LF-DC is a large inductor (approaching
-
38 -
2.2
CR
CE
Class-E DC/DC converter
CFILT
RLoAD
Figure 2.20: Schematic of the converter circuit used to gain a qualitative understanding of the
effects of reducing the size of LF
infinity) that carries DC current and is an open circuit at AC, and LF-AC is the small
resonant inductor. At AC, these two hypothetic inductors are in parallel, and since LF-DC is
infinitely large, their parallel combination has the value of LF-AC. The parallel combination
of LF-AC and CE results in the following impedance at w,:
ZEQ
,WsLF-AC
-
4
(2.19)
SW2LF-ACCE
To maintain proper converter tuning, this impedance must be the same as the impedance
of CE. By equating these impedances, the new value of CE can be found as a function of
the LF-AC:
1+
CE-NEW
Ws LF-ACCE
(2.20)
LF'AC
=
Figure 2.21 presents simulation results of a 100 MHz converter boosting 12 to 30 Volts
tuned using this method to have LF=40 nH. The figure shows that the calculated value
of CE was not quite right, as the converter does not achieve zero-voltage-switching. This
is because the impedance of the parallel combination of LF and CE was only accounted
for at the fundamental, and the harmonic content of VD(t) is presented with the incorrect
impedance. Luckily, the fix is easy, as the new value of CE is simply reduced until ZVS is
achieved. A new design methodology that will be introduced in Chapter 3 fixes this problem
and accounts for the impedances exactly.
2.2.6
Mitigation of Frequency Dependent Loss Mechanisms
This section summarizes the technique used to overcome each of the frequency dependent
loss mechanisms of a hard-switched converter as introduced in Chapter 1:
39
-
. .........
VHF Converter Architecture
VD(t)
50
45
- -
-
... ... ...... ..
4 0.
I
Ia
'35 .
Calculated
- - - Corrected
..
I
...............
0
> 25 .
-.
.
~20
.
.
.... .
....
. . . ..
> 15
I.
10
-
. .
SII
-.
.....
- -.
....
5
-
-
0.
5
0
5
10
15
Time (ns)
20
25
30
Figure 2.21: Simulated converter waveforms showing the error in equation (2.20) for a 100 MHz
converter with an input voltage of 12 Volts, an output Voltage of 30 Volts, and LF=40 pH. Simulation
script is included in Appendix A.
"
Switching Loss: The converter architecture is specifically designed to operate with zerovoltage-switching to avoid both overlap loss and capacitive discharge at the switching
instants.
" Gating Loss: If a hard-switched gate driver results in too much loss for the operating
conditions, a resonant gate driver can be used to recover a portion of the energy stored
in the gate, rather than discharging it to ground [1], [16], and [15].
" Magnetic Core Loss: With the frequency dependent device losses minimized, the converter can be operated at a frequency high enough that the inductors implemented with
either low loss low permeability RF core materials [18] or by removing the core altogether,
thus avoiding core-loss.
2.3
Relation to Other Converters
It should be noted that aside from the important aspects of component values and control,
the proposed converter circuit of Figure 2.15 is topologically equivalent to the ZVS multiresonant boost converter of [4] and to the resonant boost converter of [3]. The difference
in design between the converter of [4] and here is quite large owing to major differences
in control (constant on-time variable frequency vs. burst mode control) and the resulting
difference in the choice of component values. The design here is more similar to that of [3],
-
40 -
2.3
Relation to Other Converters
but differs substantially from both [4] and [3] in that the inductor LF in Figure 2.15 is a
resonant inductor rather than a simple choke as in [4] and [3]. This design choice provides
much faster response under on-off control than is achievable with a choke inductor and
results in different design considerations and component selections.
The same concept has also been successfully demonstrated for boost conversion at frequencies up to 110MHz using a resonant boost <b2 converter topology in [12],[11], and [10].
This topology uses a multi-resonant network to shape the switch's drain-to-source voltage
waveform to approximate a square wave with a peak value of about 2VIN (under ideal conditions). In this thesis an alternative resonant boost converter topology is explored that uses
fewer passive components but suffers from a higher peak drain-to-source voltage, further
exploring the tradeoffs that exist between complexity and performance.
-
41 -
Chapter 3
Design Methodology
A
that both provides insight
proposed converter topology
the
for
procedure
DESIGN
the converter's operation and is straight-forward to use is desirable. Single switch
into
resonant DC-DC converters are often designed using an iterative modeling approach. The
designer typically start from some approximate component values and searches for good
designs through a series of time-domain simulations sweeping parameters [5],[3]. This approach is workable, especially for a designer with good knowledge of a particular topology.
However, due to the large number of parameters, it is hard for the designer to know if they
have reached the optimal design.
Additionally, parasitic impedances in the circuit complicated the search for the optimal
design. Figure 3.1 shows the converter schematic including typical parasitics. Transistor
S1 has a parasitic capacitance between its drain and source terminals, and diode D1 has a
parasitic capacitance when its junction is reverse biased. These parasitic capacitances are
in parallel with the external resonant capacitance CE and CR, and limit the the minimum
value of the net capacitances.
PAR
VIN
I
OUT
Figure 3.1: Schematic of the proposed DC-DC converter topology showing parasitic capacitances
that limit the available design space.
-
43 -
Design Methodology
Thus, when searching for a workable design solution, the designer must be careful not to
choose a design that does not require a smaller capacitance than can be obtained. This
complicates the design problem. For instance, the main switching device, S1, is sometimes
custom designed to be optimal for a given application [19]. Finding the optimal switch
design requires knowing the converter operating currents and voltages. However, since the
converter design has not yet been found, the optimal switch design cannot be known. Thus,
when performing the initial converter design, one must use either the model of an ideal
device or a sub-optimal device. As a result, the true device parasitics cannot be known
along with the actual portion of the design space that is unaccessible.
To solve this problem, a design procedure is developed that does not rely on time-domain
simulation sweeps across parameters, but instead is based on direct analysis of the converter architecture. The proposed converter topology has four energy storage elements, and
to describe the converter mathematically requires fourth order differential equations. Additionally, since the converter contains two switching devices, there are four different possible
circuit configurations. Thus, a comprehensive mathematical description of the converter
requires four sets of fourth order differential equations. Clearly, deriving a complete set
of closed form equations to directly describe the converter is a cumbersome and unfruitful
task. Aiming to circumvent this complicated scenario, the simplifying assumption is made
the the rectifier's LC tank, formed by LR and CR, is high Q such that the current in inductor
LR, labeled IRECT , is sinusoidal with a DC offset.
IRECT =AC sin
(wst + 1) ± POUT
VOUT
(3.1)
This allows the inverter and rectifier to be separated for analysis. When designing the
inverter, the rectifier is replaced by a current source. With only two energy storage elements,
the inverter is described by second order differential equations, readily yielding a closed form
solution. In a similar fashion, the rectifier design is found by replacing the inverter with a
voltage source.
While this simplifying assumption reduces the complexity of the design problem to the
point where a converter solution is easily obtained, it comes at the cost of accuracy. In
reality, the current IRECT contains some harmonic components and is not purely sinusoidal.
The resulting difference between the actual current in LR and the assumed current leads
to a discrepancy between the predicted and actual converter waveforms and the resulting
component values. Typically, however, the rectifier has a modest loaded Q, and the error is
small enough such that the designer can easily make compensating changes to the component
values when simulating the converter design in SPICE. This approach is described in more
detail in the following sections.
-
44
3.1
3.1
Inverter Analysis
Inverter Analysis
The schematic of the inverter separated from the rectifier is shown in Figure 3.2. As stated
in the previous section, the rectifier is modeled as a sinusoidal current source with DC offset,
shown in (3.1). In this development, the duty cycle of the inverter is set to 50%. While
this is not a fundamental limit, it is a good design choice to ease the use of a resonant gate
driver.
REcT
LF
1cmt
(t)M O
+-
Vc(t)
-
VIN
TE
Figure 3.2: Schematic of the inverter used for analysis. The rectifier is modeled as a sinusoidal
current source labeled IRECT
-0.5
5
5
Time (ns)
Time (ns)
0
5
Time (ns)
Figure 3.3: Sample illustrative waveforms for the inverter circuit of Figure 3.2.
With the duty cycle of a half, the time period 0 < t < Ts/2 is defined as the period with
the switch turned off, and Ts/2 < t < Ts as the period with the switch on. The analysis
starts at t = 0, when the switch has just turned off. The node equations in this time period
(with the switch off) form a second order differential equation for the voltage Vc(t) .
LF CE
d2VC(t)
dt 2 + VC(t) = VIN - WsIACLF cos (Wst + 01)
-
45 -
(3.2)
Design Methodology
The general solution to this equation is:
VC()=WSLFJAC
VC(t) =-LFC
WSLC
s+0)+Cejt
#1) ± Clejt/ LFCE + C2 ejt/ LFCE + VIN
S
cos (wst -
(3.3)
where C1 and C2 are constants. To solve for these constants, two initial conditions are
required. The capacitor voltage at t = 0+ is known to be 0 since the switch was turned on
at t = 0-. The initial inductor current is not known, and the constants are found in terms
of the initial inductor current, IL(0) . After finding the constants, VC(t) becomes:
Zo
-
(ro - 1) IAC sin# 1 ±
I
ZoWo roJAC cos
+
0 w0
ws
-
VOUT
]OUT
sin (wot)
i + VIN cOS (Lot)
LOs
VC(t) =<
IL(0)
for
0 < t < TS/2
I
(3.4)
roIAC cOS (Wst + 01) + VIN
for
Ts/2 < t < Ts
where
1
Wo =
,
Zo=
F ,
CE
/LFCE
and ro=
(Ws/Wo )2
(ws/wo) 2
_1
From (3.4) it is observed that there are five unknown quantities in the inverter circuit that
must be found: the resonant frequency and characteristic impedance of LF and CE (Wo and
Zo), the magnitude and phase of the rectifier current (IAC and #1), and the initial current
in LF (IL(O)). To solve for these unknowns, design constraints are applied to the system.
1. Since average power is only delivered by DC current from the source, the DC current in
LF is constrained by conservation of energy.
(IL (t)) = POUT
VIN
(3.5)
where
(VIN - VC(t)) dt + IL (0)
IL (t) =
-
46 -
(3-6)
Inverter Analysis
3.1
2. The inverter must operate in periodic-steady-state:
" The average voltage across LF must be 0.
(3.7)
(Vc(t)) = VIN
" The average current through CE must be 0.
(3.8)
(Ic(t) = 0
where
f
0
IL(t) - IRECT
t < TS/2
Ts/2 < t < TS
0
Since the capacitor does not conduct any current when the switch is on and had an
initial voltage of 0, this constraint is equivalent to setting the capacitor voltage to
0 at the switching instant. Thus, a separate constraint for zero-voltage-switching is
not required.
3. It is chosen to constrain the switch voltage to have zero slope at the turn-on switching
instant. This ensures that there is no current in CE at the switching instant and results
in the least amount of ringing in the circuit.
dV= (t)
dt t=T,/2
0
(3.10)
Application of these constraints begins with:
VIN = (Vc(t))
=
Vc(t)dt
1
Taking the integral results in:
VI
VIN = --
s-wlo
27rro I
cos (worK
VOUT
(ro - 1)IAC sin(o1) + IL(0) - POUTi
VOUT
Los
ZOrOIAc
27w0 I
Lo.oK7
os
cos(i) - VIN sin
I
( WSs
From this equation, the initial current in LF,
o
-
-ZoToJACL-7
s
sin(5 1 )
-
Vs
VIN
(3.12)
2
IL(0), is found as a function of all of the other
unknowns in the circuit:
-
~--
47 -
Design Methodology
VIN
2ww
IL (0)
+
W
ZoIAC
27rwo
sin(1)
) .i
sin
o cos(#1) + VINI
Ws
(To
+ POUT
o
1I
+ 7-ZoToAC--Ws
2
WsZo
y)-1
Icos((
(3.13)
1)IAC sin(01)
VOUT
This is then substituted into VC(t) in (3.4). After some simplifications VC(t) becomes:
27rwo
VIN
Ws
2
+ZoACoo sin(01)
7ros
+ I ZoIACro cos(01) sin (I
27r
+
VC(t) =
\ Lis
27rwo
sin
<
--
(s) VIN
sin(wo)t)
VN
cos
ZoIACTo - cos(#1) + VIN
+ ZoIACro
0 < t <
Ts/2
_s
(3.14)
cos(ot)
cOS(Ost + 01) + VIN
for
T/2
< t < Ts
With VC(t) now defined explicitly, the currents in the circuit can be found.
voltage is directly across capacitor CE, its current is easily found.
(t)
IC~)= CUdVC
CE
IC(t)
dt
ci
IA
ZoIACWoTo
27rwo VIN
-ZoJACro COS(q0i) Sin I
+
)
-sin(g5
+
I
1
27r
7ros
2
wsZ 0
cos(wot)
7 VIN~
sin
+os
Since this
_
27rwo
(Ls
+ I [ZoIACrozo
0s
Sos
.ICos (
--
-0-
cos(#1) + VIN
for
0 < t < T/2
for
Ts /2< t < Ts
1
Sin(wot) -
0
IACTo sin(Wst +
01)
(3.15)
-
48
-
3.1
Inverter Analysis
The current through inductor LF is found is the time period 0 < t < Ts/2 through application of KCL, as all of the other node currents are known. In the time period Ts/2 < t < Ts
LF has a DC voltage applied across it, and its current is found by integrating this DC
voltage.
for
IC(t) + POUT
VOUT + IAC sin(wst + 01)
0 < t < Ts/2
IL (t) =
-IAC sin(#1) +
IC
OUT + VIN
for TS/2 < t < Ts
)t
(3.16)
The current through S1 is found through application of KCL since all of the other currents
in the circuit are known, and the remaining design constraints are applied to solve for the
unknown quantities in the circuit. First, the remaining periodic-steady-state requirement
is applied:
(Ic (t)) = 0
(3.17)
TS Ic(t)dt
1
Taking this integral results in a non-linear equation describing the unknown quantities in
the inverter:
0 =
1 [VIN
Zo
2
+
1,
-ZoIACio
7r
+ WsVIN sinsin
ws
2irwo
-[cosCO Wowr
---
-
1
.
Wo- sin(O1)
Ws
~~~si
o (~~Wr7 )aIC
cos
(
)1
WLis
)-
+
IZoJACroS(01) s
27r
27rZoowo
-
0__
-
/
Ws
ZoIAC To " cos(#1) + VIN
Os
(3.18)
--IACro cr O01
os(1)
Next conservation of energy is applied to the inverter, constraining the DC current in LF:
-
49 -
Design Methodology
(IL(t))
=
POUT
VIN
(3.19)
IL(t)dt
fT
=
The solution to this integral results in a second non-linear equation describing unknown
quantities in the inverter:
POUT
VN=
1
POUT
(IC(t)) +
+ 1- IC Ts
+ -IAC cos(#1)
(3.20)
VINWo7r
-)-IAC sin(#1) -+POUT
+
OUT
4Z
Finally, the only remain constraint in the inverter circuit is that the derivative of VC(t) be
zero at the turn-on switching instant (so-called class-e switching):
dV(t)
= 0
dt t=T,/2
(3.21)
Taking this derivative results in the final non-linear equation describing the unknown quantities in the inverter:
2r
Os
+
WsVIN
27rZWo
ZoJACoTo
[VIN
[2
.w
smi -
+
rs
7
Wc
Ws
cos
s.
ZoIACro
.o
S
(-)
WS
-
1
+ o
Wo
ZoIAC -To
[
o7r
WS
2w
o
s
cos(#
.
+ VIN sm(
)s
Wo7i
(3.22)
+ ZoIACWorosin(# 1 )
With four unknown quantities (wo, Zo, IAC , and #1), and only three equations, the system
has one free variable. In this development it is chosen to leave wo unconstrained. In
doing so, the designer has the ability to trade additional circulating resonant current in the
inverter for smaller values of LF and larger values of CE. A portion of CE is made up by
-
50 -
3.1
Inverter Analysis
the parasitic capacitance of S1 in Figure 3.1, and designs that require smaller values of CE
than this parasitic capacitance would be unattainable. However, by having control of wo,
the designer can increase the value of w0 until the required capacitance at the drain node is
no longer smaller than the parasitic capacitance of the device. Additionally, increasing wO
also increases the transient response speed of the inverter when Zo is held constant. Thus,
control of w, is important when designing a VHF converter.
Additionally, just as the inverter design space is limited by the parasitic capacitance of Si,
the rectifier design space is limited by the parasitic capacitance of D 1 (Figure 3.1). When
designing the inverter, the assumption was made that the rectifier could be modeled by a
current source in the form shown in (3.1), with any value of IAC and #1. Since the rectifier's
design space is limited, it is important that the inverter solution does not require a current
that the rectifier cannot provide. Thus, #1 must not be tightly constrained in the inverter
design. To gain this control, one of the constraints must be relaxed. Since conservation of
energy and periodic-steady-state operation cannot be violated, the only remaining choice
is to relax the requirement that the switch's voltage have zero derivative at the turn-on
switching instant. Rather than constraining the derivative to be zero, it can instead be held
to a relatively small value giving the designer some choice of #1.
With w, and #1 now unconstrained, the only remaining unknown variables in the circuit are
Zo and IAC. Equations (3.18) and (3.20) are linear in these two variables, and are re-written
to show this relation explicitly. Begining with (3.20):
POUT =OT
POUT
PU
VOUT
VIN
iz-
-
Lws
-cos(#1)
2 ws
1
i
sc
r, sin(1) +
ro wo
Zo
2
1
wW
os
+
+ IAC F1- coS(#1) -- 1.
- sin(01)
VINLAo7F
+~4ws
.
27r
wonr
smi-Ws
VIN7FLIo
2Zows
cos(41) sin
+
(W 0 r
cos
LOS
Wro
\is
/ J(--cos
-o1
WS
ro sin(#1)
2
1
12
smn
Wo7
-(1
Lis
CosS
coI Zoo"
+
--VIN smi
1or 2
L)7
-
WS
(3.23)
To aid is solving the system, the following substitutions are made:
a = IAC - b + 1- c
Zo
-
51 -
(3.24)
Design Methodology
where
POUT
POUT
-
VIN
b =
7r
WO1 -
1
A sin(#1)
2
+ ro WOcos(#1) sin
O
2 ws
0
-
L;)
os
os
Fw
Lw
I
(3.25)
VOUT
ro sin(#1) + 1 ro cos(# 1) sin
ros
27
W
\\WsJ/
I
Cos
Cos
(-
(0)WS)
- 1rW
+ ro sin(#1)
2
(3.26)
and
VINwo7r
F1 .(wow
I- sin -0
VINWWO),
4Los
2ZOLw)
2
OS
I
oscs((W
)
Los )I
+ -VIN
smn
2
(3.27)
Los
Similarly for equation (3.18):
0
1
zo
VIN
WsVIN
2
27rwOw
LOO
+ IAC
[-I
- rocos(#1)
-o
'
roI sin(#1)
r os
sin (Wo)
sin (O)7
\
-
(os
/
JI
Ws VIN
cos (W)WS)
-- 1
27rwio
sin
ro cos()1) sin
27r
os /)
COS (ww)
y Los )
-)]
(Wr
cos(W
LOS
-1
~
- rocos(#1) cos wowr
(
- I]
_
WS)
1
2w
(3.28)
The following substitutions are made to aid in solving the system:
1
0
Zo
d
+
- 52 -
IAC
e
(3.29)
3.1
Inverter Analysis
where
__
___
d
2
sinQ Ws )
-1
os
-\Lis /] JCos (w-7rE)
__
[NU)sV§IN
27rwo
sin
o
__07
c
-s
1
Ws]
VIN COS
%2uro
-
1)
(3.30)
\Lis
and
.(o
1 wo
7r Ws
-ro - sin(o) --
e =
1
2,7r
Tocos(#1)
27r
woi7r
cosL
LOs
T cos(0i) sin
---Ws
-
/
sin (L 7 )
cos "-0-r -r
Ws
---
cos(#1)
(3.31)
- 11
.J
These equations are solved for Zo and IACal
b I-f
where
1AC =-__
(3.32)
f = e -c
(3.33)
d -b
and
zo =
I d
IAC e
(3.34)
This solution is shown graphically in Figure 3.4 where the inductance and capacitance of
LF and CE are plotted versus switching frequency and rectifier phase, 41 (as sepecified in
(3.1). The solution describes a converter with input and output voltages of 12 and 30 Volts,
an output power of 7 Watts, and the inverter resonant frequency WOis set to 85% of the
switching frequency.
-
53 -
Design Methodology
10.
........
10 ...................
... ......
.-..
...
..............: ......
...........
10 ......................................................
40 ....
50 ............
60...................
70..80.90.100
110 .
120
Switching.Frquency.(M.z
10.
.... .....
= - . radian
.-.
.-*
...
...
........... ......... ................... ......... .- 0.
-0........... ... ..... ....... radians
~
.... ~~~~~~~~~~~~~
1rain
-2
10.
10
r 140
Figure...
3.4:.
Close
12~........
( 3.1 ) .
. . . ..
50.
. . . .. .. . .
. . .. .
60
fomslto.oteivre.Slto
. . . .... . . . . .
. .. .. . .. .. .. ..
70..80.90..100.110..120
Switching....... Frequency (M.. z)......
.
........
......
asmsa
nu
n
uptvlaeo
an 30..Volts an.notu.owro at. #1. is . th rectfie's.urrnt.
.. .
. . .0 .:. . . .. . . . .. . . . ... . . ...
-
54 -
hase.asspeifid.i
Rectifier Analysis
3.2
3.2
Rectifier Analysis
Similar to the approach taken for the inverter, the rectifier design is determined by replacing
the inverter with a sinusoidal voltage source plus a DC component, shown in Figure 3.5.
VINv = VAC sin(wst +
4) +
(3.35)
VIN
where VAC and # are the fundamental component and phase of VC(t) (the drain to source
voltage of the inverter).
VINV
VOUT
Figure 3.5: Schematic of the rectifier used for analysis. The inverter is modeled as a sinusoidal
voltage source labeled VAC
60
-40
.
.-
---
VD(t)
- V
R(t).
-1CR(t)
y
- - -IODEt
0.5
...
. .. -...
20
0
N..
0 .... . ....
-20
.
-0.5
-40
4
6
8 10
Time (ns)
12
4
6
8
Time (ns)
10
12
4
6
8
10
Time (ns)
12
Figure 3.6: Sample illustrative waveforms for the rectifier circuit of Figure 3.5.
Unlike the inverter, the rectifier's duty cycle is unknown. When the diode turns on, the
voltage VD(t) is held at VOUT, and there is no current in the capacitor CR. The diode
turns off when IR(t) crosses zero, reversing the direction of current in the diode. While the
diode is off the resonant circuit rings until VD(t) reaches VOUT again and the diode turns
-
55 -
Design Methodology
back on. For analysis the times that the diode turns on and off in a cycle are labeled ton
and toff, and equations are derived for a single cycle begining at toff.
The following differential equation describes the rectifier voltage, VD (t) , for the time period
with the diode off, toff < t < ton + Ts:
dt 2
LRCR
+ VD(t) = VIN + VAC sin (st + 0)
(3.36)
The general solution to this differential equation is:
VD(t)
2 sin
VAC
(s Wr)
(wst + q) + C1e(jwrt) + C 2 e(wrt) + VIN
(3.37)
where C1 and C2 are constants. With the rectifier, there are two known initial conditions
that occur when the diode turns off.
VD(toff) = VOUT
(3.38)
IR(toff) = 0
(3.39)
Upon applying these initial conditions the rectifier voltage becomes:
(TVAC
+
VD(t) =-
sin (wstoff + 9) +
VOUT - VIN) cos (Wr (t
r (Ws/Wr) VAC cos ( )stoff
rVAC sin (wst +
9)
+ 0) sin (Wr (t
toff))
for
toff))
VOUT
for
where
1
Wr /LRCR'
toff < t < ton - TS
-
LR
ZR=
, and r=
CR'
-
56 -
(Ws/Wr)
2
_
ton+ Ts < t < toff
(3.40)
+ Ts
3.2
Rectifier Analysis
The currents IR(t) and ICR(t) are found from the voltage VC(t).
(VAC - VD (t)) dt
f
IR(t) =
LR
toff
S[VACr sin (wstoff + 0) + VIN W
-
k)cos (
rVAC COS (Wstoff +
W ZR
+ L
rVAC cos (wst +
WrZR
L
VouT] sin (Wr(t - toff))
r(t - toff))
toff < t < ton + TS
for
d)
(VIN - VouT) (t - toff)
WrVAC [cos (est
+
d)
-
cos (wstoff +
for
d)]
ton+TS <t<toff
+Ts
ZRWS
(3.41)
ICR(t)
=
CR
dt
-
VD(t)
+
(rVAC sin (ostoff +
+ z-r
-
r
d) +
(Ws/Wr) VAC COS (stoff
rVACCos (st
+
VOUT - VIN) sin (Pr(t - toff))
+
d) COS (Wr
(t - toff))
for
toff <
t < ton + TS
)
0
for
ton+TS<t<toff+TS
(3.42)
From these equations it is found that the rectifier has four unknown quantities: the resonant
frequency and characteristic impedance of LR and CR(Wr and ZR), and the times that the
diode turns on and off (ton and toff) in a cycle. As with the inverter, design constraints are
applied to the voltages and currents in the circuit to solve for the unknown values.
-
57 -
Design Methodology
1. Since average power is only delivered to the load by DC current, the DC current in LR is
constrained by conservation of energy.
(IR(t)) = POUT
VOUT
toff+Tg
1
IR(t)dt
= S to
fy
1_ws
=2IrZR
1
27rZR
[VAC - r - sin(wstoff + 9) + VIN - VOUT] [coS(Wr (ton + Ts - toff)) - 1]
2
Wr
r - VAC cOS(UOstoff + 0) Sin(UOr(ton -+ Ts - toff))
2
- r - VAC
+ 21tZR
2+ZR[VIN
Wr
27rZRUWs
--
- sin(wstoff + 0)]
-
VoT[
VAC [sin(ostoff + 9)
F
Wsor
9)
onj
ff
FOtI
[VN-
+ WsWr
[Sin(Wston +
- Sin(Wston +
9)
1
+ 27r
[VOUT - VIN] toff + -VAC cos(Wstoff +
27rZR I
Lis9$]
[toff -
tff-t
ton
]
(3.43)
2. The rectifier must operate in periodic-steady-state:
* The average inductor voltage must be 0.
(VD (t))
VIN
1
Jtoy+Ts
tofT SV D,(t)
dt
toff
r[VIN(ton
-
+ Ts
2rrr [VAC ' r
- toff)
+ VoUT(toff
Sin(stoff +
d)
r - VAC cos(wstoff
+1
-
ton)]
+ VIN - VouT] sin(wr(ton
+
9)
+ Ts
[coS(wr (ton + TS - toff)) -
toff))
1]
kWrJ
-
-- VAC - r - [coS(Wston +
2r
9)
- coS(stof
+ $)
(3.44)
-
58 -
3.2
Rectifier Analysis
* The average capacitor current must be 0.
0
(ICR(t))
jtffI+TS CR(t)dt
TS tof
2-
[VAC * r
s
7rZRWr
(
27rZR
+
WS
27rZRr
)
Sin(wstoff +
#) +
VIN - VOUT] [cos(Wr(ton
- T - VAC cOS(Wstoff + 0) Sin(wr(ton
\Wr)
VAC r ' [sin(wston + c)
+ Ts
- toff))
-
+ TS - toff))
sin(Wstoff +
(3.45)
3. The phase of the fundamental component of IR(t) is constrained by the inverter (#1
in equation 3.1). The inverter design constrains both the amplitude and phase of the
fundamental component of IR(t). However, this analysis assumes the rectifier is lossless
and with the output power constrained the input power is set. Thus, only #1 or IAC must
be constrained to get the proper input power.
41=tan_1
-
59 -
ar
(br
(3.46)
1]
Design Methodology
where
2
ar
toff+
Tg
IR (t) Sin(wst)dt
TS Itoff
Sin (Lortoff
wus
=-
IVAC 'r
s
L
7rZR
Sin(Wstoff +
d)V IN
VOUT]
7TZRWr
Cos
2(Or -
Cos (Wrtoff
- r - VAC Cos(Ostoff
Wrtoff -
(Wr
Wr
+ 47r
F
2(Wr
+ CoS(Ostogf)
cos(2wstoff + c)
WrWs (VIN - VouT)
IrZR
+
Wr
+ +FZR
Ws) (ton
-
ws)
+ 2(Wr + ws).
wOs)
ws)(ton -4 Ts))
Ws)
Ws)(ton + Ts))
VAC cos(2wstoff +
47rZRWs I
- (Wr -
+ 0)
2(wr + Ws)
+ 4ZRWr
1
+ sin(wstoff)
2
-
2(Wr -
Sin (wrtog - (Pr- Ws)(ton + Ts
2(Wr + Ws)
(Wr
-
4)
- COS(2wston
toff cos(Wstoff)
.
+
cos(2wston
ws
)
+
2(wr ws)
+ 0)+ 2 sin(O) (toff
2 sin()(toff -
+ sin(wstoff)
s
2(Wr
--
Ws)
-
ton
-
TS) Ls
ton)WsI
t on CoS(Oston)
sin(wston)
L s
(VOUT - VIN)toff VAC COS(Ostoff +
)
COS(oston) - COS(wStoff)
(3.47)
60
-
3.2
Rectifier Analysis
and
br~=2 Jtoff+TS IR(t) cos(wst)dt
TS
toff
[ VAC ' r ' sin(wstoff
(rZR
=
[
COS
oWrtogf -
(Wr -
+
Ws) (ton
+
2(wr + ws)
sin (Wrtoff -
(Pr- Ws)(ton
+ 0)
2(Wr
- Ws)
1
s
. r - VAC
47rZRWr
2(Wr + WS)_
+ sin(stoff)
[sin(2wstoff +
sin(2wstoff +
Wr
Ws)
-
[2(Wr
#) - Sin(2wston +
sin(2wston
0)
ws)
+ 2 cos(#)
#) + 2 cOs(#)(toff
+
-
2(Wr+Ws
ton)LsI
-
I
[togf sin(Wstoff)
WrWs (VIN -
(VI
7rZR +L~
r
(Vo
TS)
(toff - ton -
47rZRWs
7rZR
-
+ Ts)
2(Pr + Ws)
-
Ws) +
CoS(Wstoff) [2(Wr
+ Ts)
sin (Wrtoff - (Pr- Ws)(ton + TS))
2
s
. r - VAC coS(wstoff
1rZRor
-
2(LLr
+ Ts))
-
_-
cos (Wrtoff - (Wr - Ws)(ton
VOUTI
5)VIN -
-L~
VoL)+I
T -
cos(wstoff)
+
ton
sin(Wston)
S
s
VIN)toff VAC coS(Wstoff
ws
+
cos(wston)l
2
s
s
Sin(Wston) s)
.
sin(wstoff)
(3.48)
Thus, applying these constraints to the system results is four non-linear equations. Since the
rectifier has four unknown values there are no free variables. As a result, no simplifications
can be made to the above equations, as was done with the inverter, to ease process of
finding a solution, and numeric techniques are used to solve the system. Rather than using
a standard numeric non-linear equation solver, a custom process was developed that exploits
specific characteristics of this system to reduce the amount of computation required to find
a solution.
From equations (3.44) and (3.45) it is observed that achieving period-steady-state (PSS)
is independent of the value of ZR. Therefore, the numerical solver has one less variable to
search over when constraining the rectifier to PSS. Additionally, Equation (3.43) shows that
-
61 -
Design Methodology
(IR(t)) is proportional to 1/ZR. Thus, once Wr, ton, and toff are found, ZR is easily found
algebraically. Keeping these facts in mind, the solver starts by first searching over values
of ton:
1. For each value of ton the solver finds the value of tof and Wr that results in PSS. This
is done in a brute force method, where (VD(t)) and KIcR(t)) are searched over all values
of toff and Wr to find where they both achieve PSS or if a solution does not exist. While
this is potentially very computationally intensive, a low-sweep-resolution grid search is
used. This keeps the computation manageable. Once the low-resolution sweep finds a
solution, the solver interpolates between the values to gain back resolution.
2. For each value of ton that has a PSS solution,
calculated from (3.43).
#1is
3. Finally, the solver interpolates between the values of
the inverter design.
calculated from (3.46) and ZR
41 to achieve the desired value from
Due to the extensive use of interpolation this custom solver (code is included in Appendix
B) is able to rapidly find a rectifier solution. Increasing the sweep resolution results in less
error between the interpolated solution and the actual solution. Since this design approach
has error inherent in its design from the sinusoidal current approximation, it is not necessary
to reduce the interpolation error to a level significantly below the built in error. A rectifier
solution generated using this approach is presented in Figure 3.7 where the inductance
and capacitance of LR and CR are plotted versus switching frequency and the phase of the
fundamental component of the rectifier current, #1. The solution describes a converter with
an input and output voltage of 12 and 30 Volts, and an output power of 7 Watts. For
each solution point, the rectifier solver requires the fundamental voltage and phase of the
inverter voltage VC(t). Thus, to generate this figure, the inverter must be solved for each
point first, the fundamental component calculated, then the is rectifier solved.
62
-
3.2
70
80
90
40.. . . . . ..
50. . . . ..60
. .. . . ...
Switching Frequency (MHz)
Rectifier Analysis
100
110
C. .. ..
100
110
120
. ..
103
10
.
40
.
50
80
90
70
Switching Frequency (MHz)
60
120
Figure 3.7: Numerical solution to the rectifier. Solution assumes an input and output voltage of
12 and 30 Volts and an output power of 7 Watts. #1 is phase of the fundumental component of
I.
.
.
-
63 -
Chapter
4
Semiconductor Devices
important when designand selection are crucially
design
device
found in the previous
was
As
EMICONDUCTOR
ing power converters with VHF switching frequencies.
chapter, device parasitics have the potential to significantly limit the available design space.
Thus, choosing the correct device or designing a device that is optimized for a particular
converter specification can open up the design space and lead to higher performance [19].
In addition, semiconductor device losses often make up a significant fraction of the total
converter loss. Typical power semiconductor devices that are available off of the shelf are
not optimized for use at VHF, and vast improvements in converter performance are achieved
when consideration is given to the parasitics that are important to operation at VHF when
S
designing the device [19].
4.1
Device Model and Loss Mechanisms
To achieve efficient operation at VHF, a thorough understanding of the loss mechanisms
that are inherent to the switching device is required. Achieving the proper balance between
the many device loss mechanisms is necessary for optimal performance. There are many
general purpose MOSFET models that include an exceedingly large number of parameters,
aiming to be as accurate is possible. While these models are very good for general circuit design, they serve to cloud the designer's vision of the important tradeoffs that exist
between the dominant device loss mechanisms at VHF. For this reason, the simple model
of Figure 4.1 is preferred when designing a VHF converter. The device parameters that
are included in this model are chosen specifically because they have the most significant
effect on converter design. Among the simplifications that might appear to be alarming
when comparing this model to a standard device model is the lumping of the gate to drain
capacitance CGD in with the gate to source capacitance CGS, and calling them a single capacitor CIss. This simplification is acceptable for soft-switched resonant converters because
they operate with zero-voltage-switching (ZVS), and the drain voltage is already at zero
when the gate voltage rises. Thus, the two capacitors are effectively in parallel (at least
during the critical switching interval). Likewise, CGD is lumped with CDStO form a single
-
65 -
Semiconductor Devices
equivalent Coss capacitance (and Ross parasitic resistance). Additionally, operation with
ZVS also permits the transistor's complicated on characteristic to be modeled as a variable
resistance (dependant on gate voltage) because the transistor is never operated outside of
the deep triode region.
D
5IsP
'COND
Ross
G
R1ss
z
CISS
Coss
CEXT
-4
T
S I
Figure 4.1: MOSFET model that is preferred for VHF converter design.
The device model of Figure 4.1 shows the primary loss mechanisms that are considered.
When the device is on, current flows through the finite on resistance of the device resulting
in a conduction loss.
CONDRMSRDS-ON
PCOND
(4.1)
While this loss is independent of switching frequency, the remaining losses are not. Gating
loss arises from charging and discharging the gate capacitor once per cycle. Treating the
input capacitance as linear and with hard gating, we get:
PGATE = CISSV2Fs
(4.2)
This loss can potentially be reduced by employing a resonant gate driver to recover a portion
of the energy that was stored in the gate, rather than discharging it to ground. With this
method, loss occurs due to the finite Q of the resonant network. For sinusoidal resonant
gating:
PGATE = 2R 1ss (7rVGFsCIss) 2
(4.3)
The final loss mechanism to be considered arises from the fact that an AC waveform is
applied to the device when it is in the off-state, resulting in circulating current IDISP through
Coss and Ross.
PDISP
DISP,RMSRoss
(4.4)
While at first glance this appears to be a frequency independent 12R loss similar to PCOND,
it is actually a frequency dependent loss due to the fact that the shape of the AC waveform
-
66 -
4.2
Device Layout Optimization
across the device in the off-state is unchanged as frequency is scaled. For a typical device
the impedance of Coss is dominant over Ross, and the net impedance of their series combination decreases with increasing frequency. Thus, to maintain the same AC waveform
shape, a larger current is required, and IDISP grows proportional to frequency. Taking this
into account:
PDISP cxCOssRossFs
(4.5)
Additionally, in a typical converter circuit, some extra capacitance is added in parallel
to Coss to provide the resonant circuit with the proper impedance. This is shown by
the inclusion of CEXT in Figure 4.1. This results in IDISP being shared between the two
capacitors, giving the following loss:
PDISP
(D
)
where CTOT = COSS + CEXT, and CossS
be negligible.
IDISP,RMSRoss
(4.6)
CTOT, and external capacitor loss is assumed to
Understanding how the device loss mechanisms scale as the size of the device is varied
brings light to the existence of a trade space. As the total device width W is increased,
RDS-ON and PCOND decrease approximately proportionally to !. CIss, on the other hand,
grows approximately proportionally to W, and PGATE grows linearly with W if a hard
switched gate driver is used, and grows proportional to W 2 if a resonant gate driver is
used. Coss also grows approximately proportionally to W resulting with PDISP growing
proportional to W 2 . Thus the total device loss can approximately described by:
PToT = ki -
1
W
+ k2 - W + k3 - W 2
(4.7)
where k1 , k2 , and k 3 are some constants that will be derived with detail later in the chapter.
What the equation shows is that there is an optimal device size that balance the loss
mechanisms that increase with W and those that decrease with W to find the device size
that results in the minimum total loss.
4.2
Device Layout Optimization
With an understanding of the parasitics that are important to converter operation at VHF
and a notion that there is an optimal switch size that minimizes loss, a method to find this
optimal device design is presented here. This work follows the general approach described
in [19].
-
67 -
Semiconductor Devices
4.2.1
Layout of a LDMOS Transistor
Figure 4.2 shows the basic cell structure that makes up an LDMOS transistor. The cell,
which is typically called a finger, is created by first doping a well of N-type semiconductor
in the P-EPI substrate. This N-well holds the entire cell, and forms the drift region between
the drain terminal and the channel. Along the outside of the N-well, an N+ region is created
that serves as the drain terminal of the device. In the center of the N-well a well of P-type
semiconductor is formed. The source of the device is created by doping N+ regions inside
and near to the edges of the P-well. The space between these N+ regions and the N-well
form the channel of the device.
Top View
T
WCAP
WF
Cross Section
OLY
im
PWELL
Figure 4.2: Drawings showing the top view and cross section layout of a LDMOS transistor cell.
Large LDMOS transistors are formed by scaling the width of the basic LDMOS finger,
labeled WF in Figure 4.2, and by building multiple copies of the finger that are connected
in parallel. For a given process and device technology, all of the device lengths, represented
by the horizontal axis in Figure 4.2, are fixed and can't be changed by the designer. The
variables that are available for the designer to use are the finger width WF, the number of
fingers NF, the orientation and spacing between the fingers, and the metallization scheme
employed to connect all of the fingers in parallel. Thus, the optimization procedure seeks
to find the combination of these variables that results in the least amount of loss.
-
68
-
4.2
4.2.2
Device Layout Optimization
Scaling of Device Parasitics
In order to perform this optimization, it is necessary to know how each of the parasitic
elements changes with each of the design variables. A portion of each of the parasitic
elements is intrinsic to the device structure itself, and the remaining part results from the
method in which the fingers are oriented and connected together. The intrinsic portion is
considered here first, and the interconnection portion with be incorporated later.
It was previously found that CIss is parallel combination of CGS and CGD. Each of these
capacitances are essentially a parallel plate capacitors between the gate and source and
between the gate and drain respectively. The plate area increases linearly with WF causing
the capacitance to do the same. Additionally, from Figure 4.2 it is seen that there is a
region at both ends of the finger of overlap between the gate with the drain and source that
does not scale with finger width. As a result there is a portion of CIss that does not change
with WF, and there is a penalty in terms of additional gate capacitance when the device is
composed of many small fingers rather than fewer long fingers, as this end-cap capacitance
can become dominant. CIss is described by the following equation:
CISS = (CGSO + CGDO)
.
NF - WF
+ 2 * Cend - NF
(4.8)
where CGSO and CGDO are the capacitance per unit width intrinsic to the device between
the gate and source and between the gate and drain, and Cend is the capacitance due to the
end cap of the finger.
Coss is the parallel combination of CDS and CGD. CDS is formed by junction capacitance
between the N-Well and the P-Well, shown in Figure 4.2, and by the junction capacitance
between the N-Well and the P-EPI layer which is formed from a component that is proportional to the area of the bottom of the N-Well and a from component that is proportional
to the outside perimeter of the N-Well. CGD is the parallel plate capacitance between the
N-Well and the gate poly.
COSS = (Cj + CGDO) - NF - WF + A - Cj,bot + P - Cj,sW
(4.9)
where Cj is the junction capacitance per unit length between the N-Well and P-Well, Cj,bot
is the capacitance per unit area between the bottom of the N-Well and P-EPI, and Cj,sw
is the capacitance per unit length between the side wall of the N-Well and P-EPI. A is
the equivalent area of the bottom of the N-Well, and P is the equivalent perimeter of the
N-Well. Both A and P are modeled by the form of (ki + k2 - NF) (k3 + k 4 - WF) where k1 ,
k 2 , k 3 , and k4 are constants that are found from the process design manual.
-
69 -
Semiconductor Devices
As with any MOSFET, RDS-ON decreases as the width of the device increases. Ross scales
the same way. We assume the following (approximate) relationships.
1
W
RDS-ON = RRDSO
NF - WF
Ross = Ross,o
(4.10)
1
NF - WF
(4.11)
where RRDS,O is the intrinsic on resistance resistance per unit length at a specified gate
voltage and Ross,o is the effective intrinsic resistance per unit length in series with Coss.
4.2.3
Semiconductor Optimization
With equations describing how the intrinsic portion of the parasitic components scale with
WF and NF and equations that describe the loss in these parasitics, the optimal value of
WF and NF can be found. This is done by looking over all values of WF and NF that
result in the minimum amount of loss, that fit in the available chip area, and that do
not result in Coss being larger than the capacitance required for proper converter tuning.
Taking for example the LDMOS transistors of a BCD process used in this thesis, the results
of performing a sweep across WF and NF are presented in Figures 4.3 - 4.6. Figure 4.3
presents graphically the variation of the parasitic elements RDS-ON, R1ss, C 1ss, and Coss
with WF and NF. Ross is not included in the figure since it is proportional to RDS-ON.
When the converter is intended to be used with a hard-switched gate driver the device
design must be chosen such that the gate time-constant (R1ss - Ciss) represents a small
fraction of the switching period. Figure 4.4 shows the gate time-constant as a function of
WF and NF.
Figures 4.5 and 4.6 shows the sum of all of the loss in all of the device parasitics as a function
WF and NF for a converter designed to boost 12 Volts to 30 Volts with a switching frequency
of 75 MHz, an inverter resonant frequency of 63.75 MHz, and the rectifier's current phase
set to -1 radian (see Chapter 3 for an explanation of these parameters). Figure 4.5 shows
the optimization for an output power of 15 Watts and Figure 4.6 shows the optimization
for an output power of 7 Watts. At both power levels the optimization result is shown for
both a hard-switched gate drive and for a sinusoidal resonant gate drive. For the purposes
of this research project it is desirable to have a transistor that is close to optimal for as
many different designs as possible. Thus, a device design that works well for both resonant
and hard-switched gating over a wide power range is chosen. From these figures, the device
size of 45,000 pm is chosen with WF = 450pim. At this design point we see from Figure
4.2
Device Layout Optimization
2000
40
1500
0.8
1000
0.6
30
E
10
5001
2
20
0.4
4
b
8
6
4
Total Device Width (um) X 104
ts
Total Device Width (um) X 104
CIss1
Coss
140
120
120
100
100
U-
80
80
60
60
40
2
40
2
8
6
4
Total Device Width (um) X 104
8
6
4
Total Device Width (um) X 104
Figure 4.3: Plots showing how the major intrinsic parasitic components of the LDMOS transistor
vary with device and finger size.
Gate Time Constant
2000
1
1800
0.9
1600[
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
2
3
4
5
6
Total Device Width (um)
7
8
X 104
Figure 4.4: Plot of the gate time-constant for intrinsic parasitics vs device and finger size.
-
71
Semiconductor Devices
4.4 that the device has a gate time-constant of about 200 ps which is sufficiently small for
operation at 75 MHz.
Hard Switched Gating
0.2
0.19
0.18
2
3
4
5
6
7
Total Device Width (urn)
8
0.17
X104
Sinusoidal Resonant Gating
0.15 0
z
0.14
0.13
0.12
Total Device Width (urn)
X 104
Figure 4.5: Predicted converter loss vs device and finger size for a converter that boosts 12 Volts
to 30 Volts with a switching frequency of 75 MHz, an output power of 15 Watts, an inverter resonant
frequency of 63.75 MHz, and the rectifier's current phase set to -1 radian.
Hard Switched Gating
).16
150
).155
100
115
0
50,
).145 (V).14
2
2.5
3
3.5
4
4.5
Total Device Width (urn)
Sinusoidal Resonant Gating
5
4
).135
CU
).13
.E
0
).125 Z
150
).12
100
).115
50,
).11
2
2.5
3
3.5
4
Total Device Width (urn)
4.5
5
4
X10
Figure 4.6: Predicted converter loss vs device and finger size for a converter that boosts 12 Volts
to 30 Volts with a switching frequency of 75 MHz, an output power of 7 Watts, an inverter resonant
frequency of 63.75 MHz, and the rectifier's current phase set to -1 radian.
-
72 -
....
..........
4.2
Device Layout Optimization
Hard Switched Gating
2000
0.18
1500
0.16
1000
500
_____________________________________
0.5
1
1.5
Total Device Width (urn)
Sinusoidal Resonant Gating
2
2.5
X 10
04
0.14
0.12
i
0
N
2000
1500
0.1
1000
0.08
z
-S 500
0.06
0.5
1
1.5
Total Device Width (um)
2
2.5
X 10s
Figure 4.7: Schematic of the proposed DC-DC converter topology showing parasitic capacitances
that limit the available design space.
4.2.4
Design of an Interconnect Network
With the total device size and finger width chosen, the remaining task to to determine the
orientation of the fingers and design a metallization scheme to connect all of the fingers in
parallel without adding significantly to the intrinsic parasitic component values. Among
the most important considerations driving this design is the aspect ratio of the available
chip area. The semiconductor optimization in the previous section resulted with a device
of 45,000 pm total width that is made up by 100 fingers each 450 pm long for the stated
converter design specifications. For the purposes of the this analysis the fingers are assumed
to have a length of 13.8 pm and an end cap width, WCAP, of 10 pm. The most logical way of
arranging the fingers is in parallel rows. While there are many reasons to choose a particular
device aspect ratio, the driving constraint in this design was the available chip area. While
in some cases it could be desirable to use extremely long or narrow aspect ratios, here we
assume that the more reasonable aspect ratios are typical, and the metallization scheme
described here is applicable to these non-extreme aspect ratios. A custom interconnection
must be designed for more drastically shaped parts.
Figure 4.8 shows the overall shape of a device for the cases where it has one through four
rows of fingers. While this figure shows a device with 16 fingers, the overall shape is similar
to the actual device that is made up of 100 fingers. Table 4.1 shows the actual dimensions
for these aspect ratios. From the this table, it is determined that for one row and for four
-
73 -
Semiconductor Devices
rows the aspect ratio is too far from unity, and either two or three rows of finger will be
used.
4 Rows
3 Rows
1 Row
2 Rows
Figure 4.8: Drawings of a LDMOS transistor broken down into 16 fingers and arranged into various
different aspect ratios.
Absolute Length (pm)
Absolute Width (pum)
Aspect Ratio
1 Row
2 Rows
3 Rows
4 Rows
1380
245
5.51
690
490
1.35
460
735
0.62
345
980
0.35
Table 4.1: Overall size of a LDMOS transistor composed of 100 fingers each with a width of 450
pm.
The scheme used to connect the gates of the transistor fingers together is shown in Figure
4.9. Metal 1 is placed around the outside of the whole device and between the rows of fingers,
shown in red in the figure. This metal has finite series resistance and RIss is increased by
its inclusion. Increasing the width of the metal, shown by WGM in Figure 4.9, lessens the
increase of R 1ss. However, this metal also overlaps the semiconductor substrate and forms
a parasitic capacitor. It is further assumed that the drain and source interconnect network
will be formed on metal 2 and will overlap the gate interconnect network entirely. This will
form an upper bound on the parasitic capacitance, as the drain and source interconnect
will only partially overlap. Increasing WGM increases the value of this parasitic capacitor.
Thus, there is an optimal value WGM that minimizes gating loss when a resonant gate driver
is used. When using a hard-switched gate driver, gating loss always increases with WGM
-
74
-
4.2
Device Layout Optimization
and WGM should only be increased to the point where the gate time-constant is sufficiently
small.
Figure 4.9: Drawing showing the scheme used to connect the LDMOS finger gates.
Figure 4.10 shows a schematic that models that gate interconnect network. In this model,
RG is the resistance of the gate poly and is determined by the length of the finger. RMETAL
is the equivalent resistance of the metal between each finger and is determined by the finger
dimensions and the width of the interconnect metal, WGM. This schematic shows the model
of a single finger, and the structure repeats in both dimensions for the number of fingers
and rows. The equivalent resistance of the network is determined from a MATLAB script,
provided in Appendix C. The script calculates the value of the resistors from the device
dimensions, and then forms a matrix with these resistances based on the node equations of
the network. From this matrix, the equivalent resistance of the network is found. The script
also assumes that the network has an input at both the top and bottom of the network, as
shown in Figure 4.9. The script also calculates the parasitic overlap capacitance from the
device dimensions and aspect ratio.
Figures 4.11 and 4.12 show the output of this script for a transistor of 100 fingers of 450
pm width that are arranged into three rows. Figure 4.11 shows how R 1ss and C1ss vary as
WGM is increased, and Figure 4.12 uses these values to plot the loss in a resonant gate drive
circuit and the gate time-constant. From these plots one can observe that there is a value of
WGM that optimizes the performance of a resonant gate driver. For hard-switched gating,
however, the optimum is less clear. Loss is proportional to CIss, so it is desirable to keep
WGM as small as possible to minimize the increase in C188 . Make it too small, however,
and the gate time-constant will be larger, leading potentially to non-ZVS conditions and
more gating loss which is not modeled.
The layout pattern used for the drain and source metal interconnect networks is shown in
Figure 4.14 in blue. This blue area represents all of the upper metal layers in the process
-
75 -
Semiconductor Devices
000
RMETAL
Figure 4.10: Schematic of the LDMOS gate model for a single finger.
RIss
.......................
-
4
-
.....
Including Interconnect
- -ntrinsic
Only
2
2
B --
2-
8
20
40
WGM(pm)
60
20
40
WGM (PM)
60
Figure 4.11: Plots showing the gate resistance and capacitance vs. the width of the metal used to
connect the gates.
-
76
-
..
.....................
..........
4.2
Resonant Gating
0.05
Gate Time Constant
--
150
--
-
Including Interconnect
-
0.045
Device Layout Optimization
-
Intrinsic Only
0.04
0.035
S0.03
.
.. .
.............
0.025002
0.015
20
40
WGM (pm)
50
60
20
40
WGM (pm)
60
Figure 4.12: Plots calculating the loss of a 75 MHz resonant gate driver and gate time-constant
using the parasitic values from Figure 4.11.
connected in parallel to reduce the effective series resistance with the device. The metal
is tapered since current decreases along the length of the stringer. Thus, by making the
stringer wider where there is more current, loss can be reduced.
Figure 4.13 shows a schematic modeling the interconnect for a single row of fingers. RMETAL
is the series resistance of the metal between the fingers. Its resistance is calculated from
the sheet resistance, the spacing between fingers, the taper angle, and its position along the
stringer.
RCONT is the contact resistance between the metal stringer and the device. Since the width
of the metal is different for each fingers along the row, the number of contacts that can fit
must be calculated for each finger.
RDS is the on resistance of a single finger. In a similar fashion to calculating the gate
resistance, a MATLAB script finds the equivalent resistance of the network. First, using
the above formulas, the script calculates the resistances. A matrix based on the network's
node equations is populated using these resistances. The matrix is inverted and multiplied
by a vector representing the input to the network to find the equivalent resistance. Figure
4.15 shows the transistor's on resistance including the resistance of the interconnect metal
for a device of 100 fingers each of length 450 pm. The plot shows the result with the fingers
arranged into two, three, and four rows with the taper angle going from zero to the largest
angle for which there is still sufficient room to contact the finger at the far end of the row.
This result additionally assumes that there is no extra resistance when connecting the rows
77
-
Semiconductor Devices
together in parallel. This assumption is made since there are many different geometries
that can be used to connect pads to the device, and there is no single equation that can
describe them all. Thus, the designer must understand that the very tall aspect ratios have
longer vertical strings of metal connecting the rows together and will most likely add extra
resistance than is shown in the Figure 4.15.
Figure 4.13: Drawing showing the scheme used to connect the LDMOS drain and source terminals.
RMETAL
RDS
RMETAL
CONT
RDS
RMETAL
RDS
RCONT
RDS
RMETAL
CONT
RDS
CONT
CONT
CONT
CONT
RDS
RMETAL
RMETAL
RMETAL
Figure 4.14: Schematic of the LDMOS drain-to-source interconnection model for a single row of
fingers.
From all these criteria described above, a device is design with 100 fingers each of width 450
pm. The fingers are arranged into three rows and connected using the interconnect methods
previously described. Figure 4.16 presents a photograph of the layout of the designed device.
-
78 -
4.2
Device Layout Optimization
On-State Resistance vs. Geometry
370
360........... 360
-
350
.....
--
-.. .....
-
-
-
2 Rows
3 Rows
-*--4 Rows
Intrinsic Only
-
-
340
330
320
310
F
300'
0
. ... .. .. .. . .. ... .. .. .
5
10
20
15
Taper Angle (degree)
30
35
Figure 4.15: Predicted drain-to-source resistance vs. taper angle for two, three, and four rows of
fingers. The device has 100 fingers each with a width of 450 prm.
-
79 -
Semiconductor Devices
Figure 4.16: Photograph of the designed LDMOS transistor layout.
-
80
Chapter 5
Converter Design
In this chapter the design methodology of Chapter 3 is demonstrated through the design
a converter with the specifications outlined in Table 5.1. Since device parasitics play a
crucial role in converter design, measurements of the components that are used to build the
converter must be performed first. The proposed design methodology is used to find a set of
component values that meet all of the converter's specifications. Since actual devices include
many non-ideal qualities such as non-linear capacitance and contain loss mechanisms that
have the potential to affect converter waveforms, careful simulations must be performed to
ensure proper converter operation. To validate the proposed converter topology and design
methodology, a prototype is constructed. The device was fabricated in a 0.4 pm BCD
process.
Input Voltage
Output Voltage
Peak Power
Switching Frequency
12V
30V
7W
> 50 MHz
Table 5.1: Target converter specifications
5.1
Device Modeling
When designing a power converter to operate at VHF switching speeds, it was demonstrated
in Chapter 3 that device parasitics limit the available design space. Chapter 4 introduced
a method to design semiconductor devices that achieve the optimal tradeoff between all of
the important device parasitic components. This procedure is uses an estimation of the
numeric value for each of the parasitics from process documentation. These values should
not be trusted for the final converter design. Rather, the fabricated device is measured to
form an accurate device model.
-
81 -
Converter Design
5.1.1
MOSFET Model
Figure 5.1 shows the MOSFET model that is preferred when designing a VHF power converter. The measurements described in the sections to follow are used to populate this
model with accurate values. Since the converter design is highly dependent on the value of
these parasitics, care must be taken when performing these measurements to be as accurate
as possible.
G
RISS
CISS
CM
Figure 5.1: MOSFET model that is preferred for VHF converter design.
5.1.2
Parasitic Capacitances
The parasitic capacitances and the resistances Ross and R1ss were measured using an
Agilent 4591A impedance analyzer. The schematics of Figure 5.2 shows that setup used.
The device capacitances are nonlinear and vary with applied voltage. Thus, each capacitance
was measured over a range of applied voltage.
Riarge
COSS=CDS+CGD
CISS=CGS+CGD
CA=CDS+CGS
Figure 5.2: Schematic of the test setup used to measure the device parasitic capacitances.
-
82 -
5.1
Device Modeling
The LDMOS device package is leadless and was mounted on a printed circuit board with
SMA connectors to allow a reliable connection to the impedance analyzer. This PCB,
however, adds parasitics to the measurement, and must be calibrated to achieve accurate
results. The two dominant parasitics of the PCB are series inductance and parallel capacitance. The parallel capacitance is easily accounted for by connecting a measurement board
to the impedance analyzer with the device removed. The series inductance is more difficult
to measure and was omitted, rendering it impossible to accurately measure the actual series
inductance of the device package. This is tolerable as the inductance of the leadless package
is not expected to be a dominant parasitic.
Figure 5.3: Photograph of the PCB used to measure the device capacitances
The measured parasitic capacitance are shown in Figures 5.4 and 5.5. Coss is dominated
by junction capacitance and is well modeled by:
Coss =
"j M
(5.1)
where Vd is the voltage across Coss and the remaining variables are fitting parameters.
These parameters chosen to minimize mean square error, and are shown in the Table 5.2.
C2 o
Vj
M
121 pF
1.2701 Volts
0.4123
Table 5.2: Parameters to fit equation (5.1) to measured the junction capacitance data for the S310
diode.
It is chosen to use the S310 1 silicon Schottky diode for its breakdown voltage of 100V,
current handling capability of 3 Amps, and small forward voltage. The reverse biased
junction capacitance was also measured using the impedance analyzer. The measurement
'The S310 used is manufactured by Fairchild Semiconductor. S310 diodes from different vendors are
known to have different characteristics.
-
83 -
Converter Design
10
15
Vs (Volts)
Figure 5.4: Measured Coss data. The model of equation (5.1) is also plotted to show the good
fit. Model parameters are: C1 0=121 pF, V = 1.2701 Volts, and M = 0.4123.
V Ds=0
V Gs=0
aGS
..........
941...........................
...........
.. .... ..
.... .... ..
U-
Ln 901
U
88
. . . . . . . . . . . ..
. .... . .
.... .....
.. ....... .... .
... ..... .
..........
821
c
10
20
30
V GS (Volts)
V DS (Volts)
Figure 5.5: Measured CISS data.
-
84-
Device Modeling
5.1
results, shown in Figure 5.6, were fit to the the model of equation (5.1). Fitting parameters
are presented in Table 5.3.
Co
V3
M
267 pF
0.365 Volts
0.421
Table 5.3: Parameters to fit equation (5.1) to measured the Coss data.
-4--
Measurement
Model
2
K
1
0
5
10
25
15
20
Reverse Bias (V)
30
35
40
Figure 5.6: Measured reverse biased junction capacitance of S310 Schottky diode manufactured
by Fairchild. The model of equation (5.1) is also plotted to show the good fit. Model parameters
are: Cj 0 =267 pF, Vj = 0.365 Volts, and M = 0.421.
5.1.3
On Resistance
RDS-ON was measured using the setup shown in the schematic of Figure
5.7. A DC voltage
source was connected to the drain of the device through a 100 ohm sense resistor. When
the device is on, its on resistance forms a voltage divider with the sense resistor. The drainto-source voltage is measured to find the on resistance. Measurement results are presented
in Figure 5.8.
-
85 -
Converter Design
100
Figure 5.7: Schematic of the setup used to measure RDS-ON.
0
1
2
3
4
5
6
7
8
VGS(Volts)
9
10
Figure 5.8: Measured RDS-ON data.
5.1.4
Compensation for Non-Linear Device Capacitance
In the previous section, it was found that the device capacitances are non-linear and their
value varies with voltage. This poses a problem for converter design, as the absolute value of
each of the capacitances must be known for proper converter tuning. The inclusion of these
capacitances causes the converter waveforms to distort. Since these capacitances decrease
as the voltage across them increase, it is expected that the converter voltage waveforms
will get more peaky. Proper tuning for ZVS can be obtained, however, by considering the
total charge transferred on and off of the capacitor. For an ideal linear capacitor, the total
charge is determined from the capacitance and peak voltage:
QT = C - Vk
-
86 -
(5.2)
5.2
Design Example
The overall expression for a nonlinear capacitor is more complicated, but the same relationship is true on an incremental basis. That is, for an incremental increase in voltage, the
capacitance at that voltage determines the incremental increase in charge.
(5.3)
AV
AQT = C(V)
where V is the voltage across the capacitor and Av is the incremental change. As Av
approaches zero, both sides of this equation can be integrated to find the total charge on
the non-linear capacitor:
QT
From the relationship
across the capacitor:
=j
QT = CEFF -Vpk,
C(v)dv
(5.4)
the effective capacitance is found for a peak voltage
1
f vk
C(v)dv
CEFF(Vpk) =~k
Vpk
(5.5)
0
The model for junction capacitance of equation (5.1) is substituted into the above integral,
yielding a closed-form expression for the effective capacitance presented to the converter
circuit.
Cj,EFF(Vpk) =
C
Vj
[ (-I1+
(1 - M) Vpk [(
pk
(5.6)
Vi
Figure 5.9 shows this relation graphically for the LDMOS transistor capacitance Coss, and
for the diodes reverse biased junction capacitance.
5.2
Design Example
The available design space that meets the specifications of Table 5.1 is quite large. The
design methodology of Chapter 3 resulted in two free variables available to the designer
for each switching frequency. To make intelligent design choices it is necessary to estimate
loss in the circuit. For converters of this type in the low power range, the active devices
dominate the loss budget. Thus, the particular value of the device parasitics plays a dominant role in which design is chosen. In this section, it is assumed that the main switching
device is an LDMOS transistor fabricated from an integrated power process. The device
layout optimization procedure of Chapter 4 produces an optimal device for a particular
-
87 -
.
..............
.......
Converter Design
LDMOS Device
S310 Diode
300
-- -
Device Capacitance
Effective Capacitance
Device Capacitance
- - - Effective Capacitanc
250
.............
'0
20
40
60
"0
C.(Volts)
20
40
60
C. (Volts)
80
100
Figure 5.9: Plots showing equation (5.6) graphically with the fitting parameters for the LDMOS
capacitance Coss and for the diode's junction capacitance.
converter design. Since we are not constrained to a single device layout, for each design
point considered the optimal device layout is found, and then the circuit losses calculated.
This allows the designer to find the best combination of device and circuit design to meet
the target specifications.
While the transistor is custom designed, the diode is not. It is chosen to use the S310 silicon
Schottky diode whose parasitic capacitance of this diode limits the value of CR. Since this
capacitor is a nonlinear capacitor, the peak voltage across it determines its effective value.
From Figure 2.17 it is found that the diode will see a peak reverse voltage of around 50
Volts. From Figure 5.9 it is found that for this peak voltage the diode has an effective
capacitance of around 55 pF.
5.2.1
Select w,
Figure 5.10 presents the results of using the combined design methodology and device
optimization procedure to predict converter efficiency and device size (for each design point)
as a function of switching frequency and rectifier current phase, #1 (see Chapter 3 for a
detailed description). From this figure it is chosen to operate the converter at 75 MHz to
achieve an efficiency in 85-90% range, and to operate slightly below the FM radio band.
-
88 -
..
....
...
.I - -
%. _ _
_ _- . .
. ...........
................. ..
5.2
--
0.95 -
Design Example
---
-
0.9
.3 0.85
LU
0.8
0.75
40
50
60
100
90
80
70
Switching Frequency (MHz)
6
-
120
110
130
8 10
(p1- 0.6
E
CU
. .. ... . .
2-
-..
-e-
e=-0.8
- 5
P = 1.2
. ..... .
5; 2.
0
50
40
60
100
90
80
70
Switching Frequency (MHz)
110
120
130
Figure 5.10: Output from the combined design methodology and device optimization procedure
for a converter with an input voltage of 12 Volts, an output voltage of 30 Volts, and an output power
of 7 Watts. The MATLAB script used to generate this figure is included in Appendix D.1
5.2.2
Select
#1
With the switching frequency chosen, the remaining task is to choose the free variables:
#1,the phase of the rectifier's current, and w0, the resonant frequency of the inverter. The
design procedure is reconfigured to present more of the available design space at the selected
switching frequency, as shown graphically in Figures 5.11, 5.12, and 5.13. The MATLAB
script used to generate these figures is included in Appendix D.2.
First and foremost, the diode's parasitic capacitance must be respected. This is shown in
Figure 5.12, where it is observed that the rectifier must operate with a phase of less than
about -0.9 radians. Figures 5.11 and 5.12 show that choosing #1 more negative has the
benefit of requiring smaller values of both LF and LR. On the flip side, Figure 5.13 shows
that efficiency suffers and Figure 5.14 shows that the slope of Vc(t) at turn-on switching
instant increases as #1 is chosen more negative. Thus, it is desirable to not outphase #1
more than is necessary. Thus, it is chosen to operate the converter with #1 = -1 radian.
-
89 -
Converter Design
.........
-..
- .....
2000
1500
....
-..
1000
-
-1.2
...
-..
..... .. ...
..... .. ..
.
. . .
-1
-0.8
-0.6
-0.4
Rectifier Current Phase, e (rad)
-1
-0.8
-0.6
-0.4
Rectifier Current Phase, e, (rad)
Figure 5.11: Plots generated from the design methodology to show the inverter's passive component
sizes as a function of the rectifier's current phase, #1 and the resonant frequency of the inverter.
Solution is for a converter with an input voltage of 12 Volts, an output voltage of 30 Volts, an output
power of 7 Watts, and a switching frequency of 75 MHz.
--- -- - - - - - - - - . .. . . . . . .. . . . . . .. . .
..... ......
............
.. . . . . . . .. ..
-
. . . .. . .
... -
..
. . . .
--
o/w =0.4
--
w /w =0.6
00
.. . . . . . .. . . .
80
..
.. . . . . . . .. .
O
S
w/w=0.8
-E-
-
/W=0.95
............
.Minimum C
..................... ............
........... .......
Unavailable Deisgn Space
-1.2
0
-1.2
-1
-0.8
-0.6
-0.4
Rectifier Current Phase, (p1 (rad)
-1
-0.8
-0.6
-0.4
Rectifier Current Phase, p (rad)
Figure 5.12: Plots generated from the design methodology to show the rectifier's passive component
sizes as a function of the rectifier's current phase, #1 and the resonant frequency of the inverter.
Solution is for a converter with an input voltage of 12 Volts, an output voltage of 30 Volts, an
output power of 7 Watts, and a switching frequency of 75 MHz. Due to the diode's parasitic
junction capacitance, the design space is limited as shown by the grey area.
-
90 -
............................
Design Example
5.2
0.9 F... ...
-
4
0.88k ...-..-
---
3.
o /w
=0.4
w/ws=0.6
W =0.8
-+-
w
s=0.95
0Os-
2.5
>
0.
-
1.2
8
-0.4
-0.6
-0.8
-1
Rectifier Current Phase, <p,(rad)
2
0.5 L
-1.2
-0.4
-0.6
-0.8
-1
Rectifier Current Phase, p,(rad)
Figure 5.13: Plots generated from the combined design methodology and device optimization to
show the converter's predicted efficiency and the optimal device size (for each design point). Solution
is for a converter with an input voltage of 12 Volts, an output voltage of 30 Volts, an output power
of 7 Watts, and a switching frequency of 75 MHz.
-15'-
-1.2
-1.1
-1
-0.7
-0.6
-0.9
-0.8
Rectifier Current Phase, <p (rad)
-0.5
-0.4
Figure 5.14: Plot showing the slope of VC(t) as a function of the rectifier's current phase, #1and
the resonant frequency of the inverter for a converter with an input voltage of 12 Volts, an output
voltage of 30 Volts, an output power of 7 Watts, and a switching frequency of 75 MHz.
-
91 -
Converter Design
5.2.3
Select w,
The only remaining task it determine the resonant frequency of the inverter. The design
methodology is again reconfigured with the selected switching frequency and rectifier phase
to show the remaining design space, presented in Figures 5.15, 5.16, and 5.17. The MATLAB
script used to generate these figures is included in Appendix D.3
In Chapter 2 it was established that decreasing the size of LF increases the converter's
transient response. Since increasing we has the effect of reducing LF, it is expected that
the transient response will speed up as well. The trade-off is more complicated than this,
however. Increasing w incites additional circulating currents which leads to additional loss.
This phenomena is shown as degraded efficiency in Figure 5.17. The decrease in efficiency
is not drastic because the value of LF is also decreasing (given a constant Q the parasitic
series resistance decreases) and because the design procedure chooses a larger device.
Additionally, with IR(t) and Vc(t) described mathematically, the peak energy stored in the
inverter can be calculated for each design point, shown in Figure 5.18. While the amount
of energy stored in the circuit is not an exact representation of transient response, certainly
the circuit will be its fastest where the amount of energy stored is greatly reduced. For this
reason, it is chosen to operate the converter with wo=0.85ws.
-
92 -
..
..
..
..
....
..
...........
5.2
Design Example
300
o
W0 w
s
Figure 5.15: Plots generated from the design methodology to show the inverter's passive component
sizes as a function of the resonant frequency of the inverter. Solution is for a converter with an input
voltage of 12 Volts, an output voltage of 30 Volts, an output power of 7 Watts, a switching frequency
of 75 MHz, and the rectifier's current phase of 01=-1 radian.
W0
O s
s
Figure 5.16: Plots generated from the design methodology to show the rectifier's passive component
sizes as a function of the resonant frequency of the inverter. Solution is for a converter with an input
voltage of 12 Volts, an output voltage of 30 Volts, an output power of 7 Watts, a switching frequency
of 75 MHz, and the rectifier's current phase of #1=-1 radian.
-
93 -
...
. ......
....
......
.....................
Converter Design
o
..................
..
0.87 ..... .............
0.865
.......... ...............
0.86 .--
---
-
......-
2.4
-.--
2.2.
0.855..........
0.85
0.4
2.6.......
2
0.6
0.8
W
1
Ws
1.8
0.4
0.6
0.8
1
O s
Figure 5.17: Plots generated from the combined design methodology and device optimization to
show the converter's predicted efficiency and the optimal device size (for each design point). Solution
is for a converter with an input voltage of 12 Volts, an output voltage of 30 Volts, an output power
of 7 Watts, a switching frequency of 75 MHz, and the rectifier's current phase of 01=-1 radian.
5.2.4
Simulation Results
To verify the design solution the converter is simulated in SPICE with an input voltage of
12 Volts, an output voltage of 30 Volts, a switching frequency of 75 MHz, and using the
component values shown in Table 5.4. The SPICE deck for this simulation is included in
Appendix A.2.1. From the simulation results, shown in Figure 5.19, the error produced
by the design methodology (e.g. owing to the sinusoidal current approximation) is readily
apparent. This error is easily corrected, however. First, both inductors are adjusted to
a standard value of 82 nH, and the rectifier capacitor CR is set to 55 pF such that no
additional capacitance is required beyond the diode's junction capacitance. From Figure
5.19, it is observed that Vc(t) crosses zero too soon; thus, CE is increased to 88 pF by
added additional (external) capacitance to achieve zero-voltage-switching.
Additionally, a higher fidelity simulation is performed that includes non-linear device capacitances and expected parasitic inductances and resistances. The results of this simulation
are shown in Figure 5.20 and confirm the design. SPICE code detailing this simulation is
shown in Appendix A.2.2.
-
94 -
.
5.3
. ...................................
Experimental Results
1.5
N
1.4
U 1.2
1.1-
0O.9
~0.8
0.4
0.5
0.7
0.6
0.8
0.9
1
o/o
os
Figure 5.18: Plot showing the peak energy stored in the inverter in a cycle normalized to the
energy delivered to the load in a cycle as a function of the resonant frequency of the inverter for
a converter with an input voltage of 12 Volts, an output voltage of 30 Volts, an output power of 7
Watts, and a switching frequency of 75 MHz, and the rectifier's current phase of <p=-1 radian.
5.3
Experimental Results
To evaluate this converter topology and design approach, a prototype power stage was
constructed. Aiming to validate the design methodology, the prototype was constructed
using the component values from the design example of the previous section.
A schematic of the experimental prototype is shown in Figure 5.21, and a photograph of the
converter is shown in Figure 5.22. Schematic and PCB layout files are shown in Appendix E.
The rectifier capacitor CR is entirely composed by the diode parasitic junction capacitance.
This allows parasitic inductance in the rectifier to be absorbed into LR, leading to more
optimal performance of the rectifier. The capacitor is made up of the parallel combination
of the transistor output capacitance (40 pF) and a discrete capacitance of 51.7pF (47 pF
capacitor in parallel with a 4.7 pF capacitor).
Figure 5.23 shows measured converter waveforms and a comparison to simulated SPICE
waveforms. The close agreement of the waveforms validates the operation of the prototype.
-
95 -
Converter Design
LF
Methodology
Corrected
80.3 nH
82 nH
CE
77.4 pF
88 pF
LR
83.5 nH
82 nH
CR
62.6 pF
55 pF
Table 5.4: Component values as predicted by the design methodology for a converter with an input
voltage of 12 Volts, an output voltage of 30 Volts, an output power of 7 Watts, and a switching
frequency of 75 MHz, the rectifier's current phase of 1=-1 radian, and the inverter's resonant
frequency set to 85% of the switching frequency. The table also show component values that result
from correcting the error in the design methodology (due to the sinusoidal current approximation)
in SPICE.
Additionally, measured converter waveforms over the input voltage range of 8-18 Volts,
presented in Figure 5.24, show good operation over a wide voltage range.
Efficiency over the input voltage range for two specified output power levels is presented in
Figure 5.25. Based on these results, it is concluded that the proposed converter topology
and design approach lead to good performance at very high frequencies.
-
96
Experimental Results
5.3
. U
- ... ...... -..
0
10
0
5
15
Time (ns)
10
20
25
Figure 5.19: Simulation results for a converter with an input voltage of 12 Volts, an output
voltage of 30 Volts, an output power of 7 Watts, and a switching frequency of 75 MHz, the rectifier's
current phase of #1=- radian, and the inverter's resonant frequency set to 85% of the switching
frequency. The figure shows the simulation result with the component values predicted by the design
methodology and with corrected component values (shown in Table 5.4)
-
97
-
Converter Design
Time (ns)
7'
- .. ..4 . . . . . . ..
A
.. . .. .. .
44%
V
If. .. .. . . . .. . . . . . . .
.. . .
4f
.. . .. .
,/
.. .4 ... .
4%
. . . .. . . . . . . .
Time (ns)
Figure 5.20: Simulation results of a converter with an input voltage of 12 Volts, an output voltage
of 30 Volts, an output power of 7 Watts, and a switching frequency of 75 MHz and a duty ratio of
50%, the rectifier's current phase of #1=-1 radian, and the inverter's resonant frequency set to 85%
of the switching frequency. Simulation uses more exact models for each of the circuit components in
preparation for building a prototype. Appendex A.2.2 contains SPICE code detailing this simulation.
VOUT
Figure 5.21: Schematic of the experimental implementation. The inductors are from the midispring family from Coilcraft, and the diode is an S310 Schottky diode from Comchip Technology. The
MOSFET is a custom LDMOS device fabricated from an integrated power process. The converter
operates at 75 MHz with a 50% duty cycle. The device characteristics of S1 are shown in Figures
5.4, 5.5, and 5.8
-
98 -
5.3
Experimental Results
Figure 5.22: Photograph of the converter PCB.
Drain Voltage
-
Measured
- - - SPICE
0
5
10
Time (ns)
Rectifier Voltage
0
5
10
Time (ns)
20
15
15
20
Figure 5.23: Measured converter waveforms compared to simulated waveforms in SPICE.
-
99 -
.......
...
Converter Design
Measured Drain Voltage
G)
0
5
10
0
5
10
15
20
Time (ns)
Measured Rectifier Voltage
25
30
o0-
15
Time (ns)
20
25
Figure 5.24: Measured converter waveforms over the input voltage range.
87.5
87
.
-..
. .
.
- -
-
86.5
86
. -..
..
~~
.~
.
- - - - --- - ---
-- - -- - -
85.5
84.5 F -
-1111- 5W
"
84
9
10
11
12
13
14
15
Input Voltage (Volts)
2.5W
16
17
Figure 5.25: Measured efficiency (not including gate drive loss) versus input voltage for two
specified output power levels. Output power is controlled by on-off modulating the converter with
a PWM signal at 1 MHz.
-
100 -
Chapter 6
Conclusion
This thesis presents a resonant boost converter topology that is suitable for operating at
switching frequencies in the VHF range. The proposed topology circumvents the frequencydependent losses of traditional power converters by operating with class-e waveforms to
reduce switching loss, and using air-core inductors to avoid core loss in magnetic materials.
While the proposed toplogy is similar to previous converters, different component selections
and different control methods differentiate this work.
A new design methodology is developed that is based on direct analysis of the topology.
This procedure does not rely on lengthy time-domain simulations across circuit parameters
to identify desirable design points, and readily yields the necessary component values.
Semiconductor devices account for a dominant portion of the loss in the a VHF power converter circuit. A method of optimizing the design of transistors to be used in VHF converter
circuits is presented. This procedure is combined with the new design methodology enabling
the designer to rapidly find the optimal combination of converter and device design.
The proposed topology, design methodology, and device optimization are verified through
the construction of an experimental prototype of the converter circuit. Measured waveforms from the prototype are in close agreement to simulated waveforms, and the converter
achieves good efficiency over a wide input voltage range. It may be concluded that the
proposed converter topology and design methods yield effective converter designs at VHF
frequencies.
-
101 -
Appendix A
SPICE Code
A.1
Chapter 2
A.1.1
SPICE Code to Generate Figure 2.2
Ideal Class E Inverter Simulation
.PARAM F=10OMeg
.PARAM numCycles=1000
.PARAM numCyclesDisp=2
.PARAM Vin = 12
.PARAM zf=18
.PARAM fc=0.84
.PARAM wf=fc*2*pi*F
.PARAM Lf = zf/wf
.PARAM Cf = 1/(zf*wf)
.PARAM D=0.5
.PARAM Rl = 5
Vin Nin 0 {Vin}
Lin Nin Nd 10u
S1 Nd 0 Ng 0 idealSwitch
V1 Ng 0 PULSE(i -1 {0.001/F} {0.001/F} {O.001/F} {D/F} {1/F})
.model idealSwitch SW(Ron=0.001 Roff=100k Vt=0)
Ce Nd 0 67.7p
Lf Nd Nr {Lr}
Cf Nr Nout {Cr}
-
103
-
SPICE Code
RL Nout 0 {R1}
.TRAN 1p {(numCycles)/F} {(numCycles-numCyclesDisp)/F} UIC
.PROBE
.END
A.1.2
SPICE Code to Generate Figure 2.7
.PARAM F=100e6
.PARAM numCycles=1000
.PARAM numCyclesDisp=3
.PARAM Vin = 5
.PARAM Pout= 1
.PARAM pone=atan(-2/pi)
.PARAM p=atan(pi/2-4/pi)
.PARAM R1 = 2*(sin(pone)**2)*(Vin**2)/Pout
.PARAM Ce = Pout/(Vin*Vin*2*pi*pi*F)
.PARAM wrf = 0.9
.PARAM wrfi = 1 / wrf
.PARAM wr = wrf*2*pi*F
.PARAM Leq = tan(p-pone)*R1/(2*pi*F)
.PARAM zr = 2*pi*F*Leq*(wrfi/(wrfi*wrfi-1))
.PARAM Lr = zr/wr
.PARAM Cr = 1/(zr*wr)
.PARAM D=0.5
.PARAM Rfactor = 1
.PARAM iac=Pout/(-sin(pone)*Vin)
Itest Nt 0 SINE(0 {iac} {F} 0 0 {pone*180/pi})
-
104 -
A.1
Rt Nt 0 100
Vin Nin 0 {Vin}
Lin Nin Nd lu
S1 Nd 0 Ng 0 idealSwitch
{0.001/F} {0.001/F} {0.001/F} {D/F} {1/F})
V1 Ng 0 PULSE(-1
.model idealSwitch SW(Ron=0.001 Roff=100k Vt=0)
Ce Nd 0 {Ce}
Lr Nd Nr {Lr}
Cr Nr Nout {Cr}
RL Nout 0 {Rl}
*.STEP param numCycles list 100 1000 10000
*.STEP param wrf list 0.9 0.95 0.975
.TRAN ip {(numCycles)/F} {(numCycles-numCyclesDisp)/F} UIC
.PROBE
.END
A.1.3
SPICE Code to Generate Figure 2.8
.PARAM F=100Meg
.PARAM numCycles=1000
.PARAM numCyclesDisp=2
.PARAM Vin = 12
.PARAM zf=18
.PARAM fc=0.84
. PARAM wr=fc*2*pi*F
.PARAM Lr = zr/wr
.PARAM Cr = 1/(zr*wr)
.PARAM D=0.5
.PARAM R1 = 5
.PARAM Rfactor = 1
105
Chapter 2
SPICE Code
Vin Nin 0 {Vin}
Lin Nin Nd 10u
Si Nd 0 Ng 0 idealSwitch
V1 Ng 0 PULSE(1 -1 {0.001/F} {0.001/F} {0.001/F} {D/F} {1/F})
.model idealSwitch SW(Ron=0.001 Roff=100k Vt=O)
Ce Nd 0 67.7p
Lr Nd Nr {Lr}
Cr Nr Nout {Cr}
RL Nout 0 {Rl*Rfactor}
.STEP param Rfactor list 1 1.25 1.5 1.75 2
.TRAN ip {(numCycles)/F} {(numCycles-numCyclesDisp)/F} UIC
.PROBE
.END
A.1.4
SPICE Code to Generate Figure 2.11
.PARAM F=100e6
.PARAM numCycles=10
.PARAM numCyclesDisp=5
.PARAM Vs=10
.PARAM Idc=1
.PARAM Lpar=3n
.PARAM Cpar=30p
Vin Ns 0 SINE(0 {Vs} {F})
C1 Ns Nti
{Cpar}
R1 Nti Ndi 1
D1 Ns Nd1 idealDIODE
.model idealDIODE D(N=.0001)
Li Ndi Nout {Lpar} Rser=0.2
-
106 -
A.1
L2
D2
C2
R2
Nout Nd2 {Lpar} Rser=0.2
0 Nd2 idealDIODE
Nout Nt2 {Cpar}
Nt2 0 1
Idc Nout 0 {Idc}
Vin2 Ns2 0 SINE(W {Vs} {F})
D12 Ns2 Nout2 idealDIODE
D22 0 Nout2 idealDIODE
Idc2 Nout2 0 {Idc}
*.STEP param D list 0 .1 .2 .3
.TRAN 1p {(numCycles)/F} {(numCycles-numCyclesDisp)/F}
.PROBE
.END
A.1.5
SPICE Code to Generate Figure 2.14
UIC
.PARAM F=100e6
.PARAM numCycles=10
.PARAM numCyclesDisp=5
.PARAM Vs=5
.PARAM Vout=10
.param fc=.975
. PARAM wr=2*pi*fc*F
.PARAM zr=50
.PARAM Lpar=3n
.PARAM Cpar=30p
.PARAM Lr = zr/wr ;82n
.PARAM Cr = 1/(zr*wr) ;32 p
Vin Ns 0 SINE(O {Vs} {F})
Lr Ns Nd {Lr}
Cr Nd 0 {Cr-Cpar}
Li Nd Ndl {Lpar} Rser=0.2
-
107 -
Chapter 2
SPICE Code
C1 Ndl
R1 Ntl
D1 Ndl
.model
Ntl {Cpar}
Nout 1
Nout idealDIODE
idealDIODE D(N=.0001)
Vout Nout 0 {Vout}
Vin2 Ns2 0 SINE(W {Vs} {F})
Lr2 Ns2 Nd2 {Lr}
Cr2 Nd2 0 {Cr}
D2 Nd2 Nout2 idealDIODE
Vout2 Nout2 0 {Vout}
*.STEP param D list 0 .1 .2 .3
.TRAN 1p {(numCycles)/F} {(numCycles-numCyclesDisp)/F}
.PROBE
.END
A.1.6
UIC
SPICE Code to Generate Figure 2.17
.PARAM F=100Meg
.PARAM numCycles=10000
.PARAM numCyclesDisp=2
.PARAM Vin = 12
.PARAM Vout = 30
.PARAM zf=18
.PARAM fc=0.975
.PARAM wf=fc*2*pi*F
.PARAM Lf = zf/wf
.PARAM Cf = 1/(zf*wf)
.PARAM D=0.5
.PARAM R1=55
.PARAM Rfactor=1
Vin Nin 0 {Vin}
Lin Nin Nd 10u
S1 Nd 0 Ng 0 idealSwitch
V1 Ng 0 PULSE(i -1 {0.001/F} {0.001/F} {0.001/F} {D/F} {1/F})
-
108
A.1
.model idealSwitch SW(Ron=0.001 Roff=100k Vt=0)
Ce Nd 0 88p
Lf Nd Nr {Lf}
Cf Nr 0 {Cf}
Di Nr Nout idealDIODE
.model idealDIODE D(N=.0001)
Rload Nout 0 {Rl*Rfactor}
Cfilt Nout 0 .Au
*Vout Nout 0 30
.STEP param Rfactor list 1 0.75 0.5
.TRAN 1p {(numCycles)/F} {(numCycles-numCyclesDisp)/F} UIC
.PROBE
.END
A.1.7
SPICE Code to Generate Figure 2.21
.PARAM F=100Meg
.PARAM numCycles=100
.PARAM numCyclesDisp=3
.PARAM Vin = 12
.PARAM Vout = 30
.PARAM zr=18
.PARAM fc=0.975
.PARAM wr=fc*2*pi*F
.PARAM Lr = zr/wr
.PARAM Cr = 1/(zr*wr)
.PARAM D=0.5
.PARAM Ce= 88p
.PARAM Lf=40n
.PARAM Ceq=(1+(Ce*Lf*(2*pi*F)**2))/(Lf*(2*pi*F)**2)
Vin Nin 0 {Vin}
Lin Nin Nd {Lf}
-
109
-
Chapter 2
SPICE Code
Si Nd 0 Ng 0 idealSwitch
V1 Ng 0 PULSE(1 -1 {0.001/F} {0.001/F} {0.001/F} {D/F} {1/F})
.model idealSwitch SW(Ron=0.001 Roff=100k Vt=0)
Ce Nd 0
{Ceq}; 128p
Lr Nd Nr {Lr}
Cr Nr 0 {Cr}
D1 Nr Nout idealDIODE
.model idealDIODE D(N=.0001)
Vout Nout 0 {Vout}
*.STEP param Ce list 88p 128p
.TRAN 1p {(numCycles)/F} {(numCycles-numCyclesDisp)/F} UIC
.PROBE
.END
A.2
A.2.1
Chapter 5
SPICE Code to Generate Figure 5.19
.PARAM F=75Meg
.PARAM numCycles=300
.PARAM numCyclesDisp=2
.PARAM Vin = 12
.PARAM Vout = 30
.PARAM D=0.5
VI Ng 0 PULSE(i -1 {0.001/F} {0.O01/F} {0.001/F} {D/F} {1/F})
.model idealSwitch SW(Ron=0.001 Roff=100k Vt=O)
Vin Nin 0 {Vin}
Lin Nin Nd 82n
-
110
-
A.2
Si Nd 0 Ng 0 idealSwitch
Ce Nd 0 88p
Lr Nd Nr 82n
Cr Nr 0 55p
D1 Nr Nout idealDIODE
.model idealDIODE D(N=.0001)
Vout Nout 0 30
Vin2 Nin2 0 {Vin}
Lin2 Nin2 Nd2 79.65n
S12 Nd2 0 Ng 0 idealSwitch
Ce2 Nd2 0
78.25p
Lr2 Nd2 Nr2 82.72n
Cr2 Nr2 0 63.2p
D12 Nr2 Nout2 idealDIODE
Vout2 Nout2 0 30
*.STEP param Rfactor list 1 0.75 0.5
.TRAN ip {(numCycles)/F} {(numCycles-numCyclesDisp)/F} UIC
.PROBE
.END
A.2.2
SPICE Code to Generate Figure 5.20
.OPTIONS
+ NOPAGE
+ NOBIAS
+ NOECHO
+ NOMOD
+ NUMDGT=8
.WIDTH OUT=132 ;TO PRINT MORE COLUMNS
111 -
Chapter 5
SPICE Code
****
OPTIONS FOR BETTER CONVERGENCE
.OPTIONS ABSTOL=1nA
+ GMIN=1p
+ ITL1=6000
+ ITL2=4000
+ ITL4=5000
+ RELTOL=0.001
+ VNTOL=0.001mV
.OPTION STEPGMIN
.PARAM Vdc=12
.PARAM F=75e6
.PARAM Vout = 32
.PARAM numCycles=200
.PARAM numCyclesDisp=2
.PARAM Lpar =
.in
.PARAM INDQ = 100
**
Input Voltage
Vin Ndcin-s 0 {Vdc}
**
Measure Input Power
XPWRIN Ndcin-s Ndcin apwrin ipwrin APWR
+ len = 10/{F}
* Input Inductor
XLin Ndcin Ndrain APWRLin IND
+ PARAMS:
+ F = 100e6
+ Q =
+
{INDQ}
L = 82n
**Gate Drive
Vg Ng 0 PULSE(5 0 {O.95/F} {O.05/F} {0.05/F} {0.5/(F)} {1/F})
X1 Ng 0 Ndrain APWRRDS APWRROSS GATEIN LDMOSNL
+Lp = 0.5n
+RISS=1.3
+CISS=95pF
+ROSS=1.3
+Cjo=121.01p
-
112 -
A.2
+M=O.4123
+Vj=1.2701
+Mult={1.7}
Cextra Ndrain 0 53p
** Rectifier Resonant Circuit
XLr Ndrain Nac-out APWRLr IND
+ PARAMS:
+ F = 110e6
+ Q = {INDQ}
+ L = 82n
Cr Nac-out 0 3p ic={Vdc}
* Rectifier Diode
XDREC Nac-out Ndc-out APWRDREC DIODENL
+ PARAMS:
+ LDS=3n
+ VDON=0.55
+ RDS=0.3
+ CJO=261.77p
+ VJ=0.36521
+ M=0.42044
+ RC=0.24
+ FS=110e6
** Measure Output Power
XPWROUT Ndc-out Ndc-out-s apwr-out ipwr-out APWR
+ len = 10/{F}
** Output Voltage
Vout Ndc-out-s 0 {Vout}
** Calcualte Average Efficiency
Eff eff 0 VALUE = {V(apwr-out)/(V(apwr-in))}
* Stimulus
.TRAN ips {(numCycles)/F} {(numCycles-numCyclesDisp)/F} UIC
.PROBE
.END
* Measure Power
.subckt APWR mpos mneg apwr ipwr
-
113 -
Chapter 5
SPICE Code
.PARAM len = 133.333n
* Measure Input Power
* Instantaneous
VSENSE mpos mneg 0
EPOWERIN ipwr 0 VALUE = {V(mpos)*I(VSENSE)}
* Average Power
GINT1 0 apwr-int VALUE={V(ipwr)-absdelay(V(ipwr),len)}
CINT1 apwr-int 0 1 IC=0
RINT1 apwr-int 0 iMEG
EAVE1 apwr 0 VALUE={V(apwr-int)/len}
.ends APWR
* MOSFET MODEL
.subckt LDMOSNL GATE SOURCE DRAIN APWRRDS APWRROSS GATEIN
.PARAM Lp=ln
* PARASITIC INDUCTORS
LGATE GATEL GATE {Lp}
LSOURCE SOURCEL SOURCE {Lp}
LDRAIN DRAINL DRAIN {Lp}
* GATE CIRCUIT
RISS GATEL GATEIN {RISS}
CISS GATEIN SOURCE {CISS}
.PARAM:
+CJCGD=41.45p
+VJCGD=5.9675
+MCGD=1.8856
*NONLINEAR CAPACITANCE EVALUATED AS A CONTROLLED CURRENT SOURCE
*GCN DRAINL GATEL VALUE={IF( (V(GATEL)-V(DRAINL)) <0,
+CJCGD*V(201), V(201)*( CJCGD / ( (1+ (V(GATEL)-V(DRAINL)) /VJ-CGD)
Cgd DRAINL GATEL {Cgd}
****CIRCUIT TO EVALUATE THE DERIVATIVE*****
*.PARAM:
*+
LDER=O.Oln
*+
PI=3.1416
*+ FS=75e6
*.FUNC RDER(LDER,FS) {1000*2*PI*FS*LDER}
*G7 0 201 VALUE={(V(GATEL)-V(DRAINL))/LDER}
*L1 201 0 {LDER}
*R1 201 0 {RDER(LDER,FS)}
-
114
**MCGD)))}
A. 2
RDS ON
PARAM:
+VGS1=0. 6
+RDS1=500100
+VGS2=0.7
+RDS2=45354.5673
+VGS3=0.8
+RDS3=2974.387
+VGS4=0.9
+RDS4=2161.7542
+VGS5=1
+RDS5=192.3807
+VGS6=1.1
+RDS6=208.9431
+VGS7=1.2
+RDS7=3.3575
+VGS8=1.3
+RDS8=2.0571
+VGS9=1.4
+RDS9=3.0877
+VGS10=1.5
+RDS10=1.3691
+VGS11=1.6
+RDS11=1.9603
+VGS12=1.7
+RDS12=1.1503
+VGS13=1.8
+RDS13=1.5713
+VGS14=1.9
+RDS14=1.0909
+VGS15=2
+RDS15=1.3502
+VGS16=2.5
+RDS16=0.7999
+VGS17=3
+RDS17=0.98671
+VGS18=3.5
+RDS18=0.67681
+VGS19=4
+RDS19=0.87328
+VGS20=4.5
+RDS20=0.67681
+VGS21=5
+RDS21=0.77438
+VGS22=5.5
+RDS22=0.60939
+VGS23=6
- 115-
Chapter 5
SPICE Code
+RDS23=0.77438
+VGS24=6.5
+RDS24=0.60939
+VGS25=7
+RDS25=0.67785
+VGS26=8
+RDS26=0.60939
+VGS27=10
+RDS27=0.59394
Si DRAINL SOURCEL GATEIN SOURCE SiMOD
.MODEL SiMOD VSWITCH(RON={RDS1*Mult} ROFF=1MEG VON={VGS1} VOFF={O})
S2 DRAINL SOURCEL GATEIN SOURCE S2MOD
.MODEL S2MOD VSWITCH(RON={RDS2*Mult} ROFF=iMEG VON={VGS2} VOFF={O})
S3 DRAINL SOURCEL GATEIN SOURCE S3MOD
.MODEL S3MOD VSWITCH(RON={RDS3*Mult} ROFF=1MEG VON={VGS3} VOFF={0})
S4 DRAINL SOURCEL GATEIN SOURCE S4MOD
.MODEL S4MOD VSWITCH(RON={RDS4*Mult} ROFF=1MEG VON={VGS4} VOFF={O})
S5 DRAINL SOURCEL GATEIN SOURCE S5MOD
.MODEL S5MOD VSWITCH(RON={RDS5*Mult} ROFF=1MEG VON={VGS5} VOFF={0})
S6 DRAINL SOURCEL GATEIN SOURCE S6MOD
.MODEL S6MOD VSWITCH(RON={RDS6*Mult} ROFF=1MEG VON={VGS6} VOFF={O})
S7 DRAINL SOURCEL GATEIN SOURCE S7MOD
.MODEL S7MOD VSWITCH(RON={RDS7*Mult} ROFF=IMEG VON={VGS7} VOFF={O})
S8 DRAINL SOURCEL GATEIN SOURCE S8MOD
.MODEL S8MOD VSWITCH(RON={RDS8*Mult} ROFF=1MEG VON={VGS8} VOFF={O})
S9 DRAINL SOURCEL GATEIN SOURCE S9MOD
.MODEL S9MOD VSWITCH(RON={RDS9*Mult} ROFF=iMEG VON={VGS9} VOFF={O})
S10 DRAINL SOURCEL GATEIN SOURCE S10MOD
.MODEL S10MOD VSWITCH(RON={RDS10*Mult} ROFF=1MEG VON={VGS10} VOFF={0})
Sl DRAINL SOURCEL GATEIN SOURCE S11MOD
.MODEL S11MOD VSWITCH(RON={RDS11*Mult} ROFF=iMEG VON={VGS11} VOFF={O})
S12 DRAINL SOURCEL GATEIN SOURCE S12MOD
.MODEL S12MOD VSWITCH(RON={RDS12*Mult} ROFF=1MEG VON={VGS12} VOFF={0})
S13 DRAINL SOURCEL GATEIN SOURCE S13MOD
.MODEL S13MOD VSWITCH(RON={RDS13*Mult} ROFF=1MEG VON={VGS13} VOFF={0})
S14 DRAINL SOURCEL GATEIN SOURCE Si4MOD
.MODEL S14MOD VSWITCH(RON={RDS14*Mult} ROFF=1MEG VON={VGS14} VOFF={O})
S15 DRAINL SOURCEL GATE-IN SOURCE S15MOD
.MODEL S15MOD VSWITCH(RON={RDS15*Mult} ROFF=1MEG VON={VGS15} VOFF={O})
S16 DRAINL SOURCEL GATEIN SOURCE S16MOD
.MODEL S16MOD VSWITCH(RON={RDS16*Mult} ROFF=iMEG VON={VGS16} VOFF={0})
S17 DRAINL SOURCEL GATEIN SOURCE S17MOD
.MODEL S17MOD VSWITCH(RON={RDS17*Mult} ROFF=1MEG VON={VGS17} VOFF={O})
S18 DRAINL SOURCEL GATEIN SOURCE S18MOD
.MODEL S18MOD VSWITCH(RON={RDS18*Mult} ROFF=1MEG VON={VGS18} VOFF={0})
S19 DRAINL SOURCEL GATEIN SOURCE S19MOD
.MODEL S19MOD VSWITCH(RON={RDS19*Mult} ROFF=1MEG VON={VGS19} VOFF={0})
S20 DRAINL SOURCEL GATEIN SOURCE S20MOD
.MODEL S20MOD VSWITCH(RON={RDS20*Mult} ROFF=1MEG VON={VGS20} VOFF={O})
116
A.2
S21 DRAINL SOURCEL GATEIN SOURCE S21MOD
.MODEL S21MOD VSWITCH(RON={RDS21*Mult} ROFF=1MEG
S22 DRAINL SOURCEL GATEIN SOURCE S22MOD
.MODEL S22MOD VSWITCH(RON={RDS22*Mult} ROFF=1MEG
S23 DRAINL SOURCEL GATEIN SOURCE S23MOD
.MODEL S23MOD VSWITCH(RON={RDS23*Mult} ROFF=1MEG
S24 DRAINL SOURCEL GATEIN SOURCE S24MOD
.MODEL S24MOD VSWITCH(RON={RDS24*Mult} ROFF=IMEG
S25 DRAINL SOURCEL GATEIN SOURCE S25MOD
.MODEL S25MOD VSWITCH(RON={RDS25*Mult} ROFF=1MEG
S26 DRAINL SOURCEL GATEIN SOURCE S26MOD
.MODEL S26MOD VSWITCH(RON={RDS26*Mult} ROFF=1MEG
S27 DRAINL SOURCEL GATEIN SOURCE S27MOD
.MODEL S27MOD VSWITCH(RON={RDS27*Mult} ROFF=1MEG
VON={VGS21} VOFF={0})
VON={VGS22} VOFF={0})
VON={VGS23} VOFF={0})
VON={VGS24} VOFF={0})
VON={VGS25} VOFF={0})
VON={VGS26} VOFF={0})
VON={VGS27} VOFF={0})
* COSS AND ROSS
DCOSS N2 DRAINL DiodeCOSS
ROSS N2 SOURCEL {ROSS}
.model DiodeCoss D(Is=0 Rs=0 Cjo={Cjo} M={M} Vj={Vj})
*DDS SOURCEL DRAINL DIODE
*.model DIODE D(N=.0001)
*.model DIODE D(N=0.5 RS=0.2 TT=5n)
.ends LDMOSNL
.SUBCKT DIODENL A K APWR
+ PARAMS:
+ LDS=3N
;SERIES INDUCTANCE
+ VDON=0.8 ;DIODE FORWARD DROP
+ RDS=0.12 ;SERIES RESISTANCE
+ CJO=550P
+ VJ=1.80372824438359
+ M=0.44880310087245
+ RC=.05 ;RESIST. IN SERIES WITH NON-LIN CAPACITOR
+ FS=30MEG
+ F=75e6
* Measure Power in RISS
VSENSE A ASENSE 0
EPOWER ipwr 0 VALUE = {(V(A)-V(K))*I(VSENSE)}
GINT 0 apwr_1 VALUE={V(ipwr)-absdelay(V(ipwr),{10/F})}
CINT apwr_1 0 1 IC=0
RINT apwr_1 0 1MEG
EAVE APWR 0 VALUE={V(apwr_1)/{10/F}}
*PARASITIC LEAD INDUCTANCE
-
117 -
Chapter 5
SPICE Code
LDS ASENSE 101 {LDS} IC=0
*IDEAL DIODE MODEL
DIDEAL 101 102 IDEAL
.MODEL IDEAL D(N=0.001)
*FORWARD VOLTAGE DROP MODEL
VDON 102 103 {VDON}
RDS 103 K {RDS}
*NONLINEAR CAPACITANCE EVALUATED AS A CONTROLLED CURRENT
*SOURCE
GCNL K 104 VALUE={IF((V(K)-V(104))<0,CJO*V(201)*
+ (1/LDER),V(201)*(1/LDER)*(CJO/((1+((V(K)-V(104))/VJ))**M)))}
RC 101 104 {RC}
****SUBCIRCUIT TO EVALUATE THE DERIVATIVE***
*PARAMETERS AND DEFINITION FOR THIS SUBCIRCUIT
.PARAM:
+ LDER=1U ;INDUCT FOR THE DERIVATIVE SUBCIRCUIT
+ PI=3.14159265
*FUNC. FOR R OF THE DERIVATIVE SUBCIRCUIT
.FUNC RDER(LDER,FS) {3000*2*PI*FS*LDER}
GY 0 201 VALUE={V(K)-V(104)}
Li 201 0 {LDER}
R1 201 0 {RDER(LDER,FS)}
.ENDS DIODENL ; CSD10060
.SUBCKT CAP POS NEG
.PARAMS:
+ ESL = in
+ ESR = 10m
+ C =
in
Li POS NI {ESL}
Ri NI N2 {ESR}
C1 N2 NEG {C}
.ENDS CAP
.SUBCKT IND POS NEG
.PARAMS:
+ F = 75e6
+ Q = 100
+ L =
in
+ ESR = 2*pi*F*L/Q
Li POS Ni {L}
Ri Ni NEG {ESR}
.ENDS IND
-
118
A.2
-
119 -
Chapter 5
Appendix B
Design Methodology MATLAB Scripts
B.1
MATLAB Code to Generate Figures 3.4 and 3.7
r = O(ws,wo) (ws./wo).^2./((ws./wo).^2-1);
X Capacitor Voltage
Vc = @(Vin,Vout,Pout,ws,wo,zo,ol,kl,t) ((-2*pi*wo/ws)*(Vin/2
+zo*k1*wo*r(ws,wo)*sin(o1)/(pi*ws)+zo*k1*r(ws,wo)*cos(ol)*sin(wo*pi/ws)/(2*pi)...
+ws*sin(wo*pi/ws)*Vin/(2*pi*wo))*sin(wo*t)/(cos(wo*pi/ws)-1)...
-(zo*kl*wo*r(ws,wo)*cos(ol)/(ws)+Vin)*cos(wo*t)...
+zo*kl*wo*r(ws,wo)*cos(ws*t+ol)/ws+Vin)*(t<=pi/ws);
% Capacitor Current
Ic = @(Vin,Vout,Pout,ws,wo,zo,ol,kl,t) ((-2*pi*wo./(ws*zo)).*(Vin/2+...
zo*k1*wo*r(ws,wo)*sin(ol)/(pi*ws)+zo*k1*r(ws,wo)*cos(oi)*sin(wo*pi/ws)/(2*pi)...
+ws*sin(wo*pi/ws)*Vin/(2*pi*wo))*cos(wo*t)/(cos(wo*pi/ws)-1)...
+(1./zo).*(zo*kl*wo*r(ws,wo)*cos(o1)/ws+Vin)*sin(wo*t)...
-kl*r(ws,wo)*sin(ws*t+ol))*(t<=pi/ws);
% Inductor Current
Il
= @(Vin,Vout,Pout,ws,wo,zo,oi,ki,t) ...
(Ic(Vin,Vout,Pout,ws,wo,zo,oi,kl,t) + Pout/Vout + kl*sin(ws*t+ol))*(t<=pi/ws)...
+(Ic(Vin,Vout,Pout,ws,wo,zo,oi,kl,pi/ws)-kl*sin(o1)...
+Pout/Vout+Vin*wo*(t-pi/ws)/zo)*(t>pi/ws);
X Transistor Current
Im = Q(Vin,Vout,Pout,ws,wozo,o1,k1,t)...
(Ic(Vin,Vout,Pout,ws,wo,zo,ol,ki,pi/ws)-kl*sin(oi)+Vin*wo*(t-pi/ws)/zo...
-kl*sin(ws*t+ol))*(t>pi/ws);
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
a = @(Vin,Vout,Pout,ws,wo,oi) Pout/Vin-Pout/Vout;
b = @(Vin,Vout,Pout,ws,wo,o1) (1/pi ...
-wo.*r(ws,wo).*sin(wo*pi./ws).*cos(wo.*pi./ws)./(2*ws.*(cos(wo.*pi/ws)-1))...
+r(ws,wo).*wo.*sin(wo.*pi./ws)/(2.*ws)).*cos(ol)...
+(-1/2 -
(wo./ws).^2.*r(ws,wo).*cos(wo*pi./ws)./(cos(wo*pi./ws)-i)...
-
121 -
Design Methodology MATLAB Scripts
+r(ws,wo)/2).*sin(o1);
c = @(Vin,Vout,Pout,ws,wo,oi) Vin*wo*pi./(4*ws)
-(pi*Vin*wo./(2*ws) + Vin*sin(wo*pi./ws)/2)...
.*(cos(wo*pi./ws)./(cos(wo*pi./ws)-1)) + Vin*sin(wo*pi./ws)/2;
d = @(Vin,Vout,Pout,ws,wo,oi) (-Vin/2 - ws.*Vin.*sin(wo.*pi./ws)./(2*pi.*wo))...
.*(sin(wo.*pi./ws)./(cos(wo.*pi./ws)-1))...
- ws.*Vin.*(cos(wo.*pi./ws)-1)./(2.*pi.*wo);
e = D(Vin,Vout,Pout,ws,wo,ol) (-r(ws,wo).*wo.*sin(ol)./(pi.*ws)...
-r(ws,wo).*cos(o1).*sin(wo.*pi./ws)/(2*pi)).*sin(wo.*pi./ws)./(cos(wo.*pi./ws)-1)...
-r(ws,wo).*cos(ol).*(cos(wo.*pi./ws)-1)/(2*pi)-r(ws,wo).*cos(o1)/pi;
colorVec = 'brgmckybrgmckybrgmckybrgmcky';
styleVec = 'o+sdp';
Vin=12;
Vout=30;
Pout=7;
ws=2*pi*[40e6:10e6:120e6];
wo=0.85*ws;
o1_vec=[-0.6 -0.8 -1 -1.2];
figure(400); clf;
for oo=1:length(olvec)
01=o1_vec(oo);
a-s(oo,:) = a(Vin,Vout,Pout,ws,wo,o1);
b-s(oo,:) = b(Vin,Vout,Pout,ws,wo,ol);
c-s(oo,:) = c(Vin,Vout,Pout,ws,wo,ol);
d_s(oo,:) = d(Vin,Vout,Pout,ws,wo,ol);
e-s(oo,:) = e(Vin,Vout,Pout,ws,wo,ol);
% b-s=b-s+e-s;
% c-s=cs+d_s;
f(oo,:) = e-s(oo,:).*cs(oo,:)./(b-s(oo,:).*d-s(oo,:));
XXXXXXXXXXXXXXXXXXXXXXXX
X Closed Form Solution
XXXXXXXXXXXXXXXXXXX%X
-
122
B.1
Iac(oo,:)
zo(oo,:)
=
=
MATLAB Code to Generate Figures 3.4 and 3.7
as(oo,:)./(b-s(oo,:).*(1-f(oo,:)));
-(1./Iac(oo,:)).*d-s(oo,:)./e-s(oo,:);
C(oo,:) = 1e12./(wo.*zo(oo,:));
L(oo,:) = 1e9*zo(oo,:)./wo;
subplot(2,1,1); hold on;
plot(ws/(2*pi*1e6),L(oo,:),[colorVec(oo)]);
grid on;
set(gca,'yscale','log')
xlabel('Switching Frequency (MHz)');
ylabel('Inductance (nH)');
subplot(2,1,2); hold on;
plot(ws/(2*pi*1e6),C(oo,:),[colorVec(oo)]);
grid on;
set(gca,'yscale','log')
xlabel('Switching Frequency (MHz)')
ylabel('Capacitance (pF)');
end
legend('o_1=-0.4','o_1=-0.6','o_1=-0.8','o_1=-1');
for oo=1:length(o1_vec)
subplot(2,1,1); hold on;
plot(ws(1:10:end)/(2*pi*1e6),L(oo,1:10:end),[colorVec(oo) styleVec(oo)]);
subplot(2,1,2); hold on;
plot(ws(1:10:end)/(2*pi*1e6),C(oo,1:10:end),[colorVec(oo) styleVec(oo)]);
end
figure(402); clf;
for oo = 1:length(oi vec)
for ww = 1:length(ws)
disp(['phi1: ',num2str(o1_vec(oo)),' - ws: ',num2str(ws(ww)*ie-6/(2*pi))]);
X Need fundumental component
t = (0:200)*pi/(100*ws(ww));
v-cap=[];
i_cap=[];
i.ind=[];
i-rds=[];
for tt = 1:length(t)
v-cap(tt) = Vc(Vin,Vout,Pout,ws(ww),wo(ww),...
zo(oo,ww),o1_vec(oo),Iac(oo,ww),t(tt));
i-cap(tt) = Ic(Vin,Vout,Pout,ws(ww),wo(ww),...
zo(oo,ww),o1.vec(oo),Iac(oo,ww),t(tt));
i-ind(tt) = Il(Vin,Vout,Pout,ws(ww),wo(ww),...
zo(oo,ww),o1_vec(oo),Iac(oo,ww),t(tt));
-
123
Design Methodology MATLAB Scripts
i-rds(tt) = Im(Vin,Vout,Pout,ws(ww),wo(ww),...
zo(oo,ww),olvec(oo),Iac(oo,ww),t(tt));
end
temp = cumsum(v-cap.*sin(ws(ww)*t));
an = 2*temp(end)/length(t);
temp = cumsum(v-cap.*cos(ws(ww)*t));
bn = 2*temp(end)/length(t);
vfund(oo,ww) = sqrt(an^2+bn^2);
phi(oo,ww) = atan(bn/an)+pi*(an<O);
[wr-sol(oo,ww) zr-sol(oo,ww) iloss(oo,ww) dloss(oo,ww)]
= rectifier-solution(ws(ww),Vin,Vout,Pout,...
vfund(oo,ww),phi(oo,ww),o1_vec(oo),O);
Lr(oo,ww) = 1e9*zr-sol(oo,ww) / wr-sol(oo,ww);
Cr(oo,ww) = 1e12 / (wr-sol(oo,ww)*zr-sol(oo,ww));
end
subplot(2,1,1); hold on;
plot(ws/(2*pi*1e6),Lr(oo,:),[colorVec(oo)]);
grid on;
set(gca,'yscale','log')
xlabel('Switching Frequency (MHz)');
ylabel('Inductance (nH)');
subplot(2,1,2); hold on;
plot(ws/(2*pi*1e6),Cr(oo,:),[colorVec(oo)]);
grid on;
set(gca,'yscale','log')
xlabel('Switching Frequency (MHz)')
ylabel('Capacitance (pF)');
drawnow;
end
legend('o_1=-0.4','ol=-0.6','o_1=-0.8','o_1=-1');
for oo=:length(oivec)
subplot(2,1,1); hold on;
plot(ws(1:10:end)/(2*pi*1e6),Lr(oo,1:10:end),[colorVec(oo) .
styleVec(oo)]);
subplot(2,1,2); hold on;
plot(ws(1:10:end)/(2*pi*1e6),Cr(oo,1:10:end),[colorVec(oo)...
styleVec(oo)]);
end
function [wrsol zrsol iloss dloss]
=
-
124
B.1
MATLAB Code to Generate Figures 3.4 and 3.7
rectifier-solution(ws,Vin,Vout,Pout,k,phi,phiid,plotofl)
if ploton
tic
end
Vd
=
C(Vin,Vout,Pout,ws,wr,zr,k,toff,ton,phi,t) (Vin-Vout...
-((k/(i-(ws/wr)-2))*sin(ws*toff+phi)+Vin-Vout)*cos(wr*(t-toff)) ..
-((ws/wr)/(l-(ws/wr)-2))*k*cos(ws*toff+phi)*sin(wr*(t-toff))...
+(k/(i-(ws/wrY-2))*sin(ws*t+phi))*(t>toff) ...
+Vout;
Iind
= O(Vin,Vout,Pout,ws,wr,zr,k,toff,ton,phi,t)
(wr/zr)*((Vin-Vout)*(t-toff)-(k/ws)*(cos(ws*t+phi)-cos(ws*toff+phi)))...
*(t>=ton)*(t<=toff) ...
+(l/zr)*(((k/(i-(ws/wr)-2))*sin(ws*toff+phi)+Vin-Vout)*sin(wr*(t-toff)) ...
-((ws/wr)/(i-(ws/wr)-2))*k*cos(ws*toff+phi)*cos(wr*(t-toff)) ...
+((ws/wr)/(l-(ws/wr)-2))*k*cos(ws*t+phi))*(t>toff);
Icap
O(Vin,Vout ,Pout,ws,wr, zr,k,toff,ton,phi,t)
=
...
-(i/zr)*((ws/wr)/(l-(ws/wr)-2))*k*cos(ws*toff+phi)*cos(wr*(t-toff)) ...
+(ws/(zr*wr))*(k/(i-(ws/wr)-2))*cos(ws*t+phi))*(t>toff)*(t<=(ton+2*pi/ws));
Idio
= (D(Vin,Vout,Pout,ws,wr,zr,k,toff,ton,phi,t) ...
(wr/zr)*((Vin-Vout)*(t-toff)-(k/ws)*(cos(ws*t+phi)-cos(ws*toff+phi)))...
*(t>=ton)*(t<=toff);
aVd = O(Vin,Vout,Pout,ws,wr,zr,k,toff,ton,phi) (ws/(2*pi)) ...
*((ton+2*pi/ws-toff)*Vin...
-(i./wr).*((k./(l-(ws./wr).-2)).*sin(ws*toff+phi)+Vin-Vout) ...
**sin(wr. *(ton+2*pi/ws-toff))...
.*(cos(wr.*(ton+2*pi/ws-toff))-i) ...
-(1/ws)*(k./(1-(ws./wr).-2)).*(cos(ws*ton+phi) ...
-cos(ws*toff+phi))+Vout*(toff-ton));
alind
=
O(Vin,Vout,Pout,ws,wr,zr,k,toff,ton,phi)
.
+Vin-Vout)*(cos(wr*(ton+2*pi/ws-toff) )-1) ...
-(1./(zr*wr))*((ws/wr)/(1-(ws/wr)-2))*k*cos(ws*toff+phi) ...
*sin(wr* (ton+2*pi/ws-toff)) ...
+(l./(zr*ws))*((ws/wr)/(i-(ws/wr)-2))*k*(sin(ws*ton+phi)..
-sin(ws*toff+phi)) ...
+(wr./zr)*(Vin-Vout)*(toff-2/2-ton-2/2)-(wr*k./(zr*ws-2)) ...
*(sin(ws*toff+phi)-sin(ws*ton+phi)) ...
+(wr./zr)*(-(Vin-Vout)*toff+(k/ws)*cos(ws*toff+phi)) ...
-
125
-
Design Methodology MATLAB Scripts
*(toff-ton))*(ws/(2*pi));
alcap
=
cO(Vin,Vout,Pout,ws,wr,zr,k,toff,ton~phi)
.*(cos(wr.*(ton+2*pi/ws-toff))-l) ...
-(i./(wr*zr)) .*((ws./wr)./(-(ws/wr).-2)).*k*cos(ws*toff+phi)..
**sin(wr. *(ton+2*pi/ws-toff)) ...
-sin(ws*toff+phi)))*(ws/(2*pi));
aldio = D(Vin,VoutPout,ws~wr,zr,k,toff,ton,phi)..
((wr/zr)*(Vin-Vout)*(toff-2/2-ton-2/2)-(wr*k/(zr*ws-2))..
* (sin (ws*toff+phi)-sin(ws*ton+phi))...
+(wr/zr)*(-(Vin-Vout)*toff+(k/ws)*cos(ws*toff+phi))*(toff-ton))*(ws,(2*pi));
an
(Vin,Vout,Pout,ws,wr,zr,k~toff,ton,phi)..
((i/zr)*((k/(i-(ws/wr)-2))*sin(ws*toff+phi)+Vin-Vout)..
*(-sin(wr*toff-(wr-ws)*(ton+2*pi/ws))/(2*(wr-ws))..
+sin(wr*toff-(wr+ws)*(ton+2*pi/ws))/(2*(wr+ws))+sin(ws*toff)..
*(l/(2*(wr-ws))+1/(2*(wr+ws))))..
-(l/zr)*((ws/wr)/(i-(ws/wr)-2))*k*cos(ws*toff+phi)*(cos(wr*toff-(wr-ws)..
* (ton+2*pi/ws) ) /(2* (wr-ws)) ...
-cos(wr*toff-(wr+ws)*(ton+2*pi/ws))/(2*(wr+ws)) ...
+cos(ws*toff)*(i/(2*(wr+ws))-i/(2*(wr-ws))))..
+(l/zr)*((ws/wr)/(i-(ws/wr)-2))*k*((cos(2*ws*toff+phi)..
=
-cos( 2 *ws*ton+phi)+2*sin(phi)*(toff-ton-2*pi/ws)*ws)/(4*ws))..
+(wr/zr)*(k/ws)*(cos(2*ws*toff+phi) ...
-cos(2*ws*ton+phi)+2*sin(phi)*(toff-ton)*ws)/(4*ws)..
+(wr/zr)*(Vin-Vout)*(-toff*cos(ws*toff)/ws+sin(ws*toff)/(ws-2)..
+(ton*cos(ws*ton)*ws-sin(ws*ton))/(ws-2))..
+(wr/zr)*(-(Vin-Vout)*toff+(k/ws)*cos(ws*toff+phi)) ...
*(cos(ws*ton)-cos(ws*toff))/ws)*(ws/pi);
bn
(Vin,Vout,Pout,ws,wr,zr,k,toff,ton,phi)..
((l/zr)*((k/(i-(ws/wr)-2))*sin(ws*toff+phi)+Vin-Vout)..
*(-cos(wr*toff-(wr-ws)*(ton+2*pi/ws))/(2*(wr-ws))..
=
-cos(wr*toff-(wr+ws)*(ton+2*pi/ws))/(2*(wr+ws)) ...
+cos(ws*toff)*(i/(2*(wr-ws))+1/(2*(wr+ws))))..
-(i/zr)*((ws/wr)/(i-(ws/wr)-2))*k*cos(ws*toff+phi) ..
*(-sin(wr*toff-(wr-ws)*(ton+2*pi/ws))/(2*(wr-ws))..
-sin(wr*toff-(wr+ws)*(ton+2*pi/ws))/(2*(wr+ws)) ...
+sin(ws*toff)*(i/(2*(wr-ws))-i/(2*(wr+ws))))..
-(I/zr)*((ws/wr)/(l-(ws/wr)-2))*k*((sin(2*ws*toff+phi)...
-sin(2*ws*ton+phi)+2*cos(phi)*(toff-ton-2*pi/ws)*ws)/(4*ws))..
-(wr/zr)*(k/ws)*((sin(2*ws*toff+phi)-sin(2*ws*ton+phi) ...
+2*cos(phi)*(toff-ton)*ws)/(4*ws))..
+ (wr/zr) *(Vin-Vout) *(cos (ws*toff) /(ws-2) +toff*sin(ws*toff) /ws ..
-(cos(ws*toff)+ton*sin(ws*ton)*ws)/(ws-2)) ...
+(wr/zr)*(-(Vin-Vout)*toff+(k/ws)*cos(ws*toff+phi))...
-
126
-
B.1
MATLAB
Code to Generate Figures 3.4 and 3.7
*(sin(ws*toff)-sin(ws*ton))/ws)*(ws/pi);
ton=(0.0:.01:0.99)*2*pi/ws;
td=(0.001:.005:0.99)*2*pi/ws;
wrvec=[0.29:.02:1.8]*ws;
zr-temp = 20;
ii = 0;
for tt=1:length(ton)
count=0;
val=[];
wr-keep=[];
toff_i=[];
for ww = 1:length(wr-vec)
wr=wr-vec(ww);
toff = ton(tt)+td;
aVdiode = aVd(Vin,Vout,Pout,ws,wr,zr-temp,k,toff,ton(tt),phi)-Vin;
aCapacitor = aIcap(Vin,Vout,Pout,ws,wr,zr-temp,k,toff,ton(tt),phi);
int = aVdiode-aCapacitor;
int-i = find(abs(diff(sign(int)))>0);
if length(int-i)>0
count=count+1;
toff-i(count) = interp1(inttoff,0);
val(count) = ...
aIcap(Vin,Vout,Pout,ws,wr,zr-temp,ktoff-i(count),ton(tt),phi);
wr-keep(count) = wr;
if ploton
figure(190); clf;
hold on;
plot(toff*ws/(2*pi),aVdiode);
plot(toff*ws/(2*pi),aCapacitor,'c');
plot(toff(int-i)*ws/(2*pi),aVdiode(int-i),'ro');
xlabel('toff');
ylabel('aVd - aIc');
grid on;
title(['wr: ',num2str(wr/ws),' ton: ',num2str(ton(tt)*ws/(2*pi))]);
drawnow;
-
127 -
Design Methodology MATLAB Scripts
end
end
end
if
(count > 0)
val-cross = find(abs(diff(sign(val)))>o);
if length(val-cross)>0
wr-i = interpl(val,wr-keep,O);
toffii = interpi(wrkeep,toff_i,wr_i);
aVdiode = aVd(Vin,Vout,Pout,wswr-i,...
zr-temp,k,toffiji,ton(tt),phi)-Vin;
aCapacitor = aIcap(Vin,Vout,Pout,ws,...
wr-i,zr-temp,k,toff-i-i,ton(tt),phi);
if ploton
figure(191); clf;
subplot(2,1,1); hold on;
plot(wr-keep/wsval);
plot(wr-i/ws,0,'co');
grid on;
title(['aVdiode: ',num2str(aVdiode),.
' - aCap: ',num2str(aCapacitor)]);
subplot(2,1,2); hold on;
plot(wr-keep/ws,toffti);
plot(wr_i/ws,toffi_i,'co');
grid on;
drawnow;
end
ii = ii+1;
aIind-zr = aIind(Vin,Vout,Pout,ws,wri,1,...
k,toffti-i,ton(tt),phi);
zr-k(ii) = aIind-zr*Vout/Pout;
ton-k(ii) = ton(tt);
toff-k(ii)=toff-i.i;
wr-k(ii) = wr-i;
an-r = an(Vin,Vout,Poutwswri,zr-k(ii),...
k,toff_ii,ton(tt),phi);
bn-r = bn(Vin,Vout,Pout,ws,wr-i,zrk(ii),...
k,toff-i-i,ton(tt),phi);
amp = sqrt(an-r^2+bn-r^2);
phii(ii) = atan(bn-r/an-r)+pi*(an-r<o);
end
-
128 -
B.1
MATLAB Code to Generate Figures 3.4 and 3.7
end
end
wr-sol = interpl(phil,wr-k,phild);
zr-sol = interpl(phil,zr-k,phild);
ton-sol = interpl(phil,ton-k,phild);
toff-sol = interpl(phil,toff-k,phild);
if ploton
figure(193); clf;
plot(ton-k*ws/(2*pi),phil,'.-');
figure(194); clf;
subplot(2,1,1);
plot(phil,wr-k/ws);
subplot(2,1,2);
plot(phil,zrk);
figure(195); clf;
subplot(2,1,1); hold on;
plot(phi1,1e9*zr-k./wr-k);
plot(phild,le9*zr-sol/wr-sol,'co');
subplot(2,1,2); hold on;
plot(phil,1e12./(wr-k.*zr-k));
plot(phild,1e12/(zr-sol*wr-sol),'co');
set(gca,'yscale','log');
grid on;
end
indQ = 120;
indQw = 2*pi*120e6;
t = tonsol+(0:400)*pi/(200*ws);
for ii=l:length(t)
Iinductor(ii)
= Iind(Vin,Vout,Pout,wswr_solzr-sol,...
k,toff-sol,ton-sol,phi,t(ii));
Vdiode(ii)
= Vd(Vin,Vout,Pout,ws,wr-sol,zr-sol,...
k,toff-sol,ton-sol,phi,t(ii));
end
if ploton
disp(['
Rectifier Peak Current:
',...
num2str(max(Iinductor)),' - only AC',...
num2str(max(Iinductor)-mean(Iinductor))]);
end
indLosst = cumsum((Iinductor-...
mean(Iinductor)).^2)/length(Iinductor);
-
129 -
Design Methodology MA TLAB Scripts
L = zr-sol/wr-sol;
if (L > 100e-9)
ACR = 2*pi*50e6*L/100;
DCR = .01*L/100e-9;
else
ACR = 2*pi*120e6*L/120;
DCR = .01;
end
indLoss = indLoss t(end)*ACR+mean(Iinductor)^2*DCR;
diodeLoss = aIind(Vin,Vout,Pout,ws,...
wr-solzr-sol,k,toff-solton-sol,phi)*0.55;
iloss =indLoss;
dloss = diodeLoss;
if ploton
figure(196); clf;
subplot(2,1,1);
plot(t*ws/(2*pi),Vdiode);
subplot(2,1,2); hold on;
plot(t*ws/(2*pi),Iinductor);
toc;
end
-
130
Appendix C
Device Layout Optimization MATLAB
Scripts
C.1
MATLAB Code to Generate Figures 4.3 - 4.6
clear all;
r = @(ws,wo) (ws./wo).^2./((ws./wo).^2-1);
X Capacitor Voltage
Vc = Q(Vin,Vout,Pout,ws,wo,zo,o,kl,t) ((-2*pi*wo/ws)*(Vin/2
+zo*ki*wo*r(ws,wo)*sin(o)/(pi*ws)+zo*k1*r(ws,wo)*cos(oi)*sin(wo*pi/ws)/(2*pi)...
+ws*sin(wo*pi/ws)*Vin/(2*pi*wo))*sin(wo*t)/(cos(wo*pi/ws)-1)...
-(zo*k1*wo*r(ws,wo)*cos(ol)/(ws)+Vin)*cos(wo*t)...
+zo*k1*wo*r(ws,wo)*cos(ws*t+o)/ws+Vin)*(t<=pi/ws);
X Capacitor Current
Ic = Q(Vin,Vout,Pout,ws,wo,zo,o1,k1,t) ((-2*pi*wo./(ws*zo)).*(Vin/2+...
zo*k1*wo*r(ws,wo)*sin(o1)/(pi*ws)+zo*k1*r(ws,wo)*cos(o1)*sin(wo*pi/ws)/(2*pi)...
+ws*sin(wo*pi/ws)*Vin/(2*pi*wo))*cos(wo*t)/(cos(wo*pi/ws)-1)...
+(1./zo).*(zo*ki*wo*r(ws,wo)*cos(o)/ws+Vin)*sin(wo*t)...
-k1*r(ws,wo)*sin(ws*t+oi))*(t<=pi/ws);
X Inductor Current
Il = @(Vin,Vout,Pout,ws,wo,zo,o1,k1,t) ...
(Ic(Vin,Vout,Pout,ws,wo,zo,ol,k1,t) + Pout/Vout + k1*sin(ws*t+ol))*(t<=pi/ws)...
+(Ic(Vin,Vout,Pout,ws,wo,zo,o,kl,pi/ws) ...
-k1*sin(o1)+Pout/Vout+Vin*wo*(t-pi/ws)/zo)*(t>pi/ws);
% Transistor Current
Im = Q(Vin,Vout,Pout,ws,wo,zo,o,k1,t)...
(Ic(Vin,Vout,Pout,ws,wo,zo,oi,ki,pi/ws)-ki*sin(ol)+Vin*wo*(t-pi/ws)/zo...
-ki*sin(ws*t+o1))*(t>pi/ws);
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
a = @(Vin,Vout,Pout,ws,wo,o1)
Pout/Vin-Pout/Vout;
-
131
-
Device Layout Optimization MATLAB Scripts
b = O(Vin,Vout,Pout,ws,wo,o1)
(1/pi ...
-wo.*r(ws,wo).*sin(wo*pi./ws).*cos(wo.*pi./ws)./(2*ws.*(cos(wo.*pi/ws)-l))...
+r(ws,wo).*wo.*sin(wo.*pi./ws)/(2.*ws)).*cos(o1)...
+(-1/2 -
(wo./ws).^2.*r(ws,wo).*cos(wo*pi./ws)./(cos(wo*pi./ws)-1)...
+r(ws,wo)/2).*sin(o1);
c = O(Vin,Vout,Pout,ws,wo,o1) Vin*wo*pi./(4*ws) ...
-(pi*Vin*wo./(2*ws) + Vin*sin(wo*pi./ws)/2)...
.*(cos(wo*pi./ws)./(cos(wo*pi./ws)-1)) + Vin*sin(wo*pi./ws)/2;
d = @(Vin,Vout,Pout,ws,wo,o1) (-Vin/2 - ws.*Vin.*sin(wo.*pi./ws)./(2*pi.*wo))...
.*(sin(wo.*pi./ws)./(cos(wo.*pi./ws)-1)) - ws.*Vin.*(cos(wo.*pi./ws)-i)./(2.*pi.*wo);
e = @(Vin,Vout,Pout,ws,wo,o1) (-r(ws,wo).*wo.*sin(o1)./(pi.*ws)...
-r(ws,wo).*cos(o1).*sin(wo.*pi./ws)/(2*pi)).*sin(wo.*pi./ws)./(cos(wo.*pi./ws)-1)...
-r(ws,wo).*cos(o1).*(cos(wo.*pi./ws)-1)/(2*pi)-r(ws,wo).*cos(o1)/pi;
Vin=12;
Vout=30;
Pout=15;
ws=2*pi*30e6;
wo=0.85*ws;
o1=-1;
Vg=5;
XXXXXXXXXXXXXXXXXXXX
X Start by finding converter design parameters that are needed for
X optimization
XXXXXXXXXXXXXXXXXXXX
abs = a(Vin,Vout,Pout,ws,wo,o1);
bs = b(Vin,Vout,Pout,ws,wo,ol);
cds = c(Vin,Vout,Pout,ws,wo,o1);
d_s = d(Vin,Vout,Pout,ws,wo,ol);
e-s = e(Vin,Vout,Pout,ws,wo,o1);
f = es*cs/(b-s*d-s);
Iac =as/(b-s*(1-f));
zo = -(1/Iac)*d-s./e-s;
-
132
C.1
MATLAB
Code to Generate Figures 4.3 - 4.6
t = (0:200)*2*pi/(ws*200);
for tt
= 1:length(t)
Ic-s(tt) = Ic(Vin,Vout,Pout,ws,wo,zo,ol,Iac,t(tt));
Im-s(tt) = Im(Vin,Vout,Pout,ws,wo,zo,ol,Iac,t(tt));
end
Ic-rms = mean(Ic-s.^2)
Im-rms = mean(Im-s.^2)
C-design = 1/(zo*wo);
X 60V Parameters
Cgso = 0.76;
Cgdo = 0.496;
Cj = 0.97;
Rdss = 141;
% 50V
X Cj=0.94;
% Cgso=0.84;
X Cgdo=0.439;
X Rdss=126;
% 40V
% Cgso=1.35;
% Cgdo=0.363;
% Rdss=108;
X Cj=0.93;
% Other Parameters
Hp = 6.9;
Cjbot = 0.087;
Cjsw = 0.445;
width = [20000 : 1000: 260000];
fingerWidth-vec = 60:2:2000;
for widthIndx = 1:length(width)
for fingerNumIndx = 1:length(fingerWidth-vec)
Rds(widthIndx,fingerNumIndx) = 1.6*Rdss*80.8/width(widthIndx)+.05;
Ross1(widthIndx,fingerNumIndx) = 1.5*(55*1000)/width(widthIndx);
Ross2(widthIndx,fingerNumIndx) = Rds(widthIndx)*3;
-
133 -
Device Layout Optimization MATLAB Scripts
fingerWidth
numFingers
=
=
fingerWidth_vec(fingerNumIndx);
ceil(width(widthIndx)/fingerWidth);
Ciss(widthIndx,fingerNumIndx)=((Cgso+Cgdo)*(numFingers*fingerWidth...
+16*numFingers*2))*10^-15;
Riss(widthIndx,fingerNumIndx) = 3.9*fingerWidth/(4.6*2*2*numFingers);
P =
2
*((2 *Hp+numFingers+4)+(0.5*fingerWidth+2*Hp+5.4));
A = (2 *Hp*numFingers+4)*(0.5*fingerWidth+2*Hp+5.4);
Coss(widthIndx,fingerNumIndx) = 0.7 *((Cj+Cgdo)*numFingers*fingerWidth...
+A*Cjbot+P*Cjsw)*10-15;
fC = min(Coss(widthIndx,fingerNumIndx)/C-design,1);
pRoss1(widthIndx,fingerNumIndx) = fC^2*Ross1(widthIndx,fingerNumIndx)*Ic-rms;
pRoss2(widthIndx,fingerNumIndx) = fC^2*Ross2(widthIndx,fingerNumIndx)*Ic-rms;
pRDS(widthIndx,fingerNumIndx)
pGate(widthIndx,fingerNumIndx)
Rds(widthIndx,fingerNumIndx)*Im-rms;
=
=
Ciss(widthIndx,fingerNumIndx)*Vg^2*ws/(2*pi);
pRGate(widthIndx,fingerNumIndx) = 2*(pi*Ciss(widthIndx,fingerNumIndx)...
*Vg*1.2*ws/(2*pi))^2*Riss(widthIndx,fingerNumIndx);
loss-h(widthIndx,fingerNumIndx) = pGate(widthIndx,fingerNumIndx)...
+pRDS(widthIndx,fingerNumIndx)+pRoss2(widthIndx,fingerNumIndx);
loss-r(widthIndx,fingerNumIndx) = pRGate(widthIndx,fingerNumIndx)...
+pRDS(widthIndx,fingerNumIndx)+pRoss2(widthIndx,fingerNumIndx);
end
end
figure(16); cif;
subplot(2,2,1);
imagesc(width,fingerWidth-vec,Rds');
set(gca,'ydir','normal');
b = colorbar;
x1 = [.08 .58 .3 .35];
x = [.4 .58 .03 .35];
set(b,'Position',x)
set(gca,'position',x1)
-
134 -
C.1
MATLAB
set(get(b,'ylabel'),'String','Ohms');
ylabel('Finger Width (um)');
xlabel('Total Device Width (um)');
title('R{DS}')
subplot(2,2,2);
imagesc(width,fingerWidth-vec,Riss');
set(gca,'ydir','normal');
b = colorbar;
xl = [.58 .58 .3 .35];
x = [.9 .58 .03 .35];
set(b,'Position',x)
set(gca,'position',x1)
set(get(b,'ylabel'),'String','Ohms');
ylabel('Finger Width (um)');
xlabel('Total Device Width (um)');
title('R_{ISS}')
subplot(2,2,3);
imagesc(width,fingerWidth-vec,1ei2*Ciss');
set(gca,'ydir','normal');
b = colorbar;
xl = [.08 .09 .3 .35];
x = [.4 .09 .03 .35];
set(b,'Position',x)
set(gca,'position',xl)
set(get(b,'ylabel'),'String','pF');
ylabel('Finger Width (um)');
xlabel('Total Device Width (um)');
title('C_{ISS}')
subplot(2,2,4);
imagesc(width,fingerWidth-vec,1e12*Coss');
set(gca,'ydir','normal');
b = colorbar;
x1 = [.58 .09 .3 .35];
x = [.9 .09 .03 .35];
set(b,'Position',x)
set(gca,'position',xi)
set(get(b,'ylabel'),'String','pF');
-
135 -
Code to Generate Figures 4.3 - 4.6
Device Layout Optimization MATLAB Scripts
ylabel('Finger Width (um)');
xlabel('Total Device Width (um)');
title('C_{OSS}');
figure(13); clf;
imagesc(width,fingerWidthvec,1e9*(Ciss.*Riss)');
set(gca,'ydir','normal');
b = colorbar;
x1 = [0.12 0.1 0.73 0.81;
x = [0.88 0.1 0.03 0.81;
set(b,'Position',x)
set(gca,'position',x1)
set(get(b,'ylabel'),'String','nS');
ylabel('Finger Width (um)');
xlabel('Total Device Width (um)');
title('Gate Time Constant');
figure(12); clf;
subplot(2,1,1);
imagesc(width,fingerWidthvecloss-h'/Pout);
set(gca,'ydir','normal');
ylabel('Finger Width (um)');
xlabel('Total Device Width (um)');
title('Hard Switched Gating')
subplot(2,1,2);
imagesc(width,fingerWidthvecloss-r'/Pout);
set(gca,'ydir','normal');
ylabel('Finger Width (um)');
xlabel('Total Device Width (um)');
title('Sinusoidal Resonant Gating')
A(1)=subplot(2,1,1); X/mesh(x,y,z)
A(2)=subplot(2,1,2); /.mesh(x,y,z)
B=colorbar;
set(B, 'Position', [.8314 .11 .0581 .81501)
Xset(get(B,'FontSize'),'String', '14');
set(get(B,'ylabel'),'String', 'Normalized Converter Loss');
for i=1:2
pos=get(A(i), 'Position');
axes(A(i))
set(A(i), 'Position', [pos(1) pos(2) .6626 pos(4)1)
end
-
136 -
C.2
C.2
MATLAB
Code to Generate Figures 4.11 and 4.12
MATLAB Code to Generate Figures 4.11 and 4.12
% Script to calculate gate metal interconnect resistance and capacitance
clear all;
clc;
numFingers = 100;
numRows-vec
=
[2 3 4 5];
for nn = 1:length(numRows-vec)
numRows = numRows-vec(nn);
disp(['numRows: ',num2str(numRows)1);
% Round to an integer number of fingers
numFingersPerRow = floor(numFingers/numRows);
numFingers = numFingersPerRow*numRows;
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
% Calculate RISS including metal
numNodes = (numFingersPerRow+2)*(numRows+1)+1;
X Resistance matrix
resMat = zeros(numNodes,numNodes);
Wgmi =
[2:1:70];
for ww = 1:length(Wgm-i)
Wgm=Wgmji(ww);
% Resistance
rG = 3.9*450/(4.6*2);
rMi = 0.06*13.8/Wgm;
rMs = 0.06*225/Wgm;
nodeIndx = 0(finger,row) ...
finger+(numFingersPerRow+2)*(row-1);
resMat =
[];
for rr = 1:(numRows+1)
if (rr==1 || rr==numRows+1)
for ff = 1:numFingersPerRow+2
node = nodeIndx(ff,rr);
if (ff==i)
resMat = addResistor(resMat,node,node+1,rMi);
elseif ( (ff > 1) && (ff < numFingersPerRow+2) )
-
137 -
Device Layout Optimization MATLAB Scripts
resMat
resMat
resMat
resMat
=
=
=
=
addResistor(resMat,node,numNodes,rG);
addResistor(resMat,numNodes,node,rG);
addResistor(resMat,node,node+1,rMi);
addResistor(resMat,node,node-1,rMi);
else
resMat = addResistor(resMat,node,node-1,rMi);
end
end
else
for ff = 1:numFingersPerRow+2
node = nodeIndx(ff,rr);
if (ff==1)
resMat = addResistor(resMat,node,node+1,rMi);
elseif ( (ff > 1) && (ff < numFingersPerRow+2) )
resMat = addResistor(resMat,node,numNodes,rG/2);
resMat = addResistor(resMat,numNodes,node,rG/2);
resMat = addResistor(resMat,node,node+1,rMi);
resMat = addResistor(resMat,node,node-1,rMi);
else
resMat = addResistor(resMat,node,node-1,rMi);
end
end
end
if
(rr==1)
resMat = addResistor(resMat,nodeIndx(1,rr),nodeIndx(1,rr+1),rMs);
resMat = addResistor(resMat,nodeIndx(numFingersPerRow+2,rr),...
nodeIndx(numFingersPerRow+2,rr+1),rMs);
elseif (rr==numRows+1)
resMat = addResistor(resMat,nodeIndx(1,rr),nodeIndx(1,rr-1),rMs);
resMat = addResistor(resMat,nodeIndx(numFingersPerRow+2,rr),...
nodeIndx(numFingersPerRow+2,rr-1),rMs);
else
resMat = addResistor(resMat,nodeIndx(1,rr),nodeIndx(1,rr+1),rMs);
resMat = addResistor(resMat,nodeIndx(numFingersPerRow+2,rr),...
nodeIndx(numFingersPerRow+2,rr+1),rMs);
resMat = addResistor(resMat,nodeIndx(1,rr),nodeIndx(1,rr-1),rMs);
resMat = addResistor(resMat,nodeIndx(numFingersPerRow+2,rr),...
nodeIndx(numFingersPerRow+2,rr-1),rMs);
end
end
X Get second input by placing a very small resistor between actual port and
% second port
inputIndx = nodeIndx(2,1);
inputIndx2 = nodeIndx(2,3);
resMat = addResistor(resMat,inputIndx,inputIndx2,0.0001);
resMat = addResistor(resMat,inputIndx2,inputIndx,0.0001);
-
138
C.2
MATLAB
Code to Generate Figures 4.11 and 4.12
resMat(inputIndx,:)=[];
inputVec = -resMat(:,inputIndx);
resVec = -resMat(:,inputIndx);
resMat(:,inputIndx) = [];
gndIndx = numNodes-1;
resMat(gndIndx,:)=[];
resMat(:,gndIndx)=[];
inputVec(gndIndx)=[];
voltages = resMat\inputVec;
equivRes(ww) = 1/sum((1-[voltages' 0])'.*resVec);
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
X Calculate CISS
%XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
fingerWidth=450;
Cgso = 0.76;
Cgdo = 0.496;
Cadded(ww) = (13.8*numFingers*Wgm+(225+Wgm*(numRows+1))*Wgm)...
*0.103*le-15;
end
Fs=75e6;
Ciss-i=(Cgso+Cgdo)*(numFingers*fingerWidth+16*numFingers*2)*10^-15;
Ciss = Ciss-i+Cadded;
Riss-i =
3.9*fingerWidth/(4.6*2*2*numFingers);
pRes-i = 2*(pi*Ciss-i*7*Fs).^2.*Riss-i;
pHard = Ciss*5^2*Fs;
pRes = 2*(pi*Ciss*7*Fs).^2.*equivRes;
[pRes-min(nn) minIndx(nn)] = min(pRes);
equivRes-min(nn) = equivRes(minIndx(nn));
Ciss-min(nn) = Ciss(minIndx(nn));
Wgm-min(nn) = Wgm-i(minIndx(nn));
figure(70); clf
subplot(1,2,1); hold on;
-
139 -
Device Layout Optimization MATLAB Scripts
plot(Wgm-i,equivRes);
plot(Wgm-i,repmat(Riss-i,1,length(Wgm-i)),'r--');
plot(Wgm-i(minIndx(nn)),equivRes-min(nn),'ro');
grid on;
axis([2 70 0.8 2.6]);
xlabel('W{GM} (\muim)')
ylabel('Resistance (Ohms)');
title('R_{ISS}');
subplot(1,2,2); hold on
plot(Wgm-i,Ciss*1e12);
plot(Wgm-i,repmat(Ciss-i,1,length(Wgm-i))*1e12,'r--');
plot(Wgm-i(minIndx(nn)),Ciss-min(nn),'ro');
grid on;
axis([2 70 58 75]);
xlabel('W_{GM} (\mum)')
ylabel('Capacitance (pF)');
title('C_{ISS}');
legend('Including Interconnect','Intrinsic Only');
figure(71); clf;
subplot(1,2,1); hold on;
plot(Wgm-i,pRes);
plot(Wgm-i,repmat(pResi,1,length(Wgm_i)),'r--');
plot(Wgm-i(minIndx(nn)),pResmin(nn),'ro');
grid on;
axis([2 70 0.015 0.05]);
xlabel('W_{GM} (\mum)')
ylabel('Loss (Watts)');
title('Resonant Gating');
subplot(1,2,2); hold on;
plot(Wgm-i,Ciss.*equivRes*1e12)
plot(Wgm-i,repmat(Ciss-i*Riss-i,1,length(Wgm-i))*1e12,'r--');
grid on;
axis([2 70 50 150]);
xlabel('W_{GM} (\mum)')
ylabel('Time (pS)');
title('Gate Time Constant');
legend('Including Interconnect','Intrinsic Only');
drawnow;
end
figure(73); clf;
subplot(1,2,1);
plot(numRows-vec,Wgmnmin);
subplot(1,2,2);
plot(numRows-vec,pRes_min);
figure(74); clf;
140
MATLAB
C.3
Code to Generate Figure 4.15
subplot(1,2,1);
plot(numRows-vec,equivRes-min);
subplot(1,2,2);
plot(numRows-vec,Ciss-min);
C.3
MATLAB Code to Generate Figure 4.15
clear all;
Nfr=[50 33 251;
figure(12); clf;
steps = 100;
fL=13.8;
rds = zeros(length(Nfr),steps);
colorVec = 'brgmk';
for jj = 1:length(Nfr)
rows = 100/Nfr(jj);
Xl=fL*Nfr(jj);
maxAlpha = atan(225/(1*(Xl+35)));
alpha=1*(1:steps)*maxAlpha/steps;
for ii=1:steps
rds(jj,ii) = calcRdsTaper(Nfr(jj),rows,60.26,alpha(ii));
Cextra(jj,ii) = (Xl*(225/2-Xl*tan(alpha(ii)))+Xl2*tan(alpha(ii))...
+50*225)*0.0024*1e-15;
end
plot(90*alpha/(pi/2),1000*rds(jj,:),colorVec(jj),'LineWidth',3);
drawnow;
end
subplot(2,1,1);
plot(90*alpha/(pi/2),repmat(301.3,1,length(alpha)),'r--','lineWidth',3)
grid on;
legend('2 Rows','3 Rows','4 Rows','Intrinsic Only');
xlabel('Taper Angle (degree)');
ylabel('On Resistance (mOhm)')
set(gca,'FontSize',12);
h_xlabel = get(gca,'XLabel'); set(h-xlabel,'FontSize',12);
h-ylabel = get(gca,'YLabel'); set(h-ylabel,'FontSize',12);
title('On-State Resistance vs. Geometry')
function rdsOut = calcRdsTaper(Nfr,rows,rds,alpha)
% Define Constants
% total distance across a finger
fL=13.8;
% total length of row of fingers
Xl=fL*Nfr;
% sheet resistance of the metal layer
msr=0.06/2;
% contact resistance of a single contact
cR = 25;
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141 -
Device Layout Optimization MATLAB Scripts
% Function to compute the width of the tapered metal
dMw = O(x,alpha,Xl) 225/2+(x-Xl/2)*tan(alpha);
sMw = @(x,alpha,Xl) 225/2+(Xl/2-x)*tan(alpha);
X Discrete function to compute the width of the tapered metal
sMwi = @(indx,steps,alpha,Xl) sMw(indx*Xl/(steps-1),alpha,Xl);
dMwi = @(indx,steps,alpha,Xl) dMw(indx*Xl/(steps-1),alpha,Xl);
% Function to compute the metal resistance between fingers
dMr = O(x,alpha,XL,msr,fL) msr*fL/dMw(x,alpha,Xl);
sMr = Q(x,alpha,XL,msr,fL) msr*fL/sMw(x,alpha,Xl);
X Discrete version of the above function
dMri = @(indx,steps,alpha,XL,msr,fL)
...
msr*fL/dMw(indx*Xl/(steps-1),alpha,X1);
sMri = @(indx,steps,alpha,XL,msr,fL)
...
msr*fL/sMw(indx*Xl/(steps-1),alpha,Xl);
X Function
to compute the contact resistance
dCr = @(x,alpha,Xl,cR) cR/floor(dMw(x,alpha,Xl)/1.2);
sCr = O(x,alpha,Xl,cR) cR/floor(sMw(x,alpha,Xl)/1.2);
X Discrete version of the above function, also puts at least 1 contact to
X avoid divide by zero errors
dCri = @(indx,steps,alpha,Xl,cR) ...
cR/max(1,floor(dMw(indx*Xl/(steps-1),alpha,Xl)/1.2));
sCri = @(indx,steps,alpha,Xl,cR) ...
cR/max(1,floor(sMw(indx*Xl/(steps-1),alpha,Xl)/1.2));
X Define Node Matrix
nodeMatrix = zeros(4*Nfr-1,4*Nfr-1);
X Define Constant Vector
b = zeros(4*Nfr-1,1);
X Set Constant Vector
b(1,1)=-1/sMr(O,alpha,Xl,msr,fL);
X Fill node vector
X disp('Loop 1');
for ii=1:Nfr
if (ii==Nfr)
nodeMatrix(ii,ii)=-(i/sMri(ii-1,Nfr,alpha,Xl,msr,fL)...
+1/sCri(ii,Nfr,alpha,Xl,cR));
else
nodeMatrix(ii,ii)=-(i/sMri(ii-1,Nfr,alpha,Xl,msr,fL)...
+1/sCri(ii,Nfr,alpha,Xl,cR)...
-
142 -
MATLAB Code to Generate Figure 4.15
C.3
+1/sMri(ii,Nfr,alpha,Xl,msr,fL));
end
if (ii>i)
nodeMatrix(ii,ii-)=/sMri(ii-1,Nfr,alpha,X,msr,fL);
end
if (ii<Nfr)
nodeMatrix(ii,ii+i)=i/sMri(ii,Nfr,alpha,Xl,msr,fL);
end
nodeMatrix(ii,ii+Nfr)=1/sCri(ii,Nfr,alpha,Xl,cR);
end
for ii=(Nfr+i):2*Nfr
if (ii==Nfr+i)
nodeMatrix(iiii+2*Nfr-1)=1/rds;
else
nodeMatrix(iiii+Nfr-1)=1/rds;
end
if (ii<2*Nfr)
nodeMatrix(iiii+Nfr)=1/rds;
end
nodeMatrix(ii,ii)=-(i/rds+i/rds...
+1/sCri(ii-Nfr,Nfr,alpha,Xl,cR));
nodeMatrix(ii,ii-Nfr)=1/sCri(ii-Nfr,Nfr,alpha,Xl,cR);
end
for ii=(2*Nfr+i):(3*Nfr-1)
nodeMatrix(ii,ii)=-(1/rds+1/rds...
+1/dCri(ii-2*Nfr+1,Nfr,alpha,Xl,cR));
nodeMatrix(iiii-Nfr)=i/rds;
nodeMatrix(iiii-Nfr+1)=1/rds;
nodeMatrix(ii,ii+Nfr)=1/dCri(ii-2*Nfr+,Nfr,alpha,Xl,cR);
end
for ii=(3*Nfr):(4*Nfr-1)
if (ii<4*Nfr-1)
nodeMatrix(ii,ii+i)=1/dMri(ii-3*Nfr+1,Nfr,alpha,Xl,msr,fL);
end
if (ii>3*Nfr)
nodeMatrix(ii,ii-1)=i/dMri(ii-3*Nfr,Nfr,alpha,Xl,msr,fL);
end
if(ii==(3*Nfr))
nodeMatrix(ii,ii)=-(1/rds...
+1/dMri(ii-3*Nfr+i,Nfr,alpha,Xl,msr,fL));
nodeMatrix(iiii-2*Nfr+1)=1/rds;
else
nodeMatrix(ii,ii)=-(/dMri(ii-3*Nfr+,Nfr,alpha,Xl,msr,fL)...
-
143 -
Device Layout Optimization MATLAB Scripts
+1/dMri(ii-3*Nfr,Nfr,alpha,Xl,msr,fL)...
+1/dCri(ii-3*Nfr+1,Nfr,alpha,X1,cR));
nodeMatrix(ii,ii-Nfr)=1/dCri(ii-3*Nfr+1,Nfr,alpha,X,cR);
end
end
c = nodeMatrix\b;
inCurrent
equivRes
=
=
(1-c(1))/sMr(O,alpha,Xl,msr,fL);
1/inCurrent;
% Perform error checking
ssym=@(x) all(all(x==x.'));
if (ssym(nodeMatrix)==O) X Node matrix must be symetric
error('Matrix is not sym');
end
if (equivRes<O) XResistance must be positive
error('equiv res less than zero');
end
if (length(find(c>1))>O) % no voltage can be greater than 1
error('c > 1');
end
if (length(find(c<O))>O) X no votlages can be less than 0
error('c < 0');
end
rdsOut = equivRes/rows;
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144 -
Appendix D
Design Example MATLAB Scripts
D.1
MATLAB Script to generate Figure 5.10
tic
r = @(ws,wo) (ws./wo).^2./((ws./wo).^2-1);
X Capacitor Voltage
Vc = Q(Vin,Vout,Pout,ws,wo,zo,o1,ki,t) ((-2*pi*wo/ws)*(Vin/2
+zo*ki*wo*r(ws,wo)*sin(oi)/(pi*ws)+zo*k1*r(ws,wo)*cos(o1)*sin(wo*pi/ws)/(2*pi) ...
+ws*sin(wo*pi/ws)*Vin/(2*pi*wo))*sin(wo*t)/(cos(wo*pi/ws)-1) ...
-(zo*k1*wo*r(ws,wo)*cos(o1)/(ws)+Vin)*cos(wo*t)...
+zo*k1*wo*r(ws,wo)*cos(ws*t+o1)/ws+Vin)*(t<=pi/ws);
X Capacitor Current
Ic = Q(Vin,Vout,Pout,ws,wo,zo,o1,k1,t) ((-2*pi*wo./(ws*zo)).*(Vin/2+...
zo*k1*wo*r(ws,wo)*sin(o1)/(pi*ws)+zo*k1*r(ws,wo)*cos(oi)*sin(wo*pi/ws)/(2*pi) ...
+ws*sin(wo*pi/ws)*Vin/(2*pi*wo))*cos(wo*t)/(cos(wo*pi/ws)-1) ...
+(1./zo).*(zo*kl*wo*r(ws,wo)*cos(o)/ws+Vin)*sin(wo*t)...
-k1*r(ws,wo)*sin(ws*t+o1))*(t<=pi/ws);
X Inductor Current
Il = Q(Vin,Vout,Pout,ws,wo,zo,o1,k1,t) ...
(Ic(Vin,Vout,Pout,ws,wo,zo,o1,kl,t) + Pout/Vout + ki*sin(ws*t+oi))*(t<=pi/ws)...
+(Ic(Vin,Vout,Pout,ws,wo,zo,ol,ki,pi/ws)-k1*sin(o1)...
+Pout/Vout+Vin*wo*(t-pi/ws)/zo)*(t>pi/ws);
X Transistor Current
@(Vin,Vout,Pout,ws,wo,zo,o1,k1,t) ...
(Ic(Vin,Vout,Pout,ws,wo,zo,o1,k1,pi/ws)-k*sin(o1)+Vin*wo*(t-pi/ws)/zo...
-k1*sin(ws*t+ol))*(t>pi/ws);
Im =
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
a = @(Vin,Vout,Pout,ws,wo,oi) Pout/Vin-Pout/Vout;
b = O(Vin,Vout,Pout,ws,wo,o1) (1/pi ...
-wo.*r(ws,wo) .*sin(wo*pi./ws) .*cos(wo.*pi./ws) ./(2*ws.*(cos(wo.*pi/ws)-1)) ..
-
145 -
Design Example MATLAB Scripts
+r(ws,wo).*wo.*sin(wo.*pi./ws)/(2.*ws)).*cos(ol)...
+(-1/2 -
(wo./ws).^2.*r(ws,wo).*cos(wo*pi./ws)./(cos(wo*pi./ws)-1)...
+r(ws,wo)/2).*sin(ol);
c = @(Vin,Vout,Pout,ws,wo,o1) Vin*wo*pi./(4*ws) ...
-(pi*Vin*wo./(2*ws) + Vin*sin(wo*pi./ws)/2) ...
.*(cos(wo*pi./ws) ./(cos(wo*pi./ws)-1)) + Vin*sin(wo*pi./ws)/2;
d = '(Vin,Vout,Pout,ws,wo,ol) (-Vin/2 - ws.*Vin.*sin(wo.*pi./ws)./(2*pi.*wo)) ..
.*(sin(wo.*pi./ws)./(cos(wo.*pi./ws)-1)) - ws.*Vin.*(cos(wo.*pi./ws)-1)./(2.*pi.*wo);
e = @(Vin,Vout,Pout,ws,wo,o1) (-r(ws,wo).*wo.*sin(ol)./(pi.*ws)...
-r(ws,wo).*cos(o).*sin(wo.*pi./ws)/(2*pi)).*sin(wo.*pi./ws)./(cos(wo.*pi./ws)-1)...
-r(ws,wo).*cos(ol).*(cos(wo.*pi./ws)-)/(2*pi)-r(ws,wo).*cos(ol)/pi;
colorVec = 'brgmckybrgmckybrgmckybrgmcky';
styleVec = 'o+sdp';
Vin=12;
Vout=30;
Pout=7;
ws=2*pi*[45e6:10e6:125e6];
wo=0.85*ws;
olvec=[-0.6 -0.8 -1 -1.2];
figure(400); clf;
for oo=1:length(o1_vec)
01=o1_vec(oo);
a-s(oo,:) = a(Vin,Vout,Pout,ws,wo,ol);
b-s(oo,:) = b(Vin,Vout,Pout,ws,wo,ol);
c-s(oo,:) = c(Vin,Vout,Pout,ws,wo,ol);
d-s(oo,:) = d(Vin,Vout,Pout,ws,wo,ol);
e-s(oo,:) = e(Vin,Vout,Pout,ws,wo,o1);
X
b-s=b-s+e-s;
X c-s=cs+ds;
f(oo,:) = e-s(oo,:).*cs(oo,:)./(b.s(oo,:).*d-s(oo,:));
XXXXXXXXXXXXXXXXXXXXXX%
X Closed Form Solution
-
146 -
MATLAB Script to generate Figure 5.10
D.1
%%%%%%%%%%%%%%%%%%%%%%%%
Iac(oo,:)
zo(oo,:)
=as(oo,:)./(b-s(oo,:).*(1-f(oo,:)));
=
-(1./Iac(oo,:)).*d-s(oo,:)./e-s(oo,:);
C(oo,:) = 1e12./(wo.*zo(oo,:));
L(oo,:) = 1e9*zo(oo,:)./wo;
subplot(2,1,1); hold on;
plot(ws/(2*pi*1e6),L(oo,:),[colorVec(oo) styleVec(oo),'-'1);
grid on;
set(gca,'yscale','log')
xlabel('Switching Frequency (MHz)');
ylabel('Inductance (nH)');
subplot(2,1,2); hold on;
plot(ws/(2*pi*1e6),C(oo,:),[colorVec(oo) styleVec(oo),'-'
grid on;
set(gca,'yscale','log')
xlabel('Switching Frequency (MHz)')
ylabel('Capacitance (pF)');
1);
end
legend('o_1=-0.6','o_1=-0.8','o_1=-1.0','o_1=-1.2');
figure(402); clf;
figure(403); clf;
for oo = 1:length(o1_vec)
for ww = 1:length(ws)
disp(['phii: ',num2str(oivec(oo)),' - ws:
% Need fundumental component
t = (0:200)*pi/(100*ws(ww));
v_cap=[];
i-cap=[];
i-ind=[];
i_rds=[];
',num2str(ws(ww)*ie-6/(2*pi))1);
for tt = 1:length(t)
v-cap(tt)
i-cap(tt)
i-ind(tt)
i-rds(tt)
=
=
=
=
Vc(Vin,Vout,Pout,ws(ww),wo(ww),zo(oo,ww),o1_vec(oo),Iac(oo,ww),t(tt));
Ic(Vin,Vout,Pout,ws(ww),wo(ww),zo(oo,ww),o1_vec(oo),Iac(oo,ww),t(tt));
Il(Vin,Vout,Pout,ws(ww),wo(ww),zo(oo,ww),o1_vec(oo),Iac(oo,ww),t(tt));
Im(Vin,Vout,Pout,ws(ww),wo(ww),zo(oo,ww),o1_vec(oo),Iac(oo,ww),t(tt));
end
temp = cumsum(v-cap.*sin(ws(ww)*t));
an = 2*temp(end)/length(t);
temp = cumsum(v-cap.*cos(ws(ww)*t));
bn = 2*temp(end)/length(t);
vfund(oo,ww) = sqrt(an^2+bn~2);
phi(oo,ww) = atan(bn/an)+pi*(an<O);
-
147 -
Design Example MATLAB Scripts
% Calculate inverter loss here
capLosst = cumsum(i-cap.^2)/length(i-cap);
rdsLoss-t = cumsum(i-rds.^2)/length(i-rds);
[capLoss(oo,ww) rdsLoss(oo,ww) gateLoss(oo,ww) bestWidth(oo,ww)] =
optimization-v4(capLoss-t(end),rdsLoss-t(end),ws(ww)/(2*pi),C(oo,ww)*le-12);
Q = 10*sqrt(ws(ww)/(2*pi*1e6));
ACR = 2*pi*(ws(ww)/(2*pi))*L(oo,ww)*1e-9/Q;
DCR = .01;
indLoss-t = cumsum((i-ind-mean(i-ind)).^2)/length(i-cap);
indLoss(oo,ww) = indLoss-t(end)*ACR+mean(i_ind)^2*DCR;
invLoss(oo,ww) = capLoss(oo,ww)+indLoss(oo,ww)+rdsLoss(oo,ww)+gateLoss(oo,ww);
[wr-sol(oo,ww) zr-sol(oo,ww) iloss(oo,ww) dloss(oo,ww)] = ...
rectifier-solution(ws(ww),Vin,Vout,Pout,vfund(oo,ww),phi(oo,ww),oivec(oo),0);
Lr(oo,ww) = 1e9*zr-sol(oo,ww) / wr-sol(oo,ww);
Cr(oo,ww) = 1e12 / (wr-sol(oo,ww)*zr-sol(oo,ww));
end
figure(402);
subplot(2,1,1); hold on;
plot(ws/(2*pi*1e6),Lr(oo,:),[colorVec(oo) styleVec(oo),'-']);
grid on;
set(gca,'yscale','log')
xlabel('Switching Frequency (MHz)');
ylabel('Inductance (nH)');
subplot(2,1,2); hold on;
plot(ws/(2*pi*1e6),Cr(oo,:),[colorVec(oo) styleVec(oo),'-']);
grid on;
set(gca,'yscale','log')
xlabel('Switching Frequency (MHz)')
ylabel('Capacitance (pF)');
figure(403);
subplot(2,1,1); hold on;
plot(ws/(2*pi*1e6),Pout./(Pout + invLoss(oo,:)+iloss(oo,:)+dloss(oo,:))...
,[colorVec(oo) styleVec(oo),'-'])
xlabel('Switching Frequency (MHz)');
ylabel('Efficiency');
grid on;
subplot(2,1,2); hold on;
plot(ws/(2*pi*1e6),bestWidth(oo,:),[colorVec(oo) styleVec(oo),'-']);
xlabel('Switching Frequency (MHz)');
ylabel('Device Width (\mum)');
grid on;
-
148 -
D.2
MATLAB Script to generate Figures 5.11, 5.12, and 5.13
drawnow;
end
figure(402);
legend('o_1=-0.6','o_1=-0.8','o_1=-1.0','o_1=-1.2');
figure(403);
legend('\phi_1=-0.6','\phi_1=-0.8','\phi_1=-1.0','\phi_1=-1.2');
D.2
MATLAB Script to generate Figures 5.11, 5.12, and
5.13
clear all;
tic
r = @(ws,wo) (ws./wo).^2./((ws./wo).^2-1);
% Capacitor Voltage
Vc = @(Vin,Vout,Pout,ws,wo,zo,oi,k1,t) ((-2*pi*wo/ws)*(Vin/2 ...
+zo*ki*wo*r(ws,wo)*sin(o1)/(pi*ws)+zo*k1*r(ws,wo)*cos(o1)*sin(wo*pi/ws)/(2*pi)...
+ws*sin(wo*pi/ws)*Vin/(2*pi*wo))*sin(wo*t)/(cos(wo*pi/ws)-)...
-(zo*k1*wo*r(ws,wo)*cos(oi)/(ws)+Vin)*cos(wo*t)...
+zo*k1*wo*r(ws,wo)*cos(ws*t+oi)/ws+Vin)*(t<=pi/ws);
% Capacitor Current
Ic = @(Vin,Vout,Pout,ws,wo,zo,o1,ki,t) ((-2*pi*wo./(ws*zo)).*(Vin/2+...
zo*k1*wo*r(ws,wo)*sin(o)/(pi*ws)+zo*kl*r(ws,wo)*cos(o)*sin(wo*pi/ws)/(2*pi)...
+ws*sin(wo*pi/ws)*Vin/(2*pi*wo))*cos(wo*t)/(cos(wo*pi/ws)-1)...
+(1./zo).*(zo*k1*wo*r(ws,wo)*cos(oi)/ws+Vin)*sin(wo*t)...
-k1*r(ws,wo)*sin(ws*t+o1))*(t<=pi/ws);
% Inductor Current
Il
= @(Vin,Vout,Pout,ws,wo,zo,oi,ki,t)
...
(Ic(Vin,Vout,Pout,ws,wo,zo,oi,ki,t) + Pout/Vout + k1*sin(ws*t+oi))*(t<=pi/ws)...
+(Ic(Vin,Vout,Pout,ws,wo,zo,oi,ki,pi/ws)-k*sin(o)...
+Pout/Vout+Vin*wo*(t-pi/ws)/zo)*(t>pi/ws);
% Transistor Current
Im =
@(Vin,Vout,Pout,ws,wo,zo,o1,ki,t)...
(Ic(Vin,Vout,Pout,ws,wo,zo,ol,ki,pi/ws)-ki*sin(o1)+Vin*wo*(t-pi/ws)/zo...
-ki*sin(ws*t+ol))*(t>pi/ws);
% Derivative at switching
dVc = @(Vin,Vout,Pout,ws,wo,zo,oi,ki) (-2*pi*wo^2/ws)*(Vin/2+...
zo*k1*wo*r(ws,wo)*sin(o)/(pi*ws)+zo*kl*r(ws,wo)*cos(o1)*sin(wo*pi/ws)/(2*pi)...
+ws*sin(wo*pi/ws)*Vin/(2*pi*wo))*cos(wo*pi/ws)/(cos(wo*pi/ws)-)...
+wo*(zo*k1*wo*r(ws,wo)*cos(o1)/ws+Vin)*sin(wo*pi/ws)+zo*k1*wo*r(ws,wo)*sin(ol);
-
149 -
Design Example MATLAB Scripts
y%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
a = O(Vin,Vout,Pout,ws,wo,ol) Pout/Vin-Pout/Vout;
b
=
O(Vin,Vout,Pout,ws,wo,ol) (1/pi..
-wo.*r(ws,wo).*sin(wo*pi./ws).*cos(wo.*pi./ws) ./(2*ws.*(cos(wo.*pi/ws)-l)) ..
+r(ws,wo).*wo.*sin(wo.*pi./ws)/(2.*ws)).*cos(ol)..
+(12- (wo./ws).-2.*r(ws,wo).*cos(wo*pi./ws)./(cos(wo*pi./ws)-)..
+r(ws,wo)/2) .*sin(ol);
c = O(Vin,Vout,Pout,ws,wo,ol) Vin*wo*pi./(4*ws)..
-(pi*Vin*wo./(2*ws) + Vin*sin(wo*pi./ws)/2)...
.*(cos(wo*pi./ws)./(cos(wo*pi./ws)-l)) + Vin*sin(wo*pi./ws)/2;
d
=
O(Vin,Vout,Pout,ws,wo,ol) (-Vin/2 - ws.*Vin.*sin(wo.*pi./ws)./(2*pi.*wo)) ...
.*(sin(wo.*pi./ws) ./(cos(wo.*Pi./ws)-l)) - ws.*Vin.*(cos(wo.*pi./ws)-l) ./(2.*pi.*wo);
e
=
O(Vin,Vout,Pout,ws,wo,ol) (-r(ws,wo).*wo.*sin(ol)./(pi.*ws) ...
-r(ws,wo).*cos(ol).*sin(wo.*pi./ws)/(2*pi))*sin(wo*pi/ws)/(cos(wo.*pi./ws>.1)..
-r(ws,wo).*cos(ol).*(cos(wo.*pi./ws)-l)/(2*pi)-r(wswo).*cos(ol)/pi;
colorVec
styleVec
=
=
'brgmckybrgmckybrgmckybrgmcky';
'o+sdp';
Vin=12;
Vout=30;
Pout=7;
ws=2*pi*75e6;
% wo-vec=[0.4 0.6 0.8 0.95]*ws;
wo-vec=0. 8*ws;
% ol-vec=[-0.6 -0.8 -1 -1.2];
ol=-0.4:-0.1:-1.2;
figure(400); cif;
for ww=l:length(wo-vec)
wo=wo-vec(ww);
a-s(ww,:) = a(Vin,Vout,Pout,ws,wo,ol);
b-s(ww,:) = b(Vin,Vout,Pout,ws,wo,ol);
c-s(ww,:) = c(Vin,Vout,Pout,ws,wo,ol);
d-s(ww,:) = d(Vin,Vout,Pout,ws,wo,ol);
es(ww,:)
=
e(Vin,Vout,Pout,WS,wo,ol);
-
150
-
D.2
MATLAB Script to generate Figures 5.11, 5.12, and 5.13
% b-s=b-s+e-s;
% c-s=c-s+d-s;
f(ww,:) = e-s(ww,:).*c-s(ww,:)./(b-s(ww,:).*d-s(ww,:));
X Closed Form Solution
Iac(ww,:)
zo(ww,:)
=as(ww,:)./(b-s(ww,:).*(1-f(ww,:)));
=-(./Iac(ww,:)).*d-s(ww,:)./e-s(ww,:);
C(ww,:) = 1e12./(wo.*zo(ww,:));
L(ww,:) = 1e9*zo(ww,:)./wo;
subplot(1,2,1); hold on;
plot(oi,L(ww,:),[colorVec(ww) styleVec(ww),'-']);
grid on;
%
set(gca,'yscale','log')
xlabel('Rectifier Current Phase, \phi_1 (rad)')
ylabel('Inductance (nH)');
set(gca,'Xlim',[oi(end)-0.0001 oi(1)]);
subplot(1,2,2); hold on;
plot(oi,C(ww,:),[colorVec(ww) styleVec(ww),'-' ]);
grid on;
X
set(gca,'yscale','log')
xlabel('Rectifier Current Phase, \phi_1 (rad)')
ylabel('Capacitance (pF)');
set(gca,'Xlim',[ol(end)-0.0001 oi(i)]);
end
legend('\omega-o/\omega-s=0.4','\omega-o/\omega-s=0.6','\omega-o/\omega-s=0.8...
,'\omega-o/\omega-s=0.95');
figure(402); clf;
figure(403); clf;
figure(404); clf;
for ww = 1:length(wo-vec)
for oo = 1:length(oi)
disp(['phii: ',num2str(o1(oo)),' - wo/ws:
X Need fundumental component
t = (0:200)*pi/(100*ws);
v_cap=[];
i.cap=[];
i_ind=[];
-
151 -
',num2str(wovec(ww)/ws)]);
Design Example MATLAB Scripts
i_rds=[];
for tt = 1:length(t)
v-cap(tt) = Vc(Vin,Vout,Pout,ws,wo-vec(ww),zo(ww,oo),ol(oo),Iac(wwoo),t(tt));
i-cap(tt) = Ic(Vin,Vout,Pout,ws,wo-vec(ww),zo(ww,oo),ol(oo),Iac(wwoo),t(tt));
i-ind(tt) = Il(Vin,Vout,Pout,ws,wo-vec(ww),zo(ww,oo),ol(oo),Iac(wwoo),t(tt));
i-rds(tt) = Im(Vin,Vout,Pout,ws,wo-vec(ww),zo(ww,oo),ol(oo),Iac(wwoo),t(tt));
end
temp = cumsum(v-cap.*sin(ws*t));
an = 2*temp(end)/length(t);
temp = cumsum(v-cap.*cos(ws*t));
bn = 2*temp(end)/length(t);
vfund(ww,oo) = sqrt(an^2+bn^2);
phi(ww,oo) = atan(bn/an)+pi*(an<0);
% Calculate inverter loss here
capLoss-t = cumsum(i-cap.^2)/length(i-cap);
rdsLosst = cumsum(i-rds.^2)/length(irds);
[capLoss(ww,oo) rdsLoss(ww,oo) gateLoss(ww,oo) bestWidth(ww,oo)]
optimization-v4(capLoss-t(end),rdsLoss-t(end),ws/(2*pi),C(ww,oo)*le-12);
Q = 10*sqrt(ws/(2*pi*1e6));
ACR = 2*pi*(ws/(2*pi))*L(ww,oo)*1e-9/Q;
DCR =
.01;
indLoss-t = cumsum((i-ind-mean(i-ind)).^2)/length(i-cap);
indLoss(ww,oo) = indLoss-t(end)*ACR+mean(i-ind)^2*DCR;
invLoss(ww,oo) = capLoss(ww,oo)+indLoss(ww,oo)+rdsLoss(ww,oo)...
+gateLoss(ww,oo);
[wr-sol(ww,oo) zr-sol(ww,oo) iloss(ww,oo) dloss(ww,oo)] =
rectifier-solution(ws,Vin,Vout,Pout,vfund(ww,oo),phi(ww,oo),ol(oo),O);
Lr(ww,oo) = 1e9*zr-sol(ww,oo) / wr-sol(ww,oo);
Cr(ww,oo) = 1e12 / (wr-sol(ww,oo)*zr-sol(ww,oo));
dvc-s(ww,oo) = dVc(Vin,Vout,Pout,ws,wo-vec(ww),zo(ww,oo),ol(oo),Iac(ww,oo));
end
figure(402);
subplot(1,2,1); hold on;
plot(ol,Lr(ww,:),[colorVec(ww) styleVec(ww),'-']);
grid on;
%
set(gca,'yscale','log')
xlabel('Rectifier Current Phase, \phi_1 (rad)')
ylabel('Inductance (nH)');
set(gca,'Xlim',[o1(end)-0.0001 01(1)]);
subplot(1,2,2); hold on;
152
D.3
MATLAB Script to generate Figures 5.15, 5.16, and 5.17
plot(oi,Cr(ww,:),[colorVec(ww) styleVec(ww),'-'1);
grid on;
%
set(gca,'yscale','log')
xlabel('Rectifier Current Phase, \phi_1 (rad)')
ylabel('Capacitance (pF)');
set(gca,'Xlim',[o1(end)-0.0001 o1(I)]);
figure(403);
subplot(1,2,1); hold on;
plot(oi,Pout./(Pout + invLoss(ww,:)+iloss(ww,:)...
+dloss(ww,:)),[colorVec(ww) styleVec(ww),'-'1)
xlabel('Rectifier Current Phase, \phi_1 (rad)')
ylabel('Efficiency');
grid on;
set(gca,'Xlim',[o1(end)-0.0001 o1(1)]);
subplot(1,2,2); hold on;
plot(ol,bestWidth(ww,:),[colorVec(ww) styleVec(ww),'-'1);
xlabel('Rectifier Current Phase, \phi_1 (rad)')
ylabel('Device Width (\mum)');
set(gca,'Xlim',[o1(end)-0.0001 ol(1)]);
grid on;
figure(404); hold on;
plot(oi,dvc-s(ww,:)*le-9,[colorVec(ww) styleVec(ww),'-']);
xlabel('Rectifier Current Phase, \phi_1 (rad)')
ylabel('Slope of VC(t) at turn-on (Volts/ns)');
set(gca,'Xlim',[o1(end)-0.0001 o(1)]);
grid on;
drawnow;
end
figure(402);
legend('\omega-o/\omega-s=0.4','\omega-o/\omega-s=0.6','\omega-o/\omega-s=0.8'...
,'\omegao/\omegas=0.95');
figure(403);
8
...
legend('\omega-o/\omega-s=0.4','\omega-o/\omega-s=0.6','\omega-o/\omega-s=0.
,'\omegao/\omegas=0.95');
figure(404);
legend('\omega-o/\omega-s=0.4','\omega-o/\omega-s=0.6','\omega-o/\omega-s=0.8'...
,'\omegao/\omega_s=0.95');
D.3
MATLAB Script to generate Figures 5.15, 5.16, and
5.17
r = O(ws,wo) (ws./wo).^2./((ws./wo).^2-1);
-
153 -
Design Example MATLAB Scripts
X Capacitor Voltage
Vc
=
@(Vin,Vout,Pout,ws,wo,zo,oi,ki,t) ((-2*pi*wo/ws)*(Vin/2 ...
+zo*ki*wo*r(ws,wo)*sin(oi)/(pi*ws)+zo*kl*r(ws,wo)*cos(o1)*sin(wo*pi/ws)/(2*pi)...
+ws*sin(wo*pi/ws)*Vin/(2*pi*wo))*sin(wo*t)/(cos(wo*pi/ws)-1)...
-(zo*kl*wo*r(ws,wo)*cos(oi)/(ws)+Vin)*cos(wo*t)...
+zo*k1*wo*r(ws,wo)*cos(ws*t+o1)/ws+Vin)*(t<=pi/ws);
% Capacitor Current
Ic =
Q(Vin,Vout,Pout,ws,wo,zo,o1,ki,t) ((-2*pi*wo./(ws*zo)).*(Vin/2+...
zo*ki*wo*r(ws,wo)*sin(ol)/(pi*ws)+zo*k*r(ws,wo)*cos(o1)*sin(wo*pi/ws)/(2*pi)...
+ws*sin(wo*pi/ws)*Vin/(2*pi*wo))*cos(wo*t)/(cos(wo*pi/ws)-1)...
+(i./zo).*(zo*k1*wo*r(ws,wo)*cos(ol)/ws+Vin)*sin(wo*t)...
-k1*r(ws,wo)*sin(ws*t+ol))*(t<=pi/ws);
% Inductor Current
Il
=
Q(Vin,Vout,Pout,ws,wo,zo,o1,ki,t)
...
(Ic(Vin,Vout,Pout,ws,wo,zo,ol,kl,t) + Pout/Vout + k1*sin(ws*t+o1))*(t<=pi/ws)...
+(Ic(Vin,Vout,Pout,ws,wo,zo,oi,kl,pi/ws)...
-kl*sin(o1)+Pout/Vout+Vin*wo*(t-pi/ws)/zo)*(t>pi/ws);
X Transistor Current
Im = Q(Vin,Vout,Pout,ws,wo,zo,oi,ki,t)...
(Ic(Vin,Vout,Pout,ws,wo,zo,o1,ki,pi/ws)-k1*sin(o)+Vin*wo*(t-pi/ws)/zo...
-kl*sin(ws*t+ol))*(t>pi/ws);
% Derivative at switching
dVc = O(Vin,Vout,Pout,ws,wo,zo,oi,k1) (-2*pi*wo^2/ws)*(Vin/2+...
zo*kl*wo*r(ws,wo)*sin(ol)/(pi*ws)+zo*k1*r(ws,wo)*cos(oi)*sin(wo*pi/ws)/(2*pi)...
+ws*sin(wo*pi/ws)*Vin/(2*pi*wo))*cos(wo*pi/ws)/(cos(wo*pi/ws)-1)...
+wo*(zo*k1*wo*r(ws,wo)*cos(ol)/ws+Vin)*sin(wo*pi/ws)+zo*kl*wo*r(wswo)*sin(oi);
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX%XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
a = O(Vin,Vout,Pout,ws,wo,ol) Pout/Vin-Pout/Vout;
b = O(Vin,Vout,Pout,ws,wo,oi)
(1/pi ...
-wo.*r(ws,wo).*sin(wo*pi./ws).*cos(wo.*pi./ws)./(2*ws.*(cos(wo.*pi/ws)-1))...
+r(ws,wo).*wo.*sin(wo.*pi./ws)/(2.*ws)).*cos(o)...
+(-1/2 -
(wo./ws).^2.*r(ws,wo).*cos(wo*pi./ws)./(cos(wo*pi./ws)-)...
+r(ws,wo)/2).*sin(o1);
c =
Q(Vin,Vout,Pout,ws,wo,ol)
Vin*wo*pi./(4*ws) ...
-(pi*Vin*wo./(2*ws) + Vin*sin(wo*pi./ws)/2)...
.*(cos(wo*pi./ws)./(cos(wo*pi./ws)-1)) + Vin*sin(wo*pi./ws)/2;
d = @(Vin,Vout,Pout,ws,wo,oi) (-Vin/2 - ws.*Vin.*sin(wo.*pi./ws)./(2*pi.*wo))...
.*(sin(wo.*pi./ws)./(cos(wo.*pi./ws)-1)) - ws.*Vin.*(cos(wo.*pi./ws)-1)./(2.*pi.*wo);
e = @(Vin,Vout,Pout,ws,wo,o1) (-r(ws,wo).*wo.*sin(o1)./(pi.*ws)...
154
-
D.3
MATLAB Script to generate Figures 5.15, 5.16, and 5.17
-r(ws,wo).*cos(ol).*sin(wo.*pi./ws)/(2*pi)).*sin(wo.*pi./ws)./(cos(wo.*pi./ws)-1)...
-r(ws,wo).*cos(ol).*(cos(wo.*pi./ws)-1)/(2*pi)-r(ws,wo).*cos(o)/pi;
colorVec = 'brgmckybrgmckybrgmckybrgmcky';
styleVec = 'o+sdp';
Vin=12;
Vout=30;
Pout=7;
ws=2*pi*75e6;
wo=[0.4:.025:.975 .99]*ws;
% olvec=[-0.6 -0.8 -1 -1.2];
01=-1;
figure(400); clf;
a-s = a(Vin,Vout,Pout,ws,wo,ol);
b-s = b(Vin,Vout,Pout,ws,wo,o1);
c-s = c(Vin,Vout,Pout,ws,wo,ol);
d-s = d(Vin,Vout,Pout,ws,wo,o1);
e-s = e(Vin,Vout,Pout,ws,wo,oi);
f = e-s.*c-s./(b-s.*d-s);
X Closed Form Solution
XXXXXXXXXXXXXXXXXXXXXXXX
Iac = a_s./(bs.*(-f));
zo
=
-(1./Iac).*d-s./e-s;
C = 1e12./(wo.*zo);
L = 1e9*zo./wo;
subplot(1,2,1); hold on;
plot(wo/ws,L);
grid on;
xlabel('\omega-o/\omega-s')
ylabel('Inductance (nH)');
set(gca,'box','on')
subplot(1,2,2); hold on;
-
155
-
Design Example MATLAB Scripts
plot(wo/ws,C);
grid on;
xlabel('\omega-o/\omega-s')
ylabel('Capacitance (pF)');
set(gca,'box','on')
figure(402); clf;
figure(403); clf;
figure(404); clf;
for ww = 1:length(wo)
disp(['wo/ws: ',num2str(wo(ww)/ws)]);
X Need fundumental component
t = (0:200)*pi/(100*ws);
v_cap=[];
i_cap=[];
i_ind=[];
i_rds=[];
for tt = 1:length(t)
v-cap(tt) = Vc(Vin,Vout,Pout,ws,wo(ww),zo(ww),ol,Iac(ww),t(tt));
i-cap(tt) = Ic(Vin,Vout,Pout,ws,wo(ww),zo(ww),o1,Iac(ww),t(tt));
i-ind(tt) = Il(Vin,Vout,Pout,ws,wo(ww),zo(ww),o1,Iac(ww),t(tt));
i-rds(tt) = Im(Vin,Vout,Pout,ws,wo(ww),zo(ww),o1,Iac(ww),t(tt));
end
ePk(ww) = max(O.5*v-cap.^2*C(ww)*1e-12 + 0.5*i-ind.^2*L(ww)*le-9);
temp = cumsum(vcap.*sin(ws*t));
an = 2*temp(end)/length(t);
temp = cumsum(v-cap.*cos(ws*t));
bn = 2*temp(end)/length(t);
vfund(ww) = sqrt(an^2+bn^2);
phi(ww) = atan(bn/an)+pi*(an<o);
% Calculate
inverter loss here
capLoss-t = cumsum(i-cap.^2)/length(i-cap);
rdsLoss-t = cumsum(i-rds.^2)/length(i-rds);
[capLoss(ww) rdsLoss(ww) gateLoss(ww) bestWidth(ww)] =
optimization-v4(capLoss-t(end),rdsLoss-t(end),ws/(2*pi),C(ww)*1e-12);
Q = 10*sqrt(ws/(2*pi*1e6));
ACR = 2*pi*(ws/(2*pi))*L(ww)*1e-9/Q;
DCR = .01;
indLoss-t = cumsum((i-ind-mean(i-ind)).^2)/length(i-cap);
indLoss(ww) = indLoss_t(end)*ACR+mean(i-ind)^2*DCR;
invLoss(ww) = capLoss(ww)+indLoss(ww)+rdsLoss(ww)+gateLoss(ww);
-
156
D.3
MATLAB Script to generate Figures 5.15, 5.16, and 5.17
[wr-sol(ww) zr-sol(ww) iloss(ww) dloss(ww)] = ...
rectifiersolution(ws,Vin,Vout,Pout,vfund(ww),phi(ww),o1,O);
Lr(ww) = 1e9*zr-sol(ww) / wr-sol(ww);
Cr(ww) = 112 / (wr-sol(ww)*zr-sol(ww));
dvc-s(ww) = dVc(Vin,Vout,Pout,ws,wo(ww),zo(ww),oi,Iac(ww));
end
figure(402);
subplot(1,2,I); hold on;
plot(wo/ws,Lr);
grid on;
xlabel('\omega-o/\omega-s')
ylabel('Inductance (nH)');
set(gca,'box','on')
subplot(1,2,2); hold on;
plot(wo/ws,Cr);
grid on;
xlabel('\omega-o/\omega-s')
ylabel('Capacitance (pF)');
set(gca,'box','on')
figure(403);
subplot(1,2,i); hold on;
plot(wo/ws,Pout./(Pout + invLoss+iloss+dloss));
xlabel('\omega-o/\omega.s')
ylabel('Efficiency');
grid on;
set(gca,'box','on')
subplot(1,2,2); hold on;
plot(wo/ws,bestWidth);
xlabel('\omega-o/\omega-s')
ylabel('Device Width (\mum)');
set(gca,'box','on')
grid on;
figure(404); hold on;
plot(wo/ws,dvc-s*ie-9);
xlabel('\omega-o/\omega-s')
ylabel('Slope (Volts/ns)');
set(gca,'box','on')
grid on;
drawnow;
figure(405); clf;
-
157 -
Design Example MATLAB Scripts
plot(wo/wsePk*(ws/(2*pi))/Pout);
xlabel('\omega-o/\omega-s')
ylabel('Peak Energy Stored in a Cycle (normalized)');
set (gca, 'box','on')
grid on;
drawnow;
-
158 -
Appendix E
Experimental Prototype Design
I
S310
II
.
VOUT
Figure E.1: Experimental schematic of the power stage.
Osc
U2
Gate
Enable
Figure E.2: Experimental schematic of the gate drive circuit.
-
159 -
Experimental Prototype Design
Component
U1
U2
C1,C2
C3
CE
CE
LF,LR
D1
Value
CMOS Inverter
CMOS And Gate
100nF
10 pF
47 pF
4.7 pF
82 nH
100V, 3A
Part Number
NC7WZ04
NC7SZ08
GRM188F51H104ZA01D
GRM32DF51H106ZA01L
GRM1885C2A470JA01D
C1005COG1H4R7C
1812SMS-82N
S310
Package
SC70-6
SC70-5
0603
1210
0603
0603
MIDI Spring
SMC
Table E.1: Converter Bill of Material
Figure E.3: PCB top metal layout.
-
160
-
Manufacturer
Fairchild
Fairchild
Murata
Murata
Murata
TDK
Coilcraft
Fairchild
. .--
I
-
-
- I
- - -
--
--
.....
......
-
-
....
......................................
Figure E.4: PCB first inner metal layout.
Figure E.5: PCB second inner metal layout.
-
161 -
Experimental Prototype Design
Figure E.6: PCB bottom metal layout.
p
0
Figure E.7: PCB holes and vias layout.
-
162 -
Bibliography
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