CAMERA-MICROCOMPUTER INTERFACE
Helen Louise Graham
,>·
SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS
FOR THE DEGREES OF
BACHELOR OF SCIENCE
and
MASTER OF SCIENCE
at
the
MASSACHUSETTS INSTITUTE OF TECHNOLOGY
June, 1980
Signature of Author
.
Department of Electrical Engineering
and Computer Science, June, 1980
Certified by........
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ARCHIVES
MASSACHUSETTS INSTITUTE
OF TECHNOLOGY
JUN 20 1980
LIBRAP.ES
R C....el
n Graduate S1iudents
PAGE
1
CAMERA-MICROCOMPUTER INTERFACE
by'
HELEN LOUISE GRAHAM
Submitted to the Department of Electrical Engineering
and Computer Science
on May 23, 1980
in partial fulfillment of the requirements for the Degrees of
Bachelor of Science and Master of Science
in Electrical Engineering
ABSTRACT
A general interface was designed to receive an analog video
signal from a Reticon solid state line scanner containing an array
of 1723 photodiodes, process the signal, and pass it on to an SBC
80/20 single board computer via an Intel multibus. Processing on
the user via control words
interface is controlled by
board the
The user has a choice of eight
sent and received on the multibus.
levels (for
sixteen quantizing
three START pulses,
CLOCK rates,
operation, and gate
conversion), four modes of
analog to digital
of operation make it possible
The four modes
width and location.
1-bit digital
form or in
4-bit digital
to record video data in
the
record the addresses of
form
for each photodiode, or to
or to record the
photodiodes where black/white transitions occur,
The user also has
string lengths of black data and of white data.
a choice of three cameras from which to receive data.
the
different
in all
been
tested
has
The
interface
combinations of CLOCK, START, quantizing level, mode of operation,
Only one camera was
and gate width and location, and works well.
for the other two cameras were
used in the tests, but connections
tested out.
Thesis Supervisor:
Title:
Professor George C. Newton
Professor of Electrical
Engineering
PAGE 2
ACKNOWLEDGEMENTS
John Beltz for
I wish to express my deep appreciation to
directing my thesis
project and
for guiding and supporting me
being my thesis
through it and to Professor George C. Newton for
advisor.
I also wish to
thank
the following
people who
have
helped me out
in a myriad of ways - Dave Bortfeld, Harvey Hook,
Bill Weiss, and Larry Larson.
PAGE 3
TABLE OF CONTENTS
LIST OF ILLUSTRATIONS
I.
.
.
.
.
.
. .
.
.
.
... 7
.
... 12
GENERAL OPERATION OF THE CAMERA-MICROCOMPUTER INTERFACE
.15
INTRODUCTION.
II.
.....................
SOFTWARE CONTROL
VI.
.
. . . ..
. .
THE SBC 80/20
IV.
V.
..
THE RETICON UNIT.
III.
. . . . . . . . . . . . . . . . 4
. .
...............
... . . .
.
.
.
.
.
. .
.
VI-1.
CLOCK, START, CONTROL . .......
VI-2.
STROBEO
VI-3.
PREGATE/DIG VID . .
VI-4.
A/D . . . . . . . . . .....
. . .
VI-5.
PIXEL . .
.
.
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.
.. .
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. .
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..
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MACR . .
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.... . .55
.
.
CONCLUSIONS .
.
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. .61
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...63
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..........
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...
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. . . . . .. . .
APPENDIX. . . . . . . . . . . . .
.68
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. .76
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...79
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.. .85
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. .90
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... 95
...
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. .54
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.
..................
REFERENCES. .
.
.
.
... 23
.
.
..............
.
.
.. .52
STRING LENGTH AND TRANSITION MODES. ...
READ .....
VI-IO .
.
.
...........
VI-8. "A" MEMORY ADDRESS CIRCUITRY
VI-9.
.
.
. . . . . . . . . . . . . . . . . . . .
VI-6. and VI-7.
IX.
.
.
. . . . . . . . . . . . . . .
QAA-QHH . .
VIII.
.
.
DETAILED OPERATION OF THE INTERFACE . .
VI-0.
VII.
.
. 5
.
111
. . . . . .
.
. .
112
. .
.
. .
113
. . . ..
.
.
SCHEMATICS. .
. . . . . . . . . . . . . . . . . .
BOARD LAYOUTS
. . . . . . . . . . . . . . . . . . . 124
CABLE CONNECTIONS . .
GLOSSARY .
.
.
.
..................
....
. 113
126
.......
...
129
PAGE 4
LIST OF ILLUSTRATIONS
Fig. II-1
Simplified Schematic of Reticon Line Scanner . .
Fig. II-2
Reticon Photodiode Array Geometry. .
Fig. IV-1
Camera-Microcomput er Interface --- Block Diagram
.22
Fig.
V-I
Test Program
.29
Fig.
V-2
Status Control Reg isters
(SCR)
Fig.
V-3
Clock Selections .
.
Fig.
V-4
Port Addresses Use,d and Their Functions.
Fig.
V-5
A/D Calibration.
.
.
.
.
.
.
.
.
.
.
Fig.
V-6
Sample Outputs
.
.
.
.
.
.
.
.
.
Video Signal from Reticon . .
.
.
.
.
.
.
.
.
Chip and Pin Identifiers.
.
.
.
.
.
.
.
.
.
.
.
.31
.
.
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.
.
.
.31
.
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.
..
.32
.
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.
.
.33
.
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.
.34
.
.
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.
.
.45
.
.
.
.
.
.
.
.53
.
.
.
QAA -
Fig. VI-1
Clock, Start, Cont rol.
Fig. VI-2
Strobe0. .
Fig. VI-3
Pregate/Dig Vid.
Fig. VI-4
A/D Mode . .
.
.
Fig. VI-5
Pixel Mode
.
.
.
Fig. VI-6
Str.L Mode
.
.
.
.
106
Fig. VI-7
Str.L or Tran Mode
107
Fig. VI-8
"A" Memory Address Circuitry .
. . . . . . . . .
Fig. VI-9
Read . .
Fig.VI-10
Macr and Read
Sheets
1-11
.
.
.
and Their Content
Fig. VI-0
QHH.
. .
.
.
. 7
S . . . . . . 8
. . .
.
.
. . .
.
.
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.
100
. . . . . . . . . . . . .
101
.
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.
102
.
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.
103
.
.
.
.
.
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.
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.
.
.
.
.
.
104
105
.
.
.
Schematics .
108
.
.
.
.
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.
.
.
.
.
.
.
.
.
.
109
.
.
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.
110
.
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.
.
.
113
Board U Layout. .
.
. . . .
.
124
Board L Layout. .
.
. . . .
.
125
Cable Connections - J1,
J2, a nd J3.
. . . . . . . . . . . .
Cable Connections - Board-Cab le-Reticon .
. . . .
Multibus Connections .
.
....
.
.
.
.
.
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.
. . . .
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.
126
127
128
PAGE 5
I.
INTRODUCTION
of
interest
and are
two systems have
end,
To this
mechanization.
reader and a
- a matrix
in use
process
scanning unit.
Because of this common
proposed
that a
of
specialized hardware
the
In fact,
well as control.
between
SBC CPU
the
microprocessor located on the SBC
and of
to
choose the
to use, the
gate size
of which
control and
8080A
(an
via an
flexibility, as
digital data),
Communication of
was
the
systems
the four
of operation, all
four modes
and one of
explained later.
information
to connect
would be able to
the user
it
conversion of much
much greater
(for generating 1-bit
quantizing level
will be
a Reticon line
START signal, which of three cameras
CLOCK rate, the
and location,
of
each
the user
would allow
software and
in
they each,
board computer,
would make possible the
This
Intel multibus.
designed
a single
SBC 80/20,
to an
Reticon unit
inspection
software control,
interface be
general
In
feature and because of the
under
systems
have these
to
gun parts
inputs to and outputs from
at some point,
desire
reader.
thing in common -
These four systems have one
system.
already been built
slit width
and a
tab welder
a laser
development are
direction of greater
is moving in the
manufacturing process, RCA
the
during
control
quality
faster
and
better
Now, however, in the
inspection.
picture tube was done by visual
an RCA
parts comprising
quality control of
Until recently,
command
single-chip
8-bit
80/20 board) and the interface,
scan data, scanner status, and interface status between the
interface
and
the SBC
Input/output control
CPU,
would be
would
be
in the form
would be stored in special registers on the
and development of such
an
Intel
multibus.
of control
words and
via an
interface.
interface, to be used not
four above-mentioned systems, but also
The design
only by the
by future systems, was the
proposed thesis project and is the subject of this paper.
This paper is
being the first.
this
introduction
in Sections
II and III,
divided into nine sections,
Immediately following,
PAGE 6
the two main characters, without
whose contributions this project
would never have been born, are
introduced - the Reticon Unit and
the SBC 80/20 single board computer.
that
in Section
INTERFACE
IV
their
itself, can at
go-between, the
brought
into the picture
software, control the
this drama;
fashion.
this point,
Finally, in Section V,
and shown how he
interactions among the three
he is also
shown samples
them so
CAMERA-MICROCOMPUTER
last be presented, though, at
only in a general, block-diagram
the user is
Enough is said about
can, with
characters in
of the different
kinds of
outputs available to him.
Section VI
(which really
should be
read before
Section V)
gets down to the nitty-gritty and gives a blow-by-blow description
of the way the interface operates.
Each subsection of Section VI
deals
interface circuitry
with
a subdivision
of
the
a timing diagram of the same
associated with it
name.
and
has
(For page
numbers of the diagrams, see the List of Illustrations on page 4.)
To
fully
understand
Section
VI,
one
may
find
helpful
the
accompanying Schematics, Board Layouts, and Cable Connections, and
the Glossary,
IX.
The
all of which are
Glossary, which
(whose names
appear
with
points
in
the text
of
not only
lists most of the main signals
in
origin
all capital
and
letters), along
and
functions,
a
few
the Appendix are two other
Between Section VI and
abbreviations.
Appendix, Section
for understanding
is helpful
the entire paper,
this section but
their
located in the
sections - Conclusions (Section VII) and References (Section VIII)
-
whose titles speak for themselves.
Now, before launching into the body of this paper, the reader
should
take
note
exceptions, words
be found
having an
in the
of
With
a
few
are signal names and can
Glossary. (2) Usually,
but
final "/"
not
always, signals
are negative true
overbar or a final
and signals
true.
(3) The
- A21 and A21/
refer to
"/" positive
overbar and final "/" are interchangeable
the same signal.
(1)
points.
in all capital letters
overbar or a
without either an
the following
PAGE 7
II.
THE RETICON UNIT
The Reticon unit, chosen for its high degree of linearity, as
well
as
for
the
fact
unit
solid-state
Reticon RL-1728H
with
that
it
low power
is
a
small,
of
consists
requirements,
solid-state line scanner
TTL-compatible
and an
a
RC-100A series
circuit; however, other Reticon systems could be used as well. The
line scanner contains a row of
centers.
Each photodiode
capacitor, Cd, on which to
switch
for periodic
1728 silicon photodiodes on 15 um.
(see Fig.
II-i) has
its own
storage
integrate photocurrent and a multiplex
readout
via
an integrated
shift
register
scanning circuit.
CLOC
STAR
(•5V)
Fig. II-1
When the
SIMPLIFIED SCHEMATIC OF RETICON LINE SCANNER
switch is turned
which includes the
(dotted line
on, once
photodiode and its parallel
delineates one cell),
the cell,
during each scan,
is
storage capacitor
charged to 5
volts (since
the VIDEO-CP line is virtual ground), and approximately 1.8 pcoul.
is stored on its capacitance.
the
charge
on the
capacitor
The
is
switch is then turned off, and
gradually removed
by
reverse
PAGE 8
This reverse current consists
current flowing ih the photodiode.
of dark leakage current, which at room temperature amounts to only
about I pA
photocurrent, which is
and thus can be neglected, and
The amount of
proportional to the light intensity
or irradiance.
charge removed from the cell during
line scan time is the product
of the photocurrent and the line scan time.
is
replaced via
the
VIDEO-CP line,
which
amplifier circuit (not shown), when the
per scan.
one at
All 1728 cells function
is
connected to
an
cell is sampled, one time
are sampled
the same way and
consecutive fashion
a time in
This amount of charge
at the CLOCK
Thus,
rate.
1728 cells are tied into the VIDEO-CP line, the VIDEO-CP
since all
output is a series of
1728
charge pulses each proportional to the
light intensity on the corresponding photodiode.
The RL-1728H array also has a
Each dummy diode is sampled
photodiode
differentially with its corresponding
to eliminate
so as
row of 1728 dark dummy diodes.
switching transients
and thus to improve
multiplex switches
due to
the quality of
the
the video
signal.
The array
geometry is
as follows,
with the
darkened areas
representing the bar-shaped photodiodes.
F- -b- - M
I
,,
J"
-
a = photodiode width
=
7 um.
b = photodiode spacing
=
15 um.
c = aperture width
= 16 um.
Ck
I
2
Fig. II-2
The entire
RETICON PHOTODIODE ARRAY GEOMETRY
aperture is photosensitive, so
between photodiodes.
some light
will fall
Photocurrent generated by such light will go
PAGE 9
to the nearest diode.
the RL-1728H I ine
The spectral responsivity and uniformity of
scanner are excellent for
is the type of
light used.
required light
intensity and scanning speed.
One element
presence of
dark
There is,
influencing
dark current,
leakage
cancellation
diodes, and
current,
(2)
a
comprised of
fixed
to
sensing and
on noise bandwidth and preamplifier
(1) is significant
Dark leakage current averages out
0.5 pA per diode
at room temperature and
1.8 pcoul.
If the
dark leakage
line scan
contribute about
time were
1%
40 ms.,
of the saturated output
also affects the dark current, causing it
in temperature,
shorter.
dark current
so at
is
drive and
higher
Looking at
level ratio
noise level ratio
All
less than
for unprocessed video and (3)
yield the saturation output c harge of
should be
dummy
(depending
to be about
rise
incomplete
(2) accounts for
0.5% of the saturated output signal
used), but
speed is the
(1) integrated
pattern due
t ransients between
(3) random pixel noise.
for less than 0.1%
however, a tradeoff between
the choice of scanning
w hich is
of switching
visible light, which
in four seconds.
signal.
current would
Temperature
to double for every 70 C
temperatures scanning
dynamic range, the
is 200:1,
1000:1,
thus would
while the
times
saturated
saturated to
to
rms
for unprocessed video.
amplifier
circuitry
needed to
operate
the
RL-1728H line scanner is contained on two printed circuit boards an
RC-100A
generators,
motherboard,
a blanking
that contains
circuit, a
clock
and
start
pulse
sample-and-hold circuit,
and
some buffer amplifiers; and an RC-108 array board, that contains a
socket
for
which is
package
clock
the array
(in
packaged in a
with ground
this case,
22-lead dual-in-line
and polished
driver circuits,
and a
of charge
pulses, and
boxcar video signal, put out on
for one CLOCK period.
line scanner,
integrated circuits
windows), along
optical
preamplifier.
circuit takes the VIDEO-CP output of
train
the RL-1728H
The RC-100A
with
series
the line scanner, which is a
converts it
to a
sampled-and-held
P2-N, with each sample being held
PAGE 10
The RC-100A motherboard contains
with frequency range depending on
and the
pot.
particular frequency
an internal clock generator
the selection of two capacitors
depending on the
The range 300 KHZ to 2 MHZ was chosen, as
and the
only one
ranged
including 500
from 300
anyway by
too slow
other clocks generated
motherboard
clocks
KHZ down,
KHZ and
also provides
generated
constraint
on
the
up.
a pulse
All
other choices
uses and
by the interface.
for an
external clock
interface
can
width between 20
a 50K
it was the fastest
for most
on the external clock is that
pulse with
setting of
be
covered
The RC-100A
input,
used.
so
The
the
only
it be an active high TTL
ns. min.
and 200
us. max.
This allows for square-wave clocks with frequencies ranging from 5
KHZ to 50 MHZ.
However, as will
be seen later, the interface can
handle frequencies only as high as 576 KHZ.
and external clock
used.
choices ranging from 9
The only adjustment
To use the internal
internal clock out
for the
needed is
KHZ to 576 KHZ
jumper El
to
on P2-C to the interface as
in use).
must jumper El
internal
can be
the jumper connection to El.
clock, one must
particular camera
interface, one
Thus all the
To use
to E3
E2 and send the
RCLOCKx (x stands
the CLOCK
from the
and receive CLOCK
from the
interface on P2-Z.
A similar
situation exists
motherboard has an
external
start
4-bit
pulses.
internal start generator, but
pulse
generation, E5
for start
to
be
would normally
rocker switches
set
sent
in.
be jumpered
to the
count
Instead E5
is
jumpered to E6,
internal
start
to E4
and the
three
desired between
start
rocker switches.
is
and E4
connector, and then sent to the
number of the camera
any count, up to
The minimum
1736 (min. count
as for external operation,
RSTARTx (x being the
With this arrangement,
provides for an
elements in the array) and 4096.
connected to P2-F, an unused edge
interface as
RC-100A
For
pulses; this count could be any number between
eight greater than the number of
The
count of
start pulses can be sent while a scan
is
4096,
1736,
can be put
needed so
in progress,
in use).
on the
that
no
is no longer
PAGE 11
a constraint
because interface circuitry
pulse to be generated except during
or., countwise, the count
minus the
number of elements
in
a START
the blanking period (the time
between the last element of one scan
next scan
will not allow
and the first element of the
of the start
pulse generator
the array), when BLANK
is high,
and then only when the computer has finished its processing.
BLANK signal,
scan time,
which is high during
is sent via
example, set
the count
where computer
scan.
P2-D to
blanking time and
the interface.)
at a small
number like
processing time varies
(The
low during
One
might,
3, for
for
the case
considerably from
scan to
This way a START pulse can be generated as soon as possible
after processing is finished, whenever
that happens to be, rather
than having to wait the maximum amount amount of time likely to be
needed for
processing before
optimum operation,
sending another
the count
should be such
doesn't exceed 40 ms. - this
integration time
plus 50
with a minimum
ns. and
it envelopes
and sent to
is because dark current
scan time
increases as
start pulse is used, it must be an active high
a maximum
period, synchronized
that
that the
For
increases.
If an external
TTL pulse,
START pulse.
P2-A.
pulse width
pulse width
with the
of one CLOCK
of
less
than one
negative-going edge
one and only one positive
In practice, a
CLOCK
of CLOCK,
so
transition of CLOCK,
START pulse equal
one CLOCK period was used successfully.
pulse width
in
width to
PAGE 12
III.
THE SBC 80/20
The SBC
80/20, a single board
complete computer
system on a
that plugs into an Intel
CPU,
system
clock,
memory, I/O
interval timer,
drivers.
card cage.
memory,
drivers, serial
80/20 was
it was
selected
the standard
is a
circuit
card
Included on the board are the
non-volatile
read-only
communications
interface,
interrupt controller, and
The
because
6.75x12-inch printed
read/write
ports and
computer made by Intel,
for
bus control
use with
system in
logic and
the
use and
interface
because
it
was
immediately available.
The CPU is
an 8-bit
n-channel MOS
8080A microprocessor with
six 8-bit
general purpose registers, addressable
in pairs,
and an
counter, so 64K
accumulator.
8080A has
a 16-bit
bytes of memory can be addressed
16-bit
stack pointer
stack,
locatable
interfacing
The
individually or
to
in
memory
address
any
an external
portion
or
I/O,
of
directly, and a
last-in-first-out
memory.
sixteen
program
Finally,
address
and
for
eight
bi-directional data bus lines are provided.
Working with
generator and
generate
the 8080A
an 8238 system
address and
ports both
control processor
on board
interrupts from
memory or I/0
controller.
control signals
and external
on board
or off,
Together,
to access
to the
8224 clock
these three
memory and
SBC 80/20,
respond
devices, fetch and execute
provide a stable
is an
to WAIT
I/O
respond to
requests from
8080A
instructions, and
timing reference for all other
circuitry in the
system.
Functioning
which
interface,
of the
includes
flip-flop, bidirectional
the Bus
signals.
Clock (BCLK/,
a
taken care
bus
P1-13) and
generates necessary
gates addresses
of by
controller,
bus drivers, and circuits
Constant
bus controller arbitrates
The
system bus,
bus is
I/O or
onto the address lines
Clock
a system
an
bus
override
that generate
(CCLK/, P1-31)
requests for use
memory command
and data onto and
of the
signals,
off of
PAGE
the data
lines of the system
bus,
synchronously with
13
respect to
the Bus Clock.
As for
memory, the
using Intel's
memory,
write
SBC 80/20
2113
has 2K
8-bit words
static
RAM'S, on
of
read/
board
and
sockets for up to 8K 8-bit words of non-volatile read-only memory.
If 8708
8308 metal mask
EPROM'S and/or
each adding
of memory,
1K bytes
Intel's and
ROM'S, both
are put
four available
in the
sockets, only 4K 8-bit words of on-board read-only memory capacity
provided.
can be
However,
ROM'S, both
or 8316
if 2716 EPROM'S
Intel's but each adding 2K bytes, are used, then 8K 8-bit words of
on-board read-only memory can be provided.
When the interface was built, an
an
80/20.
80/20-4 functions
The
80/20 does, but
80/20-4 was used instead of
same way
essentially the
the
it provides 4k 8-bit words of read/write memory by
There are other
using Intel 2114 memories in place of the 2113's.
differences, but they
they don't affect
won't be mentioned since
the functioning of the interface system.
The SBC 80/20 has two
USART
(Universal Synchronous/Asynchronous
which is
a programmable serial
interval timer,
8253
rate generator,
three features is
but
one-shot, as a
can be
None of
wave generator.
the interface
programmed to
these
the present time,
advantage of
may take
The interface does, however, make use of
controller, which
and an
communications interface;
utilized by the interface at
applications of
future
them.
a square
8251
Receiver/Transmitter),
which can be programmed as a
or as
interface
lines; an
I/O
programmable parallel
providing 48
devices
8255 programmable peripheral
the 8259
operate
in
to any
one of
interrupt
any of
four
different modes.
The SBC
80/20 RAM
address blocks (within
the
end
of
the
can be assigned
the 64K address space) and
chosen block.
The
first
will reside at
was
block
arbitrarily, so RAM occupies locations 3000H-3FFFH.
four 16K
chosen,
ROM/EPROM, on
the other hand, always begins at memory location zero.
I/O port addressing
includes the following dedicated ports:
PAGE
D4 - Power Fail
D5 - System Bus Override
D6 - LED diagnostic indicator
D7 - (not
used, but not available to the user)
D8-DB - 8259 Interrupt
Controller
DC-DF - 8253 Interval Timer
E4-EB - Two 8255 Programmable Peripheral
Interface Devices
EC-EF - 8251 USART
Other ports are available to the user for his own use.
14
PAGE 15
IV.
GENERAL OPERATION OF THE CAMERA-MICROCOMPUTER INTERFACE
Block Diagram
the
IV-1,
the
of
CAM2, and CAM3
and will
Fig IV-1)
Fig.
Camera-Microcomputer Interface,
on page 23 and to the Glossary on page
start with CAM1,
to refer to
section, the reader may wish
While reading this
Discussion will
129.
the upper left-hand corner of
(in
SBC 80/20 along
trace the flow through to the
the right edge.
CAM1,
three separate Reticon camera
CAM2, and CAM3 represent
units, all connected to the interface board.
The Camera Director,
under software control via a status register, broadcasts the START
and
CLOCK
interface
RCLOCKx,
pulses to
only
the
where x
or three
three
cameras,
four outputs
is
That's the
camera.
all
the chosen
(VIDx,
CAM's
ideal situation.
cameras could
have their
wired together once
four signals more than
number)
outputs are
outputs are
and
Reticon
however, two
at
the
same
from the three cameras are
enabling switches, the
enabled,
as
are invalid if
If,
enabled.
on the
the case
is
initialization procedures, there is no problem
signals
RSTARTx,
outputs enabled
they pass through the
one camera's
the
of one
VIDEO, BLANK, RSTART, and RCLOCK -
no camera's
hand,
BLANKx,
onto
In actuality,
Since the corresponding outputs
time.
but allows
other
during
- none of the four
is generated.
The CLOCK signal sent out to
the three cameras is the output
of the Clocks Generator and CLOCK
Selector, which takes the 9.216
(CCLK/, P1-31)
multibus and divides it down to
MHZ Clock
from the
make available seven clock
KHZ, 36 KHZ,
rates - 576 KHZ, 288 KHZ,
18 KHZ, and 9 KHZ.
144 KHZ, 72
In addition to these, RCLOCK, the
Clock signal coming from the designated camera, is also available,
so the user has eight clocks from which to choose.
to
accommodate the
existing systems
width reader, and gun parts
of at
least 500
-
the
matrix reader,
slit
inspection system require pixel rates
KHZ, so the 576 KHZ rate will
the laser tab welder
This is enough
is happy with the 144 KHZ
take care of them;
rate.
The chosen
PAGE 16
CLOCK signal, a TTL
signal,
is an inverted, delayed, level-shifted
version of the CMOS signal fB.
CLOCK and gB are sent to the
Both
Control Logic area of the interface.
The START
signal sent to the
area is
Control Logic
START Generator. The
pulses - RSTART,
and
60
the output
of the
which comes from the
COMP.START
is
The 60 HZ START
is
at a rate of
three START
the
COMP.START
interface by
sent to the
Generator, on the other hand, uses
the line voltage to generate a signal,
(i.e.,
and
chosen camera, COMP.START,
generated by
a CPSTART signal
Generator whenever
to the
PRESTART Selector
PRESTART Selector chooses among
HZ START.
the computer.
three cameras and also
60 HZ START, every 8.33 ms.
120 HZ).
Two other signals coming from the chosen camera are BLANK and
VIDEO.
low just before the first piece
BLANK goes
arrives at
the
interface and
high just
of VIDEO data
after the last
piece of
VIDEO arrives, so it signals the beginning and end of the scanning
VIDEO is the signal
period.
of
interest and is the one processed
by the interface.
first of all,
VIDEO passes,
control)
circuit that
through an AGC
adjusts its swings so that
ANALOG VID with a 0-+1 volt swing.
a 4-Bit
signal
A/D Converter that
a 4-bit digital
converts it
it is accepted by
from a 0-+1
then this
Latches.
every time
of
all four latches
fourth CLOCK period, these
every
are stored
in one
4-bit Data for each photodiode
latch, and
i.e.,
stored
Data.
volt analog
chosen A/D mode (meaning that he wants gray level data),
be
4-bit
comes out as
user has
Data will
signal,
it
If the
4-bit
to
In this formn
(automatic gain
the
four 4-Bit
3-State
is stored in a different
have received
new data,
sixteen bits of
new data
in memory as A/D Data.
4-bit Data coming out of the 4-Bit A/D Converter is also sent
to
the 4-Bit
Magnitude
Comparator
compares the 4-bit Data to a
user and
yields a 1-bit
VID.
the user desires
If
and Latch.
The
comparator
4-bit quantizing level chosen by the
digital value
a 1-bit
that gets latched
digital video value
as DIG
for each
PAGE
17
photodiode, in which case he will have designated PIXEL mode, then
DIG VID will be shifted
Every
time
sixteen
into the 16-Bit Shift-and-Store Register.
DIG VID
consecutive photodiodes)
stored
there, these
values
have
(corresponding
been shifted into the
sixteen bits
memory as PIXEL Data. Thus PIXEL
will
be taken
to
sixteen
register and
and stored
in
Data gets stored in memory every
sixteen CLOCK periods.
DIG VID
also passes
unit, which
state,
into
a TRANSITION Detector
monitors the DIG VID
i.e.,
a transition.
and Control
signal and signals a
If TRAN
arrival of a transition will cause
mode has
change of
been chosen,
the
the address (held in the STR.L
or TRAN counters) of the first photodiode after last photodiode
a string of photodiodes of the
in
same state, along with information
indicating which camera and which memory were in use and the state
of the video signal of the just-completed group of photodiodes, to
be stored
in four 4-Bit 3-State
Latches.
These sixteen
bits of
TRAN Data will then be transferred to memory during the same CLOCK
period in which the transition was detected.
STR.L mode
operates
in
the same
except that instead of storing the
in a group
it stores the number
way that
counting for
the next
during the
same CLOCK period as
that
transition occurs
if a
counter will be set to 1.
does,
address of the last photodiode
of photodiodes in the
then resets the STR.L or TRAN counters
to start
TRAN mode
to zero, so they are ready
group.
The
counters are
the occurrence of
during
group and
the next
reset
TRANSITION so
CLOCK period
the
This makes it possible to give accurate
string lengths even when a transition occurs every CLOCK period.
Now that
we've seen how the
let's compare their
bits can
hold PIXEL
four data modes
relative advantages.
Data for sixteen
four photodiodes, TRAN Data for one
one
string.
Thus,
changed state every
much space
to record
if the
digital
Note that
sixteen data
photodiodes, A/D
Data for
transition, or STR.L Data for
video signal
CLOCK period, it would take
this in TRAN
are generated,
mode or
in
were one
that
sixteen times as
STR.L mode
as
in
PAGE 18
PIXEL mode.
If, on the other
hand, the digital video signal were
to change state less frequently
it would
record
take less
than every sixteen CLOCK periods,
space to record
PIXEL Data.
Thus, for
frequently, PIXEL mode is more
TRAN or
STR.L Data
digital data
economical,
than to
that changes
state
spacewise, whereas for
digital data that changes state
infrequently, either TRAN mode or
STR.L mode
Data in any of
can be
is
more economical.
converted into either
however, is
of the
different - it stands
gray-level data, providing,
is useful when
one wishes to see
derived from
other two forms.
alone as the only
as it were, sixteen
Data can be converted to any of
can't be
these three modes
A/D mode
provider of
gray levels, and
fine detail. The fact
that A/D
the other three forms of data but
them makes
it, perhaps,
the most
useful
single data mode.
The sixteen
bits of data for
A/D mode, for PIXEL
mode, and
for TRAN or STR.L mode are wired together and to the inputs of the
appropriate memories.
modes
can have
For
proper operation only one
its selector
bit
in the
of the four
status register
high.
There is no protection against the user's setting more than one of
these mode
selector bits high causing
confusion not only
on the
sixteen data lines, but also elsewhere in the interface circuitry.
On
the other
hand, the
selector bits
remain
at
high, in
high
user might
set
which case the
impedance
and no
none of
the four
sixteen data
new data
would
mode
lines would
be stored
in
interface memory.
The interface memory just mentioned
sets of memories any one
the "A"
Memories and the "B" Memories.
scan/process period,
having scan data (in
the other set
during the
all of this
one of
of memories
actually consists of two
one of
its
data that was written
into the
computer.
are two sets of controls, the
which generate
memory addresses, write
for the write cycle; and the
of memories
is
four forms) written into it while
is having
previous scan, read
these sets
During
into it
Coordinating
Memory Write Controls,
pulses, and
chip selects
Memory Read Controls, which generate
PAGE 19
memory
addresses, read
cycle.
At the beginning of
each scan/process period the memories
switch roles so that during
that scan/process period the memories
that were
written
and the memories
be written
signals, and
into during the
chip selects
last period will
that were read from during the
into.
The
for the
Mux directs signals
Controls and the Memory Write Controls
be
read
read from
last period will
from the
Memory Read
to the proper memories for
each scan/process period.
When the computer wants to
it
executes an
IN
(Hexadecimal) on
this
address
read from the interface memories,
86H command,
the address
and sends
i.e.,
bus.
it
to
The
the
the same time.
The
the memories and
Transceivers also
are
read by
possible for one
its
outputs
88H
Address Decoder
P1-21)
to pass it on
command.
all
decodes
area,
which
from the bus controls
Memory Read
to the data
two status
At
any
the
rest
one time
will
bus.
The
registers, which
pair of memories or one status
enabled;
86H
enables the Transceivers to receive
receive data from
an IN
the number
Control Logic sets the
Controls into action and also
data from
puts
Control Logic
receives an I/O Read Command (IORC/,
at about
it
it is
only
register to have
have
their
outputs
disabled, so there can't be contention on the data bus lines.
When
the computer
wishes
commands to the interface,
Five registers must
before the first
properly.
The
to
send control
information
it does so by executing an OUT command.
receive control
information from the computer
scan begins in order for the
five registers
and the
system to function
control
information
hold are:
Register 0 -
or
CLOCK and START Selector bits
Register 1 - 4-bit Quantizing Level and
4 Mode Selector bits
Register 2 - 8-bit Start Gate
Register 3 - 8-bit
End Gate
Register 5 - Camera Selector bits
they
PAGE 20
(The Register number corresponds to the second digit of the output
port that
must be addressed in
order to load that
first digit being the arbitrarily chosen
to
load Register
executed;
0,
for example,
base address of 8.
an OUT
80H
Thus
command must
be
for Register 1, an OUT 81H, etc.)
The choices available
been
register, the
discussed.
to Registers 0, 1, and
Register
2
contains
an
5 have already
8-bit
Start
Gate,
corresponding to the upper 8 bits of the 12-bit photodiode address
of the first photodiode whose video
the user.
Similarly, the End Gate
the upper
8 bits
photodiode of
of the
interest.
with only the
PIXEL Data left
(in
Because the Start
multiple of
the
16.
is of
interest to
Register 3) corresponds to
12-bit photodiode
upper 8 bits of
will always be a
information
address of
Gate and End Gate deal
12-bit address, the
Thus there won't
dangling when the last
the last
Gate area
be any A/D or
16 bits of data are stored
in memory.
The Photodiode Address Counters feed
Detectors (as can be
End Gate
feed their results
than the
seen on the Block
Diagram), which
into the PREGATE Detector and GATE's Generator.
PREGATE marks the GATE area;
eight bits of
into the Start Gate and
it remains
high as long as the upper
the the photodiode address contain
Start Gate and
smaller than
a number larger
the End Gate.
The GATE's
Generator synchronizes PREGATE to
CLOCK and generates four GATE's
that
second, third, and fourth CLOCK
follow PREGATE on the first,
These
pulses
thereafter.
Memory
Write Controls
GATE's
so that
are
a given
used to
the
synchronize
piece of
video data
is
matched up with the correct photodiode address.
At this point, a few words should be said about
data that can be
stored for each of the four
the amount
of
modes of operation.
As mentioned before, during one scan four memories, either the "A"
Memories or
the "B" Memories, are
Since each memory has space for
used for recording
storing 255 4-bit words
scan data.
(location
0 is not used), 255 16-bit words may be stored for one scan.
means that
in PIXEL mode the
memories can store a
This
1-bit digital
PAGE 21
video value for 255 x 16 or 4080 photodiodes.
Since the array has
only 1728 photodiodes, the whole scan may be stored in PIXEL form.
For A/D
mode, each
address
records
photodiodes.
a
4-bit
Thus the
photodiodes.
designate a
group of
happy with A/D
STR.L modes both
these
of
to
1020
plus
the
value
operate in
for
17,
memories
1020
each
transitions or 255 photodiode groups.
of
four
for only 1020
mode
less,
as we shall see
store
one memory
one
or
must
else be
photodiodes starting from
one transition.
can
A/D
photodiodes or
use all sixteen data bits at
information about
modes
stored at
memories can store A/D Data
Data for the first
the Start Gate address
to store
digital
Consequently,
Gate area
sixteen bits
later.
TRAN and
one memory address
Thus,
information
in
either of
about
255
A/D DATA
(MULTIBU
ADDRESS
DECODER
FIG IV-I
CAMERA-MICROCOMPUTER
INTERFACE ---
A
Ru]
ES
Es
S
gS
BLOCK DIAGRAM
fT1
PAGE 23
V.
SOFTWARE CONTROL
Software control will
(pages 29
and 30),
one of
system.
During the
signals
generated by
signals
are described
Those signals
be explained by referring
the programs
their corresponding
in
check out
discussion reference will be
the computer
in the
and/or
by interface.
129).
along
with
page
123),
outputs (see
Fig. V-4 on page 32.
These
on page
computer are listed,
Port addresses, L41
the
made to several
Glossary (starting
generated by the
and functions,
used to
to Fig. V-1
(For best understanding,
one should read Section VI before Section V.)
The
boards,
"BB,"
program
shown
fills the
and then
scanning is
SBC 80/20
other set of
V-1
computer reads
and processing
interface memories during
which point
with
While
interface
loaded
into the
the previous scan into the
When
scanning and
locations 3000H-31FFH are reloaded
period begins.
until the interrupt
the user may
set of
was
location 3000H.
and another scan/process
processing continue
interface
in motion.
in one
the data that
processing are both completed,
the
locations 3000H-31FFH
storing data
memory starting at
with "BB"'s
initializes
memory
sets scanning
in progress,
memories, the
SBC 80/20
in Fig
display the
memory locations 3000H-31FFH to see
Scanning and
switch is
depressed, at
contents of the
the most
SBC 80/20
recent data. (Sample
outputs are shown in Fig. V-6, pages 34 through 51.)
On
lines 16
interrupts I
17,
the interrupt
and 4. Interrupt
and interrupt
GATE area
and
4 the
has been
Any time after
signal
of an
may send a
PROC.COMP. signal
processing
the
memories.
that
is the manual
indicating that
processed and
the arrival
data
1
interrupt
is
just
this isn't a problem
enable
switch interrupt,
the desired
interface memory.
request, the computer
to switch the memories
was
set to
data in
recorded in
The scan during which that
be finished, but
mask
stored
in
and to start
the
interface
data was stored may not yet
since no more data
can be
written into the interface memories, once the gate has been closed
PAGE 24
and interrupt 4
scan.
sent,
until the gate opens again
The next scan can't begin,
during the next
however, until the present
scan
is finished because the generation of the START pulse to start the
next scan can occur only when
BLANK is
is finished - BLANK goes high at
until
the next
scan begins),
the
high (i.e.,
after scanning
end of a scan and stays high
'unless
a PREBLANK
signal, to
be
explained later, is sent by the computer.
To initialize
all,
sends
request;
the interface boards,
out a
sets
RESET
PC and
signal.
the computer,
RESET
PCSYNC low blocking
sends an
sets COMP.START low;
loads the
counters with
zeros
for scanning;
GATE's
low and
all the
GATE/'s
interrupt
the generation
START pulses;
in preparation
first of
high, also
4
of any
photodiode address
resets
all the
in preparation
for
scanning; resets the outputs of Control Status Registers 0, 1, and
5 low, blocking
of the
the selection of the camera, of
quantizing level,
and MEMA
43SEL, 21SEL,
PIXAD.
and of
low;
the mode
the start pulse,
of operation;
and disables the
resets
counter generating
With all Mode Selector bits low, no writing operations can
take place, and
take place.
preparing
another
with 43SEL and 21SEL
low, no
read operations can
Thus, RESET disables read and write operations, while
various
scan.
counters
The
576
KHZ
and flip-flops
for
the way,
clock, by
the
is
start
of
selected
by
default when RESET is sent.
Lines
19-28 hold the instructions for loading the five Status
Control Registers - 0, 1, 2, 3, and 5, which must all be loaded at
the order
time, though
this
matter.
The bit
Fig. V-2 ("-"
binary
shown in
don't
care),
Fig.V-3, page
0 -
F2,
selects the
31.)
are the
S3,
F1,
Reticon start
and
CLOCK.
S2, and
are shown in
FO comprise
signal; SI
a 3-bit
(CLOCK selections
SI -
Start Selector
COMP.START, a computer-generated start
the internal
doesn't
page 31.
Register 0,
number, which
Control Register
are loaded
which they
configurations for these registers
means
Starting with
in
also
bits.
in
$3
are
Status
selects
signal; S2 selects RSTART,
selects 60 HZ START, a start
PAGE 25
signal
generated from the line voltage.
three bits must be set high.
can be
generated.
high, meaning
On
If
One and only one of these
none is set high, no START pulse
the other hand,
more than one switch
if more
than one
feeding the same
is set
output
line
(STCMOS) is closed, there will be confusion on this line, which is
sent
to generate the START pulse.
In Register I,
number
that selects
conversion of
video
Q3, Q2, Q1,
one
of
the 4-bit
value.
The
quantizing level
names.
are the
sixteen
quantizing
digital video value
range
is shown
of
voltages
a 4-bit binary
levels for
to a
the
1-bit digital
corresponding
to
each
in Fig. V-5, page 33.
The other four bits
STR.L -
and QO constitute
I -
in Register
Mode Selector
-
bits for
PIXEL,
A/D, TRAN, and
the modes
of the
same
As with the Start Selector bits, one and only one of these
mode selector bits must be set high.
If none is set high, no data
will be written into the interface
memories.
set high,
all
various strange things,
If more than one is
undesirable,
will happen,
what exactly, depending on which specific bits were set high.
Registers 2
addresses
and 3
hold the
delineating the
8-bit Start
GATE, or
Gate and
window, area
End Gate
for the
data.
These addresses actually correspond to the upper eight bits of the
12-bit
photodiode address,
so the
GATE
area will
always be
a
multiple of sixteen, as mentioned before.
In Register 5,
bits.
CAM3, CAM2, and CAMI are
As with the Start and Mode
the Camera Selector
Selector bits, one and only one
of these three Camera Selector bits must
be set high. The other 5
bits of Register 5 are no longer being used.
Continuing on with the program
now that the interface boards
are ready for action, a PREBLANK signal
possible the generation
high,
just
in
case
of a Start signal,
the BLANK
signal
interrupts are disabled (line 30) while
(GC)
is reset to
is sent
are loaded with
setting BLANK GATE
powered
up
low.
Next,
a Gate Complete test byte
0 (Lines 31 and 32), while
locations 3000H-31FFH
by
(Line 29) to make
"BB"
the SBC 80/20 memory
(Lines
33-46), while
PAGE 26
PROC.COMP./
and
CPSTART are sent to
48), and
while interrupt
enabled.
The
1 is
PROC.COMP./
be done between
loads the
photodiode address
interface (Lines
disabled leaving only
signal
that must
the
does
interrupt 4
the resetting
scans to prepare
and setting
for a new
counters with
47 and
scan.
zeros, switches
It
the
memories, clears all four memory address counters to zero, removes
the interrupt
4
high, so,
sets PCSYNC
high, all is
is sent
request, and sets PC high.
since GATE4/
The
and BLANK
ready to generate a START pulse.
to the
interface, and if
then a START pulse will
next
GATE are
If not,
already
CPSTART (Line 48)
COMP.START has
be generated.
CLOCK pulse
been selected,
a START pulse will
be generated when the selected start pulse (either RSTART or 60 HZ
START)
is generated.
this time so
still
1 is disabled (lines 49 and 50) at
that a scan can't
open,
Interrupt
Interrupt
i.e.,
while
be interrupted while the
write operations
are
gate is
still going
on.
4, only, is enabled.
The first
sending of
step in the processing
an OUTRAN signal
to the
of the previous scan is the
interface (line 56)
to read
from a status register the last memory address written into during
the
previous scan.
number out to
needs
to
instructions
on Lines
the terminal using a Monitor
Since the computer
it
The
now knows how many
read,
instructions (lines
memory
via port
3000H.
Port 86H
it
proceeds
to
SBC
do
routine called NMOUT.
so
by
executing
the data
80/20 memory
is read twice
this
interface memory locations
60-72) for bringing
86H to
57-59 send
the
from interface
starting at
location
for each interface memory location
filled because the multibus has only eight data lines and thus can
bring in
memory
only eight of
location
the sixteen data
at one
time.
When
bits stored at
all
locations written into during the previous
READ
COMP./
signal
(line
73)
already low).and 21SEL to 0 to
from are
disabled from
is
during that scan/process period.
interface
memory
scan have been read, a
sent to
assure that
being read from
the
a given
set
43SEL (which
the memories just
or written
is
read
into anymore
PAGE 27
At this point, computer processing is finished, so
are disabled and
If
74-77).
data into
will
the Gate Complete test byte
GC has been
set to FF,
to NEXT,
Preparations
line
include
30,
meaning the writing
to
resetting GC
memory locations 3000H-31FFH
prepare
to zero,
with "BB"
of scan
went high
one CLOCK after
high (meaning BLANK
a START
RSTART, or
Selector bit
so
if BLANK
has gone high indicating the end
be
START is
high (it
generated when
GATE is
of a scan),
the next
generated, depending
CPSTART,
on which
Start
is set.
1
and 4
chosen for user
finished
interrupt 4
time GATE4/ will be
If the check on line 76 shows GC has not
interrupts
80/20
remove the
INT4/ was sent),
signal will
60 HZ
reloading SBC
the memories,
counters to 0,
By this
scan.
0, switch
memory address
PC high.
next
PROC COMP. to
counters to
request, and set
for the
and sending
photodiode address
clear all
then
(GC) checked (lines
interface memories has been completed, then the computer
jump
set the
interrupts
are enabled
been set to FF, then
(lines 78-80).
(This point
interrupts because at this time
reading
data
from
the
interface
is
the computer has
memories
into
its
on-board memories, so the data in SBC memory locations 3000H-31FFH
is
the data
from one
along, the sending of
in which case
data
or
Had
interrupt
interrupt
1
or
If no
some
combination
interrupt
will cause the computer
been enabled
all
I could have occurred at any time,
the user couldn't have predicted
"BB"
3000H-31FFH.)
scan.
of
whether he'd find
the
two
1 has been sent,
in
locations
then interrupt 4
to jump to NEXT (line 30)
and proceed as
described above.
(line 47),
618 computer clock
on line 76.
Since the monitor
After PROC.COMP. has been sent
cycles elapse before GC is checked
routine NMOUT
cycle lasts
around 465 ns.,
this amounts to
Using the slowest CLOCK, 9 KHZ, which
takes
.19
seconds
to complete
a lapse of
has a period of
the scan
Using the 576 KHZ CLOCK, 1.736 us.
since one
425 cycles and
59 takes
called on line
(of 1728
111
.28 ms.
us.,
it
photodiodes).
per period, a scan takes about
PAGE 28
3 ms.
Depending on the gate size,
interrupt 4 may or may not have
arrived by the time GC is checked.
CPSTART signals,
in
the worst case, (i.e.,
arrives before GC is tes ted on line
interrupt 4
waiting for
about 4 ms. apart.
and no
interrupt 4
in which case there is no
enabling of
interrupt
If a slow CLOCK, such as 9
GATE were used, CPSTART
still
76,
when
1)
occur
KHZ, and a narrow
(line 48) would be sent while
a scan was
in progress. Since BLANK is low during scan time, BLANK GATE
(which follows it except when PREBLANK is sent) would also be low,
blocking
the
generatio,n of
a
START
computer would continue on to line
0 and
The
then halt waiting
latter
however,
because
still low.
occur
CPSTA RT
scan/process period
76,
for either
would never
if
of the BLANK
COMP.START
would have
to send a CPSTART signal .
interrupt 4.
been
only
done so
chosen,
once
per
while BLANK
was
it is necessary to add
BLANK status bit, as
register, that could be sampled by
The
generated by the rising edge
interrupt
signal or else a
1 or
COMIP.START had
To obviate t his type of problem
to the interface either an
CPSTART.
discover that GC was still
interrupt
generates
it
anc
pulse from
in a control
the computer to determine when
This problem doesn't arrise with RSTART
or 60 HZ START because these signals are periodically generated in
a continuous fashion.
No processing of
by
the computer
however,
in this
would
Instructions of
when reading
is complete, and
of
area has
after
been passed
which no
interface memory.
to
be
1, 2,
to change the
is still
5.
Also
from that
interface,
processing.
lines 73,
included somewhere
sending of PROC.COMP.
contents of
These
arrival of
scan will
the Status
registers may
in progress, as long
(signaled by the
more data
some
inserted between
line 74.
3, and
memory is done
using the
do
interrupt 4 and the
any instructions
changed while scanning
Anyone
wish
this nature would
Registers 0,
Control
program.
presumably
between the arrival
would be
the data moved to SBC 80/20
be
as the GATE
interrupt 4),
be written
into
PAGE 29
FIG.
V-I
TEST PROGRAM
ASMSO :F: TEST. ASM MACROFILE
ISIS-II
LOC
80:8/8085 MACRO ASSEMIELER,
OE:J
LI NE
'V3. 8
MODULE
PAGE
SOURCE STATEMENT
TEST:
0520
I'NMOUT
8
3900 F2
-:981 3E20
10
11
3905
12
L3:
3100:33
3:983: 2190329
22Fi3F
390E 3EED:
3910
3E04
19
28
-916
1918
3E6C.
-:91C
21
22
23
24
2920
3922 DE85
3924
16
17
18
3912
19141
391A
14
15
D381
3926
3928- D::8C
392A
3:928 3E80
!92D 32FF383930 11FF01
!933 21003:8
25
26
27
28
29
30 NEXT:P
31
42
33
34
35
0520H
EQU
ASEG
ORG
•3900H
DI
MVI A, 20H
OUT OD8H
LXI SP, 3308H
LXI H, INT4
SHLD 3FFIH
MVI R,.EDH[
OUT OD9H
OUT SAH
MVI A,H04H
OUT 88H
MVI A.0H
OUT 82H
MVI A,6CH
OUT 83H
MVI A,28H
OUT 85H
MVI H,88H
OUT 81H
OUT 8CH
DI
MVI A..OH
STA 38FFH
LXI D, 01FFH
LXI H,388000H
36 .
3:926
3938
3938
393C
393D
3948
3941
36BB
3E080
23:
1B
BA
C23639
BB
C23639
37 LOOPI:
38
39
48
41
42
43
44
45 .
MVI
CMP
JNZ
CMP
JNZ
M, OBBH
R.. OH
H
D
D
LOOP1
E
LOOPI
47
48
49
50
5:1
52
53
54
OUT
OUT
MVI
OUT
MVI
OUT
MV I
OUT
87H
89H
A, OEFH
OD9H
A, 88H
81H
A, 20H
OD8H
INX
.
46
3944 D387
3946 D389
3948 3EEF
394A D3D9
394C 3ES88
394E D381
3950 3E20
3952 D:D8
;SEND OCW2 TO 8259 SNON-SPECIFIC EOI
;SET STACK POINTER AT 3300
;VECTOR INT4
TO 3990
;SEND INTERRUPT MASK TO.
j ENABLE INTERRUPTS- AND 4
'SEND RESET TO INTERFACE
SEND CLOCK AND START
SELECTIONS TO INTERFACE
SSEND START GATE
TO INTERFACE
,SEND END GATE
TO INTERFACE
,SEND CAMERA SELECTION
; TO INTERFACE
SEND QUANTIZING LEVEL AND
? MODE TO INTERFACE
SEND PREBLANK TO INTERFACE
;RESET GATE COMPLETE TEST
; BYTE TO ZERO
*DE GETS NUMBER OF MEMORY
LOCATIONS TO BE FILLED
;HL GETS STARTING ADDRESS OF
MEMORY TO BE FILLED
*"BB" WILL BE STORED IN MEMORY
SINCREMENT MEMORY ADDRESS
SDECREMENT COUNTER
j IF REGISTER D IS NOT 0
JUMP TO LOOPI
* IF REGISTER E IS NOT 0
THEN REQUIRED NUMBER OF
MEMORY LOCATIONS HAVEN'T YET
BEEN FILLED.. 50 JUMP TO LOOPI
;SEND PROC.COMP. TO INTERFACE
jSEND CPSTART TO INTERFACE
.ENABLE INTERRUPT 4 ONLY
;SEND NON-SPECIFIC EOI
TO 8259
PAGE 30
ISIS-II
LOC
8080/8085 MACRO ASSEMBLER.
OBJ.
3954 FB
:955
3957 67
2958 CD2005
395B 110030
395E DB86
3960 12
2961
13
3962 DB86
3964
12
3965 12
3966 25
1967 C25E39
396A
D38B
296C F3
396D 3AFF38
3970 FEFF
CA2A39
3EED
2977 D3D9
3:979 FB
297A 76
3978 C32A39
3975
3990 C5
3991 D5
2992
E5
3993 F5
2994
3996
3999
399A
399B
399C
3599D
3EFF
32FF38
Fi
El
Di
C1
C9
LINE
55
56
57
58
59
60
61
62 LOOP:
63
64
65
66.
67
68
69
78
71
72
73:
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88 .
89
90 INT4:
9±1
92
93
94
95
96
97
98
99
100
101 j
102 ;
103
V3. 0
MODULE
PAGE
SOURCE STATEMENT
El
IN 88H
MOV H,A
CALL NMOUT
LXI D, 3000H
IN 86H
STAX D
INX D
IN 86H
STAX D
INX D
DCR H
JNZ
OUT
DI
LDA
CPI
JZ
MYI
OUT
EI
HLT
JMP
LOOP
8BH
38FFH
OFFH
NEXT
A,BEDH
OD9H
NEXT
jSEND OUTRAN TO INTERFACE
jPUT NUMBER OF MEMORY LOCATIONS
TO BE READ FROM IN REGISTER H
;OUTPUT THIS NUMBER TO TERMINAL
;1ST ADDRESS TO WHICH DATA FROM
INTERFACE WILL BE MOVED
;READ PORT 86
;STORE THIS DATA AT ADDRESS
HELD IN REGISTERS D AND E
INC:REMENT MEMORY ADDRESS
;READ PORT 86 AGAIN
;STORE THIS DATA AT ADDRESS
HELD IN REGISTERS D AND E
;INCREMENT MEMORY ADDRESS
.DECREMENT NUMBER OF INTERFACE
MEMORY ADDRESSES NOT YET READ
t AND JUMP TO LOOP IF NOT 0
SSEND READ COMP TO INTERFACE
;DISABLE INTERRUPTS
;CHECK GATE COMPLETE TEST BYTE IF SET TO FF, JUMP
TO NEXT
;ENABLE INTERRUPTS I AND 4
jENABLE INTERRUPTS
;WAIT FOR INTERRUPT
j THEN JUMP TO NEXT
ORG 3990H
PUSH B
PUSH D
PUSH H
PUSH PSW
MVI A,0FFH
STA 38FFH
POP PSW
POP H
POP D
POP B
RET
END TEST
PUSH CONTENTS
OF REGISTERS
ONTO STACK
SET GATE COMPLETE
TEST BYTE TO FF
POP STORED
REGISTER CONTENTS
FROM STACK BACK INTO
PROPER REGISTERS
RETURN TO PROGRAM
PAGE 31
FIG.
V-2
STATUS CONTROL REGISTERS
7
6
SCR
0
F2
5
2
2
Fl
FO
4
2
S3
COMP.
START
3
2
S2
Si
21
90
2
L7
L6
L5
L4
L3
3
H7
H6
H5
H4
5
CAM3
CAM2
-
CLOCK
PIXEL
A/D
STR.L
L2
LI
LO
H3
H2
HI
HO
-
-
-
-
DECIMAL
CLOCK SELECTED
0
0
576 KHZ
0
1
1
288 KHZ
0
1
0
2
144 KHZ
0
1
1
3
72 KHZ
1
0
0
36 KHZ
1
0
1
18 KHZ
1
1
0
9 KHZ
1
1
1
RCLOCK
Fl
FO
0
0
0
2
TRAN
SELECTIONS
F2
0
1
2
RSTART 60 HZ
START
22
FIG. V-3
2
2
23
CAMI
(SCR)
AND THEIR CONTENTS
PAGE 32
FIG.
V-4
PORT ADDRESSES USED AND THEIR FUNCTIONS
PORT
ADDRESS
L4 1
OUTPUT
ENABLED
80H
0
STROBEO
Loads SCR* 0 (U37) with
CLOCK and START selections
81H
1
STROBE1
Loads SCR 1 (U9) with
2UANTIZING LEVEL
and MODE selections
82H
2
STROBE2
Loads SCR 2 (U39) with
START GATE address
83H
3
STROBE3
Loads SCR 3 (U38) with
END GATE address
85H
5
STROBE5
Loads SCR 5 (U13) with
CAMERA selection
86H
6
MACR
Reads
87H
7
PROC.COMP.
Prepares Interface
new scan
88H
8
OUTRAN
Reads SCR 8 (L47)
89H
9
CPSTART
Sends a signal to Interface
to generate a START signal
8AH
10
RESET
Initializes
boards
READ COMP.
Disables the Interface
memories read from
PREBLANK
Enables a START pulse to
be generated, in case
BLANK powered up low
8BH
8CH
12
*SCR = Status
SIGNAL
GENERATED
FUNCTION
Interface memory
for
or 9 (L48)
to find number of Interface
memory addresses filled
during previous scan
Control Register
the Interface
PAGE 33
Fig. V-5
A/D Calibration
Input (my)
Lo
Hi
000
Output
3
2
1
0
12
0
0
28
82
0
1
93
143
1
0
159
215
1
1
228
282
0
0
297
350
0
1
361
421
1
0
436
487
1
1
496
551
0
0
568
623
0
1
635
689
1
0
704
760
1
1
771
831
0
0
844
899
0
1
908
965
1
0
979
1000
1
1
PAGE 34
SAMPLE OUTPUTS
Fig. V-6
SAMPLE
#
INPUT TO
U20-12
START
GATE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
U58-3
U58-3
U58-3
U58-3
U58-3
U58-3
U58-3
U58-3
U58-3
U58-7
U58-7
U58-7
U8-7
U8-7
U8-7
U8-7
U8-7
U8-7
U8-7
U8-7
U8-7
U8-7
U8-7
U8-7
U8-7
U8-7
U8-7
U8-7
U8-7
U8-7
U8-7
U8-7
OOH
00H
OOH
30H
30H
30H
69H
69H
69H
11H
11H
11H
OOH
00H
00H
OOH
00H
00H
00H
00OH
00H
00H
00H
00OH
00H
00H
00H1
10H
20H
60H
25H
00H
END
GATE
are shown
MODE
LEVEL
PIXEL
TRAM
STR.L
PIXEL
TRAM
STR.L
PIXEL
TRAM
STR.L
PIXEL
TRAM
STR.L
PIXEL
TRAM
STR.L
PIXEL
TRAM
STR.L
PIXEL
PIXEL
TRAM
STR.L
PIXEL
TRAM
STR.L
PIXEL
TRAM
TRAM
TRAM
TRAM
TRAM
A/D
8H
8H
8H
8H
8H
8H
8H
8H
8H
8H
8H
8H
8H
8H
8H
4H
4H
4H
2H
AH
AH
AH
CH
CH
CH
EH
8H
8H
8H
8H
8H
8H
6CH
6CH
6CH
32H
32H
32H
74H
74H
74H
29H
29H
29H
6CH
6CH
6CH
6CH
6CH
6CH
6CH
6CH
6CH
6CH
6CH
6CH
6CH
6CH
6CH
6CH
6CH
6CH
45H
6CH
In the following discussion are
whose specifications
QUANTIZING
shown samples of the outputs
in the table
above.
It will be
noted that three different inputs to U20-12, the Data input to the
flip-flop
generating DIG
VID,
were used.
For
the first
nine
PAGE 35
samples U58-3, a signal that changes
used
to
show
that
the interface
photodiode. Samples 10,
input was
U58-7, a
11,
and
the
signal that changes
1-bit
from the Reticon as
picture of
resolution
is
12 show various
periods, and samples 13 through 32
was U8-7,
state each CLOCK period, was
good
to
one
outputs when the
state every
eight CLOCK
various outputs when the input
digital version of
the VIDEO
signal coming
it scanned across 4 slits of a shadow mask. (A
this VIDEO signal
is shown on
page 45.)
For
all 32
samples, the 576 KHZ CLOCK and 60 HZ START signals were used.
Samples
1, 2,
and 3 show outputs for PIXEL,
modes, respectively, when
photodiode address
the START GATE is
000) and
photodiode address 6COH, or
photodiodes in the
80/20
memory
1728 in
GATE 6CH
decimal).
eights
=
214 (decimal)
-
00 (corresponding to
(corresponding to
Since the first
GATE area are not recorded and
location holds
(1728-16)/8 =
locations
the END
TRAN, and STR.L
-
3000H-30D5H
bits
since each SBC
of PIXEL
D6
(hexadecimal) SBC
are
filled with "AA"
binary) when PIXEL mode is chosen, as shown
16
Data,
then
80/20 memory
(10101010
in
in sample 1.
TRAN mode and STR.L mode can store information for as many as
255 transitions
bits of data,
memory.
or strings.
For each
in the form of 4 hexadecimal
The upper
4 bits,
15
I
14
2
I
13
2
I
string, 16
digits, are recorded in
which comprise
hexadecimal digits, give the following
2
transition or
the first
of the
4
information:
12
2
I
II
I
MEMA
(MEMORY BEING WRITTEN INTO)
0 = B MEMORY
I = A MEMORY
STORE VID (STATE OF DATA)
0 = BLACK
1 = WHITE
CAMERA IN USE
00 = NONE
01 = CAMERA I
10 = CAMERA 2
11 = CAMERA 3
The lower 12 bits, or 3 digits, give the photodiode address of the
PAGE 36
first
photodiode after
the
length of the string, i.e.,
transition, for
the
TRAN
mode, or
the
number of photodiodes in a string
of photodiodes of the same state, for STR.L (string length) mode.
Looking at
sample 2,
3001H information about
one can
the first
find in
locations 3000H
transition -
digit, 6H, or 0110 in binary, indicates
6012H.
The first
that camera 1 was
in use,
white data was received, and the "B" memory was written into.
digits -
last three
first
-
012H
photodiode after
give
the
the hexadecimal address
transition,
and
meaning that
The
of the
the
last
photodiode in the group for which the state of the video was
1 was
O11H.
Locations 3002H and 3003H hold information about the second
transition - 4013H.
in
binary, which
transition only
this time is
into don't
In this case, the
differs
from the
in the third
black.
bit,
first
first
the
digit
digit
a scan,
so,
for the
state of the
(The camera in use and
change during
is 4H, or 0100
first
data, which
memory being written
unless
one is
doing some
unusual operation, the first, second, and fourth bits of the first
digit
don't change
sample 2
one will
during a
see that
alternates between
being written
would have
the first
Looking on
digit of
transition data
1 and 0. (Had the "A"
into, the
alternated between
first digit
7H and
through
to the state
6H and 4H, corresponding
data's alternating between
memory
scan either.)
of the
memory been the
of transition
5H, as
in sample
data
8.
Had
camera 2 or camera 3 been used instead of camera 1 the alternation
would have been
examples of
between other pairs of
this type
are available,
digits; unfortunately, no
as camera
1 was
the only
camera used to make samples.)
The last 3 digits of TRAN Data in sample 2 increase by I each
time -
012H, 013H, 014H,
transition occurred
point,
however,
locations
recording the fact
each CLOCK period.
that
31FCH and
transition, but rather
the GATE area.
etc. - duly
the information
31FDH,
is
not
the
information
255th
position,
about the
information about the final
This is because once the
at this
One should note
in
that a
255th
transition in
memory address counters
PAGE 37
reach
255
(FFH)
they
interface memories has
transition from the
information
stay there;
thus
location
information overwritten
255th until the last
255
into it
in the
in
the
for every
GATE area, whose
is what gets transferred to SBC 80/20 memory.
Sample 3 shows STR.L Data, the first digit of which is loaded
in the
same way as
last three
photodiodes
digits give
in a
Thus,
CLOCK period,
Note at
more economical
length, i.e.,
photodiodes
since the
the string
this point, by
of TRAN Data.
the string
string of
mentioned earlier.
each
the first digit
of the
the number
of
same state,
as
input data was changing state
lengths recorded
comparing samples 1,
is PIXEL mode than
However, the
are each
2, and 3,
001H.
how much
either TRAN mode or STR.L mode
when transitions are many.
Notice should also be made
here that the photodiode counters
and GATE's miss being synchronized by 1 photodiode.
The GATE's go
one CLOCK (and thus I photodiode)
too late with
up and come down
respect to the photodiode address counters.
very slow functioning of the
PREGATE
signal,
from
This is why PIXEL,
(0101)
CMOS comparators, which generate the
which are
generated
in sample 1,
is "A"'s
- the leading 0 is missed.
2, the addresses
GATE area) looked
at
in each of
i.e.,
GATE's.)
instead of "5"'s
1 off - i.e.,
is 007H,
Parallel coordination among
however, is still synchronized -
(1010),
last 6BFH,
not 012H, and the
for example, the first string length
sample 12.
the various
This is also why, as
of the transitions are
should be 011H,
(This could be due to
in sample
the first
not 6COH;
and why,
instead of 008H,
the various
in
data modes,
the first photodiode (in a
the four data modes
is the same
photodiode.
Samples 4, 5, and
6 differ from samples 1, 2,
the GATE area,
which, for samples 4,
(corresponding
to
photodiode
address
5, and 6, extends
300H,
(corresponding to photodiode photodiode address
is thus 32
photodiodes wide.
not recorded, only 16 are, and
and 3 only
Since the first
or
768)
in
from 30H
to
32H
320H, or 800) and
16 photodiodes are
their PIXEL values are recorded in
PAGE 38
SBC 80/20 memory
locations 3000H and 3001H, as seen
in sample 4.
Samples 5 and 6 show TRAN and STR.L Data for the same GATE area.
Sample 5
shows another
last transition arrives
(for the memories
peculiarity of
interface.
and advances the memory
being written into),
the transition data
the
but the
gets recorded at this
The
address counters
GATE falls before
address.
The computer
reads this address as the final memory address filled and so reads
whatever happens
to be
stored there
from before.
This problem
occurs, however, only if the END GATE is less than 6CH.
In
samples 7,
through
74H
(i.e.,
(corresponding
The
and 9
the GATE
photodiode
to 1728),
photodiode in
point.
8,
the array,
area
addresses
however,
is the
so output
is
same output would
designated is
690H-740H).
address
16 photodiodes
are missed,
the way, with
so recording
last
beyond that
GATE greater than 6CH, given the same START GATE, 69H.
first
6COH
of the
not recorded
appear, by
69H
any END
Again, the
starts at
6AOH.
Recording must stop before 6COH is reached, so PIXEL Data for only
32 photodiodes is recorded in sample 7.
Samples 8 and 9 give the
corresponding TRAN and STR.L Data.
Samples 10,
the input
11,
to U20-12
eight ones.
and 12 show
PIXEL, TRAN, and STR.L Data when
is alternating
The GATE area is
groups of
11H through 29H
eight zeroes
(i.e.,
and
photodiode
addresses 110H-290H).
Samples
13
through 32
coming from the Reticon,
46.
The
are all
as shown
peaks correspond to
shadow mask.
Samples 13,
14,
data from
in the picture on
the locations
15,
the VIDEO
signal
pages 45 and
of the slits
in the
and 32 show PIXEL, TRAN, STR.L,
and A/D Data for this VIDEO signal when the quantizing level was 8
and the GATE
area OOH-6CH.
to store either TRAN
in
a case
such as
transitions few.
the GATE
PIXEL, TRAN, and STR.L
seen yet.
space is required
or STR.L Data than either PIXEL
this where
been seen before, but
we haven't
Note how much less
area is
or A/D Data
large and
modes of data
the
have all
sample 32, which shows A/D mode data, is one
A/D mode,
which records
gray level
data,
PAGE 39
gives more detailed information than does PIXEL mode (or either of
the other
modes), but
times as
much as
it also
for
PIXEL mode.
locations are available
data for
on the
4 photodiodes,
stored,
as
are needed
locat ion,
so
510,
in
interface,
Section
to
or
locations are needed.
Since only 255
1FE
in
Two
from
SBC
can be
80/20
memory
one interface
memory
hexadecimal,
This can be seen
four
16-bit memory
1020 photodiodes
IV.
store data
-
and each location holds
data from only
mentioned
locations
requires more mei-mory space
SBC
80/20
memory
in sample 32, where memory
locations 3000H through 31FDH are filled.
Sarples
16,
17,
and
20,
18;
21,
show PIXEL, TRAN, and STR.L Data
and CH, respectively.
outputs
thresholds,
same
tihe
samples
VIDEO
data,
in
as
only
high as
EH
samrple 32,
one can see
once and
never
or threshold,
quantizing level,
enough to reach it and so all
was set
to reach
Data bits were ones,
that
different
to scan
corresponding
was high
On
so all PIXEL
it,
it
to be "F"'s.
and sample
that the VIDEO
16 doesn't
output varied
held very securely
to the fact
that
be slightly
but with different
note concerning samples
tightly
secured in
the VIDEO
causing
data
the
the
EH level
lower that the
Finally are shown several outputs using the
input,
As a result,
When
was set at 2H, no VIDEO
in the output
in
the A/D converter might
same VIDEO data as
not
fact
also be due
EH.)
By looking
EH no VIDEO
the shadow mask was not
as
It could
A final
has an EH
be due to the
quantizing level
scan
with
but
less go below
causing all digits
from scan to scan,
of
much
it,
samcple 32
show this could
made.
a comparison of
the PIXEL Data bits were zeros.
was lowe enough
mask was
is
below 3H.
at
when the quantizing level
coming out
levels of 4H, AH,
that the VIDEO reached
got
the other hand,
in place.
24, and 25
or quantizing levels - EH, 8H, 4H, and 2H.
at the A/D Data
(The fact
and 23,
for quantizing
Following these
from
made
and 22;
in
what
different
through 32 _
13
place when
signal
appear
gates.
the shadow
these samples
were
from the Reticon varied from
to
be discrepancies
modes,
corresponding data in the same mode but
as
well
as
between
between
from different scans.
PAGE 40
# 1
PIXEL DATA
A
-)
= >
302C
30T
OLU
304U
Hf i M )
AH
H i-:
AA Pif
AP AA P
AA
W,
AA AA
AA
AA
AA AA
Aff AA
AA AA
A
AA AA
AA AA
AF HA
AA
AA
AA
onr
H AA
AA
AA
AF
AA
AA AA
z09 AN
AF AA FB
AA
30A• HH AA AA
PA
AA
30O3
AA
AH AA tBA
I_,BFB
309L (-;
30U PP
BB BB BB
BB
Bb BB
130
13 E1
31)
I(i
B
B BB
BBbP
'110 BB
BB
LiL
bB
FBB PBB
BB
(;d BE, BB
BB
BB
BB
pBB
1t3
'1 B11
31 Cl 13tC
BE BB
13,3
13131
B1: BB
1313
BB1
13L,
13
t PB F; 3 BB BB
BB3
1313
BB
3 1313
1313I
'313
8i1
BLB DB
Bu 1313
13BB
31i3 iU bB
131L
B
BF. BB
1313_
13
Li
t; B
BE;
1313
1317
1313
BU
32
10 0
31BC,
1313
h1
0F
AA
1RiAC n
APAA AA
0
A 0n
A,
(1H~n
lc Hii (ý~~Ni (k
I 1-i(ý M'i W) 00 fiO W1c
AA AA AA
A FAA AH
AA AA
AA AA SAA
AA
AA AA AA
AA AA
AA
AA
bb
AA
AA AA
AA
AA
BB
BB
BB BB
BB
BB BB BB
FBB
Bb
BB BB BB
BB t P.UFm
BB
BB
BE
BB BB
BB
BB
BB
BB FB BB
BB
AA
BB
BB
BB1 BB
B1BBb
BB
BB
BB
BI BB
BD
BB BE
BB 1313
BB
BB
BB
B
BB
BB
BB
BB
BB
BB
BB
BB
BB BB BB BB
3BB
AA AA AA
AA
AA
AA AA
ARt AA AA AA
AF
AA AA
AA AA CAA
AA
AA AA AA
AA
AA AA AA
AA
AA AA AA
AA
AA
AA
SAA
AA
AA AA AA AA AA
AA AA AA PA AA
AA
AA
AA
AA AA AA
BB BB
BB
BE;
BB
PB
BE; BB BB BB
BB
BB
BB BB DB BE,
BB
BB
BB BB
BE; BB BB BB BB
BB BB
BE1
BB
BB BB 131
BB
BB BB
BB BB
BB
BB
BB 1313 BB
BB BB BB BB
BB 131
BB
BB
17.1
BB
BB
131
BB
131131
131 BB
BB BB
1313
BB BB BB
BB
BB
1313
131
131'
BB
BB
BB
BH
bF
BBF BB
131
131
B3B1
BE
FB
BB
1313
BB
BB
BB
131
1313
131
BB
17;
1
B
B
EB
131 BB BE;
131 BB BB
BB
BB
131 BB
131 BB BE;
Bb BB 131 B
B BB
BB
BEB
1313 BE;
BB BB 131 BB
BB
BE; BB 131 131 BB
[-B BE:
1513
BB
BB BB
BB 131
BB
31
AA
bB
3200
AA AA (HEXADECIMAL) = 100101010101010
(BINARY)
This sa~'mpe snot.:s PIXEL Data for
a complete scan, since the
START
GATE
is
OTH and
the
END GATE 6CH,
corresponding
to
photodiode acdresses
C00 and
1723, respectively.
The first
26
photodiodes in the GATE area are not recorded, so, since each SBC
80/20 mnerory location holds eight bits of PIXEL Data, (1728-16)/8
= 214 = DSH SEC 80/20 memory locations - 3000H through 30D5H - are
are filled
The
rest of the memory locations
filled with "AA".
with "B3" becCuse before tho interface data was transferred memory
locations 3000H-3200H were zll filled with "BB" by the program.
PAGE 41
# 2
TRANSITION DATA
...
3000
12 40 1360
CO
301
6bu 1A 40 1E 60
3020
3030
3040
305S
3060
60
60
60
bU
60
22
2A
32
3M
42
40 23
40 2S
O033
40 36
40 43
60
60
60
60
60
3070 oU 4H 40 46 60
3080
3096
30AO
30BG
30CO
30DG
30E0
30F0
3100
3116
3120
313G
3140
3156
3160
3176
3180
319b
31A0
31BC
31CO
31Db
31E0
31FU
60
6u
60
6u
60
bU
60
bU
60
60
60
6u
60
60
60
60
60
bO
60
bu
60
bO
61
bl
52
SA
62
6A
72
7A
82
8A
92
9A
A2
AA
B2
BM
C2
CA
D2
DO
E2
ER
F2
FA
02
O
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
41
41
53 60
56 60
63 60
G6 60
73 60
76' 60
83 60
8B 60
93 60
96 60
A3 60
AB 60
63 60
BE 60
C3
CB
D3 60
DB 60
E3 60
EB
F3 60
FE
03 61
0H 61
,'012
I0
TI 1
lIi
I
I
14
1C
24
2C
34
3C
44
4C
54
SC
64
GC
74
7C
84
8C
94
9C
A4
AC
B4
BC
C4
CC
D4
DC
E4
EC
F4
FC
04
OC
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
41
41
15
1u
25
2D
35
3J
45
4D
55
50
65
60
75
7D
85
81
95
9D
A5
AD
B5
BD
C5
CD
DS
D0
E5
EU
F5
FD
05
OD
60
bO
60
60
60
60
60
GU
60
60
60
60
60
60
60
60
60
60
60
60
GO
60
60
60
60
60
60
60
60
60
61
61
16
1L
26
2L
36
3E
46
4E
56
5E
66
GE
76
7E
86
8E
96
9E
AG
AE
BC
BE
C6
CE
D6
DE
E6
EE
FG
FE
06
OE
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
41
41
17
1F
27
2F
37
3F
47
4F
57
SF
67
6F
77
7F
87
8F
97
9F
A7
AF
B7
BF
C7
CF
D7
DF
E7
EF
F7
FF
07
OF
60
60
60
60
60
60
GO
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
III
III
iI
Sii1
LCAMERA
iI
A8
BO
B8
CO
C8
DO
D8
EO
E8
FO
F8
00
61 08
66 CO
o
0110
(BINARY)
I II
MEMORY BEING WRITTEN INTO
IL
III
18
20
28
30
38
40
48
50
58
60
68
70
78
80
88
90
98
AO
0 = B MEMORY
1 = A MEMORY
STATE OF DATA
0 = BLACK
= WHITE
IN USE
00 = NONE
01 = CAMERA 1
10 = CAMERA 2
11 = CAMERA 3
ADDRESS OF IST PHOTODIODE
AFTER TRANSITION
40
40
40
40
40
40
40
40
40
40
40
40
40
40
19
21
29
31
39
41
49
51
59
61
69
71
79
81
89
91
99
40
40
40
40 Al
40 A9
40 61
40 B9
40 Cl
40 C9
40 D1
40 D9
40 E1
40 E9
40 F1
40 F9
41 01
41 09
&BB31
PAGE 42
# 3
3000
3010
3020
303C
3040
305,
3060
3076
3080
3090
30O
308U
30CU
300D
30EO
30FC
3100
3110
3120
3130
3140
3150
3160
3170
3180
3190
31AO
31BG
31CO
31D0
31EO
31FC
0 04
6U 01
60 01
60 01
60 01
60 01
60 01
GU 01
0G01
6u 01
60 01
bu U1
60 01
60 ui
60 01
60 01
60 01
60 01
60 01
60 01
GO 01
bO 01
60 01
6GO 0
60 01
6U 01
60 01
bO 01
6G 01
GU 01
60 01
6l 01
STR.L
40
40
40
40
40
40
40
40
40
40
,U
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
01
01
01
01
01
01
01
01
01
01
01
U1
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
(String Length) DATA
O60
01
60 01
GO 01
60 01
GO 01
60 01
60 01
60 01
60 01
60 01
60 01
bU U1
60 01
bU ui
60 01
60 01
60 01
60 01
0G01
GO 01
GO 01
60 01
60 01
60 01
GO 01
60 01
GO 01
60 01
GO 01
60 01
60 01
60 01
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
01
01
01
01
01
01
01
01
01
01
01
Ul
01
uI
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
6O 01
GO 01
GO 01
60 01
60 01
60 01
60 01
60 01
GO 01
GO 01
60 01
bU U01
60 01
bb Ul
GO 01
60 01
60 01
60 01
60 01
60 01
60 01
60 01
60 01
60 01
60 01
60 (1
60 01
GO 01
60 01
60 01
60 01
60 01
40
40
40
40
40
40
40
40
40
40
40
4U
40
4U
40
4U
40
40
40
40
40
4U
40
40
40
4U
40
40
40
40
40
40
01
01
01
01
01
01
01
01
01
01
01
U1
01
01
01
U1
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
w'*6001
AS FOR TRAN
n(SAME
_WH
II1
MODE)
-NUMBER OF PHOTODIODES
IN STRING JUST COMPLETED
60 01
60 01
60 01
60 01
GO60
01
60 01
60 01
GO 01
60 01
60 01
60 01
60 01
GO 01
0
U 1
GO60 01
GU 01
60 01
60 01
60 01
60 01
GO 01
60 01
60 01
G60 01
60 01
60 01
60 01
60 01
60 01
60 01
60 01
60 01
40 01
40 01
40 01
40 01
40 01
40 01
40 01
40 01
40. 01
40 01
40 01
40 01
40 01
40 01
40 01
40 01
40 01
40 01
40 01
40 01
40 01
40 01
40 01
40 01
40 01
40 01
40 01
40 01
40 01
40 01
40 01
EB 31
PAGE 43
ALTERNATING 0-1 DATA
DIFFERENT GATES
-
DIFFERENT MODES
GATES
# 4
30H
32H
3000 AA AA BB BB B BB
BB B BB BB BB BB BB BB BB BB BB
01 BB BB EB BE; BB BB B
B BB BB BE BB BB
BE;
# 5
30H
PIXEL
TRAN
3000 63 12 43 13 63 14 43 15 63 16 43 17 63 18 43 19
32H
3010 6-3 1A 43 1S 63 1C 43 10 63 1E 43 1F 63 20 40 01
3020 BB BB BB BB BB B
# 6
30H
32H
74H
74H
301
74H
STR.L
PIXEL
BB BB BB BB B
B
BB BB BB BB BB BE BB BB BB BE
TRAN
3000 76 A2
3010 76 AA
3020 76 B2
3030 76 BA
3040 BB BB
# 9
69H
BBBB BB BBB
3000 AA AA AA AA BB BB BB BB BB BB BB BB BB BB BB BB
# 8
69H
BB BB
3000 70 01 50 01 70 01 SO 01 70 01 50 01 70 01 50 01
3010 70 (;1 50 01 70 Ci 50 Ul 70 01 5 01 70 01 50 01
3020 BB BB BB BB BB BBBB BB BB BB BB BB BB BB BB BB
# 7
69H
BBB
56 A3 76 A4 56 A5 76 A6 56 A7 76 A8 56 A9
56
76 AC 56 AD 76 AE 56 AF 76 BO 56 B1
AB
56 B3 76 B4 56 B5 76 B6 56 B7 76 B8 56 B9
56 BB 76 BC 56 BD 76 BE
BF 76 CO BE BB
BB BB BB BB BB BB BB BB BB BB BB BB BB BB
STR.L
60 01 40 01 60 01 40 01
60( 01 40 01 60 C1l
60 01 40 01 60 01 40 01
60 Cl 4B 01
40 01
3040 BB BB BB BB RB
BB PB
BB BB BB
3000
3010
3020
3030
60 01 40
1l 40
60 01 40
60 0 1 40
BB BB BB
60 01
GO cl
60 01
60 01
BB BB
40 01
40 01
40 01
BE; BB
BB BB
PAGE 44
DATA = ALTERNATING GROUPS OF EIGHT ONES AND EIGHT ZEROS
START GATE
= 11
END GATE = 29
# 10
3000
301,
3020
3036
01 FE
01U FE
01 FE
Bs BB
PIXEL
01
C1
01
BB
# 11
FE 01 FE 01 FE 01 FE 01 FE 01 FE 01 FE
FE 01 FE 01 FL 01 FE 01 FE 01 FE C1 FE
FE 01 FE 01 FE 01 FE 01 FE 01 FE BB BB
BEB B
B B
B BB
BB BD EB BE BB B B
BB
TRAN
3000 41 28 61 30 41 38
3,01U
b8 61 /U 41 78
3020 41 A8 61 BO 41 B8
FO 41 F18
3030 41
3040 42 28 62 30 42 38
3050 42. 68 6b 70 4B 18
3060U B8 BB BB BB BR BD
# 12
61
61
61
62
62
Gz
61 9G 41 58
9U 41 98
61 DO 41 D8
b 10 42 18
62 50 42 58
bZ 9U EB BB
BB BB BB BD BB BB BB BB
/'.o
80
CO
UU
40
8JU
41 48
41
41 C8
42 GB
42 48
q42FB
61 60
61 AO
61 EO
G6220
62 60
BE BB
BB BB
STR. L
3000 5U 07 70 08 50 08 70 U8
3010 bU US /U 08 50 U8 /1U U'
3020 SU 00 70 08 SO 08 70 08
3030 bu U0 /U Ob so50 08 U u
50 08 /0 08 50 08
LO uU u U0b 5U U8
50 08 70 08 50 08
bu Ub tO U0 50 08
3040 SO 08 70 08 50 08 70 08 50 08 70 08 50 08
3050 sO 08 ?0 Ol 50 08 ?u ub O 00 70 08 BB BB
3060 BR PB FPD RB BB BB BB BB BB BB BB BB BB BB
70 08
0O08
70 08
10 08
70 08
LB1 BEB
BB BB
PAGE 45
VIDEO SIGNAL FROM RETICON
# 13
3000
3010
3020
3030
3040
3050
3060
307U
3080
3090
30AO
S0 B
30C0
30D0
30EU0
UU
0U
FF
UO
00
UD
00
uo
00
FF
00
OU
00
FC
00
CO
FF
00
00
3F
00
00
00
FF
00
00
FF
CO
00
00
FF
00
00
FF
00
00
00
FF
00
00C,
FF
00
PIXEL
C0 00 00 00 00 00 00 00 00 00 00 00 00
00
FF
00
00
FF
00
00
00
FF
00
00
FF
00
BR BB BB BB
# 14
00
FF
00
00
FF
00
00
00
FF
00
00 0? FF
FF FO 00
00 00 00
00 00 00
FF FF FF
00 00 00
0C000 00
00 00 00
FF FF FF
00 00 00
00 00 00 0U
FF FF FF FF
00 00 BBE B
BBEBB BB BB
FF
00
00
00
FF
00
00
FF
80
00
00
FF
RB
BB
FF
00
00
00
FF
00
00
FF
00
00
00
FF
RB
BB
BB
FF
00
00
00
FF
00
00
FF
00
00
00
FF
BB
BB
FF
00
00
00
FF
00
00
FF
00
00
00
FF
00
00
FF FF
00 00
00 00
00 00
FF FF
BB BB
BB BB
FF FF
00 00
00 00
00 00
FF FF
00 00
00 O0
FF FF
00 00
00 0.0
CO 00
FF FF
BB BE;
BB BB
FF
00
00
00
00
00
00
FF
00
00
00
FF
BB
BB
TRAN
3000 40 C6 61 46 42 98 63 OC 44 59 64 DB 46 21 66 9F
3010 BB BB B; BB BB BB BE;
BB B BB BB BB BB BB BB
B
# 15
STR.L
300(0 40 B 60 81 41 53 60 72 41 4E 60 81 41 47 60 7E
301' t,;
1u E6,-P
D
E: b Bb L
H b b
bRb B; BE; BB BB E;E BE
PAGE 46
VIDEO SIGNAL FROM RETICON
# 32
A/D
3000 33 33 33 33
301U 33 33 33 33
3020 333 33 33 33
3030 33 3,_3 33 33
3040 34 34 34 34
305U 44A 44 14444
3060 88 BB =ABAA
3070 LC, CC BC BB
3080 CC CC CC CC
30!9u uC uLL Cc 8C
30A0 44 34 34 34
30BU 34 33 33
30CO
30D0
30EO
30F U
3100
3110
312U
3130L
3140
3150
3160
31/
3180
319U
31 AO
3180
31CO
3100
31E0
310
3200
33
33
33 33
33 33
ij3
33 34 33 33
JJ 33 3:3 33
33
33 33
33
33' 33
.34 34 34 34
4 44 34 34
56 67 78 78
vuu CL DD DD
DD DD ED CC
u D DC Cc CC
44 44 34 34
33
33 33
33 34
33 33 33
J3
33 33
33 33 33 33
3J3 33 33. 33
33 33
3J 33 33
j3 ,3333 33
ED
33 33 33
33 33 33
33 33 33
33 33 33
34 44 34
44 /45SSb
BB CB BC
BC CC Cc
CD DC CC
BC BB 0
34 44 33
'3"
33 33
33
33
33 33 33
33 33 33 33 33 33
33 33 33 33" .3343
33 33 33 33 33 33
.J33 33 3j42 33 33
34 44 44 34 34 44
ý
9n AA
sb 18
SAD
33 33 33
33 33 33
34 33 33
44 44 44
AA AB AB
BB BC B8 BB BB BB BB BC BC
Clc CC CL Cu CCO CC CC CC BC
CC CC CC CC CC CC CC CC CC
/6 55 514 44 44 44 44 34 34
33 33 33
34 34 34 33 34 34
33 33 33 33 33 33
33 33 33 33 33 33
33 33 '33 33 33 33
33 33 33 33 33 33
33 33 43 33 J3333
34 34 34 33 34 34
33 34 44q 33: 34 34
33 34 33
33
33
33 34 33
34 34 33
34
34 34 44 44 34 34 44
44 44 144 34 44 44q 44 44 44
99 99 AB AB
DD Dl)D DUI00
CC BC CC BB
CC .CcBi 99
34 44 33 33
33 33 3.3 33
33 33 33 33
33 33 33 .33
33
33
33
33
33 33 33
33 33 33
33 33 3.3
33 33 33
34- 43 JJ
33 33 33
33 43 33
33 33 33
34 33 33
33
33
34
34
44
33
33
33
34
44
33
33
34
34
45
BB BB BC BC CD DD CD CC
DD DUD DD) DD D1) DD DD DD
BB BC CC BC CC CC CC CC
3
99
8 ?/ 65 54 44 44
33 33 33 33 33 43 33
33 S3 33 33 34 33 33
33 33 33 33 34 43 33
3333
33 33 33 33 33
33 33 33 33 33 33 33
33 3J .Z; 33 33 33 33
33 33 33 33 33 33 33
33 34 34 34 33 33 BE
34
33
33
33
33
33
33
33
FD
PAGE 47
THRESHOLD = 4H
# 16
3000
301L
3020
3030
00 00
55 75
FF FF
00 00
3040 00 00
30S5 Ff FF
30bO0 00 00
3070( UU0 00
3080 00 10
309L -F FF
30AO0 00 00
30B0 00 00
30CO FF FF
30D0 F--DO
30EO BB BB
PIXEL
00
FS
FF
00
00
FF
00
00
55
FF
00
00
FF
00
BB
# 17
00 00
FFT FF
FF FF
00 00
00 10
FF FF
00 00
00
75 FF
FF
00 00
00 00
FF FF
00 00
BB BB
00
FF
00
00
F5
FF
00
00
FF
00
00
00
FF
B
BB
BB
00
FF
00
00
F5
FF
00
00
FF
00
00
00
FF
BB
BB
01 11
FF FF
00 00
000 00
F5 FF
FF DC
00 00
00 00
FF FF
00 00
00 00
15 77
FF FF
BB BE
BB BB
TRAN
30001 50 73 70 74
3010 so
50 AS6 70 A7
3020
BO 70 85
71 53
3030 51
71 9C
3040 51
3050
60 72 61
3060 52 68 72 69
307U0 52 /0 72' 71
72 79
3080 52
52 78
3090 52
80 ,2 83
30A0
8E 73 15
308u 54 30o 74 31
54 3E 74 47
30 0 S4 E2 74 E3
30EO 56 10 76 11
30FO 1B3 8BB BEU BB
# 18
3000 40 83
3010 40 01
3020 40 01
3030 40 01
3040 40 03
3050 '40
3060 14021
3070 Li 0 01
01
3080 40 01
3090 40 01
30AO0 40 01
3080 40
30CO 40
40 03
30DU 40
30EO v 0 01
01
30FO
00 00 00 18 00 00 00
FF FF FF FF F -Ff FF
FF F5 55 10 40 00 00
00 00
00
00
00 14 00 15 51 55 55
FF-FF FI- FF FF FF FF
00 00 00 00 00 00 00
00 Ou 00 00 00 CO 00
FF FF FF FF FF FF FF
FF FF FF FS 40 00 00
00 00 00 00 00 00 00
00 GO OFF00 00 00 00
FF FF FF FF FF FF FF
00 BB BEBB BB BB
B BB BB BB BB BB
50 AO 70 Al 50
50 A8 70 AS9 50
50 B6 71 4D 51
51
52 54 71 55 51
30 72 31 52
52
52 62 72' 63 52
52 GA 72 6B 52
52 72 72 13 52
52 7A 72 7B 52
84 7;" 85 52
53 3C 73 3D 54
54 32 74 35 54
54 48 74 DD 54
54 E4 74L ES 56
56 12 76 13 56
BB BB BBR 8 . BB
A4 70 AS
AE 70 AF
50 71 51
5C 71 5D
5E 72 5F
66 72 67
6E 72 6F
76 72 77
7E 72 7F
88 72 8D
2E 74 2F
38 74 3D
EO 74 El
CO 76 OD0 56 OE 76 OF
14 76 15 56 16 76 AS
b2 BB BB BB BB BB BB
A2
AA
4E
56
SC
64
GC
74
7C
86
2C
70
IC
71
71
72
72
72
72
72
72
74
A3 50
AD
4F 51
51
57
5D 52
65
6D 52
75 52
7D 52
52
87
2D 54
36 174 37 54
DE 74 DF 54
STR.L
GO 01 40
03 40
60 01 40
01 40
U,
600 01 40
01 40
60 01 40
60- 01 40
60
6_, 01 40
,O 01 40
60 01 40
60 83 40
60
60 01 40
60 01 40
60 01 41
01 40
01
01 40 05 60 01 40 03 60 01
01 60 01 40 01 1C 01 40 01 60 03
01 60 9F
01 60 01
01 60 01
CB 60 01
01 60 01
S160 01
01 60 01
60 03
01 60 03
01
01 60
03
60
01 60 9F
01
27 60
01 60 8F
40 01 60 03
40 G0160 01
40 01 60 01
40 G0 60 01
40 01 60 01
40 c01 60 01
40 01 60 01
40 01 60 01
40 01 60 01
40 5bB60 01
40 01 60 01
40 01 6C 01
40 01 60 01
BB BB BE; BB
40
40
40
40
40
40
40
40
40
40
40
40
40
BB
01
01
01 60 01
BF 60 01
01 60G 01
01 60 01
01 60 01
01 60 01
01 60 05
01 60 01
BB 60 01
01 60
60 05
C11 60 01
01
03
BB BB BB
PAGE 48
THRESHOLD = AH
3000
3010
3020
3030
3040
3050
3060
3070
3080
3090
300O
30BO
30CO
30DU
30EO
00
00
FF
U0
00
UO
00
00
00
FF
00
00
00
CO
BB
# 20
PIXEL
00 00
OU 0G
FF FF
CO0O
00 00
FF FF
00 00
O0 06
00 00
FF FF
00 00
GO 0
FF FF
O 06
BB BB
00
00
FF
00
00
FF
00
00
00
FF
00
00
FF
00
BB
# 21
00
00
FF
00
00
FF
00
00
00
FF
00
00
FF
00
BB
00 00 00 00 00 00 00 00
00 03 FF FF FF FF FF FF
FF EO 00 00 00 00 00 00
Go 06
O0 00
UO 00
O0 O0
bO 06 00 00
O0
00 00 00 00 00 00 00 00
FF FF FF FF FF FF FF FF
00 00 00 00 00 00 00 00
6O 06 00 00 60 O0 00 00
00 00 01 FF FF FF FF FF
FF FF FE 00 CU O0 00 00
00 00 00 00 00 00 00 00
O0 0C 00 00 1) 0 G 00 00
FF FF FF FF FF FF FF FF
70 Bb BB BB EB BB BB BB
B B BB BR BB
BB BB BB
00
FF
00
O0
00
FF
00
CO
FF
60
00
CO
FF
BB
BB
00
FF
00
00
00
FF
00
06
FF
00
00
00
FF
BB
BB
00
FF
00
00
00
80
00
00
FF
00
00
00
FF
B
BB
TRAN
3000 SO C6 71 44 52 99 73 07 54 57 74 D7 56 1F 76 9A
BB BB bBBB8 BB BB BB BB BBBB BB
BB B
B B
301
# 22
STR.L
3000 50 B4 70 7E 51 55 70 CF 51 4F 70 81 51 47 70 7B
BE B
BB
BB B BB BB BB BR BB BB
BB B
B B
301 B BB BB BB
PAGE 49
THRESHOLD = CH
# 23
PIXEL
3000 00 00 00 00
3010 uu U0 GO0 00
3020 FF FF FF FF
3030 UU OU 60O 00
3040 U00 00 00 00
305L uo 01 FF
30b0 UO 00 00 00
30/1 u
0 00 60 00
3080 00
00 00
3091 F[F
FF FF
30A0 00
00 00
30BG 00U OU G0 00
30CO 00 00 FF FF
30106 FF OU GO 00
# 24
00 00 00 00 00 00 00 00 00 00 00
U I. 00 GOu tFF F
FF FF FF FF FF
FF FF CO 00 00 00 00 00 00 00 00
OU 00 Ou Ub
UU 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00
FF FF FF
FF: FF FF FF FF FF CO
00 00 00 00 00 00 00 00 00 00 00
00 00 CU 0G0 UO0 00
00 00 00 00
00 00 00 00 00 FF FF FF FF FF FF
FF FF FF F F FC UU 00
C000 00 GO
00 00 00 00 00 00 00 00 00 00 00
00 00 GO 00 00
Go 00 00 00 GO
FF FF FF FF FF FF FF FF FF FF FF
00 00 BB
BB BB EB BE; B3 BBR BB
00
FF
00
00
00
00
00
00
FF
00
00
00
FF
BB
TRAN
3000 50 CA 71 43 52 9E 72 9F 52 AO 73 04 54 59 74 D7
3010U b 21 76 99 BB BB Bb B
BB B BB BB BB BB BB BE BB
3020 BB BB BB BB
BB BB BB BB BB BB BB BB BB BB BB
# 25
STR.L
3000 40 B8 60 7A 41 5D 60 63 41 56 60 7E 41 4A 60 78
3010 BB BR B RE BB B B B BB
BB BB BR B BB BB BB BB
3020 BB BB BR B
B BB
BB DD BB RB BB BB BR B BB 8B
PAGE 50
PIXEL MODE
THRESHOLD
SAMPLE
#
613
8H
-
SAME INPUT DATA
-
DIFFERENT THRESHOLDS
)00 uO0 00 00 00 00 00 00 00 00 00 00
uf)00 GU 00
00 00t O0 00 00
3020 O0
00 00 00 00 00 00 00 00
00
UO O
L LI 00 00 00 00 00 00
3030 00
00
Gou 00
3040 UO
00 00 00 00 00 00 00 00
30501 00 00
0 Li OC 00 00 CO 00 00 00
00
0CI 0C 00 00 00 00 00 00 00 00
0(1GL 00 00 00
UO
0(1
0G
0C
3080 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 (00 00 L)G
3.090 O0 00
,(J0R 0
00
10)00 00 00 00 00 00 00
0 U 00 00 (O
30 Hu 00
00 00 00 00 00 CU 00
30CO0 00
00 00 00 00 00 00 00 00 00
0;00
(
3000 00 00
00 00 00 00 00 00 00 00
OU
3010 00
00 00 0 ; FF FF
FF
F F FF FF FF FO 00 00
3020 FF
00
3,030 00
00 00 00 GO 00 00 00
00
3040 00 0 00 00 00 00 00 00 00 00
00
FF
3050 0(
FF FF FF F' FF FF FF 00
00 FF
3060 00) 00 00 00 00 00 00 00 00 FF
00 00
3070 uO 00 00 00 00 P00 00 00 00 00 00
3080 00
00 00 00 00 00 00 FF
FF
3090 [F F F FF FF FF FF FF FF 80 FF
00 00
30AO 00 00 00 00 00 00 00 00 00 00 00
30CB0 OU 00 00 00 00 cO0 00 00 00 00 00
30CO 00 FF
00 FF FF FF FF FF FF FF FF FF
OU
UGG
# 13
8H
# 16
4H
# 19
2H
00 00 00 00 00
00 00 00 00 00
00 00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
O00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
FF
00
00
00
FF
00
00
FF
00
00
00
FF
00
FF
00
00
00
FF
00
00
FF
00
00
00
FF
00 00 00
FF FF FF
3000U 00 00 00 00 00 00 00 00 18 00 00 00 00
FF
301
00 [5 FF FF FF FF FFE FF FF FF FF FF
302 ( fF
EU
FF FF FF FF F5S 55 10 40 00 00 00
3030 00
00 00 00 00 00 0JO 00 00 0 00 00
3040
0
00 10 00 14 00 15 51 55_ 55 F5
F
00
3050.
FF
FF
FF FF FF-F F
F
F
FF Fi- F-FFF
00
30b0(
FF 00 00 00 00 00 [F 00 00 00 00 FF
00
00
00
3070 UL OU UL 00 00 00 00
00
00 00 00
3080 00
55 75 FF FF FF FF
FF FF FF FF FF
3090t
FF FF FF FF FF FF FS 40 O000 00
30nO 00
00 00 00 00 00 00 00 00
0( 00
00 00
30B, 00
00
00 00 Or; 00 00
00 00
30CO FF FF FF FF FF FF FF FF FF FF FF FF FF
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00 00
00 00
00
FF 00
00 00
00 00
FF FF
00
00
0.000
CO 00 00
FF FF FF
00
00
00
FF
00
00
FF
00
00
00 01 11
FF FF FF
00 00 00
00 00 00
F5 F5 FF
FF FF
DC
00 00
00 01
0)
00
FF FF
FF
00 00
00( 00
00 15 00
77
00
FF FF FF
3000 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
3010 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
3020
3030
3040
3050
3060
30/C
3080
3090
30A0
30B0
30CO
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF* FF
FF FF
FF FF
FF FF
FF FF
FFFF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF F
FF FF
FF FF
FF FF
FF FEF
FF FF
FF
FF
FF
FF
FF
FF
F
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
PAGE 51
TRAN MODE
-
SAME DATA FROM RETICON
-
DIFFERENT GATES
GATES
# 27
OOH
6CH
30UU 40 C3 61 44 42 9G 63 08 44 55 64 D7 46 1D 6- 9B
301 B B
B BE; BB BB
BB BBB L B
BBBB
BB
Bb BB B BB BB
3020 BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB
# 28
10H
6CH
3000 61 44 '12 96 63 08 44 55 64 D8 46 ID 66 9C BB BB
3011, RB BB B BE B
B BE RB Rb B BE BB BB BB BB
# 29
20H
6CH
3000 42 98 63 OA 44 57 64 D9 46 1F 66 9D BB BB BB BB
3010 bB BB BB BR BB BB BB BB B BB BB BB BB BB BB BB
# 30
60H
6CH
3000 46 IE 66 9D BB BB BB BB BB BB BB
301U BB BB BE BB BB
BBBB 8B BR B
B
BB BB BB BB
BB BBBB BB BB
* 31
25H
45H
3000 S2 94 73 07 BB BB BB BB BB B
BB BBBB
BB BB BB
3010 bB BB Bb BB BB BB BE 8B BB BB BE BR BB BB BB BB
PAGE 52
VI.
DETAILED OPERATION OF THE INTERFACE
Now that the general operation of the system and the software
related to it have been described, it
is time to look at the nuts
and
in
bolts of
Appendix.
the
as shown
The discussion is broken
each of which
parentheses
give,
system,
the
immediately following
the title
sheet
system.
Numbers in
of each
subsection
numbers of the schematics
on which that subsection's circuitry is located.
of Section VI,
starting on page 100, are
one for each subsection.
matches its related
the
down into eleven subsections,
deals with one function of the
in order of appearance, the
schematics in
Then, at the end
eleven timing diagrams,
The Figure number on each timing diagram
subsection's number.
drawn for a CLOCK rate of 576 KHZ,
The diagrams
since this is
have been
the fastest clock
rate used, with one exception noted later for Fig. VI-0.
A
few
words
development
of the
of CMOS and
the
all,
of CMOS
there were
this
point
Secondly,
CMOS memories.
going to be
Fourthly, some
for this
interface was to
Thirdly, there
in the
available in
was a
large
stockroom, whereas
the
called a selection
functions available
binary counter/divider.
the
why the mixture
the memories
available on TTL chips, as, for
7-state ripple-carry
about
were several reasons
chips could hardly have been
so few.
chips were not
There
chips available
selection of TTL
at
the hardware systems the
CMOS systems.
stockroom were
variety
said
Originally the interface was
CMOS chips.
First of
replace were
be
circuit, since one may wonder
TTL logic.
designed using
choice.
should
in CMOS
example, the 4024
Fifthly,
CMOS
has
lower power requirements than TTL logic.
is much slower than TTL
CMOS logic, however,
timing constraints
possible (by
made
it
necessary and
this time the stockroom
logic, so when
made it
the stockroom
selection of TTL
chips was
growing at an admirable rate),
TTL chips were substituted for CMOS
chips.
it
With
such a
mixture,
is advisable
to attach
pullup
PAGE 53
resistors to TTL outputs that
value a TTL
value
is around 3.4
(Vih) for
practice things
CMOS chips
worked quite
they don't appear
board when
volts)
has a
input high
3.5 volts.
In
pullup resistors,
for TTL
to TTL,
regular CMOS
so
removed, however.
the maximum
is around 0.4 volts,
is
is another
chips
were not
aren't a problem since
maximum input low voltage for CMOS
since
minimum of
was discovered
voltage (Vol)
direction, CMOS
, whereas the
well without
on the other hand,
output low
inputs, since the minimum
in all TTL to CMOS connections; those already on
this fact
The lows,
CMOS
high output (Voh) may have is around 2.4 volts (though
the typical
voltage
feed
1.5 volts.
Going the other
story; drivers
aren't powerful
while the
are required
enough
to drive
TTL
chips.
In the
following discussions, the
chip and
pin
identifiers
are as follows:
IBoard identifier
L~hChip number
U1-5
t
)Pin number
U50-A
-- Gate identifier (for
multiple gate chips)
The Board identifier
may be "U" or "L,"
depending
chip is on Board U (the upper board, i.e.,
of the card cage) or on Board
in the
third slot
used).
The
124
and
125.
and
encircled
location
in
actual board.
chip number
On
those
included
a box
cage, the
of the
schematics on
layouts
along with
corresponding to
On the
the
Board
the board
not being
which a
chip
is
layouts on pages
type and
the chip's
are encircled together, as
i.e.,
of each
number
the chip
schematics, the
in the top slot
second slot
the Board U and Board L
indicated on
located is
L (the lower board,
of the card
sheet number
the one
on whether the
chip
schematic
position on
identifier
for example,
is
e.
the
and the
A few
PAGE 54
oddities
appear, such
number.
P1
as (
indicates a
,
in which
case 33A
multibus connection and
is the
J1,
chip
J2,
and J3
make
timing
cable connections.
VI-O.
QAA-QHH
In
(SH.
order
4)
sy nchronize
to
operations
features more precise, the CLOCK signal
the A
and B inputs of
register
(U15).
At
a 74LS164 8-bit
the
beginning of
generated elsewhere in the circuit
of the shift
START/
pulse goes
hi gh,
11,
to
(U18-15 or 2) is
parallel-out
a
scan
(L38-8),
register (U15-9), which
register (U15-3, 4, 5, 6, 10,
and
fed into
serial shift
a START/
pulse,
feeds the Clear input
clears the Q outputs of that
12, and 13)
disabling the
to zero.
Clear
input,
After the
the
shift
register Clock, U15-8, fed by the 9.216 MHZ multibus Clock, causes
the signal at the A an d B
QA and all the
inputs,
i.e.,
CLOCK, to be shifted into
other Q outputs to be shifted
one position in the
direction from QA to Q H every time it rises.
As can be
diagram and
seen
in Fig. VI-0,
lower diagra m -
2 for
following discussion) follows
after
CLOCK.
QAA (subscripts - 1
respectively,
later.
follows QBB by
108.5
Thus
ns.;
CLOCK that can be used in
QBB
etc.
this
1-7 9.216
follows QAA
As a result,
9.216 MHZ Clock
MHZ Clock
by
of the
periods,
108.5 ns.;
QCC
is the fastest
system because exac:tly eight
9.216
is high and eight while
QHH follows QAA high before QAA falls and
follows QAA low before QAA rises again.
timing details were
in most
The 576 KHZ CLOCK
MHZ Clock pulses occur while the 576 CLOCK
it is low.
out
C LOCK on the first
follow QAA
QBB-QHH
are left
for upper
set up.
It was on this basis that
Thus a signal
lasting
of QHH to
the rise of QAA,
108.5 ns.
If a much faster CLOCK were used, QAA would rise before
QHH fell,
so one
for example, would last
from the fall
would have to wait much of
a minimum of
another CLOCK period
PAGE 55
This would throw off any timing involving a
until QAA rose again.
or vice versa.
rise of one signal and a fall of another signal,
KHZ CLOCK at the top and a
timing with a 576
shows the
Fig. VI-0
KHZ are fine.
that 576
CLOCKS slower
slower CLOCK at the
The timing between two rising, or two falling, signals as
bottom.
the rise of QGG doesn't change,
sho-wn between the rise of QBB and
regardless of
However,
the
signals
between
time
Timing was
in the
would occur
case.
the worst
CLOCK as
the 576
time for things to settle,
Slower CLOCK's would simply allow more
but events
different
in
is much shorter than B-2.
note that B-I
designed for
changing
of QHH and the rise of QAA, varies
directions, as between the fall
with the CLOCK rate;
same length.
and A-2 are the
A-I
the CLOCK rate.
proper sequence.
Faster CLOCK's
would wreak havoc in the system.
VI-l.
This
section
control between
There
are two
of
deals
the circuit
10,
Start
signals,
3, 4, 5)
coordination
with
chosen for
COMP.START is
other possible
11,
the computer.
the interface and
situation when
the
(SH.'S 2,
CLOCK, START, CONTROL
Fig.VI-I
the Start
of
shows
signal.
the generation
of
which will be described before going on to explain Fig. VI-1
RSTART
is
simply the Start
signal generated by
motherboard and described in Section II,
START, on the other hand,
Not
the RC-100A
the Reticon Unit.
60 HZ
is generated from the 60 HZ line signal.
shown on the schematics is the following:
240 K
240 K
60 HZ
PAGE 56
J2-14 feeds into a pair of
HZ, to vary
1N914 diodes that clamp that signal, 60
between -5.6 volts and +5.6 volts.
line another pair
of diodes clamp U23-2
and U23-3 to a low of -0.6
uF capacitors give
1.35 ms.
ground
Vout
frequency to
by the
diode on
to a peak of
1.35 ms.
volts
Thus there
(U23-6) every 8.33
be really
U24
+0.6
The 27K resistors and the 0.05
a time constant of
long pulse at
the signal
volts.
Farther down the
120 HZ.
so that
ms.,i.e., making
Vout
the
is a
is
clamped to
Data input
to the
D
flip-flop (U29-5) swings between ground and +5 volts.
%B, of much higher frequency than 120 HZ, clocks the Q output
of U29-A high following the rising edge
Q/ output of
on the 120 HZ pulse.
U29-A goes low removing the Reset
U29-1 and U29-12 are
both high within 300 ns.
from U29-B.
of
The
Thus
the rise of OB,
causing 60 HZ START (U27-4), the output of the AND gate into which
they both feed, to go high within 550
next
rise of
fB causes U29-12 to
ns. of the rise of XB.
go low and thus
of this rise of VB, 60 HZ START falls.
the 60 HZ
START envelopes one and
(which occurs within
within 550 ns.
The result of this
only one rising edge
250 ns. of the
fall of PB),
The
as
is that
of CLOCK
required by
the Reticon for external Start pulses.
A note
should be made
here about
for proper
functioning of
Section VI-0,
needs to have a positive pulse at
sent out by
the circuit,
least 868 ns.
the Reticon doesn't have that
so it has to be put through
must
RCLOCK also.
be taken
to feed
a one-shot,
U48 so
long
U44.
that when
long.
As
seen in
the CLOCK
The RCLOCK
a positive pulse,
The negative output
the output
of U48
is
inverted by U36-B to form ýA and then later CLOCK, that CLOCK will
have the needed positive pulse width.
With this,
VI-1 and
let
us turn to the explanation
the circuitry related to
it.
A RESET/
of timing diagram
pulse (L69-12),
sent out by the computer to initialize the interface boards, feeds
one input
input,
of L23-A (sh.
EOS/
RESET/ pulse
(U17-2),
is sent
10),
a
two-input AND gate.
is unlikely to be low at
since the
(The other
the same time that a
functions set
in motion
by the
PAGE 57
RESET/
pulse
progress.)
would
invalidate
So, assuming
AND gate,
L23-3,
the remainder
EOS/ (L23-1)
feeds
the clock
of
the
is high, the
input of
scan
in
output of the
a D-type
flip- flop
(L21-3) causing DATA READY/ (L21-6) to go low within 64 ns. of the
rising edge of RESET/ and INT4/ (L35A-13)
thereafter.
The
the flip-flop.
timing is similar
Thus
to go low within 35 ns.
when EOS/ arrives
INT4/ goes low within
101 ns.
and clocks
of the rising
edge of either RESET/ or EOS/, or of the latter of the two signals
to rise should
remains
they both happen to
low until 52 ns. max.
be low at the
after PROC.COMP./
same time, and
(L69-2 and L21-1)
goes low to clear the flip-flop (L21-A) and to disable INT4/.
The
RESET/
pulse
(L69-12) feeds
L33B-C,
setting its
RESET/.
The fall of the other input,
output
the output of L33B-C low.
into
low within
As with
another
24 ns.
SSt/
of
AND
gate,
the fall
of
(U54-2), similarly sets
EOS/, SSt/
is not
likely to be
low at the same time as RESET/ is low.
At any rate, the output of
the AND gate,
ns. of the fall
SSt/
or
L33B-8, falls within 24
RESET/ and
rises within
signals are high again.
L36-1)
BLANK/
of the fall
time when
both
the AND gate output,
outputs, PC (L35-5)
output, BLANKSET/
of either SSt/
and PCSYNC
(L36-6),
or of RESET/.
high within
BLANKSET/ and
(L61-4) are the inputs to a NAND gate, L34-A, whose output,
BLANK GATE (L34-3), goes high 20
low
the
of three D-type flip-flops (L35-1,
setting the Q
(L21-9) to zero and the Q/
64 ns.
of
The low appearing at
L33B-8, feeds the clear inputs
L21-13, and
24 ns.
of either
and low
BLANKSET/
20
ns.
ns. max. after either
max. after
is high, BLANK
both
GATE is
inputs
input goes
are high.
in the same state
While
as BLANK, but
delayed by 40 ns. max.
Another
function
of
RESET/
is to
quadruple D-type flip-flop,
via its clear
the GATE outputs
10,
(U43-2, 7,
and
clear
U43,
a
74LS175
input
(pin
1),
causing
15) to go low
and the GATE/ outputs (U43-3, 6, 11,
and 14)
ns. of
on the other
the fall
RESET/ by
about
of
RESET/.
20 ns.
RESET,
and feeds into
within 35 ns.
to go high within 25
an OR gate,
hand, precedes
U28-C, whose
PAGE 58
output feeds
causing
the Reset
its Q output
of RESET.
input of
(U31-1)
a 4013 D-type
to go
low within 650 ns. of the rise
RESET also directly feeds
4013 D-type
(U31-13),
flip-flop, U31-10,
flip-flop, U31-4,
the Reset
setting
its Q
input
of another
output, COMP.START
low within 400 ns. of the rise of RESET.
Not
shown on
resets the
the timing
outputs of
U37, U40,
and U41)
registers.
several 4508
to
zero.
Three of them -
registers whose
diagram
dual 4-bit
These
various aspects
Thus, sometime between the RESET
scanning
these three
latches must
scanning won't
(U9, U13,
as storage
of the
scanning
pulse and the start of
be properly
take place
other functions that are not shown
they don't affect
latches
loaded from
at all.
some
on this timing diagram because
CLOCK, START, or control
the computer
the
RESET has
functions.
Once all the latches have been loaded and everything
for scanning,
RESET
and U37 - are status control
process.
computer or
fact that
latches are used
U9, U13,
outputs govern
is the
sends out
a PREBLANK
is ready
pulse (L72-6).
Within 40 ns. of the rise of PREBLANK, which feeds the Clock input
of a D-type flip-flop (L36-3), BLANKSET/
max. later BLANK GATE
(L34-3) goes high, as it must
the START/
pulse (L38-8)
(J2-43)
high and thus so
first
is
scan,
i.e.,
to be
generated.
is BLANK GATE.
during power up,
to assure
Between
GATE will
be
scans BLANK
However,
As a result,
To avoid such an occurrence,
that BLANK
in order for
before the
BLANK usually sits
blocking generation of a START/ signal.
would take place.
(L36-6) goes low; 20 ns.
high and
low, thus
no scanning
PREBLANK is sent
thus that
a START/
signal can be generated.
Next,
clocks
a PROC.COMP.
the D-type
(L35-5),
high
flip-flop,
within 25 ns.
D-type flip-flop
Thus PCSYNC
(L54-6)
is sent.
L35-A, setting
PC
causes PCSYNC
is synchronized
Its rising edge
its
Q output,
feeds the data input
(L21-12), so once PC
edge of CLOCK (L21-11)
ns.
signal
goes high the
PC
of another
next rising
(L21-9) to go high within 25
to
(except during RESET) and PRESTART, as
the CLOCK,
as are
we shall see later.
GATE4/
BLANK
PAGE 59
GATE
(L38-12)
isn't
doesn't need to
sets PC
necessarily synchronized
be since PREBLANK sets it
high.
Once
PC goes
to
CLOCK, but
it
high before PROC.COMP.
high, three
of the
inputs to
the
4-input NAND gate, L38-B, are high, and nothing more happens until
the fourth input,
PRESTART (L38-13) goes high.
PRESTART (018-4) may come from
-
COMP.START,
a
one of three possible sources
computer-generated
signal;
RSTART,
generated by the designated Reticon's motherboard;
a signal
generated by the interface
timing diagram shows the timing
CPSTART (L37-8),
is used.
edge of
sets
0B
that
or 60 HZ START,
from the line
voltage.
output (U31-1)
U31-1
Thus when
rises within 300
feeds the D input
U31-1 goes
of another
high, the
next rising
occurs more than 340 ns. after the rise of CPSTART
COMP.START
high within
300
ns.
enabled by a high on its control input,
Assuming that
U42-A
fall
COMP.START (U31-13) and falls within
of COMP.START.
The high on
From
the rise of the
high, a maximum of
first flip-flop
flip-flop (U31-9), goes
low.
by the system, as explained
a period of
1.736
input
us.
150 ns.
of the
PB (U31-11)
of D-type flip-flop,
that
clocks COM1P.START
940 ns. may elapse before the
(U31-1), and
180 ns.
COMP.START passes through a 4071
OR gate, U28-C, on its way to the Reset
U31-A.
is
U42-13, and that U42-B and
U42-C are both disabled, PRESTART (018-4) goes high within
of the rise of
The
CPSTART feeds the clock input of a 4013
rise of CPSTART.
flip-flop (U31-9).
signal
when a computer-generated signal,
D-type flip-flop (U31-3), whose Q
ns. of the
a
thus the data
Q output of the
input of
The fastest CLOCK that
in Section VI-0,
Thus U31-9 is
the second
can be used
is 576 KHZ, which has
low in plenty
of time to be
clocked through to COMP.START on the next rise of AB after the one
that
set
COMP.START high.
COMP.START and
All
the START signal
this
derived
is
done to
assure
that
from it farther down the
line are one CLOCK period wide, the apparently optimum START pulse
width for the Reticon system.
PRESTART (U18-4 and L38-13)
NAND gate,
L38-B, to
go high
is the
and the
last
first
of the inputs to the
to
go low,
so the
PAGE 60
START/ pulse (L33-8)
Measured
from the
within 500 ns. of
OB
that sets
START/
scan underway.
is
COMP.START
first
an SSt/
scan
is
of the first
on the timing
diagram.
scan.
GATE
This
high,
is
PROC.COMP. is not
sent until
The first
scan is,
the second scan
at
the
be generated.
by BLANK staying
remain high, BLANKSET/
through
In normal operation
scanning and processing are finished;
by SSt/
at the beginning of
PROC.COMP. sets them
for another START pulse to be sent.
therefore, most
likely to be invalid, but
is fine because BLANK goes high for the first time
end of the
first scan.
From here
on BLANK falls
at the
beginning of each scan and rises at the end of each scan.
be seen
in the discussion of
first rise
inverted form of
120 ns.
max. after
falls, PC
rises.
Since BLANK/
PCSYNC),
low.
SS falls.
(L61-4)
pulses will
GATE4/, and
is
SSt/, an
after SS rises
and rises
Then, within
(L21-9) fall and
is high during the
be
the
64 ns.
after SSt/
BLANKSET/ (L36-6)
scan, BLANK GATE
during the gated part of the
generated until
go high at
sent following
is low
BLANK falls.
BLANK GATE have all,
GATE4/ and BLANK GATE will
PROC.COMP.
max.
falls 65 ns.
GATE4/ also is low
No START/
same time that CLOCK
of CLOCK after
(L35-5) and PCSYNC
(L38-12) is
scan.
SS,
As will
the "A" memory address circuitry, SS
(U51-9) is high for approximately the
following the
any
(L38-10) goes high whether
we shall see, remain low until
high indicating a readiness
If
the situation pictured
or not.
thus PC and PCSYNC, which are cleared
the scan, as
will
thus allowing
PREGATE pulse that arrives after GATE4/
scanning and processing are finished
other
be generated.
The only problem caused
and BLANK
from
power up and doesn't rise
PC (L35-5) and PCSYNC (L21-9)
low,
falls
470 ns. of the
different
when power is turned on, SSt/
until the end
(L36-6)
high, START/
signal may not
However, BLANK usually stays low during
low is that
in inverted form.
inverted to form START, which sets the
The
scans, however, because
BLANK goes high
but
the rise of OB and rises within
next rise of JB.
first
follows it by 20 ns.,
once
PC (and
thus
again, gone high.
the end of the scan, PC when
end
of processing
for
that
PAGE 61
scan/process period, and PCSYNC following
the first rise of CLOCK
after PC goes high.
VI-2.
STROBEO
(5H.'S 11,
10)
Much of the functioning of the interface boards
by the computer via input and output ports.
(MACR)
and 88H
(OUTRAN), bring
85H,
87H, 89H,
8AH, 8BH,
from the
ports -
8CH, and
8DH
information in the opposite direction,
the interface boards.
The input ports, 86H
information
The output
boards into the computer.
is controlled
8011H,
81H, 82H, 83H,
(see page
i.e.,
As an example of
interface
32) -
carry
from the computer to
output port
functioning,
let's look at port 80H operation.
The computer instruction
to be put
on the multibus address
55, 58, and 57)
in
(P1-68, 67, 70,
negative true form.
valid on the multibus at
of 50 ns.
Thus the
the same time.
and address
Details of
VI-1O.
covered in the
off the
because
to be put on
71,
74, and 73),
data and the
address are
From this time, a minimum
becomes active (low).
discussion of MACR
remain stable a
the
generation, Section
mention the results.
bus and rises
bus.
In the
IOWC/ plays the role played by
correct
the same
of when a valid address (i.e.,
8) is on the
address goes
and at
goes awtay (high).
Suffice it here simply to
is
53, 56,
the timing for BASE ADR/, READ, BOARD ENABLE/, and
falls within 58 ns.
digit
69, 72,
lines of the multibus
minimum of 50 ns. after IOLWC/
54,
the 8080A
elapses before the command IOWC/
Also, the data
XACK/ are
lines (PI-52, 51,
in the A register of
the multibus data lines
in
the address 80H
its negative true binary form
time causes the data
also
- OUT 8011 - causes
s i gnal
within 58 ns.
generation of
IORC/
of
its first
of
is
the
hex
when this
BOARD ENABLE/,
in MACR generation.
interest
two-input NAND gate (L33A-C) whose two
BASE ADR/
output
This is
of
a
inputs are IORC/ and IOWC/.
Thus, BOARD ENABLE/ goes low 40 ns. max. after BASE ADR/ and IOWC/
PAGE 62
are both low
max. after either of
and high 40 ns.
XACK/ goes
goes high.
low from
READ, however,
remains low because one
information
1
13 of
and
through to the DOUT7-DOUTO (J2-39, 38, 37,
10,
where they are stable
from A
U38, and U39),
they were stable
only one of
data, however, will be strobed into
The
on the bus.
low,
five 4508 latches (pins
18 ns. of the time
within
is
35, 34, 42, and 40)
22 of U9, U13, U37,
18, 20, and
16,
36,
inputs of
lines, which feed into the Data
4, 6, 8,
L63)
and
on the multibus data lines passes
Thus data
inputs to B outputs.
L62
two bus transceivers
passed through these
is
the NOR
of the inputs to
IORC/, remains high.
gate generating READ (L37-A),
(pins
ns. after
IOWC/ rises.
after BASE ADR/ or
and rises 63 ns.
READ
and 931
between 796
IOWC/ goes low
Because
these signals
these latches, as we shall see.
of
which output
indicates
by the way.
L41-1
feeds
(or both) of
away,
thus
assuring
Register 0
(U37).
falls 20 ns. max.
after IOWC/ goes away,
the correct
None of the
them because
strobed into
by IOWC/.
fed also
is on
remain high.)
will
The
after either
data
STROBEO goes
Register 0 goes
data at the Data inputs of
that
L41
Since the address and data remain on
them goes high.
away (low) before the
4-line-to-16-line
(The 0 output of
of L41
digit, 0,
(L56-8), rises 20 ns. max. after
are both low and
minimum of 50 ns.
the bus a
the second
74154
gate (L56-C),
output of this NOR gate, STROBEO
IOWC/ and L41-1
a
All other outputs
a NOR
into
L41,
the
enabled (low).
demultiplexer, will be
pin 1,
80H,
are dealing with port
Because we
strobed
was
other four latches had
they each
require a
into
this data
different Strobe
pulse for that purpose.
Once
before the
that the
STROBEO goes
maximum
high, a
desired data is at
and U39) are all
ns. may
the outputs of Register
Output Disable inputs of
U13, U37, U38,
of 760
each of the five
tied low so that
these latches are enabled at all times.)
0.
elapse
(Note
latches (U9,
the outputs of
PAGE 63
VI-3.
PREGATE/DIG VID
(SH.'S 2, 3, 1, 4)
To indicate the start of a
new scan, BLANK (J2-43), which is
sent out by the chosen Reticon's RC
stays low
for the
duration of
100A board, goes low;
the scan.
BLANK feeds
input of a 4013 D-type flip-flop (U50-5) whose Clock
is CLOCK
output
(U18-2), whose Q output
(U50-2) is SCAN.
following the
feeds the
BLANK2X.
input (U50-3)
is SCAN/, and
whose Q/
of another
falls and SCAN
4013 D-type
is again CLOCK
rises.
SCAN/
flip-flop (U50-9),
and whose Q output
(U50-13) is
BLANK2X falls within 300 ns. of the second rise of CLOCK
following
second
input
the data
Within 300 ns. of the first rise of CLOCK
fall of BLANK, SCAN/
data input
whose Clock
(U50-1)
it then
the fall
rise
of BLANK.
of CLOCK
Between
following
BLANK2X, which are two of the
the
the first
fall
rise and
of BLANK,
the
SCAN
and
inputs to U51-A, a 4073 three-input
AND gate, are high and thus gate ýB through to the output where it
appears as SS (U51-9).
(U36-B), delayed
110
Because fB
is
ns. max. by it,
inverted by a 4069
inverter
and then is delayed
110 or
140 ns. max. by a 4050 buffer/converter (U18-A) to form CLOCK, the
fall of 0B occurs
rise
of $B
250 ns.
220 ns.
max. before the rise
max. before
the
(U51-A) then delays the passage of the
that the positive
at which point
It should be
high, followed
the second CLOCK
all
noted that at the end of
after the first
by BLANK2X.
CLOCK
4073
so
Within 300 ns. of the second
falls, BLANK2X falls
SS
The
coincides, timewise,
blocking the
more SS pulses until the beginning
generation of any
scan.
CLOCK.
gB a maximum of 250 ns.
SS pulse generated almost
with the negative portion of CLOCK.
CLOCK rise,
fall of
of CLOCK and the
of the next
the scan BLANK goes
by SCAN/ (U50-1)
Thus BLANK, SCAN/,
and after
and BLANK2X are
high when the next scan starts.
Three 74LS191
synchronous 4-bit up/down counters
and U62) serve as photodiode
loaded
with zeros
within 74
address counters.
ns. of
the fall
(U58, U61,
Their outputs are
of either
RESET/
PAGE 64
(L69-12)
or
of PROC.COMP./ (L69-2), both
inputs of the
counters (pin 11 of
Thus the
gate (U70-C).
start
of a scan.
inputs (pins 4)
fall of SCAN/
go low, which occurs
or 410 ns. max.
the
(the fastest
second CLOCK,
counting
1.736
us),
with the
so
within
This
via an AND
zero before
CLOCK
of the
the first
KHZ, having
address counters
BLANK
CLOCK
the arrival of
used, 576
CLOCK after
the
their G
110 ns. max.
is well before
the photodiode
second
to
after the rise of
of BLANK.
of
reset
the Load
enabled for counting until
following the fall
period
U58, U61, and U62)
counters are
They are not
of which feed
falls.
a
start
Since
the
counters' Down/Up inputs (pins 5) are tied to ground, the counters
will only
count up.
address will
This being the
be 0,
the second
continue until SCAN/
case, the
1, and
rises, following
first photodiode
so forth.
Counting will
the first CLOCK after BLANK
rises.
The
outputs of
the
photodiode
(pins 7, 6, 2, and 3 of U58, U61,
after
CLOCK
rises.
The
address, PA11I-PA4, are fed
4-bit magnitude
U67 compare
L7-LO
and U62),
upper
eight
(U39-5, 7,
11,
17,
19,
address,
then U67-5,
the A>B
set
U65-7, the
smaller than
A<B output,
goes high.
high, meaning the photodiode address
inverters
(U17-B
buffer/converter (U68-E),
U47-C high.
the Start
U64 and
photodiode address
If U67-5 and U65-7
Gate
U65
is
are both
is between the Start Gate and
the End Gate, then the output of the AND gate
delay
address with
End Gate address, and
the
if the
high
the End Gate address.
(U47-B), U65-7 via a 4050
U66 and
the photodiode address with H7-HO
and 23),
19, 21,
pair of 4063
larger than the Start Gate
output,
compare the upper eight bits of
photodiode
U66 and U67).
and 23),
21,
If the photodiode address is
17,
this
of the photodiode
address.
(U38-5, 7, 9, 11,
bits of
comparators (U64 and U65;
9,
are stable 36 ns. max.
into the A inputs of two
the upper eight bits
PAI1-PAO
address counters,
into which they feed
buffer/converter (U68-C) and two 74LS04
and
C)
and
will go high.
The other input to
U67-5
via
This sets one
a
4050
input to
U47-C is high when either BLANK2X
PAGE 65
(U50-13), via a
4050 buffer/converter, or SCANt/
(U68-10)
is low
forcing the output of the NAND gate into which they feed (U7-C)
go high.
Thus PREGATE (U47-8) will
address is
between the Start
either SCANt/
Gate and the
(U63-10) or BLANK2X
condition assures
go high when
that PREGATE
will go
scan, regardless of whether the End
The need for this will be seen
noted,
also,
that
the
designated Gate area
is low.
low at
long as
This latter
the end
of each
Gate has been reached or not.
later.
first
the photodiode
End Gate, as
(U50-13)
to
At this point
seventeen
it should be
photodiodes
will not be seen, the
in
the
first sixteen because
only the upper eight bits of the photodiode address are considered
in the generation of PREGATE and
the seventeenth because the GATE
opens one CLOCK late.
Turning to
timing, from
the rise of
CLOCK that
causes the
photodiode address to fall between the Start Gate and the End Gate
for the first time
may elapse.
to the rise of PREGATE, a
maximum of 2514 ns.
any CLOCK slower than 397.77
With
is 2514
ns.,
(With a
faster CLOCK, PREGATE may
PREGATE will
go high
KHZ, whose period
before the next
CLOCK rises.
not rise until after
the next
CLOCK rises, though the typical delay time is only 1257 ns., which
is
well within
the period of the fastest CLOCK,
period is 1.736
us.)
576
A similar delay occurs between
KHZ, whose
the rise of
CLOCK and the fall of PREGATE
resulting from that CLOCK, when the
fall
fall of U65-7.
of PREGATE
is set low
than the
is due to the
by the rise of
rise of SCANt/),
However, if PREGATE
BLANK2X (which occurs one
CLOCK later
this will
after CLOCK
happen 454 ns.
rises.
PREGATE feeds
flip-flops aboard
the Data
the first
a 74LS175, quadruple D-type
RESET/ feeds the Clear
GATE2, GATE3, and
input of
input (43-1)
of four
flip-flops, (U43).
causing the Q outputs -
GATE4 (U43- 2, 7, 10,
and 15)
- to
the Q/ outputs - GATE1/, GATE2/, GATE3/, and GATE4/
and 14)
-
to go high within 35
PREGATE (U43-4)
goes high, the Q
ns. of the fall
output of the
D-type
GATEI,
go low and
(U43-3, 6, 11,
of RESET/.
When
first flip-flop,
PAGE 66
on
third rises
second, and
the first,
10,
and GATE4 (U43-7,
GATE2, GATE3,
CLOCK.
max. after the next rise of
follows PREGATE 30 ns.
(U43-2),
GATEI
this point
it
thereafter.
At
fall at the
end of the scan.
and
follow GATE1
15)
respectively,
of CLOCK,
PREGATE must
becomes apparent why
EOS (U16-3), the output
of an AND
(U16-A), fed by GATE3/ and GATE4, goes high within 24 ns. of
gate,
the rise of GATE3/
and falls within 24 ns. of
and GATE4 don't fall,
If GATE3
consequently, neither is
setting all
or if RESET/ arrives
low simultaneously, then
the GATE's
the fall of GATE4.
generated and,
EOS is never
and 8).
STROBE8 or STROBE9 (U16-6
by one of these three signals,
any operation triggered
Thus
or by the
falling edge of one of the GATE's, or by the rising edge of one of
the GATE/'S never occurs.
GATE's are generated, let's look
Now that we've seen how the
at what happens to
sent out by
the video signal
First of all, as many as three video signals may arrive at
board.
board -
the interface
VIDI
(J1-32)
They each enter
one of
VID2 (J1-40),
VID3 (JI-38),
3, 2, and 1,
from cameras
respectively.
but only the one from
the 4066 bilateral switches (L4-A, B, or C),
the
camera
designated
be
will
CAM3, CAM2, and
designators -
three designators enter input
signal
swings on
control
swings
CAM1 (U13 pins 13,
VID3, VID2,
inputs
(L4-13,
which VID3,
VID2,
of -5
to +5
and VID1, and
5,
through.
only one of the
11,
switches (L4-2, 3, and 9) are wired
and 9 of
volts to
then sends
and 6) of the
and VID1
5, 7, and
For
feed.
proper
three camera
9).
These
a 4054 level
signal swings of 0
which converts them from
shifter (L8),
volts to
allowed
be a high on
functioning there can
into
the Reticon 100A
to +5
match the
signal
them on
to the
three bilateral switches
outputs of
The
together, so
these
if more than one
switch is enabled, the output, VIDEO, has a fight on its hands.
Assuming that only one video switch
video signal
all,
L2-1,
from
the designated camera.
through an AGC (automatic
that
renders
ANALOG
is enabled, VIDEO is the
VIDEO
passes, first of
gain control) circuit, starting at
VID (L10-15),
a
signal
that
swings
PAGE 67
between 0 and +1 volt and thus
Analog
In
input
to
Conversions take
the ADC-SH4B
4-bit
input
A/D
converter
(U21).
time, when BLANK
is low
to a D-type flip-flop (U20-2),
While BLANK/ is high, START CONVERT, the Q output of the
flip-flop (U20-5) rises
within 45 ns.
within 25 ns. of the rise
of the fall of
inverted by
inverter (U5-A)
(U70-D) on
its way
signal
in the range allowed for the
place only during scan
and BLANK/ (U35-6), the Data
is high.
falls
QAA.
20
conforming to the 20
(U20-1)
ns. and
so
that the
40 ns.
after
ns. min. - 40 ns. max.
in
11 ns.
is low, i.e.,
after QEE falls.
relationship to
it rises,
CLOCK, a
be the one
thus
input
(U21-6).
from 45 ns.
of 400 ns.
after QAA falls
Depending upon when BLANK goes low
conversion could
first CLOCK after BLANK falls.
of interest will
START CONVERT
digital conversion takes a maximum
and occurs while CLOCK
until
an AND gate
positive pulse width
required by the ADC-SH4B for its Start Convert
The analog to
i.e.,
START CONVERT is
and delayed by it and by
to Clear
falls between
The rise of
of QAA/,
occur before
the
Nevertheless, the first conversion
occurring when the first CLOCK, after
BLANK falls, goes low.
The outputs
15),
next
which are
of the
valid from 11
QAA falls,
clocked D
ADC-SH4B converter
are fed
latch (U3-4,
ns.
max. after QEE falls
into the
7, 13,
(U21-9, 11,
Data
inputs of
and 14).
The 4042
follows the output of NAND gate U71-D and thus falls
of the fall
of QFF and rises within
The Polarity
input of the latch
is low the Q
when the 4042 Clock
(U3-2, 10,
and 1) -
11,
220 ns. and that
follow the
20 ns.
(U3-6)
valid until the
which is
until the
of the fall
the
next fall
of
quad
Clock (U3-5)
within 40 ns.
meaning that
DI4, DI3, DI2,
and DI1
inputs after a maximum delay of
of the
is latched by
at the inputs
is
The latch outputs are
4042 Clock
Since A/D
inputs of U3 from
QAA,
a 4042
is tied low
outputs -
next 4042 Clock falls.
valid at
until the
fall of QHH.
when the 4042 Clock rises data
450 ns.
and
of the
latched (until the 4042 Clock falls again).
valid within
13,
and remain
data from U21,
11 ns. after
the rise of
QEE falls
the 4042
PAGE 68
Clock, 20
ns. max. after
min. data setup
QHH falls,
requirement),
(easily meeting the
the outputs of U3 -
50 ns.
DI4, DI3, D12,
and DI1 - are valid from 490 ns. max. after the fall of QFF, or 56
ns. max. after the rise of
the next
QBB, until
some time after the
the 4-bit digital
video signal or A/D
next QFF falls.
DI4, DI3, DI2, and DII,
4063 4-bit magnitude comparator
signal, enter a
chosen 4-bit quantizing level.
are compared with a previously
the quantizing level
value, then
low.
Thus
U8-7
is less than the 4-bit
(the
is
if a 576 KHZ CLOCK
is used).
U8-7
feeds
is clocked by
Thus 60 ns. max. after the next QHH falls the value of
transferred to
(U20-9).
takes
video signal.
comparing inputs is 1250 ns.
of a D-type flip-flop (U20-12) that
the Data input
QHH/.
falls
U8-7 is
after QFF falls (or by about the
is valid 1740 ns. max.
time the next QFF
otherwise
digital version of the
Since the propagation delay time for
max, U8-7
As
place
can be
at a
Q
the
output of
seen on
time
when
changing, but when a change of
If
digital video signal
high;
A<B output) goes
U8 is the 1-bit
(US), where they
the
the timing
the
4042
flip-flop
as DIG
diagram, this
(U3) outputs
U8-7
VID
transfer
could
be
state has not yet affected the 4063
(US) outputs.
In sum, whatever
In input
ANALOG VID signal is present
at the Analog
A/D converter when
START CONVERT
of the ADC-SH4B 4-bit
arrives will be available
in 4-bit
the 4042 latch (U3) as DI4-DI1
digital
form at the outputs of
from 56 ns. after the first rise of
QBB after START
CONVERT until the following fall of
be available in
1-bit digital
flip-flop as DIG
form at
VID from 40 ns.
QFF and will
the Q output of
after the second rise
the U20-B
of QHH/
after START CONVERT until the first rise of QHH/ thereafter.
VI-4.
A/D
A/D mode
(SH.'S 4, 6, 9, 7, 8)
stores the 4-bit
digital video value
generated by
PAGE 69
the ADC-SH4B A/D converter (U21)
eight
1822
for each photodiode
memories (256-word by
memories)
occupying locations
used at a time
static random-access
four memories
to record scan data and since
for one
scan.
overwritten, except at
memory address
LSI
L25-L32. Since
not used, a total of 255x4 or
be stored
4-bit
is
no chance
the last memory
circuitry causes
are
memory address 0 is
1020 4-bit digital
There
in one of the
video values can
that
data
address (# 255),
the memory
will be
since the
address counters
to
stop counting when they reach 255 (the four memories used together
being addressed together).
The 4-bit digital video signal
the 4042 latch
until QFF
falls and
inputs of the
and 11
(U3) as DI4-DI1
from
at the same
56 ns. max. after
time is
U12, and U26).
A/D (U9-19)
must
For A/D mode
be high
selectors - PIXEL (U9-17), TRAN
As long as A/D is high, A/Dt/
and
being
determined
by
rise
of
clock
available at the inputs
of QBB,
i.e.,
of 200 ns.
270
A/Dt
of
U6,
a
transferred
for
the
which 4076
74LS195
inputs are
to its outputs
4076's.
Since the
of the 4076's from 56 ns.
ns. before QEE rises, the 4076
4-bit
by the
data
is
after the rise
data setup time
is satisfied.
i.e.,
(U18-6),
high when
mode
(U9-23) -low.
That 4076 whose Data
When A/D mode is chosen, A/D
period,
12,
At any given time, however,
outputs
the data DI4-DI1,
QEE, the
other three
data inputs enabled,
parallel-access shift register.
enabled has
13,
their Output Disable inputs (pins I
has its
the
14,
operations to
(U9-21), AND STR.L.
and 2 of U30, U25, U12, and U26) low.
of the 4076's
the
the data
(U35-4) is low, enabling the outputs
of the four 4076's by setting
only one
QBB rises
available at
four 4076 4-bit D-type registers (pins
of U30, U25,
function,
is available at the outputs of
long before
BLANK falls
the Data input to
BLANK/ (35-6) goes
flip-flop (U1-6),
74LS195 shift
is set
high during the blanking
and BLANK/
rises,so that
Ul, a D-type flip-flop,
high setting
and consequently
register (U6-9), low.
the Q/ output
the Shift/Load
will be
of the
input of
Shift/Load (U6-9)
the
goes low
PAGE 70
145 ns. max. after BLANK falls and rises 45 ns. max. after the 195
CLOCK
(U6-10) rises;
flip-flop (Ul),
(U6-9) high.
195 CLOCK
setting
(U5-4),
its Q/ output
inverted,
(U1-6)
Thus Shift/Load stays low
144 ns.
after BLANK falls.
same time
time
that Shift/Load goes low
195
CLEAR goes low is
after GATE2/, GATE3,
the NAND gate
195 CLOCK
195 CLEAR (U6-1), on the
BLANK rises and stays
Thus 195
for loading.
and QBB are all
into which they feed
low until
CLEAR goes away
at the end
D
and thus Shift/Load
until the first
pulse (U7-6) arrives and then goes high.
other hand, goes low 89 ns. after
clears the
about the
The
only other
of the scan, 44
high, forcing
ns. max.
the output of
(U32-A) to go low;
195 CLEAR
then rises 44 ns. max. after any one of these three signals falls.
195 CLEAR goes away as Shift/Load goes low for load mode, but both
occur a
long time
before 195
CLOCK rises
to parallel
load the
outputs and then to set Shift/Load high for shift mode.
is
asynchronous
synchronous
and
and
direct,
follow
but
shifting
the positive
and
transition
195 CLEAR
loading
of
195
are
CLOCK
(U6-10).
low
Shortly after BLANK
goes low, Shift/Load goes
until
high
PREGATE goes
transition that causes
B,
C, and
D
(U6-4, 5,
6, and
7)
feeds the Gi
Clock
PREGATE and
4076-A will
that
rises.
4076-A has
the
inputs - A,
into
14,
their
13, and
Since A/Dt/, which
of GATE1,
its inputs enabled
its
register when QEE,
may be a rise of QEE
rise of
began, both Data
enabling the data at
4076 output
simply be replaced by
rises between
CLOCK
inputs of all four 4076's (pin 9 of U30,
There
the rise
195
is inverted by U5-6 to form
was set low before the scan
clocked into the
input,
loaded
QB, QC, and QD - (U6-15,
Disable inputs to 4076-A are low,
to be
be
input for 4076-A (U30-10).
Data Disable
U25, U12, and U26),
of
- to
QA (U6-15), which is loaded low,
the G2 Data Disable
a positive
the data at the Parallel Data
corresponding outputs - QA,
12).
generating
low and stays
but the
inputs
the 4076
between the rise
data gated
through
that gated through by
the QEE
GATE1 and
the entire
the
rise of
time from the
GATE2.
rise of
PAGE 71
PREGATE until the
result the last
the rise of GATE2.
rise of QBB following
4076-A before
data clocked into
its G2 input goes
inputs corresponds to the data
high disabling the
As a
from the first
photodiode after the Start Gate.
The QB,
low, so their inverted forms,
12) are loaded
which feed
(U5-8,
high.
13,
10,
and
and 12),
three 4076's
data will
Thus
be
4076-C when
4076-A, 4076-B, and
being clocked into
blocked from
are
and U26),
U25, U12,
(U6-14,
inputs of the other
the G2 Data Disable
10 of
(pin
of the 74LS195,
QC, and QD outputs
QEE goes high.
the rise of PREGATE clocked U6,
serial
as a D-type flip-flop.
in
the outputs
of U6
parallel
closed ring that
beginning of the scan form a
through the outputs
shift register acts
QD (U6-12) feeds the J-K/ pair so that the
loaded into
inputs
3) are
K/ inputs (U6-2 and
that the first stage of the
tied together so
four
way is clear for QBB to clock
the
The J and
U6.
shifts through
shortly after
Shift/Load having gone high
When GATE2 rises,
in the
at the
fashion
shifts sequentially
QD.
direction from QA to
This
way there is always one of the outputs (QA, QB, QC, or' QD) that
and, consequently, one of
high and three that are low,
G2 Data Disable inputs that
data,
three
and
that
Once QBB rises,
clocking in data.
chosen G2
rise.
to fall
and 89 ns.
disabling
it
other three
G2's to
ns.
before QEE,
max.).
minimum data
data input positions (pins
the latest, 56 ns. after QBB
the 4076
setup time
Clock, rises,
requirement
CLOCK pulse, and therefore of the
rate;
the
narrowest pulse
for the other three
QEE rises (the minimum data
input disable setup time is only 180 ns.
at
from
235 ns. min. before QEE rises
4076's to disable their inputs before
13, and 12),
4076's
for the
data and allows 237 ns. min.
Data is ready at the 4076
those
in
takes 95 ns. max.
max. for the
This enables the chosen 4076
to clock in the
the 4076's
is low, enabling that 4076 to clock
are high,
is
is
rises.
so the
met.
The
15,
14,
This is 270
4076's 200
ns.
width of
the
QEE pulse, depends on the CLOCK
is 868 ns.
(corresponding to
a CLOCK
PAGE 72
min.
meets the 4076's 120 ns.
rate of 576 KHZ), which generously
clock width requirement.
the outputs -
The data clocked into 4076-A arrives at
Q2,
after QEE rises and
4, 5, and 6) 600 ns. max.
Q3, and Q4 (U30-3,
Q1,
stays there until another QEE clocks data into this chip (four QEE
clocks later).
The first QBB to rise after GATE2 rises causes a shift
outputs of
QB
U6.
(U6-14) is
while QA,
now high,
(U6-15, 13,
and 12)
are low.
Thus 4076-B
enabled and
so when
QEE rises
next the
data at
QC, and
QD
data inputs
its inputs
is
The other three 4076's have their
clocked through to the outputs.
data
has its
in the
inputs disabled.
The second QBB to rise after GATE2 rises causes another shift
in the
being clocked
the third
Similarly,
disabled.
QBB
into 4076-C
their data inputs
three 4076's remain unchanged,
while the other
being
resulting in data
U6 outputs,
enables
4076-D
to
receive data.
At this point each of the 4076's is holding a 4-bit
digital video
signal
Data
feeds A3 and
these eight
17)
the Data inputs
of
B3; 4076-C A2 and
the outputs of
B2; and 4076-D Al
Since
their CS2 (chip select)
inputs
chip enable mode, the responsibility for
left to the other
write cycle, the
CS1/
chip select
A3 (L27),
B2 (L30), and B1
A2 (L29), and
(L32))
input
loaded is
counter, and
(L52-11)
During the
enabled at
the
the outputs of
into four memories (either
Al (L31)
or B4 (L26),
B3 (L28),
within
controlled by L52, a 74LS191
its surrounding
each scan feeds
START/ pulse sent out to initiate
Load
the proper
simultaneously.
When the memories are
synchronous up/down
CSI/.
A/D, values at
or
the four 4076's can be, and are, loaded
A4 (L25),
input,
inputs of four memories are
Thus the four 4-bit,
same time.
B4; 4076-B
and BI.
enabling the proper memories for reading and writing at
times is
to the
its outputs
Memories A4 and
1822
1822 memories all have
tied high, i.e.,
sends
1822 memories -
inputs of a different pair of
4076-A feed
(pin
Each 4076
value.
24
ns.
max.
The
circuitry.
into this
Since
191's
Load
is
PAGE 73
(L52-7, 6, 2, and 3) go low
asynchronous, the Q outputs of the 191
74 ns. max. after START/ goes low, and PIXAD (L51-3) falls 140 ns.
max. after START/
for
falls (unless, of course, PIXAD
other reasons).
PIXAD
feeds the
Data
is already low
input
of a
D-type
rise
of QBB
flip-flop (L35-12),
so when PIXAD goes
(arriving at L35-11)
causes the Q/ output of the flip-flop (L35-8)
to
go high
(L52-11)
within 25
ns. max.
to go high within 49
Q/ (L35-8)
max. later.
ns.
low.
will
flip-flop
(L70-9).
computer,
it presets
counting.
Q and
(L52-14)
the G
RESET/
pulse
is
(via L70-10)
thus the G input (L52-4) to
which is
set high before
of QCC
immediately following the rise
disables the
Thus
to the
A/D, goes
so the
follows the inverse of GATE1
the counter,
of GATE 1 does not clock the
enable d
until after
in fact , enab les
Once GATEI falls, the
(L52-14) and
191 Clock
The rise
then QEE
the QCC's
next QCC
rises and
191 counter (L52).
Counting, for
gate (L53-B).
(L52-6
of QEE,
the scan b egins,
counter isn't
while GATE2 is high.
gets through
high.
plenty of
(L52) because the
of QEE.
that occur
Q
A/Dt and GATE1
time before QEE ri ses.
by 74 ns. max.,
the rise
the
or the rise of CLOCK (causing a chan ge of state in
GATE1)
191 counter
rise
buffered v ersion of
just a
Data input to the flip-flop (L70-12)
by 44 ns. max.,
causing the
following the first
go low
by
go high disabling
are high.
after A/D is
low, so the
sent out
flip-flop via L70-11, after both
high just
24 ns.
(enable) input
(L52-5) is tied
which clocks the
A/Dt,
is high).
it is enabled.
the flip-flop
G will
191
is controlled by the Q output of a D-type
When a
(L70-9) and
of the 191
occur until
The Down/Up input
(L52-4)
to the
835 ns. before QCC rises and thus
counter will only count up when
The G input
Load input
(assuming that START/
to the Clock input
No counting
(L52-4) goes
output
and the
is high a minimum of
gates QCC through
low the next
One
A/D mode,
input,
The other two
and 2)
is monitored
L53-5,
by a
is held high as long
inputs (L53-3 and 4) go high
go high.
three-input AND
This happens
when
as A/Dt
is
when QC and QB
the count
of 3
is
PAGE 74
reached.
At
that time the
high making
one
input of
output of
is
The other
held low because PIXELt
(L24-6),
to be low causing,
of that AND gate (L19-8)
through
If,
high, L51-1
PIXELt were
some error,
held low because
in turn, the output of
to be low and thus also
(L19-11)
the AND gate into which it feeds
still be
goes
inputs to the AND gate L19-C, is low causing the output
one of the
L51-1.
(L53-6)
gate (L51-2) high.
the XOR
input to the XOR gate (L51-1)
the AND gate
would
be low
and 7) would
QA and QD (L52-3
gates into which they feed, L53-12
forcing the outputs of the AND
and L19-8, to be low, thus forcing the next
AND gate to have a low
output, L19-11.
L51-1
L19-11
is high, causing
101
feeds L51-1.
QCC that clocked the
PIXAD feeds the
Data
via L35-11 by
is clocked
high, the Q/
input of D-type
QBB. Since PIXAD,
at this
(L35-8)
goes low enabling
the 191
output
outputs, QA-QD (L52-3, 2, 6, and
to the
191
though
PIXAD has
Clock
input
gone low, until the next
to
Q (L35-9)
stored
of QDD
in
arrives at
thus a
and
low, even
L35-11
high to
Q/
rise of QBB,
QCC to pass through to the 191
(L52-14).
While PIXAD
counters
QBB
high within 25 ns. of the
Q/ (L35-8) goes
Clock input
(L35-8) remains
Q/
thus opening the gate for the next
rise
into the 191
resulting in PIXAD going low
7),
(L52-14).
low through
gate the
(L35-8).
to be loaded
ns. of the rise of QBB, and blocking the passage of QCC
within 141
to
flip-flop L35-12 which
the rise of
(L52-11), which causes zeros
Load input
191 counter, L52,
just before the rise of QDD.
to 3, i.e.,
time, is
is low and L51-2
this happening within
to go high,
PIXAD (L51-3)
ns. of the rise of the
Thus
is high,
rise of
to the
are advanced
memory.
which lasts,
four 4-bit
TRANSAD (L51-4) will
values
digital video
be low during
the
address
the memory
next QBB,
the
and the
approximately, from
any scans
done in PIXEL or A/D mode, unless the STR. L. or the TRAN selector
bit (U9-23 and 21)
PIXAD (L51-5)
whose
inputs
were somehow
were both
they feed
set
high, then
would go
high.
If TRANSAD (L51-4) and
the output
low blocking
of the
XOR gate
any writing
into
PAGE 75
memory.
Assuming, however,
that TRANSAD is low,
high, L51-6 goes high enabling the
be generated.
MADCLKW/ falls
MADCLKW/ and WRITE/
20 ns.
rises 40 ns. max. after QFF rises.
its way
to the Count Up
counter, let's
say L65-5.
73 ns.
order for one Count
The
eight
AA7-AAO (pins
the Count
(L65-4 and
7, 6, 2,
the
1,
"A"
and 3 of
Up input
131 ns.
and L65)
(L65-5) rises.
into the
A7-AO (pins 7, 6,
L31).
L29, and
-
counters
) - feed
memories -
in
be high.)
memory address
L49 and L65
L25, L27,
2, 3, and 4 of
lines are stable
and 3 of L49
L49-4) are tied high because
eight address inputs of the four "A"
5, 21,
memory address
cascaded 74LS193
input to count the other must
outputs of
rises and
is delayed 18 ns. on
of the
(pins 7, 6, 2,
pulses to
after QEE
MADCLKW/
The outputs
max. after
(The Count Down inputs
max.
input of the appropriate
4-bit synchronous counters
are valid
when PIXAD goes
These address
after QFF rises and remain so until
just
after the next QFF rises.
pulse (L50-12) falls within
Meanwhile, the WRITE/
the fall of QCC
and rises within 20 ns. of the
74LS257 quad 2-line-to-I-line data selector, L43,
low 58
falls (when PIXAD
ns. after
before
setup time;
overall
its circuitry, for A/D
0, 1, 2,
which
3,..."
function of
least
305
rise at
most
- all
recovery time
the 73LS191 counter,
L52, and
"0,
1, 2, 3,
mode operation,
fourth
amply satisfying
become unstable,
lines
450
1822 memories.
and load data into
occurs every
at least
low for at
ns. min write
these being requirements of the
Thus the
stay
after QFF
write pulse width; and
the address
the 50
generously satisfying
38 ns. max.
lines are stable,
the 250 ns. min.
800 ns.
delays WRITE/ by
Thus, these R/W's fall
the memory address
satisfying
least
is high).
The
forcing these R/W inputs to go
L31)
QCC falls and high
ns. min. address
the 200
ns.,
L29, and
ns. max. after
fall of QFF.-
the R/W inputs of the "A" memories
18 ns. and sends it as R/WA to
(pin 20 of L25, L27,
40 ns. of
count.
fourth latch to be loaded, are valid
is to count
memory on the count
The
outputs
of
of 4076-D,
3
the
58 ns. max. after QBB rises,
PAGE 76
which leaves 51 ns.
min. before QCC rises and thus
before
R/W falls.
The
become
valid three,
before those
valid data
two, and
of the 4076-D.
will
memories (pins
least 51
outputs of
have
15,
one
13,
11,
the Data
Since R/WA is
inputs
for
at
least
satisfying the
memories.
at
inputs of
and 9 of L25,
ns.
250 ns. min.
R/WA falls,
all four
L29, and
"A"
L31)
at
until about 720 ns. after R/WA
least 305 ns.
356
L27,
4076-C
respectively,
by the time that
ns. and will remain there
rises.
4076-B, and
CLOCK periods,
Thus,
been at
4076-A,
51 to 109 ns.
wide, the
before
R/WA
data is at the
rises,
more
data-in-width-effective of
R/WA rises about 720 ns.
at the Data inputs of the 1822's,
than
the
1822
before the data goes unstable
thus satisfying the 50 ns. min.
data-in-hold time required by the 1822's.
Looking at the
timing diagram, one can see
that the outputs
of 4076-A become valid during the latter half of the period during
is 0, outputs of
which the count at
the outputs of the 191
4076-B during count
1, and the outputs of 4076-C and 4076-D during
count 2 and
of
count 3, respectively.
the count
3
period
that the
(L52)
It
is during
four
4076's
the latter part
have their
data
recorded in memory.
VI-5.
PIXEL
From the
know that the
of
the
CONVERT
(SH.'S 4, 6, 7)
discussion of
analog video signal
ADC-SH4B 4-bit
pulse
available as
PREGATE and
A/D
arrives at
DIG VID
present at
converter
the
Start
(U11-2) of one of
bus registers (U11
Convert
DIG VID
and U10).
inputs of
Analog In input
input
the
START
(U21-6)
second rise
is
of QHH/
is fed into the Data
two cascaded 4094 8-stage shift-and-store
These registers
(U9-17), the selector bit for pixel mode,
Output Enable
the
generation, we
(U21-31) when
(U20-9) following the
after that same START CONVERT pulse.
input
DIG VID
operate when PIXEL
is high.
the two 4094's (pins
1 and
The Strobe and
15 of U10 and
PAGE 77
U11) are tied to PIXEL.
shift register has
Strobe input
shift
a storage latch associated with
of a 4094
register stage
register location.
high, data in
4094.
Each of the eight stages of a 4094 serial
is high, as
in
is transferred
When the
in each
its associated
storage
to
Output Enable
input of
the storage register appears at the
of the 4094 follow
When the
pixel mode, data
When both the Strobe and the Output
the outputs
it.
a 4094
is
outputs of the
Enable inputs are high,
the shift register data,
after a
delay.
Shifting takes
when
GATE2, one
place
of
the
in
the two 4094's
inputs
to NAND
U11)
(U10 and
gate
(U7-A),
is
only
high,
allowing the rise of the other
input to the NAND gate, QBB, (which
is
and then reinverted by
inverted
by the NAND gate
(U52-F) ), to reach
and U11)
within
the Clock
a maximum delay of
QBB delayed, rises,
the 4094's
(pins
within 840 ns.,
latest,
4, 5, 6, 7, 14,
i.e.,
register.
13,
12,
and 11
subsequent
make,
After sixteen shifts
sixteen data bits at their outputs,
Q outputs of
U10 and U11)
rises or, at the
shift register (U11-9)
upper order shift
the two registers to
of
4094 Clock,
fall of QBB.
of the lower order
Data input of the
thus cascading
Once the
by 880 ns. max. after QBB
12 ns. after the first
feeds the
40 ns.
inverter
(pin 3 of U10
the shifted data appears at the
The Serial output
shift
inputs of the 4094's
an
register (U10-2),
in effect,
one 16-bit
of these two registers, the
i.e.,
the 1-bit digital video
values of sixteen consecutive photodiodes, are loaded into memory.
The 74LS191
synchronous counter (L52)
and its
support circuitry
govern the loading of the 1822 memories for pixel mode in much the
same way as they
do for A/D mode, as described
two major differences.
First,
40 ns.
rises following
max. after QEE
having been set
clock the
GATE3 is high.
the fall
191
of GATE2.
counter
Thus the
(L52) are
Second, PIXAD (L51-3)
(L52-4) goes low
the rise of
high between scans) and rises 25
QEE rises following
in fact
the G enable input
earlier, but with
GATE2 (PIXEL
ns. max.
after
QCC pulses that
those appearing
while
goes high when the count of
PAGE 78
15
is reached by the 191 counter,
the count of
15
instead of the count
is reached, QD, QC, and QB (L52-7,
of 3.
6, and 2) are
high setting the inputs of the three-input AND gate (L53-1,
13)
and thus
also the output
(L52-3) and PIXELt
of
that AND gate (L53-12)
(L24-6) are also high setting the
two-input AND gate (L19-9 and 10)
output
(L19-8).
two-input AND
At
to go
(L51-1).
The other
high and
gate feeding
and 13)
inputs
are
thus also
input
to
high. QA
inputs to the
the next
high causing
one
input to
it, L53-B,
is held
inputs, A/Dt, which must be low while
PIXEL
stage
the output
the XOR
to the XOR gate (L51-2)
into
2, and
high and, subsequently, also the
point the
gate (L19-12
(L19-11)
the AND
this
When
gate
is low because
low by one
of
its
is high, in order for
the system to function p,roperly in pixel mode.
As can be seen on t he timing diagram, PIXAD goes high shortly
after the
count
of
15 is
counter L52, just as
clocked into
As seen be_fore in
rise
transfers
(L52-11)
to go
goes
low,
(L35-9)
on PIXAD
the Data
low causing the Load input
loading of
forcing the
counter (L52-7, 6, 2,
the
QCC
pulse
(L52-14).
The
load operation causes PIXAD
from reaching
of QBB, Q/ (L35-8)
the
input
Thus the
to the counter
zeros
into the
and 3). and the
next
rise
from
of a D-type flip-flop.
outputs of the
the next
191
the A/D mode discussion, the next
the high
(L35-12) to the Q output
Q/ output (L35-8)
of the
it went high after the count of 3 was reached
in A/D mode.
of QBB
the outputs
counter's
Q
blocking of
Clock
to go low so
input
that at
will go high removing
the load
enable and reopening the gate through which QCC must pass to reach
the counter
counter (L52)
long as
The
Clock
input (L52-14).
counts "0,
1,
...
As a
15,
result of all
0,
1,...,
this, the
15,..."
for as
it is enabled.
clocking
of
the
memory
generation of the R/W pulses to cause
1822 memories
is the same as
when PIXAD is
high.
one clock period
address
counters
data to be written
for A/D mode,
i.e.,
The L52 circuitry starts
later for pixel mode
and
the
into the
happening only
and ends operation
than it does for
A/D mode
PAGE 79
because DIG VID is ready approximately one clock period later than
the corresponding
4-bit digital video
signal data coming
out of
the 4042 (U3).
Data is ready at the outputs of the 4094's, (pins 4, 5, 6, 7,
14,
13,
12,
and 11 of U11 and U10), and thus at the Data inputs of
the 1822 memories,
12 ns. after the
R/W falls 58 ns. max. after QCC
QFF
falls.
The
from 12 ns.
ns.,
fall of QBB, at
the latest.
falls and rises 38 ns. max. after
data-in-width-effective extends,
after QBB falls until
at the
QFF falls, which is
least,
about 314
and meets the minimum of 250 ns. required by the 1822's.
The
data becomes unstable after QBB rises, meaning it is stable around
400 ns.
after the R/W pulse goes away and therefore satisfies the
1822's 50 ns.
min. data-in-hold time.
VI-6. AND VI-7.
STRING LENGTH AND TRANSITION MODES
(SH.'S 4, 10,
In
order
for string
Control Register
PIXEL, A/D,
U9 must
to
result, the Q
low within
to be
a
19, and
21)
low.
(U9-23)
When
D-type flip-flop
after START/
Status
high and
the START/
input of a two-input AND
the output, TRCLEAR (U47-11),
(U34-13) to
output of this flip-flop,
64 ns.
recorded,
with STR.L.
is generated, it enters one
gate (U47-12) causing
input
data
be loaded
and TRAN (U9-17,
pulse (L38-8)
Clear
length
5, 7, 9)
go
and thus the
low.
As
a
TRANSITION (U34-9),
goes
TRANSAD (U72-6),
the
goes low;
output of an AND gate fed by TRANSITION, follows TRANSITION low by
24 ns.,
feeds
into an AND gate (U72-A) causing
to go low within
and within another
24 ns.
its output (U72-12)
110
ns. the delayed,
buffered version, STROBE (U68-4), which feeds the Strobe inputs of
two 4508
low on
latches (pins
TRANSAD feeds
output (U70-6) to
NAND
gate (U71-6)
another NAND gate
2 and 14 of U40 and U41),
into another AND
go low and SLOAD1,
to go
high.
The
to go low.
gate (U70-B)
the output
low on
(U71-A) setting its output
The
causing its
of the following
TRANSAD feeds
into
(U71-3) high within
PAGE 80
20 ns.
and within another 140
ns. setting its
version, OD (U68-2), which feeds the
two 4508's
Output Disable
(pins 3 and 15 of U40 and U41),
passes through
LOAD (U72-8),
another AND gate
low
of U46,
40 ns.
of a
before
thereafter.
QBB (U34-3)
the
As a result,
2, 6, and 7 of U46, U69,
output
However, when DIG
opposite states,
feeds
2).
the XOR
into
As long
within 102
ns.
state into
DIG VID.
of
gate,
to its
that fall of
TRCLK
157
the Q
as they are in
TRCLK
ns.
output
it and
Clock
output,
QHH that
is
low.
STORE VID/ of
input of
a D-type
the flip-flop's
TRANSITION
clocked the
remains high,
the same
(U56-3),
goes high clocking the high at
(U34-12) through
Data
STORE VID/ are the two inputs
TRCLK, which feeds the
Data input
least
through to
VID changes state, making
flip-flop (U34-11),
(U34-2), the
settled at
clock it
DIG VID and
of
does so between the rise of
and is
rises to
XOR gate (U56-1 and
state,
191
of three 74LS191
U69, and U57).
it
It
D-type flip-flop,
(U34-5) as STORE VID/.
to an
output,
used to generate string length
When DIG VID changes state,
input
The START/ pulse
low within 74 ns. of the fall of START/.
DIG VID (U20-9) is the signal
QHH/ and
inputs of the
(U72-C) setting its
the Q outputs of these counters (pins 3,
data.
high.
and thus also the Load inputs
synchronous counters (pin 11
and U57) are all
delayed, buffered
(U34-9),
change of
for sure, from
17 ns.
max. after DIG VID changes state, (or 77 ns. max. after QHH falls)
until STORE VID/ changes state to agree
after QBB
rises.
which is greater
by the 74LS74
Therefore TRCLK is
ns. wide,
pulse width required
flip-flop (U34).
cleared by a low
on TRCLEAR, which
of the flip-flop (U34-13).
max. after START/
falls.
falls
again
and
a minimum of 130
than the 25 ns. min. Clock
TRANSITION is
Clear input
with DIG VID, 40 ns. max.
high
TRANSITION falls 64
TRCLEAR goes
It also goes low 64 ns.
44
ns.
max.
after
QGG
ns. max. after START/ falls and
feeds the
low
24 ns.
max. after QFF
falls.
Thus
104 ns. max.
after QFF falls.
TRANSITION rises 102 ns. max. after QHH falls, which could be
PAGE 81
before or
after CLOCK
after CLOCK
rises.
(U9-21),
but
(U72-5) is
is high.
output of the three-input AND gate,
both TRANSITION
latest,
the same
fed by the output of an
(U9-23) or TRAN
Assuming U56-6
so before the scan began),
(having been set
max.
a three-input AND
which is high if either STR.L.
not both of them,
30 ns.
rise at about
two inputs (U72-3 and 4) of
The third input
XOR gate (U56-6)
GATE3 rises
TRANSITION and GATE3
time and feed into
gate (U72-B).
(U18-2) rises.
is high
TRANSAD (U72-6), the
goes high within 24 ns. after
and GATE3 have gone
high, which will be,
at the
by 54 ns. after QAA rises.
TRANSAD, in
its high state, gates through the signals causing
the 1822 memories to be written
into.
before, TRANSAD is inverted by a
First of all,
as mentioned
NAND gate (U71-A) and delayed by
a 4050 buffer/converter (U68-A) to form OD, which feeds the Output
Disable inputs of two 4508's (pins 3 and 15 of U40 and U41).
result,
OD goes low within
within 160 ns. of
As a
160 ns. of the rise of TRANSAD and high
the fall of TRANSAD.
Data
is
available at the
outputs of these 4508's from 180 ns. max. after OD falls until
ns. max. after OD rises, or from
until 340
180
340 ns. max. after TRANSAD rises
ns. max. after TRANSAD
falls. Thus the outputs
of the
4508's are enabled from 466 ns. max. after QHH falls until 468 ns.
max. after QFF falls.
Secondly,
when
(U72-A) to go high
max.
after
TRANSAD is
The
through a 4050
output
of
feeds the Strobe inputs
and 14 of U40
and U41).
falls
184
ns. max.
after QEE
pulse width required by the 4508's.
the outputs of the 4508's
of
10 ns. before QGG rises.
gate
pointed
the two 4508's
out
to form
(pins 2
ns. max. after QCC
rises.
Thus
STROBE is
the 140 ns. minimum Strobe
The delay time from Strobe to
is 260 ns. max.
is at the outputs of the 4508's
AND
rises until 44 ns.
U72-A, as
STROBE goes high 164
approximately 237 ns. wide, satisfying
by
enables the
buffer/converter (U68-B)
STROBE, which
rises and
it
from 24 ns. max. after QCC
QEE rises.
earlier, passes
high
Therefore, strobed data
by 424 ns. after QCC rises,
i.e.,
PAGE 82
The data feeding the Data
10,
16,
18,
20,
and 22 of
inputs of the 4508's (pins 4, 6, 8,
U40 and U41)
are available
outputs of the 74LS191 counters (pins 7,
and U57) within
36 ns. of the
counters to count, as
input(s) (pin
(pin 5
4 of U46,
of U46,
U69,
6, 2, and 3 of U46, U69,
rise of CLOCK, which
long as
191
LOAD (U72-8)
U69, and
U57)
and U57) are tied
from the
low.
is
causes these
high and the G
The
Down/Up inputs
low so that
the counters
only count up.
Thirdly, a high
controls the
on TRANSAD enables a HNAND
loading of
the counters
(U46, U69, and
TRANSAD and STR. L. are both high, SLOAD1,
(U71-B) goes low 88
68 ns.
QDD falls.
low within
SLOAD2, the
20 ns. max.
U57).
the output of
ns. max. after QAA falls and
max. after
U71-C, goes
gate (U71-B) that
When
NAND gate
stays low until
output of
NAND gate
rise of
GATE2/ and
of the
stays low until 20 ns. max. after GATE2/ falls (assuming STR.L.
high).
SLOAD2
is low
SLOADI only when
fall of GATE3.
when
mostly during
SLOAD1
occurs between the fall of
(U72-C), with the
while GATE2 is
low,
the
other two
inputs
to
one exception just mentioned,
GATE2 and the
It takes a maximum of 50
191 LOAD (U72-8),
11
of
which feeds
U46, U69,
and U57),
the AND
gate
are high.
high, loading of the counters (U46,
is controlled by SLOAD1.
counters (pin
and overlaps
The START/ pulse occurs before the scan begins, so
SLOAD1 goes
time that
non-scan time
U69, and U57)
ns.
the Load inputs
goes low
Thus,
from the
of
Q outputs are in
flux from some time after the
after QAA falls. 191
LOAD stays
falls, so since no CLOCK's arrive while 191
high), the Q outputs of the three
191
the
until the
outputs (pins 3, 2, 6, and 7 of U46, U69, and U57) are valid.
162 ns. max.
is
Q
The
fall of QAA until
low until after QDD
LOAD is low (and GATE2
counters (and thus the Data
inputs of the 4508's) are stable from 162 ns,. max. after QAA falls
until the next CLOCK rises.
During a CLOCK period in which TRANSITION goes high, the data
to be written
into the 1822 memories
U46, U69, and U57 and thus at
is valid at the Q outputs of
the Data inputs of the latches
(U40
PAGE 83
and U41)
from 36 ns. max.
QAA falls.
The STROBE pulse arrives
and falls
strobed
after CLOCK rises until
184 ns.
max.
into the
164 ns. max. after QCC rises
after QEE
4508's
is
shortly after
rises.
at their
Thus
the data
Data inputs
to be
over 380
ns.
before STROBE arrives (the required data setup time for the 4508's
is only 50
ns.)
and stays until
low (no hold time is
is strobed
required
into the
about 250 ns. after
by the 4508's).
U40 and
U41, and
STROBE goes
Thus, correct
that data
data
remains stable
until the next STROBE pulse arrives. (See Fig. VI-7.)
Fourthly, when TRANSAD
XOR gate, L51-B,
goes high, it sets the
high, (assuming that PIXAD is
be during string length mode
of MADCLKW/
ns. max.
after QAA rises,
low, or, at
low,
as it should
operations), enabling the generation
(L71-8) and of WRITE/
after TRANSAD goes
output of the
(L50-12).
high, or, at
and stays high until
the latest, by 37
L51-6 goes
the latest, by
17 ns.
71 ns.
after TRANSAD goes
ns. after QGG falls.
high, approximately, from the
high 17
Thus L51-6
rise of QBB to the fall
is
of QGG and
thus is high when needed to gate through the signals that generate
MADCLKW/
(from the
rise of
QEE to
the
rise of
signals that generate WRITE/ (from the fall
QFF).
In the discussion of A/D mode,
is high,
the address lines of
stable from 131
QFF) and
of QCC to the fall of
it is shown that, when L51-6
the appropriate 1822
ns. max. after QFF
the
memories are
rises until the next
rise of
QFF, and the R/W pulse goes low
from 58 ns. after QCC falls until
38 ns.
Valid data
max. after
QFF falls.
inputs from the 4508
ns. before QGG
latches (U40 and U41),
rises.
after QHH falls until
after QDD rises, at
the latest.
the rise
at
the 1822
Data
latest,
by 10
the
The 4508 outputs are enabled
468 ns. after QFF falls,
Thus the
data at the 1822 Data
the next rise
least 760 ns. before R/W falls
data-in-width-effective time
400 ns. after R/W
so
from 32 ns.
QBB rises, at
inputs
of QBB,
from 466 ns.
i.e.,
the latest, until 34 ns. after
of QGG until
valid about
is at
is valid from
it is
(thus meeting the 250 ns.
required by the
1822's)
rises (thus meeting the
valid at
minimum
and remains
1822's 50
PAGE 84
ns. minimum data-in-hold time requirement).
So,
in
U69,
U46,
string length data
U57 - are loaded with
and
After GATE2 goes high the counters
CLOCK
U46,
as the
in
O's at the start
counters (U58,
count
state,
sets in
it
in the
in
these three
motion the
string), and MEMA
-
(1 bit
value of
STORE
DIG VID
VID
and U57),
that the
the
this way,
if a
following a
transferred to
state of
the
length data
respectively) and
data of the
"A"
or "B"
by the time
VID/,
length
the first
recorded is
the new
making
data
being
1's
the camera
counts 1;
CLOCK period
1, as
it should
1 photodiode, which would
change state each CLOCK
period, in
would be recorded for the string
other three bits
which camera is being
2-bit camera
are enabled)
transition occurs during
mode -
changes
U69, and U57) are loaded with O's so
DIG VID were to
The
STORE
string
(once the counters
which case a whole series of
the DIG
12-bit count
along with a
This makes possible a resolution of
lengths.
VID
latches, U40 and U41,
load, the string length
be needed if
DIG
STORE VID is used because
The counters (U46,
first CLOCK
When
indicating which memory bank -
is already
match
recorded.
be.
counters.
information is strobed into the
U62).
to the same photodiode as
indicating the state of the
into).
is being written
the
bit
and
so that
machinery to record the
counters (U46, U69,
number, STORE VID (1
U61,
starting to count
VID signal being acted upon corresponds
does the
of a scan.
start counting, using the same
photodiode address
U69 and U57 are delayed
counters -
mode, the synchronous
of
information stored
number, a 2 bit
number specifying
used (U40-4 and 6 coming from
MEMA (U40-10
from L20-8
for string
via J2-5)
U28-3 and 4,
- are
set
before the scan and don't change during the scan.
TRAN mode (transition mode) functions
STR.L mode (string length mode) does,
counters (U46,
time a
only at
U69, and U57) are
transition occurs.
the start of
BLANK2X falls.
This
the same way that
with the exception that
not reloaded with
Instead,
a scan and then
they are loaded
start
way they contain the
the
zeroes every
with zeroes
counting as
soon as
photodiode address for
PAGE 85
the current
DIG VID signal so
address stored is
i.e.,
the
that when a transition
that of the first
address of
the first
itself.
The other four data bits,
and the
states of
STORE VID
occurs the
photodiode in
the new group,
photodiode after
the transition
indicating the camera selection
and of
MEMA, are
the same
as for
string length data mode.
VI-8. "A" MEMORY ADDRESS CIRCUITRY
The timing
diagram shows
(SH.'S
11,
7, 8, 2, 3, 10,
three scan/process
periods, i.e.,
the time between two successive PROC.COMP. signals sent out
computer, and
many scans.
input to a
part of a
midst of
The rising edge of PROC.COMP. feeds L20-11,
the Clock
(L20-12),
to switch states.
MEMA high
into MEMB (L20-9),
thus causing MEMA and MEMB
and MEMB low,
in which case
the "A" memories
will be
into during the first period shown.
counters
- L49
counters) -
and L65
low
it also
to be cleared
within 35
PROC.COMP./
causes the "A" memory address
(two 74LS193
outputs of these counters
to set
is also the
The first PROC.COMP. on the timing diagram sets
When PROC.COMP. rises,
all
by the
taken from the
D flip-flop, clocking MEMA (L20-8), which
Data input
written
fourth period,
9)
ns.
via pin 14
of
the
(L44-9)
rise of
The Q
and L65) are
PROC.COMP.
Meanwhile
input of the L44-B flip-flop
high, thus
Load inputs of the "A" memory address
up/down
of these counters.
(pins 3,2,6, and 7 of L49
falls enabling the Preset
its output
synchronous 4-bit
removing the low
counters (pin 11
from the
of L49 and
L65).
Next,
the computer sends out
feeds
into a NAND gate, L67-B.
MEMB
(L20-9),
consequently
is
low
the Output
latch (L47-3 and 15)
latch.
at this
an OUTRAN pulse (L54-12), which
The other input to this NAND gate,
time, so
Disable inputs
remain high
the
to the
output L67-6,
4508 dual
and
4-bit
disabling the outputs of the L47
PAGE 86
The START
PROC.COMP.
pulse, sent
signal has set
to the
Reticon some
time after
things up for a new scan,
on the timing diagram, but
the
is not shown
its existence is implied by the lows on
the BLANK signal.
Once BLANK goes low, the positive portion of $B
(U48-3) occurring
soonest after
through a
4073 three-input
pulse, U51-9.
falls 250
Because %B
ns. before
maximum delay
of
rises 220
ns. SS
negative portion of CLOCK.
two-input
Reset
inputs of a
CLOCK rises
AND gate, U51-A,
CLOCK rises
250
a 4081
the first
to generate
ns. before
and because
U51-A can
coincides, approximately,
SS and
of the latch (L47-5, 7, 9, 11,
19,
21,
430 ns. of the rise of SS (or of the fall
have a
inputs to
L68-4, feeds the
inputs follow
17,
and
with the
MEMA (L20-8) are the
4508 latch (L47-pins 1 and 13).
and the Reset
the SS
CLOCK falls
AND gate, L68-B, whose output,
already high, L68-4
is gated
Since MEMA
SS.
is
The outputs
and 23) are low within
of CLOCK).
Now that the outputs of the "A" memory address counters (pins
3,2,6, and
7 of L49
latch (pins 5, 7,
all
and L65) and the
9, 11,
17,
is ready for scanning.
counter (L65)
to count
19,
21,
outputs of the
and 23 of
COUNT A (L43-4)
up via
L65-5, the
dual 4-bit
L47) are all
low,
causes the lower order
Count Up
input.
The
Count Down inputs (pin 4 of L49 and L65) are tied high because the
Count Up pulses can cause the counters
Down inputs
feeds the
are high.
The Carry
Count Up input,
L49 into L65.
output, pin
only if the Count
12,
of
5, of counter L49,
input of
MEMB
With
counter L65
thus cascading
(The Carry output produces a pulse
to the Count Up
tion exists.)
pin
to count
equal
in width
its own counter when
an overflow condi-
low, the Select
to
2-line-to-l-line data selector (L43-1)
input
a 74LS257 quad
is low causing the A inputs
to be passed through to the outputs.
Thus COUNT A (L43-4)
MADCLKW/ (L71-8),
after QFF rises and falls 38
rising 38 ns. max.
ns. max. after QEE falls.
of L49 and L65)
The
counter outputs (pins 3,2,6, and 7
are stable within 73 ns.
which feeds L65-5,
and thus within 111
and stay stable until
follows
of the
rise of COUNT A,
ns. of the rise
just after the next QFF rises.
of QFF ,
PAGE 87
On
the timing
pulse, but
it
diagram
could
receive as many
the particular mode
(U17-2)
in use
44 ns.
falls
is
hig h,
ST ROBE8
goes low.
max.
(L47-5, 7, 9, 11,
of STROBE8.
Within 30 ns. of
the third
17,
19,
and
The data latched
rise s one
after GATE4 (U43-15) falls.
inputs of
is
4-bit
the dual
the outputs of the latch
23) within 260 r1s.
in
When
EOS/ (U 17-2)
goes high as
Data is at
21,
falls.
GATE3 (U4 3-10)
GATE3 falls an d
the Strobe
latch (pins 2 and 14 of L4 7).
one
gate for
STR OBE8 (U16-6)
feeds
receives only
as occur while the
max. after
44 ns.
period later, i.e.,
MEMA (U16-4)
is high.
(L65-5)
after PREGA TE (U47-8) falls,
rise of CLOCK
EOS/
COUNT A
the last
"A"
of the rise
memory address
into which data was written during that particular scan.
Nothing else
PROC.COMP.
happens until
signal.
As
the computer
before, the
outputs of
address counters (pins 3,2,6, and 7 of
another
the "A"
memory
L49 and L65) are low within
35 ns. of the rise of PROC.COMP. (L54-6 and pin
and the memories switched within 40
serids out
ns.
14 of
L49 and L65)
Now MEMA (L68-5)
is low,
so the SS signal generated at the beginning of the scan is blocked
from passing through the AND gate
latch (L47).
(Instead SS
(L67-4)
the
is high
,
outputs of the L47
emory address counters
NAND gate,
L67-B,
will
go
-
reset the
L48.)
sent out from
low enabling
holding
into during the previous scan, so this is the data
and 23) within
200 ns. of the rise of
high
395 ns. of the
approximately
(P1-57, 58,
timing as
the data
55, 56,
120
70,
rise of OUTRAN.
ns. after
53, 54,
described for MACR
51,
the
and
69, 72, 71,
OUTRAN
multibus
19,
52) are
written
into)
74, and
(L54-12) goes
address
stable (the
generation - Section
(the last memory address
17,
OUTRAN (L54-12) and on
the data lines of the multibus (P1-68, 67,
73) within
the
the last memory
that appears at the outputs of the latch (L47-5, 7, 9, 11,
21,
MEMB
latch via the Output Disable inputs (pins 3 and
The latch outputs are still
address written
L68- A to
though, so when OUTRAN (L67-5) is
computer, the
15 of L47).
s passed throu gh
the "B"
latch connected to
(L68-B) to reset the dual 4-bit
VI-10).
is valid
lines
same
Thus
on the
PAGE 88
multibus data lines
from 515 ns. max. after
lines are stable (with, of course,
OUTRAN) until
READ
just after IORC/
(L37-12) falls
the multibus address
the proper address to generate
(P1-21 and L37-1)
blocking
the passage
rises,
of
i.e.,
when
data through
the
74LS242 bus transceivers (L62 and L63) onto the data bus lines.
In order
L27,
to move the data
L29, and L31)
the computer
number of
in the "A"
during the last scan to the
must send
memory address
stored
two MACR read
filled,
i.e.,
when the OUTRAN pulse was sent
SBC 80/20 memory,
signals (L54-8)
twice as many
memory locations filled,
address of
this number having
out.
the last
for every
MACR signals
as the
been read
No adjustment of this number
is necessary because the first address used was
case the
memories (L25,
1, not 0, in which
location filled
equals the
total
number of memory locations filled.
Within 21
starts
ns. of the rise
following 43SEL
Because
only address
during the
last
of MEMB (L43-1), COUNT
(L43-3
01
of
from L20-5)
the
and
"A" memories
scan, OUTRAN read
A4,
A3,
A2, and
described in
Al
MACR generation,
L54-8) sets 43SEL
order
address
pulse
Since
sets 43SEL
a
(L25,
was written
into
computer will
in location 01
L27,
the first
(L65)
43SEL
and A3 memories
undergoes
low.
L29, and
MACR pulse
of the
L31).
As
(L20-3 from
(L20-5 and L43-3) high and thus pulses the lower
counter
counters to 01.
the A4
memories
thus goes
01 and thus the
send two MACR pulses to read the data stored
A (L43-4)
and
negative
doesn't advance the
21SEL
"A"
in
high.
instead
L49 and L65;
of
of
second MACR
Because
the
43SEL
positive
second MACR pulse
what it
the other two "A"
address
location 01
The
advance the counters, the
01 of
memory
is read.
(L70-5)
transition,
counters,
the data in location
the
is high, the data
(L25 and L27)
low
transition needed to
setting
does is cause
memories, A2 and Al
(L29 and L31), to be read and put out onto the data bus.
The next PROC.COMP.
that MEMA
outputs of
(L20-8)
is
sent
high and
out again switches
MEMB (L20-9)
the memory address counters
the memories so
low and
clears the
(pins 3,2,6,and 7
of L49
PAGE 89
and L65).
the "A"
MEMB (L67-4)
is
memory address
high, so
SS (L68-6)
outputs
(L47-5,
circuitry; MEMA,
is
7,
low,so OUTRAN (L67-5)
11,
17,
19,
on the
other hand,
L68-B to reset
passed through
9,
doesn't affect
21,
and
23)
is
the latch
low.
This
scan/process period, the third one shown on the timing diagram, is
like
the
first,
counters (L49
that
except
and L65)
it
reach
shows
what happens
their maximum
when
the
count of 255
(FF in
the counters (pins 3, 2,
6, and
hexadecimal).
When all
of the Q outputs of
7 of L49 and
has been
equal
L65) are high, meaning the count of
reached, the
in width
(L49-5),
to
the
(which is
(L65-5) of the
Carry output
Count Up
also equal
(L49-12) sends
input
in width
lower order counter).
feeds the Clock
255 (FF
of
that
to the
This
same
(L44-9) to go low within 40
the Load
the two
counters (pin
pulse
counter,
Count Up
input of a D flip-flop (L44-11);
inputs to
out a
Carry output
causes the Q output
in hex)
input
(L49-12)
its rising edge
ns. and likewise
11 of
L49 and
L65).
These Load inputs remain low from 40 ns. max. after Carry (L49-12)
rises
until
computer.
outputs
the
next
PROC.COMP. signal
Within 40 ns.
PROC.COMIP./
the 74LS193's,
is
independent of
of
(L44-10), which
L49 and
the
count
counters reach
removes the low from
L65) by
presetting the
until a
a count
of 255 (FF
PROC.COMP. signal
STROBE8 pulse (U16-6 and L47-2 and
number 255 (FF hex)
the
low, the Q
setting MEMA
hex),
the Load inputs
Q output
they
arrives. In
14)
pulses, so
of the
D
Thus, once the
are held
at that
the meantime
the
is generated to strobe the
into the dual 4-bit latch, L47.
The next PROC.COMP.
memory
by
of Load and the fall of
flip-flop (L44-9) high, are blocked from counting.
number
out
of when these Load inputs go
any count pulses arriving between the fall
11
sent
(pins 3, 2, 6, and 7 of L49 and L65) are loaded with ones.
Load , for
(pin
is
low and MEMB
address counters
pulse arrives, switches the
high,
and
to zero.
therafter, enables the outputs of the
memories by
sets the Q outputs of the "A"
The OJUTAN
latch
pulse, sent
(047-5, 7, 9, 11,
soon
17,
PAGE 90
19,
21,
and 23), as described
earlier for the second scan/process
period, so the number 255 (FF hex) is
taken
in by the computer.
This covers the
counter
circuitry.
addresses to
memory
"A" memory address
It
generating
alternates
into
between
during one scan/process
be read
from during
the next
way as
the "A"
times.
circuitry
memory
That
is,
is generating
memory address
from,
address counter
when
the "A"
addresses to
counter circuitry
and
vice
scan/process
essentially independently
memory address
be written
The
two
of each other,
in the
circuitry, but
is generating
versa.
memory
period and
The "B" memory address counter circuitry functions
opposite
read
basic functioning of the
be written
addresses to
period.same
put out on the data bus and
counter
into, the
addresses to
circuitries
under the
at
"B"
be
operate
direction of
the 74LS257 data selector, L43.
VI-9.
READ
(SH.'S 11,
7, 8, 3, 9)
During initialization procedures, a
sent out
by the computer.
Within
MEMB (L20-9)
is high and MEMA
(L20-5) and
21SEL (L70-5)
finished with whatever
PROC.COMP. signal
scan.
40 ns. after RESET/
(L20-8)
are both
to start
(L54-6) to set
things
and L31)
will
MEMA
memories (L26,
two successive
it
is
sends out a
in motion to start another
(L20-11)
rises, MEMB
is low
is high, so the "A" memories
into them during
scan/process period
PROC.COMP. signals),
the first, what would be read
be the
information written
being the
while the
L28, L30, and L32) will be read from.
any scan other than
memories would
the computer
have data written
scan/process period (a
time between
When
Sometime therafter a START pulse will be generated
L29,
the coming
goes low,
Within 64 ns. 43SEL
processing it needs to do,
the scanning routine.
(L25, L27,
is low.
low.
Within 40 ns. after PROC.COMP.
and MEMA high.
RESET/ pulse (L69-12) is
"B"
If this were
out of the "B"
into them
during the
PAGE 91
previous scan/process
period.
However, since
scan, the "B" memories have garbage
in
this
is
them, so that
the first
is what will
be read.
When the computer has finished reading from the "B" memories,
it will
send out
a READ COMP/
signal
L33B-A, will clear 43SEL and 21SEL
has finished
to 0.
signal,
L20-B flip-flop,
to do,
which, among
causing
MEMB and
MEMA
MEMB high
written
into and the "A" memories read from.
are
written into
low.
is covered
Now
in
it will
send out
other things, will clock
making
and MEMA
via AND gate
Then after the computer
whatever processing it has
another PROC.COMIP.
the
(L69-4) which,
to switch
the "B"
the A/D
states,
memories will
be
The way the memories
mode description.
Of
interest now is how the memories are read.
The PROC.COMP./
flip-flops (L44-A
memory address
pulse presets
and B),
the Q
thus disabling
counters (pin 11
of
At the end
memories were
L49, L65, L64, and
of the previous
having data
written
location
into 4508
written
latch L47.
switched the memories,
out an OUTRAN
signal
into L47 at the
into
into
them and
making MEMB high.
Now
(L54-12) to read the
and
OUTRAN
Since
feed
-
MEMB
L67-B -
is already
low,
and,
the 4508 latch (pins 3
19, 21,
180 ns. max.
later.
a PROC.COMP.
memory address strobed
low, enabling the Q outputs (L47-5,
knows how many memory addresses
to be latched
the computer sends
and 15 of L47)
multibus data lines and sent to
was
force the output of the NAND
consequently, the Output Disable inputs of
and 23)
the "A"
when MEMA
data was latched,
end of the previous scan.
which MEMB
and
causing the memory address of
high, the positive OUTRAN pulse will
gate
L66),
scan cycle, when
in the "A" memories
Since that
of the
0 via their Clear inputs
into
high, STROBE8 (U16-6) was generated
the last
two D-type
the Load inputs
PROC.COMP. clears these same counters to
(pin 14).
outputs of
7, 9, 11,
17,
These outputs are put on the
the computer, so the computer now
it has to read.
For every memory address to be read, the computer must do two
reads because
at
each
memory address there
are sixteen
bits of
PAGE 92
data (four data bits in each of the four "A" memories) to be read,
whereas the
receive
multibus has only eight
data.
Each
time the
data lines via which
computer
wants to
memories it sends out a MACR pulse (L54-8).
was set
COMP/ (L69-4)
high when READ
PROC.COMP.
was sent,
43SEL feeds
feeds the
the Data
and L70-3),
43SEL goes high
the
43SEL/ (L20-6), which
Data input
goes high clocking these flip-flops
read from
cleared 43SEL to
input of flip-flop
it can
of
0 before
flip-flop
L70-A.
Thus
L20-A.
when MACR
via their Clock inputs (L20-3
within 25
ns. and 21SEL
stays
low.
The next MACR pulse sets 43SEL low and 21SEL high. Each MACR pulse
after that
changes the state of
and 21SEL
i.e.,
are in opposite
until READ COMP/
is
43SEL and of 21SEL.
states throughout the
sent (at
Thus 43SEL
reading period,
the end of the reading) to set
them both low.
GG (L33A-6), the output
high from
20 ns. max. after
falls until
rises.
of a NAND gate, is a
one of
20 ns. max. after
ns.
its inputs,
GATE1/
(L33A-4),
its other input,
GATE2/
(L33A-5),
max. after GATEI
GATE2 falls, thus
and L32)
rises until 64 ns.
enabling the four "B" memories
for this period
of time.
MEMA,
low, forcing the output of the NAND
(L34-11), high.
Since GGA
gate
is one of
(L60-8)
will
follow L71-12.
(L20-5), MEMB
on the other
ns. max. after the
MEMB
from the start of.
is high
within
MACRd rises within
the inputs to both L60-A and
falls
the scan.
all
signals falls.
43SEL rises
within 40 ns.
high and
within 25
of the next rise
140 ns. of the rise of MACR and falls
L50-B to rise and
184 ns. max. after MACR rises
MACR falls.
follow L50-6 and
first of these 3
110 ns. of the fall of MACR.
three inputs to
hand, is
L50-6 goes low 20 ns. max. after
ns. of the rise of MACR and falls
of MACR.
L28, L30,
into which it feeds, GGA
(L20-9), and MACRd (L24-15) are
goes high 20
max. after
(L26,
L60-C, two two-input AND gates, A43/ (L60-3) will
43SEL
is
With MEMB high, GGB (L34-8) goes low setting B43/ and B21/
low from 64
A21/
signal that
Thus MACRd is the last of the
the first to fall.
Thus A43/
and rises 154 ns. max.
after
PAGE 93
A21/
21SEL
(L60-8) follows L71-12, which goes low 20 ns. max. after
(L70-5), MEMB (L20-9), and MACRd
21SEL were high at
the rise
MACR.
this time, A21/
of MACR and
At
would fall
would rise 154 ns.
this point,
Thus the A4 and
however, 21SEL
240 ns. max.
fall of
so A21/
are
is high.
enabled and the A2
after the
L50-6 rises,
L58-2
L58-2.
Thus OD43A falls 470 ns.
rises after MACR
these two
after MACR rises, and falls 60
which is
falls.
first of
L58-2 rises 60 ns. max. after
L50-6 falls, which is 220 ns. max.
max. after
ns. max. after
max, after MACR and L58-2 are
inputs to to NAND gate L22-A falls.
ns.
is low,
If
disabled.
OD43A (L22-3) goes low 250 ns.
and rises
184
max. after the
A3 memories (L25 and L27)
and Al memories (L29 and L31)
both high
(L24-15) are all high.
190 ns.
max. after
rises, whereas MACR
MACR
falls before
max. after MACR rises and rises
250 ns. max. after MACR falls.
OD21A (L22-11)
both high.
goes
L58-6 can
low 250 ns. max. after L58-6 and MACR are
go high only when 21SEL and
MEMB are high,
in which case OD21A would fall 470 ns. max. after the rise of MACR
and would
rise 250 ns.
this point, 21SEL
max. after the
is
L58-4
of
its inputs,
remain
MEMA (L50-9),
low forcing OD43B (L22-4)
one of its
Since, at
is low, OD21A remains high.
OD43B (L22-4) and OD21B (L22-10)
because one
fall of MACR.
inputs, MEMA, (L71-3),
high.
is
low.
high.
is low.
L71-6
is
L50-8
As
is high
a result,
high because
Consequently, L58-8 is
low forcing OD21B (L22-10) high.
At any
L50-B,
L50-C,
one time
of the
L71-A, and L71-B -
the Output Disables that
only one
is low.
Therefore only
OD43A, OD21A, OD43B, and OD21B - is
is the one generated by the
gates -
three-input NAND
one of
low, and
one low NAND gate among the four
just listed.
MEMB
(L43-1)
is high, so
2-line-to-l-line data selector
the B
(L43-3, 6, 10,
through to the outputs (L43-4, 7, 9,
(L43-15) is
tied low
inputs of the
enabling the
and 12).
outputs at
and
74LS257 quad
13)
are passed
The G enable input
all times.
Thus
PAGE 94
43SEL
through to COUNT A (L43-4),
is passed
memory address counter, L65, at pin
signal
sent out
counters (L49,
scan.
43SEL
The
by
first MACR
(L20-5), which
outputs to
set
all
four memory
a low-to-high
in turn causes the lower
be stable.
1.
It
Once the
(L49 and L65) are involved,
in
the PROC.COMP.
address
to 0 before the beginning of the
pulse causes
counter, L65, to count up to
clocks the "A"
5. Recall that
the computer
L65, L64, and L66)
which
transition in
"A" memory address
takes 38 ns. max. for the L65
count is above 15
both counters
which case the longest
the outputs are settled is 73 ns.
delay until
Thus, for the worst case, the Q
outputs of the "A" memory address counters (pins 3, 2, 6, and 7 of
L49 and
L65) are stable, and
1822 "A" memories (pins
L29, and L31),
116
likewise the address
7, 6, 5, 21,
inputs
1, 2, 3, and
ns. max. after MACR rises and
4 of
to the
L25, L27,
remain so until
43SEL rises again.
Again, since MEMB (L43-1)
is high
R/W (L43-7)
input and thus remains high (read mode).
after MACR rises
and rises
falls 470 ns. max.
MACR falls.
elapse before
From the
From the
A43/ to
valid is 450 ns.
i.e.,
670
ns. after
the A4
max. or 634 ns.
max.
and A3
after
the A4 and
A3 memory
14, and 16 of L25 and L27) are valid, at the
12,
The outputs remain valid until
after OD43A rises, which
falls, until 20 ns.
may
the A4 and
or 566
the time
outputs are valid,
670 ns. after MACR rises.
20 ns. min.
200 ns.
three of these conditions for valid outputs
Since all
10,
maximum of
450 ns.,
OD43A
ns. max. after
The access time from when
is
max.
MACR falls.
memory outputs are valid,
fall of
met before the
outputs (pins
latest,
rises.
OD43A a
lines are stable
memory outputs are
must be
154 ns. max. after
fall of
the A4 and A3
A3 memory address
MACR rises.
falls 184 ns.
after MACR rises and rises 250
ns. max. after MACR
MACR rises.
A43/
follows the 2B
min. after A43/
is 270 ns. max.
rises, which is
after MACR
174 ns. max.
after MACR falls, or until the memory address changes, which isn't
until after 43SEL
rises again.
max. after MACR falls.
The earliest of these
So the outputs of the A4
is
174 ns.
and A3 memories
PAGE 95
are valid from 670
ns. max. after MACR rises until
about
max. after MACR falls, or, to be -sure, until MACR falls.
discussion of MACR generation (the next section),
174 ns.
From the
one can see that
the multibus timing requirements are satisfied.
One read being
the computer.
21SEL high.
The "A" memory address
This time the
are on
the "A"
put out on
their outputs
A43/ and OD43A will remain high and A21/
and OD21A will
A43/ and
OD43A, respectively, did with
Meanwhile,
B21/, which feed
L28,
be
before.
six memories having
same timing with
L26,
lines as
Al memories will
have the
pulse.
low and
counters don't change, so the
memory address
data in the A2 and
bus lines, the other
disabled.
sent out by
Within 40 ns. of the rise of MACR, 43SEL is
same addresses
the data
finished, the next MACR pulse is
respect to
as long as
the CS1/
respect to the
or
inputs of
L30, and L32), will
enabled, while OD43B
GATE1
the present MACR
remain low keeping
L28,
843/ and
(pin
19 of
those memories
and OD21B, the Output Disable
"B" memories (pin 18 of L26,
last MACR
GATE2 is high,
the "B" memories
pulse as
inputs to the
L30, and L32), will
remain high
disabling the outputs of these memories.
When the "A"
sent to
memories have been read, a READ
reset 43SEL
circuitry
and 21SEL
has. finished
low.
writing
Then, as
into the
"B"
COMP/ pulse is
soon as
the scan
memories and
the
computer has finished processing data
from the "A" memories (data
from the previous scan), a PROC.COMP.
pulse is sent to switch the
memories in preparation for a new
memories will
Thus A43/,
OD43B,
be written
OD43A, A21/,
During this scan the "A"
scan.
into and
and OD21A
the "B"
will
821/, and OD21B, respectively.
memories read
trade
roles with
from.
B43/,
These alternating roles can
be seen on the Read timing diagram.
VI-lO.
MACR
MACR
(L54-8)
(SH.'S
is
11,
7, 9, 10)
generated when
the
computer
executes
a
PAGE 96
command to
read port
binary form
is HLLLLHHL.
multibus address
(P1-52,
86H.
51,
lines
54,
hexadecimal number,
However, addresses
56,
respectively, which are
55,
true form.
58,
and
-11,
13,
15,
17,
57)
on the
Thus ADR7/-ADRO/
receive
LHHHHLLH,
a 74LS241 octal
8, 6, 4, and
is tied low and the OEb
all eight outputs (L40-9,
whose
are put out
sent on to the inputs of
input to the buffer (L40-1)
high so that
is a
in negative
53,
3-state buffer (L40
86H
2).
The OEa/
input (L40-19)
7, 5, 3, 12,
14,
16,
and
18) are always enabled.
Once the negative true binary
86
is on the
decoded by
(L38-6),
address lines, the 8, which is
a 4-input
goes low
86
when the
valid address
is
it sets the GI and G2
low enabling the chip.
decoded by
within 71 ns. after
L41
causing
the address, 86,
The digit 6 of the
PMACR/ (L41-7)
is stable on
other L41
outputs remain high.)
PMACR/
ns. after
the address is stable
on the bus,
may take that
BASE ADR/
74154 4-line-to-16-line decoder/demultiplexer
19 of L41)
is
ns. of
the base address, is
whose output,
When BASE ADR/ goes low,
chip enables of the
(pins 18 and
NAND gate (L38-A)
within 58
stable on the bus.
number
form of the hexadecimal number
to go
the bus.
may not go low
however,
low
(All
until 85
because
it
long for the output to be enabled via the strobes GI
and G2 (L41-18 and 19).
PMACR/ stays
low until 71
ns.
max. after
the address (86H) on the bus goes away.
The multibus manual points out that
minimum of 50 ns.
after IORC/
into which it feeds
inputs of this shift
goes low,
the output of the
NAND gate
(L33A-C) goes high removing the Clear from the
register, L57.
Both Data
register, Dsa and Dsb (L57-1 and 2), are tied
that when the
transiton of
the bus and goes
the address on the bus goes away.
74LS164 8-bit parallel-out serial shift
high so
(P1-21) goes low a
after the address is valid on
high a minimum of 50 ns. before
Within 20 ns.
IORC/
Clear input
the Clock input, which
(L57-9)
is high
is the 9.216iMHZ
the positive
clock, will
cause a high to be shifted into QA (L57-3) and all
other Q outputs
to
QA
shift
one
position
in the
direction
from
toward
QH.
PAGE 97
Following this procedure, QH will go
ns.
to 895
follows QH
ns. after
Clear
(L57-13) by
(L57-9) goes
feeds the
inverter (L59-1),
is low.
enable
input
low a
maximum of 58
ns.
after the
(L59-5)
to
high
address
low
796
within the
IORC/ (P1-21)
23 ns.
According
goes away.
ns. after
multibus' 0
63 ns. after
ns. -
100 ns.
multibus
50 ns. min.
Thus XACK/ goes
IORC/
IORC/
goes
later XACK/
to
goes low
ns. - 10 ms. acknowledge delay
and rises
the multibus.
remains valid on the bus
and 931
ns. after
BASE ADR/ goes
is on
goes high, and
in this case IORC/,
the multibus)
low 40
(L38-6) or
after the command,
adhering to the 0
74LS368 3-state
and 915 ns. after IORC/ goes
impedance.
specifications, the address
from between
BOARD ENABLE/
16 ns. of when QH goes high.
either BASE ADR/
ENABLE/ (L33A-11)
goes
of the
(L59-5)
is low long before QH (L57-13)
XACK/ (L59-5) goes low within
high BOARD
long as
is on the multibus, whereas
goes high, which happens between 780
40 ns. after
XACK/
IORC/ goes low a minimum of 50
Either way, BOARD ENABLE/ (L33A-11)
low.
high.
BOARD ENABLE/ goes
BASE ADR/ and IORC/ are both low.
address
, as
16 ns. max.
(L33A-11), which
ns. after the
high anywhere from about 760
(thus
time allowed by
rises
(thus staying
allowed acknowledge
hold
time).
READ (L37-12) goes
high 20 ns. max. after
BASE ADR/ (L37-2 and 13) are both
IORC/ (L37-1)
and
low and falls 20 ns. max. after
either one of these signals rises.
READ/ (L39-10)
form of READ (L37-12), delayed by 20 ns. max.
is the inverted
Thus READ/ goes low
40 ns. max. after IORC/ (P1-21) and BASE ADR/ (L38-6) are both low
and high 40 ns. max. after one of these signals goes high.
MACR (L54-8)
READ/ are low.
goes high
20 ns.
PMACR/ goes low as
max. after
long as 85 ns.
address lines are stable and READ/ within 40 ns.
BASE ADR/ are both low.
58 ns.
IORC/ goes
both PMACR/
and
after the bus
of when IORC/ and
low 50 ns. min.
and BASE ADR/
max. after the bus address lines are stable, so the rise of
MACR will
be, perhaps, around
are stable, unless
IORC/
118
ns. after the bus address lines
goes low later than BASE
ADR/, in which
PAGE 98
case MACR will rise 60 ns. max. after IORC/ falls.
within 60
ns. after
the rise of
IORC/, the
MACR will
first
of
fall
the three
signals to go away.
43SEL (L20-5)
max. after
routine
rises 25 ns. after
the next
for the
MACR rises
duration of
MACR rises and falls 40 ns.
and repeats
the reading
this rise
cycle.
and fall
21SEL
(L70-5)
follows the same timing as 43SEL, but one MACR pulse later.
and 21SEL are always
43SEL
in opposite states while reading is going on.
Between reading cycles 43SEL and 21SEL are both low.
When MEMB (L20-9) and 43SEL are
fall
154 ns.
after MACR rises and
both high, A43/
(L60-3) will
rise 184 ns. after MACR falls.
When MEMB and 21SEL are both
high, A21/
(L60-8) will
of A43/,
timing as
just mentioned
but with
Otherwise
the same
A43/ and
(L60-6) and
B21/
A21/
remain high.
(L60-11)
(If
follow the
MEMB
fall
instead
for A43/.
is low,
timing just
B43/
mentioned for
A43/ AND A21/.)
Shortly
L50-6, goes
after L50-6
high gating
causing OD43A (L22-3)
MACR rises and
the read
the
timing
Disable,
to go low.
which L50-6
descri bed
ODxxx, will
go
either 0 D43A
alternate going
low as
memories
OD43A falls 670
x4 and
x3 and
for 0D43A.
Thus
a
MACR
and OD21A or
the computer
memories
ns. max. after
only in
Similarly, when
(L22-11) will
fall and
only
read.
one
Output
During
0D43B and
xl
it's
rise with
one
OD21B will
alternates between
x2 and
of
pulse (L22-1)
after MACR falls, but
low during
reading period,
inverted form
the MACR
goes low.
to go low, OD21A
just
L22-2, the
through part of
rises 250 ns. max.
cycle in
L71-12's turn
goes low
(x being
reading
A or
B,
whichever memory bank is being read.)
The outputs of A4 an d A3 (pins 10,
12,
14, and 16 of
L27) are valid within 450 ns. max. of the fall of A43/,
after MACR rises; within
max. after the rise
address
lines are
200 ns.
address lines are stable.
or 604 ns.
the fall of OD43A, or 870 ns.
of MACR; an d 450 ns. max.
stable, or
L25 and
541
ns. max.
from when the 1822
after the
multibus
Thus the A4 and A3 outputs are valid by
PAGE 99
870 ns. after MACR rises, or about
930 ns. after IORC/ falls.
takes a maximum of
195 ns. for the
data to get
memory outputs to
the multibus data lines, which
data (in
(L62 and
negative true form, due
L63), quad
It
from the A4 and A3
thus have valid
to passage through the 74LS242's
inverting bus
transceivers) on them
by 1125
ns. max. after IORC/ falls.
Valid data remains
at the outputs of the A4
until 20 ns. min. after OD43A rises,
or until
falls.
20 ns.
min. after
However, data
transceivers (L62 and L63)
13 of L62 and
READ falls.
from 1125
ns.
which is shortly
the computer.
after IORC/
or 204
through the
ns. after
74LS242 quad
to the bus only when READ
L63) is high and is
Thus the valid
or 270 ns. after MACR falls;
A43/ rises,
is allowed
and A3 memories
invalid from
data is
MACR
bus
(pins 1 and
25 ns. max. after
on the multibus
falls, essentially until
after IORC/ rises, so correct data
data lines
READ falls,
is
read into
PAGE
100
9.216 MHZ
CLOCK,
ij.......
I..........
QAA,
QBB,
QCCI
QDDI
QEEI
QFFI
QGG,
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1
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Fig. VI-O
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RESET
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Fig. VI-I
CLOCK, START, CONTROL
I_
PAGE 102
BUS ADDRESS
BUS DATA
,J
I
IOWC/
BASE ADR
I
I
READ
BOARD ENABLE
I
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U37 DATA IN
1
.
STROBEO
1
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M DATA VALI
Fig. VI-2
STROBEO
BLANK
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ss
PREGATE
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GATE3
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DATA VALID
I
Fig. VI- 3
B
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........
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195 CLEAR
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4076-B OUT
4076-C OUT
40760 OUT
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L52 LOAD
L52 G
L52 CLOCK
..
.
....
PIXAD
1802 ADDRESS
R/W
DATA VALID
---
SIGNA,-
DISABLED
Fig. VI-4
A/D MODE
i
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4 •
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QCC
I
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PREGATE
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LASTIN GATE
AREA
AREA
FIRST
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Fig. VI-5
PIXEL MODE
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Fig. VI-6
STR. L
MODE
4
L
PAGE 107
CLOCK
I
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1822 ADDREI
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PROC.CO9P
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"A" MEMORY ADDRESS CIRCUITRY
RESET
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PAGE
110
BUS ADDRESS
BASE ADR
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q
|
r
it,
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-- I
-
1822 OUTPUTS VALID FROM GIVEN SIGNAL
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Fig. V I 10
MA CR and READ
-
PAGE 111
CONCLUSIONS
VII.
very well and does,
The Camera-Microcomputer Interface works
as has
been pointed out
deal
great
as
flexibility,
of
shortcoming of the interface, at
concerned, is
estate --
appear, since
boards, partly
there
This
already in
Register 5 on board, whon its
two
unused positions
feature will be
new
version -
(Direct Memory
in
ones
use on
is being
were needed), and
a corresponding
example, Status
Register
Status Control
board of
Access) capability
designed, work
of applications programs.
with a
Control
functions could be taken over by the
done by hardware on the present
version
for
a
0).
One
microprocessor with
to do
interface.
new
greatly enhance the
provided, however, that will
the
the
for example, having to use
when only two-input
used (leaving,
real
elements on
partly due to simplification of the design without
in chips
of
progress to
of having to design
limited variety of chips available (as,
reduction
major
is not as difficult as it
superfluous
are many
due to the constraint
three-input NOR gotes
amount
rather large
Thus designs are
two boards.
The
control.
as far as future users are
least
reduce it to a one-board version.
may
as
well
of a
its occupation
with a
provide the user
in this paper,
some of
DMA
the processing
Meanwhile, as the new
is being done
on the development
PAGE
VIII.
112
REFERENCES
Peatman, John B.
New York,
Microcomnurtr-Basrd
D-sign.
McGraw-Hill,
Inc.,
1977
Wickes, William E.
logic Dosiqcn with Integratod
Circuits.
John
Wiley and Sons, New York, 1968
Manuals published by Intel
Corporation, Santa Clara California:
MCS-80 Usnr's Mrnual
8080/80F5 Ass•,rblv Lanquage Program'nin q
Manual
System 80/20-4 Microcorinuter Hardware Reference Manual
8080 Microcornouter Sy__tepm IJser's Manual
Intel Multibus
Int.rf•acing
by Thomas Rolander
a-]1
(0 -+IV)
220
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CABLE CONNECTIONS
J1
(BD.2 - EXT.*)
PIN
SIGNAL NAME
1 -+15 V
2 -- -15 V
3 -- GND
4 -RCLOCK3
5 -RCLOCK1
6 -RCLOCI:2
7 -60 HZ
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
--
RSTART1
--
RSTART2
--
RSTART3
--
BLANKI1
J2
(BD.2 -
--
BLANK3
BLANK2
--
VID1
--
VID3
10 --
VID2
39
41
42
43
44
45
46
47
48 -49
50 --
START
CLOCK
BD.1)
PIN
SIGNAL NAME
1 -RESET
2 -576 KHZ
3 -GATEI/
4 -GATE2/
5 -MEMA
6 -- CPSTART
7
8 -- 2HH
9 -- TRANSAD
10 -- STROBE1
11 -GATE2
12 -PIXEL
13 -START
14 -60 HZ
15 -113
16 -CLOCK
17 -r11
18 -M2
19 -MO
20 -SS
21 -M7
22 -- M6
23 --
--
38
PAGE
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
--------------------
M4
M5
M11
M10
J3 (BD.2 - BD.1)
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
SIGNAL NAME
--
QBB
--------
2CC
MEMB
QEE
STROBEO
STROBE2
STROBE3
2FF/
-- STROBE8
-- STROBE9
-- START/
--
2FF
-----
EOS/
PRESTART
GATE4/
SSt/
------
PROC.COMP./
RESET/
A/Dt
STROBE5
GATEI
r8
--47 -48 -49 --
M9
M15
ANALOG VID
M14
M13
M12
DOUT2
DOUT3
DOUT4
DOUT5
DOUT6
DOUT7
DOUTO
RSTART
DOUT1
BLANK:
RCLOCK
CAM3
CAM2
GND
CAMl
+15 V
50 --
-15
---
126
V
*RETICON UNIT,
POWER SUPPLIES,
and 60 HZ LINE
BOARD - CABLE - RETICON
SIGNAL NAME
BLANK
START
CLOCK
VIDEO
GND
from
from
from
from
PAGE 127
CONNECTIONS
CABLE
RETICON
RETICON
RETICON
RETICON
START to RETICON
CLOCK to RETICON
60 HZ
*RC-100A EDGE CONNECTOR PINS
**LINE VOLTAGE DOESN'T GO TO RETICON
RETICON'
P2-D
P2-B
P2-C
P2-N
P2 1-22
P2-E
P2-A
P2-Z
mx
Multibus Connections
PAGE
(COMPONENT SIDE)
PIN
POWER
SUPPLIES
BUS
CONTROLS
INTERRUPTS
ADDRESS
DATA
POWER
SUPPLIES
MNEMONIC
(CIRCUIT SIDE)
DESCRIPTION
PIN
MNEMONIC
1
3
5
7
9
11
GND
+5V
+5V
+12V
-5V
GND
Signal GND
+5VDC
+5VDC
+12VDC
-5VDC
Signal GND
2
4
6
8
10
12
GND
13
15
17
19
21
23
BCLK/
BPRN
BUSY/
MRDC/
IORC/
XACK/
Bus Clock
Bus Pri. In
Bus Busy
Mem Read Cmd
1/O Read Cmd
XFER Acknow
14
16
18
20
22
24
INIT /
BPROI
BREQI
MWTC/
IOWCI
INH1/
25
AACKI
Advance Acknow
26
INH2/
28
30
32
34
27
29
31
33
CCLK!
INTAI
Constant Clk
Intr Acknow
35
37
39
41
INT61
INT4/
INT2/
INTO/
Parallel
Interrupt
Requests
43
45
47
49
51
53
55
57
ADRE/
ADRC/
ADRA/
ADR8I
ADR6/
ADR41
ADR2/
ADR01
59
61
63
65
67
69
71
73
DATE/
DATCI
DATA/
DAT81
DAT6/
DAT4/
DAT21
DATO1
128
Address
Bus
Data
Bus
+5V
+5V
+12V
-SV
GND
36
38
40
42
INT71
INT5!
INT31
44
46
48
50
52
54
56
58
ADRF/
ADRD/
ADRBI
ADR9/
ADR7/
ADR5/
ADR3/
ADRIl
60
62
64
66
68
70
72
74
DATFI
DATDI
DATBI
DATS/
DAT7/
DATS/
DAT31
DAT1 /
DESCRIPTION
Sig GND
+5VDC
+5VDC
+12VDC
-5VDC
Signal GND
Initialize
Bus Pri. Out
Bus Request
Mem Write Cmd
II/O Write Cmd
Inhibit 1 disable
RAM
Inhibit 2 disable
PROM or ROM
Parallel
Interrupt
Requests
INT1 I
Address
Bus
Data
Bus
GND
Signal GND
GND
Signal GND
-12V
+5V
+5V
GND
-12VDC
+5VDC
+5VDC
Signal GND
-12V
+5V
45V
GND
-12VDC
+5VDC
+5VDC
Signal GND
--
Copied from the SBS 80/20-4 Hardware Manual
PAGE 129
GLOSSARY
In the following definitions, a "/"
is used in
place of the
overbar that appears
in the schematics.
In cases
where a signal
is used
in both negative true and positive true forms,
only one
form, usually the positive true form, is defined.
Imbedded blanks
in signal names are not significant - CAMI and CAM I refer to the
same signal.
Finally, the
information appearing
in parentheses
immediately following
the signal name
indicates, in
most cases,
the point of origin of that signal.
AACK/ (L59-3) - Advanced acknowledge signal, sent on bus to CPU in
response to memory read or memory write command.
AA7-AAO (pins 7,6,2,3 of L49 and L65) - "A" memory address
AB7-ABO (pins 7,6,2,3 of L64 and L66) - "B" memory address
ADR7/-ADRO/ (P1-52,51,54,53,56,55,58,57) - 8
bus address
with ADR7/ being the most significant bit (MSB)
ANALOG VID (L10-15) - 0-+1
volt boxcar video signal
A/D (U9-19) - Selector bit for A/D (or 4-bit
A/Dt/
(U35-4) -
lines,
data) mode
TTL version of A/D/
A21/
(L60-8) -
Chip Enable for memories A2 and Al
A43/
(L60-3) -
Chip Enable for memories A4 and A3 (L25 and L27)
BASE ADR/
BCLK/
(L38-6) - Low when
address) is 8
(P1-13) -
upper digit
(L29 and L31)
on address
bus (base
Bus clock, asynchronous to CPU clock
BLANK (J2-43) - Reticon signal that
is low from just
before the
1st piece of VIDEO data is sent out until just after the
last is sent out and is high during the blanking period
BLANK GATE (L34-3) - high when all
be generated
is ready for
a START pulse to
BLANKSET/ (L36-6) - set low by PREBLANK to assure that BLANK GATE
is high when needed to generate a START pulse
BLANKx (J1-26,22,20) - BLANK signal
coming from camera x
BLANK2X (U50-13) - Follows BLANK, 2 CLOCK periods later
PAGE 130
BOARD ENABLE/ (L33A-11)
B21/
(L60-11)
B43/ (L60-6) -
-
- Allows AACK/ or XACK/ onto the multibus
Chip Enable for memories B2 and B1
(L30 and L32)
Chip Enable for memories B4 and B3 (L26 and L28)
CAMX (U13-5,7,9) - Selector bit for camera x
(P1-31) Constant Clock,
9.216
multibus by SBC 80/20 board
CCLK/
MHZ signal
sent out
on
Clock - Any clock input or clock generated
CLOCK
(U18-2,5) - Basic clock for the photodiode array and for the
interface
CO7MP.START (U31-13) - Computer-generated Start
signal
COUNT A (L43-4) - Clock for the "A" memory address counters
COUNT B (L43-9) - Clock for the "B" memory address counters
CPSTART
(L37-8) - Computer signal used to generate COMP.START
CPU - Central processor unit
DATA READY/ (L21-6) - Enables INT4/ to
be sent as soon as data in
the GATE area has been stored in interface memory
DIG VID (U20-9) - 1-bit digital video data signal
DIN7-DINO (L42-3,5,7,9,11,14 and L24-3,5) - Data being sent to the
data bus (and thus to the CPU) from the interface
DI4-DI1
(U3-2,10,11,1) - 4-bit,
or A/D, data
DOUT7-DOUTO (J2-39,38,37,36,35,34,42,40) - Data being sent to the
interface from the CPU via the data bus
END GATE
- L7-LO
- Upper
eight bits
of the
marking the end of the GATE area
photodiode address
EOS (U16-3) - Positive pulse generated when the GATE area has been
passed, should really be EOG (for End of Gate)
ES (U51-6) - End-of-Scan - Positive pulse generated just after the
end of the scan
PAGE
GATEx (U43-2,7,10,15) - Follows PREGATE, on
thereafter
131
the xth rise of CLOCK
area That portion of the photodiode array whose output is
to be
processed by the interface;
START GATE and END
GATE delimit the GATE area
GATE
GG (L33A-6) - High as long as either GATEI
GGA (L34-8) GGB (L34-11)
or GATE2 is high
Low when "A" memories being written into
-
Low when "B" memories being written into
H7-HO (U38-5,7,9,11,17,19,21,23) - END GATE
INT4/
(L35A-13)
- Set
low when data
in
stored in interface memory and
SBC 80/20 memory
IORC/
(P1-21)
- I/O Read Command - Bus signal that is low when the
address of an input port is on the address bus
ICO!C/
(P1-22) I/O Write Command Bus signal that is
low when
the address of an output port
is on the address bus and
corresponding data is on the data bus
the GATE area has been
is ready for transfer to
L7-LO (U39-5,7,9,11,17,19,21,23) - START GATE
MACR (L54-8) Signal sent out by
the computer when it wants to
read
interface memory
- serves
as the Clock for the
Memory Address Counters during the Read cycle
MACRd (L24-15) - Delayed version of MACR
MADCLKW/ (L71-8) - Memory Address Counter Clock for the Write cyle
MEMA
(L20-8) -
High when "A" memories being written into
MEMB (L20-9) -
High when "B" memories being written into
MUX (L43) - Quad 2-line-to-1-line multiplexer
M15-MO
(J2-29,31,32,33,25,26,28,27,21,22,24,23,15,18,17,19) data inputs to the interface memories
16
OD (U68-2) - Output Disable input for U40 and U41 latches
OUTRAN (L54-12)
- Signal
sent out
by the computer to
read the
number of
interface memory addresses filled during the
PAGE 132
last scan
OD21A (L22-11) - Output Disable input
and L31)
for memories A2 and Al
(L29
OD21B
(L22-10) - Output Disable input
and L32)
for memories B2 and B1
(L30
OD43A
(L22-3) - Output Disable
and L27)
input for memories A4
and A3 (L25
OD43B
(L22-4) - Output Disable
and L28)
input for memories B4
and B3 (L26
PA1I-PAO
(pins
7,6,2,3 of
U62, U61,
used to generate PREGATE
U58) -
PC (L35-5) - Process Complete flip-flop
is sent out by the computer
- Set
Photodiode Address,
high when PROC.COMP
PCSYNC (L21-9) - PC synchronized to CLOCK
PIXAD (L51-3)
- High when PIXEL or A/D data ready to be,
process of being, written into interface memory
PIXEL (U9-17)
- Selector
mode
bit
for PIXEL
(or 1-bit
or in
digital data)
PIXELt (L24-6) - TTL level version of PIXEL
PMACR/ (L41-7)
- "PREMACR" - goes low to generate MACR
PREBLANK (L72-6)
- Signal sent out
by the computer to
set BLANK
GATE high to assure, in turn, that a START signal can be
generated
PREGATE (U47-8) - Signal
that is high as long as the upper eight
bits of the photodiode address are larger than the START
GATE and smaller than the END GATE
Start
PRESTART
(U18-4) - Signal
selected by user from
the 3
signals to become START farther down the line
PROC.COMP
signal
sent out by
the
(L54-6)
- Process
Complete
have been
both processing and scanning
computer, when
completed, to prepare the interface for a new scan
that follow the CLOCK
QAA-QHH (U15-3,4,5,6,10,11,12,13) - Signals
signal 1 to 8 9.216 MHZ Clocks later, respectively
03-QO (U9-5,7,9,11) -
4-bit quantizing level, chosen
by the user
PAGE 133
and used to convert A/D data to 1-bit PIXEL data
READ (L37-12) - Signal that is high when the
(receiving data) from the interface
RESET (L37-6) - Signal sent out
interface boards
computer
by the computer to
is reading
initialize the
RCLOCKx (J1-4,6,8) - Internal Clock signal coming from camera x
RSTARTx (J1-16,12,10) - Internal Start signal coming from camera x
R/IJA (L43-7) - Read/Write signal that
are being written into
R/WB
(L43-12)
- Read/Write signal
memories are being written
SCAN/ (U50-1)
SCANt/
is low when the "A" memories
that
into
is
low when
the
"B"
- Follbws BLANK on next CLOCK
(U68-10) - TTL version of SCAN/
SCR - Status Control Register
SLOADI and SLOAD2 (U71-6,8) - Signals
that control the loading of
the string
length counters (U46,
U69, U57)
with zeros
between scans and at the end of each string
SS (U51-9)
SSt/
- Positive pulse generated
scan
just after the start
of a
(U54-2) - TTL version of SS/
Start - Any
start signal other than
(START)
START (L69-10)
-
the one sent to
Positive Start signal
the cameras
sent out to the cameras
START CONVERT
(U20-5) Narrow positive pulse sent
to the A/D
converter to
start the conversion
of the video coming
from the Reticon camera (in the form of ANALOG VID) from
a boxcar signal to 4-bit, or A/D, data
START GATE
- H7-HO - upper eight
address in the GATE area
bits of the
first
photodiode
STCMOS (U1S-5) - CMOS version of PRESTART
STORE VID (U34-6) - holds the state of the data of the string at
the time
that STR.L or TRAN mode data is written into
PAGE 134
interface memory
STR.L (U9-23) -
Selector bit for STR.L (string length data) mode
STROBE (U68-4) - Signal to strobe
U40 and U41
STROBEx
TRAN
TRAN or STR.L data into latches
(L56-8,6,12; L55-8,12;)
Computer-generated signal
to
load data into
SCRx, where x is
0, 1, 2, 3, or 5; and
(U16-6,8) interface-generated signal
last
to
load
memory address written
into, into
latch L47 or
L48,
where x is 8 or 9, respectively
(U9-21) - Selector bit for TRAN (transition data) mode
TRANSAD (U72-6)
- Signal
that goes high to generate
store STR.L or TRAN data in interface memory
signals to
TRANSITION
transition
(U34-9) -
Signal
that goes
high
when a
occurs
TRCLEAR (U34-13) - Signal that
TRCLK (U56-3) - Signal that
occurs
resets TRANSITION to zero
sets TRANSITION high when a transition
uF - Microfarad
um - Micron
us - Microsecond
VIDEO
(L4-2,3,9)
- Boxcar video
signal
(from
the
camera) to be processed by the interface
VIDEO-CP (page 7) - Charge-pulse
array
video output of
designated
the photodiode
VIDx (J1-38,40,32) - Boxcar video signal coming from camera x
W4ITE/ (L50-12)
- Signal used to
generate R/WA or R/WB
to allow
data
to
be written
into
interface memory
"A"
or
interface memory "B," respectively
XACK/
/A
(L59-5) - Transfer acknowledge signal sent to the CPU on the
multibus to
indicate the completion
of an I/O
Read or
Write operation
(U36-4) - Delayed, inverted version of XB
PAGE 135
&B
(U48-3) - Selected CMOS Clock, used to generate the TTL CLOCK
191 LOAD (U72-8)
- Signal that controls the loading
or TRAN counters (U46, U69, and U57)
of the STR.L
195 CLEAR (U16-11) - Signal used to clear U6, thus disabling data
from being loaded into latches U30, U25, U12, and U26
195 CLOCK (U7-6) - Clock for U6
21SEL
(L70-5) - Signal that goes
high when either memories A2 and
Al or memories B2 and B1 are being read from
43SEL
(L20-5) - Signal that goes
high when either memories A4 and
A3 or memories B4 and B3 are being read from
60 HZ START (U27-4) - Start signal
9.216
MHZ (P1-31)
CLock sent
multibus as CCLK/
generated from the line voltage
out
by the
SBC
80/20 on
the