A Continuous-Time Multi-Stage Noise-Shaping
Delta-Sigma Modulator for Next Generation AROHIVE
MA SSACHUSETTS NSTI~ TTE
Wireless Applications
OF fECHNOLOLGY
by
JUL 0 7 2015
Do Yeon Yoon
LIBRARIES
B.S., Electrical Engineering
Korea Advanced Institute of Science and Technology (2010)
S.M., Electrical Engineering and Computer Science
Massachusetts Institute of Technology (2012)
Submitted to the Department of Electrical Engineering and Computer
Science
in partial fulfillment of the requirements for the degree of
Doctor of Philosophy in Electrical Engineering and Computer Science
at the
MASSACHUSETTS INSTITUTE OF TECHNOLOGY
June 2015
Massachusetts Institute of Technology 2015. All rights reserved.
Author .....
redacted
Signature
Engneerin
of Electrial-
.....................
Department of Electrical Engineering and Computer Science
May 14, 2015
Certified by......
Signature redacted
Hae-Seung Lee
ATSP Professor of Electrical Engineering
Thesis Supervisor
Accepted by .....
,
.
.
*
Signature redacted ............
(f( Leslie A. Kolodziejski
Professor
Chair, Department Committee on Graduate Students
/
2
A Continuous-Time Multi-Stage Noise-Shaping Delta-Sigma
Modulator for Next Generation Wireless Applications
by
Do Yeon Yoon
Submitted to the Department of Electrical Engineering and Computer Science
on May 14, 2015, in partial fulfillment of the
requirements for the degree of
Doctor of Philosophy in Electrical Engineering and Computer Science
Abstract
A continuous-time (CT) delta-sigma (AE) modulator for modern wireless communication applications is investigated in this thesis. Quantization noise is suppressed
aggressively by increasing the effective order of the noise transfer function (NTF). In
order to increase the effective order of the NTF, a 2-loop sturdy multi-stage noiseshaping (SMASH) architecture is utilized. The proposed CT SMASH architecture
has a much wider signal bandwidth which was limited in the discrete-time (DT)
SMASH architecture due to the inherent sampling frequency limitation of the DT
implementation. Furthermore, the proposed CT SMASH architecture provides a better quantization noise suppression capability than the DT SMASH architecture by
more completely canceling the quantization noise from the first loop. The CT SMASH
architecture is implemented with several circuit techniques suitable for high operation
speed. These circuit techniques allow the proposed CT AE modulator to achieve wide
bandwidth, high resolution, and low power consumption for modern wireless communication applications. As a result, the prototype fabricated in 28nm CMOS achieves
DR of 85dB, peak SNDR of 74.9dB, SFDR of 89.3dBc and Schreier FOM of 172.9dB
over a 50MHz bandwidth at a 1.8GHz sampling frequency.
Thesis Supervisor: Hae-Seung Lee
Title: ATSP Professor of Electrical Engineering
3
4
Acknowledgments
During my Ph.D. journey at MIT, I have met many people who have helped and
supported me.
First and foremost, I would like to express my sincere gratitude to my advisor,
Professor Hae-Seung Lee.
I have always been inspired by his extensive knowledge
and creative intuition in analog circuit design. His technical guidance and constant
encouragement have allowed me to complete my research successfully.
Moreover, I
have been able to learn his teaching, writing, and presentation skills. It has been an
enormous privilege to work with him.
I would like to thank Stacy Ho at MediaTek for his unwavering support and caring
guidance. He has been always willing to discuss all my complicated technical issues.
His great insight from his profound experience in delta-sigma converters showed me
the right directions, whenever I faced difficult technical problems. He also provided me
the fantastic working environment, resources, and many opportunities at MediaTek.
I would also like to thank Professor Ruonan Han for being on my thesis committee.
He has given me many priceless suggestions to improve my thesis.
I would like to thank Michael Ashburn, Chi-Lun Lo, Steven Chiu, Yun-Shiang Shu,
CC Hsiao, Joshua Bamford, Vinh Thai, Pier Bove and Zchicheng Wei at MediaTek
for their technical support. Since they are the real experts in circuit design, layout,
and measurement, I have been able to learn invaluable skills from them.
I would like to thank Jeffrey Gealow and Paul Ferguson at ADI, who initially
suggested the interesting research topic I have worked on. They helped me to understand delta-sigma converters. I am thankful to Jialin Zhao and Jose Silva at ADI for
valuable discussions.
I would like to thank Sabino Pietrangelo for his tremendous support. I have relied
on his support and encouragement during my entire Ph.D. life. He has been not only
a great colleague but also a fantastic teacher who has taught me writing, presentation
and even exercise skills.
SungWon Chung, Sunghyuk Lee, and Philip Godoy were senior members of my
5
research group. Every time I had problems in any topics, they patiently answered my
questions with their deep knowledge and experience.
I would also like to thank all the other members of the Lee and Sodini research
groups for the best office environment ever and the many memorable social events. I
will not forget the enjoyable memories with senior members (Kailiang Chen, David
He, Jack Chu, Mariana Markova, Albert Chang, Khoa Nguyen, and Daniel Kumar)
and junior members (Xi Yang, Joohyun Seo, Grant Anderson, and Meggie Delano).
Frank He was a great colleague at MediaTek. Technical discussion with him was
truly helpful. Also, we had lots of fun together at MediaTek.
Last but not least, I would like to thank my family. My father and mother have
always given me unconditional love, which I have completely depended on during my
entire time at MIT. I would also like to thank my sister for her full support. I could
never have completed my journey this far without them.
6
Contents
15
1.1
M otivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
1.2
Thesis Organization. . . . . . . . . . . . . . . . . . . . . . . . . . .
20
.
Introduction
.
1
2 AE Modulator Overview
21
2.1.1
Quantization Noise . . . . . . . . . . . . . . . . .
22
2.1.2
Oversam pling . . . . . . . . . . . . . . . . . . . .
23
2.1.3
Noise Shaping . . . . . . . . . . . . . . . . . . . .
25
.
.
.
Quantization Noise Suppression . . . . . . . . . . . . . .
.
2.1
21
DT A E ADC . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . .
27
2.3
CT A E ADC
. . . . . . . . . . . . . . . . . . . . . . . .
. . . . . .
28
2.3.1
Comparison between DT and CT AE Modulators
. . . . . .
29
2.3.2
CT AE Modulator Issues
. . . . . .
30
2.3.3
Practical Synthesis of a CT AE Modulator with High Sampling
.
.
Frequency . . . . . . . . . . . . . . . . . . . . . .
. . . . . .
34
Overall Design Process
.
2.4
. . . . . . . . . . . . .
. . . . . .
38
. . . . . .
41
. . . . . . . . . . . . . .
Strategies for Quantization Noise Suppression
. . . . . .
.
2.3.4
.
.
2.2
3 Multi-Stage Noise-Shaping AE Modulator
45
Original MASH Architecture . . . . . . . . . . . . . . . . . . . . . .
45
3.2
DT Sturdy-MASH (SMASH) Architecture
51
.
3.1
4 CT 3-1 SMASH AE Modulator
.
. . . . . . . . . . . . . .
53
7
4.1
Advantages of a CT 3-1 SMASH AE Modulator . . . . . . . . . . . .
4.2
Two Main Challenges of CT 3-1 SMASH AE Modulator Implementation 61
4.2.1
Analog Delay . . . . . . . . . . . . . . . . . . . . . . . . . . .
61
4.2.2
Feedforward Path in the
65
2 nd-loop
. . . . . . . . . . . . . . . .
5 Prototype Implementation
5.1
5.2
69
Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . . . .
69
5.1.1
CT 3-1 SMASH AE Modulator
. . . . . . . . . . . . . . . . .
69
5.1.2
A m plifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
5.1.3
Quantizer to DAC Path
. . . . . . . . . . . . . . . . . . . . .
85
5.1.4
DACs and Their Calibration . . . . . . . . . . . . . . . . . . .
87
L ayout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
91
6 Prototype Characterization
7
54
99
6.1
Test Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100
6.2
SNR, SNDR, and SFDR . . . . . . . . . . . . . . . . . . . . . . . . .
103
6.3
Intermodulation Distortion . . . . . . . . . . . . . . . . . . . . . . . .
106
6.4
Signal Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . .
106
6.5
Power Consumption
. . . . . . . . . . . . . . . . . . . . . . . . . . .
107
6.6
Com parison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
108
Conclusions
111
7.1
Thesis Contribution. . . . . . . . . . . . . . . . . . . . . . . . . . . .
111
7.2
Future Work . . . . . . . ..
113
. . . . . . . . . . . . . . . . . . . . . . .
8
List of Figures
1-1
Signal bandwidth and DR requirements for ADCs in wireless applications 16
1-2
LTE-A cellular base-station receiver block diagram
1-3
Signal bandwidths and DRs of recent ADCs
1-4
Signal bandwidths and FOMs of recent ADCs
2-1
Analog-to-digital conversion
2-2
2-bit quantizer characteristics: (a) transfer curve, (b) quantizer error,
. . . . . . . . . .
17
. . . . . . . . . . . . . .
18
. . . . . . . . . . . . .
18
. . . . . . . . . . . . . . . . . . . . . . .
21
(c) probability density function
. . . . . . . . . . . . . . . . . . . . .
22
2-3
Power spectral density
. . . . . . . . . . . . . . . . . . . . . . . . . .
23
2-4
Attenuated in-band noise . . . . . . . . . . . . . . . . . . . . . . . . .
24
2-5
Linear model of a DT AE modulator . . . . . . . . . . . . . . . . . .
25
2-6
Shaped in-band quantization noise
. . . . . . . . . . . . . . . . . . .
27
2-7
Block diagram of a DT AE ADC
. . . . . . . . . . . . . . . . . . . .
28
2-8
Block diagram of a CT AE ADC
. . . . . . . . . . . . . . . . . . . .
28
2-9
CT AE modulator with a DAC error . . . . . . . . . . . . . . . . . .
30
2-10 Quantizer to DAC path . . . . . . . . . . . . . . . . . . . . . . . . . .
31
2-11 DAC output with jitter . . . . . . . . . . . . . . . . . . . . . . . . . .
33
2-12 Open-loop block diagrams: (a) DT AE modulator, (b) CT AE modulator 34
2-13 Common DAC waveforms and their Laplace transforms: (a) NRZ, (b)
return-to-zero (RZ), (c) Exponential
2-14 Impulse response comparison:
matched impulse response
. . . . . . . . . . . . . . . . . .
36
(a) DT loop filter and CT path, (b)
. . . . . . . . . . . . . . . . . . . . . . . .
37
2-15 Enhanced impulse response matching method for the 3rd-order modulator 37
9
2-16 Outputs in Figure 2-15: (a) y[n] and [ho hi h 2 h3] C, (b) outputs from
all paths
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-17 Overall design process
. . . . . . . . . . . . . . . . . . . . . . . . . .
2-18 Feedback structure with an opamp and impedance components:
38
39
(a)
schematic, (b) block diagram . . . . . . . . . . . . . . . . . . . . . . .
40
3-1
A general MASH architecture
. . . . . . . . . . . . . . . . . . . . . .
45
3-2
A 2-loop MASH architecture . . . . . . . . . . . . . . . . . . . . . . .
47
3-3
1'-loop of a CT 3-1 MASH AE modulator . . . . . . . . . . . . . . .
48
3-4
SQNR results based on different DC gain values . . . . . . . . . . . .
49
3-5
Three feedforward coefficient variation effects with a -2dBFS input . .
50
3-6
A DT SMASH architecture . . . . . . . . . . . . . . . . . . . . . . . .
51
4-1
A CT SMASH architecture . . . . . . . . . . . . . . . . . . . . . . . .
53
4-2
E1 path
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
54
4-3
Further reduction of E 2 by gain and attenuation blocks . . . . . . . .
56
4-4
Block diagrams: (a) CT 4th-order single-loop AE modulator, (b) CT
3-1 SMASH AE modulator . . . . . . . . . . . . . . . . . . . . . . . .
57
4-5
STFs from the behavioral simulation
. . . . . . . . . . . . . . . . . .
59
4-6
Quantizer input spectra from the behavioral simulation . . . . . . . .
60
4-7
Quantizer input transient wave forms from the behavioral simulation
60
4-8
Block diagram of the CT 3-1 SMASH AE modulator
. . . . . . . . .
62
4-9
Analog delay implementation
. . . . . . . . . . . . . . . . . . . . . .
63
4-10 SQNR results based on different LPF time constants with different
input frequencies
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
64
4-11 STF variation based on different LPF time constant values . . . . . .
65
4-12
65
2
"d-loop implementation
. . . . . . . . . . . . . . . . . . . . . . . . .
4-13 2ndloop implementation: (a) with a feedforward path, (b) without a
feedforward path
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
66
4-14 SQNR results with and without a feedforward path at different input
frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
67
Overall schem atic . . . . . . . . . . . . . . . . . . . .
69
5-2
Overall timing diagram . . . . . . . . . . . . . . . . .
71
5-3
Additional DACs for the zero-order path
72
5-4
All feedforward paths using outer-feedback DACs
5-5
1s-loop NTF change due to
5-6
Two-stage opamp without compensation:
.
.
5-1
response ......
.
. . . . . . .
72
30% Rzi variation . . .
74
.
.
. .
(a) topology,
(b) frequency
..........................
76
5-7
M C topology
5-8
Two cases of the FFC topology
5-9
FFC topologies: (a) option 1, (b) option 2
.
. . . . . . . . . . . . . . . . . . . . . .
.
. . . . . .
.
80
5-10 FFMC-PZ: (a) topology, (b) frequency response . . .
81
5-11 Two-stage amplifier in the lIt-loop . . . . . . . . . . .
84
5-12 OTA in the 2 nd-loop
. . . . . . . . . . . . . . . . . .
85
5-13 Quantizer 1 to DAC 2 path . . . . . . . . . . . . . . .
.
85
5-14 Comparator schematic
86
.
.
.
79
.
. . . . . . . . . . . .
77
. . . . . . . . . . . . . . . . .
5-15 DAC unit-cell schematics: (a) DAC, and DAC1 ', (b) D AC 2 and DAC 3
88
5-16 DAC 1 NMOS element connecting to a current copier refe rence cell and
DAC1 driver for an NMOS element. . . . . . . . . . . . . . . . . . . .
89
...................
92
5-18 Die photograph of the analog core
...................
92
5-19 Overall floor plan . . . . . . . . .
...................
93
5-20 Layout of the modulator......
...................
93
5-21 Layout of two loop filters . . . . .
...................
94
5-22 Layout of Quantizer 1
. . . . . .
...................
95
. . . . . . . . . .
.. . . . . . . . . . . . . . . . . .
95
5-24 Layout of DAC, NMOS element .
...................
96
5-25 Layout of DAC 1 drivers and DAC1
.. . . . . . . . . .. . . . . . . .
97
5-26 Layout of NMOS mirrors in the curr ent copier circuit . . . . . . . . .
97
6-1
99
.
.
5-23 Layout of DAC
.
.
.
5-17 Die photograph of the entire chip
.
Measurement setup . . . . . . . . . . . . . . . . . .
11
6-2
PCB for the measurement
. . . . . . . . . . . . . . . . . . . . . . . .
102
6-3
Test environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
102
6-4
Measured 16384-point FFT spectrum with a -3.1dBFS input signal at
5.93M H z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
103
6-5
Measured SNR/SNDR based on different input amplitudes . . . . . .
104
6-6
Measured SNDR results at 30, 40 and 50MHz
104
6-7
Measured two tone test results with -8.4dBFS inputs: (a) at 21 and
25MHz, (b) at 13.5 and 15.5MHz
. . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . .
105
6-8
M easured STF
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
106
6-9
Power breakdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
107
12
List of Tables
Component parameters
. . . . . . . . . . . . . . . . . . . . . . . .
6.1
Package information
6.2
Comparison with sate-of-the-art>50MHz CT AE modulators
.
5.1
74
. . . . . . . . . . . . . . . . . . . . . . . . . . .
100
13
. . . .
108
14
Chapter 1
Introduction
The majority of electronic systems interface with the physical world in the analog
domain.
Since many systems process signals in the digital domain, it is necessary
to convert from the analog to the digital domain.
Therefore, an analog-to-digital
converter (ADC) is one of the most vital parts in most electronic systems. Wireless
communication applications, in particular, need fast and accurate ADCs, because the
data frequencies keep increasing with the progress in communication technology.
Among many types of ADCs, the popularity of continuous-time (CT) delta-sigma
(AE) modulators for wireless communication applications has increased in recent
years [1-12]. Since the first idea of AE operation was presented [13] and adapted to
an actual ADC
[14], many architectures and techniques for CT AE modulators have
been investigated in order to improve the signal bandwidth with high resolution and
low power consumption. However, they have not been able to achieve performance
metrics for next generation wireless applications. Therefore, this thesis presents an
architecture and several techniques for CT AE modulator design which help to achieve
high resolution and signal bandwidth for modern wireless applications.
1.1
Motivation
Wireless communication is a rapidly advancing field and new wireless applications
are continuously being developed.
15
DR(bit)
14
GSM
12
CDMA 2000 1x
10
TD-SCDMA
Bluetooth
4G LTE
CDMA 2000 3x
New
Wireless
Application
HSDPA
WCDMA
8
WLAN
6
0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9
11
50
BW(MHz)
Figure 1-1: Signal bandwidth and DR requirements for ADCs in wireless applications
Figure 1-1 shows the signal bandwidth (BW) and dynamic range (DR) requirements of ADCs for wireless applications [15]. As wireless applications have progressed,
the required specifications of ADCs have also become more demanding. New applications, such as the Long Term Evolution Advanced (LTE-A) communication standard,
demand signal bandwidth and resolution over 50MHz and 14-bit, respectively.
Figure 1-2 shows a cellular base-station receiver block diagram for the LTE-A
standard at a radio-frequency (RF) bandwidth of 100MHz. At the front of the re-
ceiver, the low noise amplifier (LNA) amplifies the RF signal. This amplified signal
is down-converted by mixers. The base-band signals are further amplified by variable
gain amplifiers (VGAs), and then filtered by low-pass filters (LPFs). Finally, signals
are sampled by ADCs.
For a higher system-level integration, the power consump-
tion of ADCs must be limited. The requirement of power consumption is important
for longer battery lifetimes in cellular mobile receivers as well.
In order to meet
these speed, resolution, and power requirements for modern wireless communication
applications, an ADC architecture selection is critically important.
Figure 1-3 shows the reported DRs and signal bandwidths of ADCs at the International Solid-State Circuits Conference and Symposium on VLSI circuits from 1997
16
VGA
BW:
ADC1
50MHz
D11
RF BW:
10MHz
PLL1
PLL2
LNA
900
90*
X,..gDQ
ADCQ
,.
Figure 1-2: LTE-A cellular base-station receiver block diagram
to 2014 [16]. Figure 1-3 shows that AE modulators or pipeline ADCs achieve high
DRs over 70dB. For DRs over 80dB, AE modulator based designs are dominant. CT
architectures are typically used for signal bandwidths over 10MHz.
In terms of power consumption, CT AE modulators are advantageous in wide
signal bandwidth applications. When comparing designs, a Figure-of-Merit (FOM)
is a good criterion, since it can account for speed, resolution, and power. A common
FOM used in ADC design is calculated as shown in Equation 1.1, where P is power
and BW is signal bandwidth.
FOM = DR+
10 10g(
BW)
P
(1.1)
ADCs with higher FOMs are more power-efficient. Figure 1-4 shows the reported
FOMs of ADCs.
With signal bandwidths over 10MHz, CT AE modulators have
relatively high FOMs. Moreover, a CT AE modulator has a simple resistive input,
unlike SAR or pipeline ADCs that require power-hungry input buffers to drive their
large switched input capacitors.
Also, the anti-aliasing function inherent in a CT
AE modulator reduces the anti-alias filter (AAF) requirements. Therefore, a CT AE
modulator is a suitable architecture for use in modern wireless applications requiring
17
120
*
110
U
U*
90 0
C
i
aV
C
a
C
Pipeline
m
13 a'
A
*
60
:A
50
*Ax
A*
0
0,>
40
SAR
51E+06
A
0
A
+ Flash
A
A&
A A&0oh
0
* Folding
o Two-step
A*
A
EA
o Others
1E+A
1E+0
M E0 'E1A
A+
30
++ t
#+
+~ +
+0
+
*
+
S
S
70
E
E This Work
* CT Delta-Sigma
* DT Delta-Sigma
.U
*
C
S
U
80
V
*
100
x1+
+
20
IE+03
IE+04
1E+C 5
IE406
IE.07
IE.08
1E+09
IE+10
IE+11
Signal Bandwidth (Hz)
Figure 1-3: Signal bandwidths and DRs of recent ADCs
190
180
S
160
S
0
0
AAL
A
xA
S
C
EThis Work
* CT Delta-Sigma
* DT Delta-Sigma
A
-
E
gO
*
e~~~
0
0140
0
A
A
a
.. A P 4'"
EA
q
A:
S
a
a
*P
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A
4
130
A
x
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U.
~
A
I
A
U
0
+0A
A
Ai
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A
A *t- . A4-o
%U
A
0
0
a
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++
A
A
+
+
* Folding
120
0
110
IE+04
IE+05
IE+06
IE+07
IE+0B
1E+09
IE+10
IE+11
Signal Bandwidth (Hz)
Figure 1-4: Signal bandwidths and FOMs of recent ADCs
18
Two-step
* Others
+
i
100
IE+03
SAR
Flash
+
0
+
170
0150
a
0
~0
S
wide signal bandwidth, high resolution and low power consumption.
Unfortunately, the design of CT AE modulators is significantly more complex
than discrete-time (DT) AE modulators. Since the implementation methodologies
of AE modulators began with DT, many DT implementation schemes have been
thoroughly examined. On the other hand, the implementation of CT AE modulators
is not straightforward, since it is based on the conversion from DT AE modulators.
Also, all distortion sources of CT AE modulators are different from those of DT
AE modulators. Thus, new approaches to implement CT AE modulators for high
resolution and wide bandwidth are an active area of research.
Several state-of-the-art CT AE modulators reported recently achieved signal bandwidths 50MHz or higher, which are required in next generation wireless communication standards [3,6,7,11,17]. However, the resolution and power consumption of these
designs can be improved.
For these reasons, this thesis presents a new CT AE modulator architecture to
achieve high resolution and wide bandwidth, while consuming low power [12]. This
work seeks to achieve 50MHz signal bandwidth, DR greater than 84dB, and power
consumption below 100mW. Along with this architecture, several practical techniques
are proposed to achieve these target performance metrics. The fundamental idea is to
implement a CT multi-stage noise-shaping (MASH) AE modulator consisting of
3 rd
and 1st-order loop filters based on a Sturdy-MASH (SMASH) architecture previously
reported in a DT AE modulator [181. This architecture achieves the similar noise
suppression to the ideal MASH architecture without requiring digital filters for quantization noise cancellation. Moreover, several circuit techniques in this thesis mitigate
speed constraints and help to achieve wide signal bandwidth and high resolution while
maintaining low power consumption.
There are three distinct objectives for this thesis. First, this thesis introduces
the advantages of the proposed CT 3-1 SMASH AE modulator. In the proposed CT
3-1 SMASH AE modulator, benefits from the previous DT SMASH AE modulator
are enhanced. Furthermore, the proposed AE modulator has improved performance
compared to a CT single-loop AE modulator with the same noise-shaping capability.
19
Second, this work presents the main challenges and their solutions of the proposed
CT 3-1 SMASH AE modulator in the architecture-level. Compared to the previous
DT SMASH AE modulator, there are several differences in the CT SMASH implementation. These differences bring about new unique design challenges. To overcome
these issues, proper architecture-level solutions are proposed. Third, this thesis shows
several circuit-level techniques, which mitigate design complexity and improve performance. After solving key challenges in the architecture-level, there are still several
practical issues in the circuit-level implementation. This thesis will show the circuitlevel techniques employed to relax the requirements and improve the performance of
each essential block in the modulator.
1.2
Thesis Organization
A CT AE modulator with a SMASH architecture for next generation wireless applications is proposed in this thesis. The thesis is organized as follows:
Chapter 2 describes the fundamentals of AE modulators. CT AE modulators are
studied primarily to help motivate the remainder of the thesis. Several issues arise
when a DT AE modulator is converted to a CT AE modulator, which are described
in detail.
Chapter 3 provides an explanation of MASH architectures. The original MASH
and SMASH architectures are investigated.
Chapter 4 proposes a CT AE modulator based on the SMASH architecture. In this
chapter, advantages and challenges of a CT 3-1 SMASH AE modulator are presented.
Chapter 5 describes the actual implementation of the proposed CT 3-1 SMASH
AE modulator. Details from the circuit-level design are presented.
Layouts of the
core blocks are shown as well.
Chapter 6 shows the measurement results from the prototype integrated circuit
of the CT 3-1 SMASH AE modulator.
Chapter 7 concludes the thesis and discusses future work.
20
Chapter 2
AE Modulator Overview
This chapter provides fundamental information about AE modulators.
First, the
main characteristics of AE modulators, which is to suppress quantization noise, are
described. Based on these characteristics, the overall structure of a AE modulator is
illustrated with operational descriptions. In addition, differences between DT and CT
AE modulators are discussed. The main advantages and issues of CT AE modulators
are presented to aid in understanding the rest of the thesis.
2.1
Quantization Noise Suppression
This section shows the quantization noise suppression characteristic of a AE mod-
ulator. First, general quantization noise in an ADC is described. The quantization
noise is suppressed by the oversampling and noise shaping characteristics of a AE
modulator. These two characteristics are explained in this section.
S/H
X(t)
f
--
+
_
f-fN-bit
fs
AAF
Quantizer
Figure 2-1: Analog-to-digital conversion
21
yd
2.1.1
Quantization Noise
Quantization noise is the difference between the analog input value and quantized
digital ADC output. Figure 2-1 shows the general conversion process from an analog
signal to a digital signal. The process of this conversion is to sample a CT signal
using a sample-and-hold (S/H) circuit and then to assign this sampled value to one
of the discrete values. This process is commonly referred to as quantization. Before
the CT signal is sampled, an AAF is required to prevent high frequency components
from folding into the signal bandwidth. This conversion is further explained with a
2-bit quantizer.
Y.O
e=y-xA
...........
....
1...........
A
A
LSB
A
e
2
Non-overload
Input range
(a)
(b)
(c)
Figure 2-2: 2-bit quantizer characteristics: (a) transfer curve, (b) quantizer error, (c)
probability density function
The characteristics of a 2-bit quantizer are shown in Figure 2-2. Figure 2-2(a)
shows the transfer curve of this quantizer from input to output. The quantizer step
size is shown as A.
The least significant bit (LSB) is the difference between the
two adjacent quantizer levels. These two values are equivalent, and are given by A
= LSB = FS/4, where full-scale (FS) is the maximum input range. With an n-bit
quantizer, in general, the quantizer step size and the LSB are given by A = LSB =
FS/2'. Figure 2-2(b) shows the quantizer error e, which is the difference between the
input and the output of the quantizer. Within the non-overload input range, given
by [-FS/2, FS/2j, e is distributed within the range -A/2, A/2]. In this example, e is
correlated with the input, but under certain circumstances [19-22}, it can be modeled
as white noise that is uniformly distributed in the range I-A/2, A/2}, as shown in
Figure 2-2(c).
Based on this probability density function, the total quantization
22
SE ()2
12fs,
A2
12fs 2
fs2
fS
2
-fB
fB
fS I
S2
2
2
2
Figure 2-3: Power spectral density
noise power a2 can be calculated. Since quantization noise power is also uniformly
distributed in the range [-fs/ 2 , fs/ 2 ] where fs is the sampling frequency, the power
spectral density of the quantization noise is given by:
2
SE
1
1
e
A2
A/2
2
--
e d
fs fs[A
-A/2
__
=12fs
(2.1)
Figure 2-3 shows the power spectral density of the quantization noise, which is
constant in the range [-fs/2, fs/2. Total integrated noise power is always A 2 /12,
regardless of a sampling frequency. However, within the signal bandwidth, the integrated quantization noise power is given by:
PE
fB
SE(f)df
-
2fBA 2
12fs
_fB
(2.2)
where fB represents the signal bandwidth.
2.1.2
Oversampling
According to the Nyquist Theorem, the sampling frequency fs must be greater than
twice the signal bandwidth
2
fB, generally referred to as the Nyquist rate.
Unlike
Nyquist ADCs, which use the Nyquist rate as their sampling frequencies, oversampling
23
SE
IM)
Attenuated in-band
quantization noise (PE)
fsi/2
fB
fs 2 /2
f
Figure 2-4: Attenuated in-band noise
ADCs use the sampling frequencies much higher than the Nyquist rate 2fB. The
oversampling ratio (OSR) is defined as fs/2fB. Figure 2-3 and Equation 2.2 show that
the quantization noise power within the signal bandwidth decreases as the sampling
frequency increases for given signal bandwidth. This effect is shown more clearly in
Figure 2-4. Equation 2.2 is rewritten using OSR.
SE(f)df
PE =
2
2fBA
2
fs
12fs
_ B
__2_
12OSR
120SR
(2.3)
Equation 2.3 shows that the in-band quantization noise power is inversely proportional
to the OSR. Since the fixed quantization noise power o is uniformly distributed in
the range [-fs/2, fs/2, the in-band quantization noise is reduced with increasing
sampling frequency. Another advantage of oversampling ADCs is that a high sampling
frequency relaxes the requirements of the AAF in Figure 2-1, since the sharp AAF
at the input of the S/H circuit is not required. These advantages of oversampling
ADCs are obtained by increasing the sampling speed, potentially at the cost of higher
overall power consumption of the ADCs.
24
Loop Filter
++
H(z)
Loop Filter
V
U
++
H(z)
+
V
+
U
Quantizer
E
E
Figure 2-5: Linear model of a DT AE modulator
2.1.3
Noise Shaping
With a sampling frequency higher than the Nyquist rate, the oversampling characteristic of a AE modulator reduces the in-band quantization noise power.
A AE
modulator has another characteristic, known as noise shaping, that suppresses the
in-band quantization noise power further.
This noise shaping characteristic comes
from the feedback architecture of a AE modulator and proper loop filter design. The
main idea of noise shaping is that the loop filter in a AE modulator pushes in-band
noise to out-of-band frequencies.
Figure 2-5 shows a general block diagram of the DT AE modulator. It consists
of a feedback system with a loop filter H(z) and a quantizer.
the input and output of the AE modulator, respectively.
U and V represent
The quantizer block can
be modeled as an addition of quantization noise, E, in a linear system model. The
output of this linear feedback model in Figure 2-5 is given by:
~ H(z) + E11(2.4)
V =U-Hz
1+H(z)
1+H(z)
From Equation 2.4, the signal transfer function (STF) and the noise transfer function
(NTF) are defined:
STF =
H(z)
NTF =
1+ H(z)
1
1(2.5)
I1+ H(z)
Within the signal bandwidth, if the loop filter H(z) has large gain, then STF and
NTF become nearly 1 and 0, respectively, based on Equation 2.5. This means that a
AE modulator passes its input signal and blocks the quantization noise at its output.
For low-pass AE modulators, integrators are used in the loop filter to implement large
25
gain near DC. For band-pass AE modulators, resonators, which have large gain at
their given center frequency, are used in general.
To explore the noise suppression effect from the NTF further, the general Lth-order
NTF is given by:
NTF = (1 - z-1)L
(2.6)
To calculate the in-band quantization noise power suppressed by this NTF, the magnitude of the NTF is calculated.
INTF(ej")
=
=
1-
-,
1- cos(Q) + j sin()
=
[2-2cos()]L
2
L
2sin( Q)]
(2.7)
where normalized Q is defined as 0=27rf/fs. In a AE modulator, the quantization
noise is reduced by a high sampling frequency, and then suppressed further by the
NTF. The final in-band quantization noise power at the output of a AE modulator
is the integration of the shaped quantization noise power spectral density.
PQ
1
JO
|
,2NTF(e") 2 df
=
2
J2
sin( )] df
(2.8)
where normalized QB is defined as QB=r/OSR. Due to the oversampling characteristic, generally, ir/OSR is very small. Then, within the range [0, ir/OSR], the sine
term is simplified as:
2 - sin
2
2
2
=
Q
(2.9)
The final in-band noise power shaped by the given NTF is represented as:
p
A2
2
fr/OSR AA
12
127r Jo
12L
(2L + 1)OSR2L+1
Compared to using the oversampling characteristic alone, as shown in Equation 2.2,
26
the noise shaping characteristic further suppresses quantization noise. As shown in
Equation 2.10, the quantization noise power is reduced by the OSR at a rate of 6 L-3
dB/octave.
In summary, the in-band quantization noise is suppressed with a high sampling
frequency, because the fixed quantization noise is distributed uniformly over the range
[-fs/2, fs/ 2 ]. This in-band quantization noise is reduced further by the feedback
system with the NTF. This final shaped quantization noise is illustrated in Figure 26.
SE M
(Te 2
NTF12
s
B
Shaped in-band
quantization noise (PQ)
Figure 2-6: Shaped in-band quantization noise
2.2
DT AE ADC
Figure 2-7 shows the overall block diagram of a DT AE ADC. There are an AAF,
a DT AE modulator, and a decimation filter. Unlike a CT AE modulator, the
CT input signal x(t) is sampled at the front of the AE modulator to process the
received signal in the discrete-time domain. Therefore, in order to avoid aliasing
when the signal is sampled, an AAF is required before the DT AE modulator. The
27
+
x(t)
S/H
Loop Filter
+
Quantizer
H(z)
t:
E
fst
AAF
DT AX Modulator
Yd(n)
+
N-bit
Decimation
Filter
E
Figure 2-7: Block diagram of a DT AE ADC
quantization noise E is suppressed by the NTF from the DT loop filter H(z) and
the feedback loop. The feedback path typically consists of switched-capacitor (SC)
digital-to-analog converters (DACs). The DT loop filter is also a SC type. Since the
output of the AE modulator is generated at a high sampling frequency, the output
data frequency of the AE modulator must be reduced to the Nyquist rate for use in
subsequent signal processing blocks. Therefore, a decimation filter is required at the
output of the DT AE modulator, in order to realize an overall DT AE ADC.
2.3
CT AE ADC
Loop Filter
x(t)
+
S/Hit
H(s)
:
Quantizer
*
+ OSR J-
:t
CT Al Modulator
:
yd(n)
t
E
fs
Decimation
Filter
Figure 2-8: Block diagram of a CT AE ADC
The overall block diagram of a CT AE ADC is shown in Figure 2-8. One of main
characteristics of a CT AE ADC is that the CT input signal x(t) is directly applied
to the input of the CT AE modulator. Thus, the loop filter in a CT AE modulator
employs CT components such as RC and Gm-C integrators.
RC integrators are
employed for larger signal swing and better linearity, whereas Gm-C integrators are
28
employed for higher operation speed [23, 24J.
For the feedback implementation, in
general, either SC DACs [25-28] or current-steering DACs [1,3,6-8,11,12,29-35] are
employed. Unlike the DT AE ADC, the CT signal is sampled at the quantizer. The
CT loop filter provides an inherent AAF [36]. Therefore, the AAF requirements can
be relaxed in a CT AE ADC. However, following the CT AE modulator, a decimation
filter is still required.
2.3.1
Comparison between DT and CT AE Modulators
The modulators in AE ADCs can be implemented in either DT or CT. In general, DT
AE modulators consisting of SC circuits more readily achieve higher accuracy than
CT AE modulators. This is because the accuracy of the DT AE modulator relies on
precise capacitor matching. Also, DT AE modulators are robust to process variation
for the same reason.
However, SC circuits limit the operation speed of DT AE
modulators, because operational amplifiers (opamps) for SCs circuits need to settle
within each half-clock cycle. Another significant drawback of DT AE modulators is
the more stringent AAF requirement at the input.
The loop filters of the CT AE modulators, however, do not use SC circuits.
Thus, the opamps require much lower gain-bandwidth, therefore easing the design
requirements of the opamp. Since there is no sampling process within the filters, the
constraint of maximum sampling frequency depends mainly on the regeneration time
of the quantizer and the update rate of the DAC [37]. Thus, it is possible for CT AE
modulators to operate at higher sampling frequencies and achieve wider bandwidths
compared to DT AE modulators.
Modern wireless applications demand wide bandwidths 50MHz or higher. Without increasing a sampling frequency, it is difficult to simultaneously achieve high
resolution and wide bandwidth, due to a lower OSR. Therefore, in order to achieve
both wide bandwidth and high resolution, it is necessary for the AE modulator to
operate at high sampling frequencies over 1GHz. In order for opamps to fully settle
with SC circuits, the unity gain-bandwidth (UGBW) of the opamp in a DT AE modulator must be greater than about five times the sampling frequency [38]. Therefore,
29
it is not power-efficient for DT AE modulators to function at sampling frequencies
over 1GHz. On the contrary, the UGBW of opamps in active RC integrators that
CT AE modulators use can be lower than about four times the sampling frequencies, depending on the chosen scaling coefficient [39]. Moreover, due to their inherent
AAFs, CT AE modulators can save additional power and circuit complexity.
For
these reasons, CT AE modulators are appropriate to meet the demands of modern
wireless applications.
2.3.2
CT AE Modulator Issues
Quantizer
U
-dl
HLF(S)
CLK
+DAC(s)
Z d
DAC Driver
EDAC
Figure 2-9: CT AE modulator with a DAC error
Despite the several advantages of CT AE modulators, such as low power consumption and high speed operation, there are three main issues, especially when high
sampling frequencies are exploited for wide bandwidths: (1) excess loop delay (ELD),
(2) non-linearity of multi-bit DACs, and (3) DAC clock jitter. Figure 2-9 shows a CT
AE modulator with a DAC error. The error EDAC added at the output of the DAC
is the most important error because it is not shaped by the loop filter. On the other
hand, the error occurring between the loop filter and the quantizer is suppressed by
30
the loop filter similarly to quantization noise.
The ELD is due to the finite response times of the quantizer and the DAC circuits
in the modulator
[40]. In a CT implementation, since the quantizer cannot generate
its output instantly, the quantizer is given a delay for regeneration. Thus, at least one
latch is located between the quantizer and DAC. In Figure 2-9, two latches with T dl
and
Td2
are for the quantizer and DAC driver, respectively. The quantizer latch is
triggered after the comparators make the decision. The DAC cannot also generate its
output immediately, due to DAC driver propagation delay, DAC switch delays, and
the DAC settling time. Moreover, the delays that occur from all integrators due to the
finite UGBWs add ELDs [41], especially at high sampling frequencies. To compensate
for ELDs, several methods have been proposed [42]. Among these methods, the most
popular technique is to allow a certain delay between the quantizer to the DAC and
add an additional fast feedback path from the output to the input of the quantizer [43]
to compensate the ELDs.
f
-Tdl
-Td2
At2
Output
0
''Time
Td.1
DAC(s)
Ata"
Td2
Comparator
CLK
Quantizer
DAC Driver
EDGE
Latch CLK
Latch CLK
EDGE
EDGE
At1 : Regeneration Time
A2 : Latch Propagation Delay
ta: Latch Propagation Delay + DAC Switch Delay
Figure 2-10:
Quantizer to DAC path
Figure 2-10 shows ELDs from the quantizer to the DAC, when there is no circuitry between these two blocks. After the comparator is triggered, the quantizer
31
latch and the DAC driver are triggered at Td, and Td2, respectively. At,, At 2 , and
At3 are the comparator regeneration time, quantizer latch propagation delay and the
sum of DAC driver latch propagation and DAC switch delays, respectively. A sufficiently large Tdl is necessary in order to allow for the variation in regeneration time
At,, and alleviate quantizer metastability concerns [441. Also, Td2 must occur after
Tdl+At 2 .
At Td2+At3 , the loop filter receives the DAC output. In general, from the
system-level design, the DAC output timing is given and the ELD budget is set based
on this timing. At high sampling frequencies, At1 , At 2 , and At3 are not negligible.
As a result, the sum of At,, At 2 , and At3 may limit the sampling frequency. Moreover, if any additional circuits such as dynamic element matching (DEM) circuits are
added between the quantizer and the DAC, the timing budget becomes even tighter.
Therefore, proper timing allocation is crucial at high sampling frequencies.
In recent state-of-the-art CT AE modulators, multi-bit quantizers have been used
to further reduce quantization noise, to improve the modulator stability, and to reduce
the effect of timing jitter. Along with additional power consumption from more comparators, a multi-bit quantizer requires a multi-bit DAC. A multi-bit DAC consists
of several unit cells, based on the number of bits. Ideally, the current value from each
unit cell should be exactly the same. However, due to mismatches, each unit cell has
a different current value. The output of a multi-bit DAC therefore creates non-linear
errors. This is modeled as EDAC in Figure 2-9. Unlike the quantization and loop filter
errors, EDAC is not shaped by the loop filter, because this error is added to the loop
at the input. As a result, EDAC is seen at the output without suppression by the loop
filter. Therefore, it is often necessary to reduce this error with additional calibration
or mismatch shaping methods.
Many techniques have been proposed to calibrate
the non-linearity from multi-bit DACs such as analog calibration
[45],
digital correc-
tion [4,31,46], and dynamic element matching (DEM) [47] [48]. DAC non-linearity
is a common problem for all AE modulators, but it is much more severe in CT AE
modulators with current-steering DACs, since the matching in current-steering DACs
is worse than in SC DT DACs.
Finally, the DAC clock jitter from uncertainties in the DAC clock edge also de32
Ideal NRZ
DAC Output
:Error
from
SJifter
DAC Output
with Jitter
STime
*
n
(n+1)
S
(n+2)
(n+3)
(n+4) *Ts
OFm
Figure 2-11: DAC output with jitter
grades the resolution [491. This effect is shown in Figure 2-11. The ideal non-returnto-zero (NRZ) DAC output is the step waveform with the identical sampling period
Ts. However, with the DAC clock jitter, each actual sampling period is not identical. Then, the amount of charge transferred to the loop filter becomes inaccurate as
shown in Figure 2-11. Since this is equivalent to a DAC error, it is not suppressed by
the loop filter. The similar clock jitter error occurs at the quantizer as well, but is
reduced by the loop filter because it is considered quantization noise. The clock jitter
error from the DAC can be attenuated by using a multi-bit quantizer and DAC, since
the amount of the error introduced by jitter between each level is reduced.
However,
this solution suffers from the same multi-bit DAC linearity issues. It is possible to use
a SC topology for DACs in CT AE modulators to reduce the jitter error, since these
DACs move stored charge on the capacitors into the loop filter within the sampling
time and this amount of charge is barely affected by the DAC clock
jitter. However,
at high sampling frequencies, a SC DAC topology presents the same disadvantage as
the DT AE modulator due to the opamp settling requirement.
33
2.3.3
Practical Synthesis of a CT AE Modulator with High
Sampling Frequency
The synthesis methodology for DT AE modulators has been well investigated [37,
50, 511.
The main part is the implementation of a loop filter.
It is not different
from designing an active filter by using SC circuits in the z-domain to implement a
target NTF. There are several convenient design tools such as the AE toolbox for
MATLAB [51] in order to obtain coefficients for the target active filter.
On the other hand, the synthesis of a CT AE modulator is more complicated. This
is mainly because the CT loop filter can only handle a CT signal, while the target
NTF is represented by a z-transform in which only a DT signal can be represented.
Therefore, it is important to find the CT loop filter equivalent to the DT loop filter
which can implement the target NTF.
H(z)
y[n]
xDT[n]
YC (t)
y[n] -
H(s)
DAC
XCT
)
(a)
-
W'
xc[n]
(b)
Figure 2-12: Open-loop block diagrams: (a) DT AE modulator, (b) CT AE modulator
Figure 2-12 shows the simplified open-loop block diagrams of DT and CT AE
modulators from the output to the input of the quantizer.
In Figure 2-12(a), the
quantizer output y[n] is applied to the DT loop filter H(z). Then the DT loop filter
produces the quantizer input XDT[n]. In Figure 2-12(b), y[n] is applied to DAC and
DAC produces the CT pulse y, (t) which is injected into the CT loop filter H(s). The
34
CT loop filter output is
X,
xCT
(t) which is sampled to become the DT quantizer input
[n]. The CT AE modulator can act as the DT AE modulator, if both quantizer
inputs in DT and CT AE modulators are equal as follows:
XDT[n]
(2.11)
= X,,(t)It=nTS
If the impulse responses of both open-loop blocks in Figure 2-12 are identical at
sampling times, Equation 2.11 is satisfied [52].
Z- 1 {H(z)} = L-{DAC(s)H(s)} t=nT,
where DAC(s) is the DAC transfer function.
(2.12)
This can be represented in the time
domain [53].
h[n] = [hDAC(t) * h(t)]|t=nTs
j
hDAC(-r)h(t -
T)dIt=nTs
(2.13)
where h[n], hDAC(t), and h(t) are the impulse responses of the DT loop filter, DAC,
and CT loop filter, respectively. This transformation between DT and CT domains
is called the impulse-invariant transformation [54].
Many previous works solved Equation 2.12 or 2.13 to find H(s) [40,47,53]. H(z) is
determined from the target NTF. Once DAC(s) is modeled as shown in Figure 2-13, a
loop filter transfer function H(s) can be found by solving Equation 2.12 or 2.13 [40].
Figure 2-13 shows three common DAC waveforms [47].
Based on the loop filter
topology, coefficients of the loop filter are finally obtained.
This mathematical method to synthesize a CT AE modulator can provide practical loop filter coefficients, if the sampling frequency is low. However, this method does
not provide accurate loop filter coefficients for a target NTF at high sampling frequencies. The first reason is that it is difficult to model a DAC output waveform precisely
at high sampling frequencies. Even with many different waveform models [47], since
Ts becomes smaller, it is difficult to represent the actual DAC waveform with limited
equations. The second reason is that this mathematical method relies on the assump-
35
DACNRZ(t)
DACNRZ
DACNRZ (s)
ot
fi,1
0 z sTT
: t
0, otherwise
- e-'TS
S
Ts
0
(a)
DACRZ(t)
DACR (t)= 12t t t2
0, otherwise
1+
t
DA CR (s)= eS t
es(t21)
S
0 t1
t2
Ts
(b)
0,
0: t:5 ti
DACEXP (t)
-1-e
e~(-t2
t
0 t1
DACExP (s)2 es!1 (1
2
es(2t1))
t)/,
t2
2
i
est1 (r r~eS(t2
s(l+sr1 )(l+sr2 )
t2 Ts
TS
(1+sr,)(1+sr2
)
DACEXP(t)
(c)
Figure 2-13: Common DAC waveforms and their Laplace transforms: (a) NRZ, (b)
return-to-zero (RZ), (c) Exponential
tion that active blocks in the loop filter, such as integrators and resonators, are ideal
to obtain loop filter coefficients. However, this assumption is no longer true at high
sampling frequencies, because any ELDs from active blocks due to finite UGBWs of
opamps are not negligible. These effects change pole and zero locations of the NTF
from their ideal locations and degrade their noise-shaping ability.
Instead of the previous mathematical method, a simulation-based impulse response matching method is more practical, especially at high sampling frequencies.
The basic concept of the simulation-based impulse response matching method is
shown in Figure 2-14(a).
By tuning coefficients in the CT loop filter, for a given
DAC, the actual impulse response from the CT path and the ideal impulse response
from the DT loop filter can be matched through transient simulations. If these im36
Impulse Input
Loop Star pulaalhspulaa reaponses (negaWa)
. . . ...I- - --- .. .. . - - -----.....
.
. . .. . . .. . . .- - - ----
3. 5
10 Hirl
Hkz)
--
-
4 -----
smpulIse response
3 ..
--------..
..-- --------
-
-
of aDT loop filter
2.
~
DA
Impulse response
aCT pats
)of
1.
0.
04
(a)
(-
- -- -
-1
2
3
4
5
6
-
Delay
---....
....
------..
.
......-----.
1
1 4L
7
8
9
i0
(b)
Figure 2-14: Impulse response comparison:
matched impulse response
(a) DT loop filter and CT path,
(b)
pulse responses are well matched at every sampling step, as shown in Figure 2-14(b),
this CT path shapes the quantization noise in the same manner as the DT loop filter.
This method can be used in MATLAB using Simulink or in Cadence using Verilog-A
models, actual transistor-level circuits, or even extracted layout models, which include
additional non-idealities.
LF (s)
6[ny
LdDelay
DAC (s)
fr-oder
hNTF(z)
h3[n]
Path (s)
Path (s)
NTF(z)
h2[n]
6[n]
1
NTF(z)
h[n]
-]
z-rdeT
y[n
Path (s)
6[n]
Zerorder[
1 L-
NTF(z) -hi[n]
-NTF(z) -ho[n]
Figure 2-15: Enhanced impulse response matching method for the 3rd-order modulator
More accurate loop filter coefficients can be obtained through the enhanced impulse response matching method
155].
Figure 2-15 shows the overall flow to use this
37
method for the 3 d-order modulator. Loop filter coefficients for the target NTF are
determined by solving the equation shown below:
h[n] * [ lo[n] 1 1 [n] 12 [n] 13 [n] ] C = 5[n] - h[n] = y[n]
(2.14)
where C is the coefficient matrix [CO C 1 C 2 C3 1T, h[n] is the impulse response of
the target NTF, and li[n] is the sampled pulse response from the input of the DAC
to the output of the ith-order path in the CT loop filter. Equation 2.14 determines
C by minimizing the rms difference between the right and left side of the equation.
As mentioned before, this method can be easily utilized at the circuit-level with all
non-idealities. Since this is a simulation-based method, even with all non-idealities,
loop filter coefficients for the desired NTF are easily obtainable without complicated
DT to CT conversion. Figure 2-16 shows the examples of the outputs in Figure 2-15.
hi[n] is h[n]*l[n].
0.4
C 3 -h3[n
0.3
C 2 h 2[n]
0.2
------- ...-.
-----
-
....
..
-.. ---
C1 -h[n]
0.1
Co -ho[n]
-0.21
0
y[n]
-0.1
-0.4
[ho h1 h2 h 3 ]C
.. - .....
-0.2
.-..-..
.
-0.6 -.
-0.3
-0.4
-A
0
5
10
15
20
n
(a)
30
.0
35
n
-05
5
10
15
20
i5i
30
35
40
n
(b)
Figure 2-16: Outputs in Figure 2-15: (a) y[n] and [ho hi h2 h3] C, (b) outputs from
all paths
2.3.4
Overall Design Process
Figure 2-17 shows the overall design process of the CT AE modulator. After the
specifications and topologies of the AE modulator are decided, the AE modulator
is first implemented in MATLAB using Simulink in order to develop general insight
38
Specification
and Topology
Decisions
Behavioral
Simulations
IVerilog-A Models
Circuit-Level
Simulations
U-
m
U-
m
-
Models
-
SSimulink
4
Debugging
Process
CircuiDt
-esign-
Post-Layout
Simulations
I
Layout
Figure 2-17: Overall design process
39
Z15)
+2+A(s)
into the target AE modulator design. To obtain initial loop filter coefficients, ideal
models for the DAC and the loop filter are initially used. Each block can then be
successively replaced by a more realistic model and its effects on performance are
observed. The impulse response matching method, described in the previous section,
is used to update the loop filter coefficients and restore the target NTF, including all
non-idealities. As examples of realistic models, the active blocks in the loop filter are
modeled.
Zf
Vi n
Z1
-ou
AA(S)
Vout
-
in
Zf/Z2
Zf11Z2
IZ1+
P14't.'
Vout
Z1//Zz
Z2
=fZ+Z1/1 Z2
(a)
(b)
Figure 2-18: Feedback structure with an opamp and impedance components:
schematic, (b) block diagram
(a)
In order to deal with arbitrary opamp models, active blocks are modeled using
opamp open-loop transfer functions, A(s).
Figure 2-18 shows a general feedback
structure with an opamp and arbitrary impedance components connected around it.
These impedance components can be resistors, capacitors, or combinations of both.
Z1 and Z 2 are driven by the input of a modulator or the opamp of the previous stage.
As shown in Figure 2-18(b), the transfer function is expressed as:
Vo
-A(s)
_
n
z1
Zf
(
Z2
Open-loop active blocks using an operational transconductance amplifier (OTA),
such as Gm-C integrators, can also be used in the loop filter. The transfer functions
of these blocks are straightforward to derive by using the transfer functions of OTAs
40
due to the absence of feedback as follows.
=
Gm(s) - ZLoad
(2.16)
where Gm(s) and ZLoad are the transfer function and the load impedance of the OTA,
respectively. Through the impulse response matching method, loop filter coefficients
are obtainable for the updated loop filter with active block models including nonidealities.
More realistic behavioral simulations are performed in Cadence using VerilogA blocks. Each Verilog-A block can be successively replaced by its own circuit-level
block and the performance degradation due to the circuit-level block is verified. Since
the performance difference can be observed by replacing each block, the debugging
process becomes straightforward. Therefore, it is important to build the entire AE
modulator with Verilog-A blocks. Through the impulse response matching method,
loop filter coefficients are continuously updated to restore the NTF with non-idealities
from the circuit-level blocks. If the restored NTF with updated coefficients is not good
enough, redesign of critical circuit-level blocks such as opamps is necessary to improve
their performance.
Similarly, circuit-level blocks are then replaced by the extracted circuit models
from the layout. With extracted circuit models, loop filter coefficients must again be
updated. Because additional non-idealities are added from layout parasitic effects,
critical blocks may need to be redesigned iteratively. Once all blocks are replaced by
their extracted models from the layout and adequate performance is obtained, the
overall design is completed.
2.4
Strategies for Quantization Noise Suppression
To achieve a DR 85dB or higher and to meet block requirements for next generation
wireless standards, quantization noise needs to be suppressed aggressively. The quantization noise in a AE modulator can be reduced by increasing three main factors:
41
the OSR, the number of bits of the quantizer (N), and the order of the loop filter
(L). Each method, however, has its own costs.
First, increasing the OSR brings about speed and power issues. Since the transistor
fT
is limited, simply increasing OSR is not an option in many cases. It also
increases speed requirements and power consumption of every block in a AE modulator, because a higher sampling frequency increases the overall operating speed
of a AE modulator.
Increasing the number of bits of the quantizer increases its
complexity and power consumption. Furthermore, if a multi-bit quantizer is used,
non-linearities from multi-bit DACs degrade the linearity of a AE modulator. Since
DAC non-linearities add directly to the input signal, they are not suppressed by the
NTF. Increasing the order of the loop filter raises stability and complexity issues. A
modulator with a high-order loop filter becomes conditionally stable with a limited
input range [56]. Although less aggressive NTFs provide better stability [57], the inband quantization noise is higher, and implementation of these NTFs increases circuit
complexity because of additional coefficient paths.
Since each method has its own drawbacks, it is important to choose the most
effective combination to reduce quantization noise especially at wide signal bandwidth
and high DR. To investigate the quantization noise suppression effects of these three
methods, the signal-to-quantization-noise ratio (SQNR) is used. When the input of
a AE modulator is a sine wave, the SQNR is calculated by comparing the power of
the non-overloaded input signal and the in-band quantization noise in Equation 2.10.
The non-overloaded input power is given by:
INPUT
P
(FS/2)2
(2N-1A)
42
2
2 2 N23
(2.17)
Based on Equations 2.10 and 2.17, the SQNR is calculated as:
SQNR
=
10 log1 0
INPUT
PQ
= 6.02N + 1.76 + (20L + 10)logiOOSR - 10lo 2
=
20LlogjO(
7r
7r2L
) + 6.02N + 1.76 + 10loglo(OSR(2L + 1))
(2.18)
Equation 2.18 shows that with the three given factors, L, OSR, and N, the first term
20Lloglo( OR) has the largest effect in improving the SQNR. The order of the loop
filter L, is the key factor.
In state-of-the-art CT AE modulators that achieved signal bandwidths greater
than 50MHz [3,6,11,17], their OSR and N values are lower than or equal to 30 and
4 bits, respectively. These limitations show that it is practically difficult to increase
OSR or N further due to the issues as discussed before.
Therefore, in this work,
OSR is set to 18. The sampling frequency is 1.8GHz for a 50MHz signal bandwidth.
N is set to 4 bits or less (by utilizing two quantizers).
To reduce the quantization
noise further, the effective order of the NTF increases, instead of increasing the order
of the loop filter directly. This method provides more aggressive noise shaping, while
maintaining a stable lower-order loop filter. This alternative method is investigated
in this thesis.
43
44
Chapter 3
Multi-Stage Noise-Shaping AE
Modulator
A higher-order loop filter causes stability and complexity issues.
In order to cir-
cumvent these issues, several architectures have been investigated [58-63].
These
architectures increase the effective order of the NTF while maintaining the order of
the loop filter. One of the best-known architecture is a MASH architecture [62,631.
3.1
Original MASH Architecture
X
orModultr n1(z)
+Y
E l
AlModulator2H
-'
-
Al Modulator 3
HT()
E2-
MModulator n
E
Figure 3-1: A general MASH architecture
Figure 3-1 shows a generalized block diagram of a n-loop MASH AE modulator.
45
Ei represents the quantization noise extracted from the ith-AE modulator. In general,
each loop consists of a stable low-order AE modulator. The input signal U is applied
to the 1S"-loop, and the quantization noise of the Is'-loop E1 is extracted.
extracted quantization noise is injected into the
2
This
"d-loop. Likewise, the input of each
following loop is the quantization noise of the previous loop. Therefore, except for the
lM-loop, the output of each loop is the sum of the quantization noise of the previous
loop and the shaped quantization noise of the current loop. Finally, all outputs from
n loops are canceled by digital filters H1 (z)-H (z), expect for the input signal from
the Is'-loop and the last quantization noise from the nth-loop E". The overall output
is described by:
VMASH
=
(STF 1 - U + NTF1 - E1) - H1 - (STF2 - E1 + NTF2 E2 ) H2
-
+(STF3 - E2 + NTF3 - E3 ) - H3 + - -
+( -)n+1(ST Fn - En- 1 + NTFn - En) - Hn
=
ST F1 . H1 _U + ( -1)n+1 - NT F, Hn - En + ( NT F1 -H1,
-(NTF
2
ST F2 - H2) - E1
- H2 - STF3 - H3 ) - E 2 + ...
+(-1)"(NTFn_1 - Hn-1 -
STFn - Hn) - En_1
(3.1)
where STFi and NTFi are signal and noise transfer functions of the ith-loop, respecn
tively. In Equation 3.1, if Hi = 1H STFi
i+1
i-1
Hl NTF,
then all terms are canceled except
1
for U and En terms. Also, En is effectively suppressed by all NTFs of n AE modulators. Since each AE modulator has its own feedback and a low-order loop filter, the
stability issue is alleviated.
A 2-loop MASH AE modulator is illustrated in Figure 3-2 to examine the MASH
AE modulator in more depth. The input U is applied to the 1 -loop, and the extracted quantization noise from the It-loop E1 is injected into the
2 nd-loop.
Two
digital filters H 1 (z) and H 2 (z) at the outputs of both loops cancel El and further
suppress the quantization noise from the 2nd-loop E2 . The overall output is described
46
LN1
U+ Ls1
+
Figure
-
E I
VMASH
E1
LS2H2(Z)
LN2
E2
Figure 3-2: A 2-loop MASH architecture
by:
VMASH = (STF1 -U + NTF1 - E1) - H1 - (STF2 - E1+ NTF2 - E 2 ) - H2
(3.2)
In this architecture, if H1=STF 2 and H 2 =NTF 1 , E1 is canceled and E 2 is doubleshaped by NTF 1 and NTF 2 . Then, the final output is represented by:
VMASH
= STF1 - STF2 - U - NTF1 - NTF2 - E 2
(3.3)
With the nth-order loop filter in the Is'-loop and the mth-order loop filter in the
2 nd-loop,
E 2 is effectively suppressed by a n+mth-order NTF. However, since each loop
consists of its own loop filter and feedback, the stability requirement of the MASH
architecture is determined by the local AE modulators.
The full potential of quantization noise suppression is realized if perfect cancellation of the quantization noise is achieved. In Figure 3-2, since E 1 is canceled completely by digital filters, only double-shaped E 2 by NTF1 and NTF 2 is seen at the final
output, providing excellent noise suppression. However, in practice, it is difficult to
exactly match the actual STF and NTF of the analog loop filters with digital transfer
47
functions.
The mismatch between analog and digital transfer functions causes the
quantization noise leakage and degrades the noise suppression ability significantly.
The effect of the mismatch is examined next.
VMASH
=
(STF,A- U + NTF,A -E1 ) -STF2 ,D
=
STF1,A - STF2 ,D
-U
-
(STF2 ,A -E1 + NTF2 ,A -E 2 )
-NTF,D
+(NTF1,A -STF 2,D - NTF,D - STF2 ,A) . E1
-NTF,D - NTF2 ,A -E 2
(3.4)
where subscript A and D represent the analog and digital transfer functions, respectively. Equation 3.4 shows the leakage effect due to the mismatch between analog and
digital transfer functions in detail. Ideally, STF 2,D and NTF,D are exactly matched
to STF 2 ,A and NTF,A, respectively. Then, in Equation 3.4, E1 is canceled and E2
is double-shaped by NTF1,D and NTF 2 ,A. However, analog transfer functions vary
due to process variation and non-idealities such as parasitic loading effects and finite
DC gain and UGBW of opamps. Furthermore, the analog transfer function variation
is much worse in CT MASH AE modulators compared to SC DT MASH AE modulators due to resistor and capacitor value variations. Therefore, precise matching
between analog and digital transfer functions is the main challenge in CT MASH AE
modulators [26,64-661.
CFF
U+0+A >
1+Ajs
2
1+A2 s
+FF3
.
F
1+A 3 s
T
CTd
Figure 3-3: 1I -loop of a CT 3-1 MASH AE modulator
48
Z
In order to see the actual quantization noise leakage effect from the mismatch, a
CT 3-1 MASH AE modulator is shown as an example. In Figure 3-2, the 1 " and the
2 nd
loops have the
3 rd
and 1 -order loop filters, respectively. Figure 3-3 shows the 1 st-
loop of the CT 3-1 MASH AE modulator for which a feedforward structure is used.
The coefficients for the
CFB,
3 rd, 2 nd, 1
', and zero-order paths are CFF3, CFF2, CFF1, and
respectively. OSR and N are chosen as 18 and 4 bits, respectively. The ideal
coefficients can be easily obtained from [51] or the method outlined in Section 2.3.3.
These four coefficients compose C in Equation 2.14 and Figure 2-15. In the 1St-loop,
finite DC gains are applied to all three integrators as shown in Figure 3-3.
100:
90
- All 3 Integrators
-1st
Integrator Only
-----
--
---
85: -GY
z
75
8 5 ------- --+--------- ------
--
- ------ -
10
20
30
40
----
-
------7
0---
50
60
----- -
70
- -- ---- ------
80
90
100
Integrator DC gain (dB)
Figure 3-4: SQNR results based on different DC gain values
First, finite DC gains (Ar-A 3 ) are used to see the degradation in quantization
noise suppression. Figure 3-4 shows SQNR values based on different DC gain values.
The blue trace shows the SQNR when all DC gains are equal and varied at the same
time. The red trace shows the SQNR when the DC gain of the 1 tntegrator is varied
only and DC gains of other integrators are set to 120dB. The SQNR from the ideal
CT 3-1 MASH LAX modulator is 100dB. Figure 3-4 shows that SQNR values decrease
49
below the DC gain of 60dB in both cases. These finite DC gain values change the
analog transfer functions in Equation 3.4 and cause the E1 leakage. Although the
DC gain between 40dB and 60dB is the practical target value using modern CMOS
technologies (below 65nm), there is a huge degradation in the SQNR in the MASH
architecture within this range.
0 -I 4 -
---I---
[ 1 1 -------
-
-50
TB
100dB
0% variation
89.6dB 10 o variation
83.2dB 20 Y% variation
CO)
~1~
B-100
-
---
--
--------I
-I
I 'i'-1 8i
cm -150
ILJ --------
- -- -L-----
--
- --
-200
i
10
106
10
Frequency (Hz)
108
Figure 3-5: Three feedforward coefficient variation effects with a -2dBFS input
Figure 3-5 shows the performance degradation from coefficient variations. Three
coefficients for feedforward paths CFF1, CFF2, and CFF3 are varied. With 20% variations, the whole noise floor goes up due to the E 1 leakage, and the SQNR is degraded
by 16.8dB.
50
3.2
DT Sturdy-MASH (SMASH) Architecture
The ideal MASH architecture provides an aggressive noise suppression capability
In spite of their advantages, MASH AE modulators
have seen limited use, because of the mismatch issues [26, 64-66].
If analog and
digital transfer functions are not well matched, the quantization noise for the 1
-
without a stability problem.
loop cannot be canceled completely and this quantization noise leakage degrades the
performance. To address this issue, a new MASH architecture, referred to as SMASH
was reported in a DT MASH AE modulator [18].
EMMMONOWENNNEEMENNOM
LN(Z)
U
ULs1 (z)
-
E1
'I
+
VS MASH
E1
Ls2(Z)
-U
LN'2(Z) -.
E2
a
Figure 3-6: A DT SMASH architecture
The block diagram of a 2-loop DT SMASH architecture is shown in Figure 3-6.
Compared to the original MASH architecture in Figure 3-2, the SMASH architecture
has several different features. First, there are no digital filters at the outputs of either
loop for quantization noise cancellation. Also, the output of the 2 d-loop is subtracted
from the output of the 1"-loop inside the loop before the feedback. After this
2 nd-
loop output subtraction, the final output VSMASH, is fed to the 1st-loop through the
feedback loop. Then, the output of the 2nd-loop can be treated as the quantization
noise of the 1S-loop along with original E1 . The output transfer function of the
51
SMASH architecture is given by:
VSMASH
=
STF1 -U + [E1 - (STF2 - E1 + NTF2 - E2 )] - NTF1
= STF1 -U + NTF1 - (1 - STF2 ) - E1 - NTF1 -NTF2 -E 2
(3.5)
In a DT SMASH AE modulator, El is not eliminated unlike the El of an original MASH architecture.
Equation 3.5.
Instead, E 1 is shaped by NTF 1 .(1-STF 2) as shown in
(1-STF 2 ) is set to NTF 2 , in order to shape both E1 and E 2 by
NTF1 .NTF 2 [18]. Since there is no transfer function matching requirement, this architecture is more tolerant of non-idealities from active blocks and coefficient variations
than the MASH architecture.
However, the DT SMASH AE modulator has two issues. The first issue is the
limited signal bandwidth due to the inherent sampling frequency limitation of the
DT implementation. The second issue is the uncanceled E 1 . E1 in the DT SMASH
AE modulator is shaped by the effective NTF, not canceled as in the ideal MASH
architecture. To solve these issues, a CT SMASH AE modulator is presented in the
following chapters.
52
Chapter 4
CT 3-1 SMASH AE Modulator
.
U +
Q1
TdV
HLF1
d
-d CLK
Z-Td1. E1
Q2
+
F-Td2
HLF2
z-TdlI
Figure 4-1: A CT SMASH architecture
A CT AE modulator based on a 2-loop SMASH architecture is proposed in this
chapter. Figure 4-1 shows the block diagram of the general 2-loop CT SMASH AE
modulator.
A 3-1 architecture is chosen to reduce E, as much as possible before
applying it to the input of the 2nd-loop. This allows an additional reduction of E 2 as
explained later in this chapter.
53
This block diagram shows two main differences in CT implementation. First, two
loop filters,
HLF1
and
HLF2,
are implemented in CT. Second, to extract delayed E1
from the 1St-loop, another delay block is necessary to delay the input of
Q, to
match
the delay in the output of Q, for the proper extraction of E1 . This chapter shows the
key advantages from the CT implementation of the SMASH AE modulator.
Then,
this chapter illustrates main challenges of the implementation of the CT 3-1 SMASH
AE modulator and solutions to those challenges.
4.1
Advantages of a CT 3-1 SMASH AE Modulator
The main advantages of the CT implementation are the much higher signal bandwidth
for given UGBW of opamps as well as relaxed anti-aliasing requirements [37,47,49,
67]. There are two additional advantages compared with the previous DT SMASH
AE modulator. The first advantage is that the CT 3-1 SMASH AE modulator can
effectively cancel the in-band quantization noise from the 1 -loop, instead of shaping
.
it by the product of NTF1 and NTF 2
E1
a
UN
HLF1
Path 3
Path 2
-T1'P
-
-Td
H
" V
Path 1
STF2
Figure 4-2: E1 path
Figure 4-2 shows the E1 path in the proposed CT 3-1 SMASH AE modulator
54
architecture. To see El path clearly, E 2 is ignored, and then the 2nd-loop is replaced
by a single STF 2 block. As shown in the blue path in Figure 4-2, if in-band STF
2
is delay-less unity-gain, then the in-band E 1 detouring through the 2nd-loop (Path
1), cancels the in-band E1 coming from Q, (Path 2) by the subtractor before the
feedback. In the previous DT SMASH architecture, this STF 2 had an unavoidable
delay and the in-band E 1 was not canceled, but suppressed by NTF 1 .NTF 2 . The
proper
2 nd-loop
implementation for the desired STF 2 to provide delay-less unity-gain
within the signal bandwidth will be presented in the later section. Another interesting
point is that this in-band E1 cancellation is unaffected by the mismatch between the
Qi output delay, Tdi, and input delay, Td. This is because in-band E 1 does not go
through the delay block for the Q, input signal (Path 3), as shown in Figure 4-2.
However, if there is a mismatch between
Tdl
and Td, the input signal Y to Qi
shown in Figure 4-2, is not canceled at the input of the 2nd-loop. If the mismatch
is large, the residual signal circulates through both loops and may compromise the
in-band noise floor and stability, since E 1 is no longer canceled effectively due to
saturation of the
2
nd-loop quantizer Q2. The delay mismatch which does not cause
saturation of Q2 affects only the out-of-band characteristics and does not degrade
the in-band performance.
Therefore, there is no precise delay mismatch matching
requirement for in-band E 1 cancellation.
Another advantage of the CT 3-1 SMASH AE modulator is that, since the overall
in-band quantization noise comes from the shaped E 2 , it can be further reduced
without being limited by the residual E 1 . Thanks to in-band E 1 cancellation, any
E 2 reduction is directly reflected in improved SQNR. In the CT 3-1 SMASH AE
modulator, E 2 can be reduced further without decreasing the step size of Q2. The
way to reduce E 2 is shown in Figure 4-3. There are gain and attenuation blocks at
the input and output of the 2 nd-loop. These blocks do not affect the magnitude of
E,
whereas E 2 can be reduced by the attenuation block at the output of the 2nd-loop.
A larger gain can improve the SQNR directly, but there are several constraints. A
larger gain may saturate Q2. Also, it needs the additional levels in Q2 requiring more
comparators, DAC cells, and drivers.
In this prototype, gain-of-2 is used in order
55
.
Q1
U+ HLF1-Tdi
+
-Td2
HLF2
+
V
-TF
z~LCL
Figure 4-3: Further reduction of E 2 by gain and attenuation blocks
to obtain 6dB SQNR improvement. This would not be effective in the previous DT
SMASH implementation. Since E1 is not completely canceled in the DT SMASH
ZALX
modulator, the further reduction of E2 would not improve the noise suppression
significantly. The same problem exists in the original MASH architecture due to EB 1
leakage from the mismatch between analog and digital transfer functions.
If in-band E 1 is fully canceled, then only the double-shaped E 2 shows up at the
final output of the CT 3-1 SMASH AE modulator.
In the CT 3-1 SMASH LAEX
modulator, B 2 is double-shaped by a 3rd-order NTF and a 1st-order NTF. Thus, the
CT 3-1 SMASH A)2 modulator provides 4th-.order noise shaping. The CT 3-1 SMASH
AE modulator requires additional DACs and one extra quantizer to implement the
2nd-loop, compared with a CT 4th-order single-loop AE~ modulator. However, the
CT 3-1 SMASH architecture has significant advantages over a conventional 4th-order
single-loop L\E modulator.
Figure 4-4 shows the simple block diagrams of the CT 4 th-.order single-loop LE
modulator and the CT 3-1 SMASH LE modulator. For both AE1 modulators, feed56
4th-order FF
U
Ls
+
Vsingle-loop
(a)
3 rd -order FF
U
Ls
+
+
VSMASH
NTF2E2/2
(b)
Figure 4-4: Block diagrams: (a) CT 4th-order single-loop AE modulator, (b) CT 3-1
SMASH AE modulator
forward loop filters are employed, instead of feedback loop filters due to their better
power efficiency. These two blocks diagrams look similar, if the 2"d-loop output of
the CT 3-1 SMASH architecture is considered as quantization noise to the 1 -loop.
Then, both AE modulators consist of one loop filter and one feedback path.
The main advantage of the CT 3-1 SMASH AE modulator compared to the CT
4th -order single-loop AE modulator is a lower out-of-band STF peaking when a feedforward loop filter is used. Since a feedforward loop filter is power-efficient, many
recent state-of-the-art AE modulators used feedforward loop filters instead of feedback loop filters [3,8,11,17,27,28,30,68]. However, a feedforward loop filter causes a
substantial out-of-band STF peaking. This is a problem for wireless communication
applications in particular, in the presence of strong out-of-band interferers. Although
these signals are reduced by the AAF, a feedforward loop filter amplifies these signals
57
by the out-of-band peaking. Therefore, it is important to reduce an out-of-band STF
peaking as much as possible. The CT 3-1 SMASH AE modulator provides a lower
out-of-band STF peaking, because the STF is determined by the 3rd-order feedforward loop filter instead of the 4th -order transfer function as shown in Figure 4-4. This
is also demonstrated by behavioral simulations.
For a fair comparison, both AE modulators are designed to have same rms gains
of NTFs within the signal bandwidth to achieve the SQNR of 100dB. For both AE
modulators, OSR and N are chosen as 18 and 4 bits, respectively. In the CT 3-1
SMASH AE modulator, the Hinf values of the NTFs for the
1
" and the
2
nd
loops
are set to 1.5 and 2, respectively. Hinf is the maximum magnitude of the NTF and
shows the aggressiveness of the NTF. High Hinf provides an aggressive noise-shaping
capability but makes the modulator less stable. The implemented NTFs for the 1st
and the
-41
2
nd
NT F1
loops from the MATLAB toolbox [51] are as follows:
(z - 1)(z 2 - 1.982z + 1)
(z - 0.6664)(z 2 - 1.525z + 0.6608)
NT F2 =
1
z
(4.1)
The overall NTF of the CT 3-1 SMASH AE modulator is given by NTF 1 .NTF 2 . This
overall NTF is what is actually implemented in the prototype.
The Hinf value of the CT 4th-order single-loop AE modulator is 2.8. The implemented NTF for the behavioral simulations is given by:
(z 2 _ 1.996z + 1)(z 2 - 1.977z + 1)
(z - 0.9382z + 0.2386)(z 2 - 1.081z + 0.5273)
2
Figure 4-5 shows the STFs from both AE modulators. The blue and green traces
show the STFs of the CT 3-1 SMASH AE modulator. Compared to the STF of the
CT 4th-order single-loop AE modulator shown on the red trace, the CT 3-1 SMASH
AE modulator has a lower out-of-band STF peaking. This is due to the 3rd-order
feedforward loop filter in the signal path as shown in Figure 4-4. The green trace is
the STF of the CT 3-1 SMASH AE modulator with the Q, input delayed by an ideal
S/H circuit as shown in Figure 4-1. The blue trace is the STF when the ideal S/H
circuit is replaced by an LPF, which will be explained in Section 4.2.1.
58
14
-e- CT 3-1 SMASH with the ideal S/H
12 - -- CT 3-1 SMASH with the LPF delay
-CT single-loop 4th-order
10 -
8 ---------
--
----------
46-26 -----2106
10
Frequency (Hz)
10
10
Figure 4-5: STFs from the behavioral simulation
Another advantage of the CT 3-1 SMASH AE modulator is the smaller quantizer
input signal, Y. As shown in Figure 4-4, E 1 is seen at the input of the quantizer
directly in the CT 4th-order single-loop AE modulator. On the other hand, shaped
E1 and E 2 are seen at the input of the quantizer in the CT 3-1 SMASH AE modulator.
These different quantizer inputs are also shown through behavioral simulations. Both
AE modulators have the NTFs with the same rms in-band gain. Also, in order to have
same DAC full-scales, the full-scale of the quantizer in the CT 4th-order single-loop
AE modulator is set to the sum of full-scales of Qi and Q2 in the CT 3-1 SMASH
AE modulator.
Figure 4-6 shows the quantizer input spectra from both AE modulators. As
mentioned above, the shaped quantization noise is shown on the blue spectrum from
the CT 3-1 SMASH AE modulator. However, in the CT 4th -order single-loop AE
modulator, quantization noise is directly shown on the red spectrum.
Figure 4-7 shows the quantizer input transient wave forms from both AE modulators. As expected, more quantization noise is seen on the red wave form from the CT
59
_
-134 OF$
~-50
*1
444
-
4th-order
-3-1
SMASH
O
L
cc
Id
-------------
0.
f 'I
CL
:-100
TIlT
ai
I;
-
-
-150' 5
10
10
106
108
10
Frequency (Hz)
Figure 4-6: Quantizer input spectra from the behavioral simulation
.
-------...
-------------------..
....
.
0 . '.------------------ -----
--..
..-
------ -
V
-
-
-
---I
2
-
-
--
0
VFSp-p=1
-
-
-
-
3
4
Time (9)
-
---
0
67V
-4th-order
-3-1
SMASH
0.20.1
AVs=0
--------- --
0 .4
5
-7
Figure 4-7: Quantizer input transient wave forms from the behavioral simulation
4th-order single-loop AE modulator. The averaged peak value of the red wave form
is higher by 6% of the full scale of the quantizer than that of the blue wave form from
the CT 3-1 SMASH AE modulator. Thus, in the CT 3-1 SMASH AE modulator, the
60
noise floor at the input of the quantizer is lower and allows a larger input signal to
the modulator. As a result, the quantizer has more input margins before it saturates.
The maximum allowable input range of the CT 3-1 SMASH AE modulator before
the entire modulator becomes unstable is 1dBFS larger than that of the CT 4th-order
single-loop AE modulator.
In summary, in-band E 1 cancellation of the CT 3-1 SMASH AE modulator provides an enhanced SQNR, compared to the previous DT SMASH AE modulator. The
CT 3-1 SMASH AE modulator also has lower out-of-band STF peaking and better
stability, compared to the CT 4th-order single-loop AE modulator. Of course, these
advantages come at the cost of the additional quantizer and DACs which require
additional power and area. However, the benefits outweigh the cost.
Two Main Challenges of CT 3-1 SMASH AE
4.2
Modulator Implementation
So far, the advantages of the CT 3-1 SMASH AE modulator have been discussed.
However, there are two main challenges from the CT 3-1 SMASH AE modulator
implementation. The first challenge is how to delay the
8.
Q1.
Q 1 input
signal Y in Figure 4-
To extract delayed E1 correctly, Y needs to be delayed to match the delay of
The second challenge is how to cancel in-band E1 through the proper 2,d-loop
implementation. These two challenges will be explained in detail.
4.2.1
Analog Delay
The first challenge is that the CT quantizer input signal Y needs to be delayed. In the
SMASH architecture, the ideal input to the 2nd-loop is the delayed E1 . For correct
extraction of E 1 , Y must be delayed to match a delay from the output of
Q 1.
In order
to delay the CT signal Y precisely, Y needs to be sampled first, and then delivered
to the input of the 2nd-loop after a delay. However, it is difficult to implement an
accurate S/H circuit operating over 1 GS/s.
61
Y
U+
Q1
zTdl
HLF1
-Td2
+
V
-Tdl CLK
Z
2+
Q21/
+HLF2
-Td
Figure 4-8: Block diagram of the CT 3-1 SMASH AE modulator
Therefore, it is necessary to find an alternate way to delay the CT signal from the
input of Q, to the input of the 2nd,-oop. In this prototype, the signal Y is delayed by
an analog delay instead of an S/H circuit. The analog delay is implemented by a 1
-order LPF as shown in Figure 4-9.
Figure 4-9 shows a CT 3-1 SMASH AE modulator with the delay block replaced
by the 1st-order LPF. If the time constant of the LPF is set to the desired delay Tdl,
and the input frequencies of the LPF are much lower than 1/Tdl, then the group
delay of the LPF is very close to the time constant Tdl within the signal bandwidth.
In this prototype, a time constant TdI is set to 0.5Ts.
The amplitude and phase characteristics of a 1st-order LPF are given by:
1
sTd1 + 1
M(W)
1
,
(w) = -tan(wTdl)
(4.3)
(wTdl) 2 + 1
If the input of the LPF is sinusoidal with amplitude A and angular frequency WIN,
62
+
LPF
HLFI
-dl
z
-z
n1+
-Td2
-Tdl
z2 OLK
+~d
HI2z-d
z~ '-CLK
Figure 4-9: Analog delay implementation
the output of the LPF is given by:
A
VoUT(t)
=
2
(wINTdl) + 1
x sin(WINt - tan-1 (WINTd1))
(4.4)
If WIN <1Td1,
A
~ A,
tan-1
(wINTdl) -_,TINTdfl
(4.5)
+
V(WINidI)2
As a result, the final LPF output is given by:
VouT(t)
A x sin(WINt
- WINTd1)
=
A x
sin(WIN(t -
Tdl))
(4.6)
This indicates that the LPF can delay the CT signal by its time constant when the
input frequencies of the LPF are much lower than the inverse of its time constant.
As discussed before, even with considerable mismatch between the LPF time constant and the desired delay
Tdl,
the SQNR and stability are maintained. Figure 4-10
shows the SQNR results based on different LPF time constant values from behavioral
simulations. As shown in Figure 4-10, the LPF time constant can range between 0.3T s
63
z S50-
---------------
--
-20MHz
- 30MHz
-40MHz
30
-50MHz
_
-....
-.
_
-J----J
--------- I - ---------2 ----------- ---
o 40
-
-
----------------
------------+-+.-------------- ----- -----I--------- ------- ---90 -- -----1
41
/
00
----------------------------__L
10
_ _
0
I_I
__
___ _ _ __ _ _ _ __
0.5
1
1.5
2
2.5
LPF Time Constant (Ts)
3
3.5
Figure 4-10: SQNR results based on different LPF time constants with different input
frequencies
and 2Ts without SQNR degradation. On the prototype chip, the LPF time constant
was also made programmable. The measured peak signal-to-noise-and-distortion ratio (SNDR) remained unchanged for the maximum adjustable range of t13%. For
the actual implementation, the LPF is embedded within the existing OTA in the
2nd-loop as explained in Section 5.1.2.
Another interesting point is that the LPF affects the shape of the STF. As shown
in Figure 4-5, when an ideal S/H circuit is employed to delay the input signal of Q 1,
the STF of the CT 3-1 SMASH AE modulator is the exactly same as that of the
CT single-loop AE modulator with the identical 3rd-order loop filter. However, there
is a second peak with an LPF. This is because the LPF attenuates high frequency
components and the discrepancy between the zero-order-hold
Q1
output and the CT
LPF output causes the out-of-band signal leakage, making signal circulate both loops
at high input frequencies.
Figure 4-11 shows the STF variation based on different LPF time constant values.
With a lower LPF time constant, the second peak of the STF is higher because more
64
10
STF with LPF TC variation
- -
- STF with an
ideal S/H circuit
- - --
'4
--
+3
U.
--
030%
C
I
"i:30%
--------------r
-j
2
106
108
10
10
10
Frequency (Hz)
Figure 4-11: STF variation based on different LPF time constant values
high frequency components are attenuated by the LPF. However, even with 30%
variation, the maximum peak is 8dB, which is significantly smaller and at a higher
frequency than in the CT 4th-order single-loop AE modulator.
4.2.2
Feedforward Path in the 2 nd- 10 0 p
01 output
>
DAC 2
02
101
Input
-T2 .To the
11 0
++
-H
z IiCLK
let-loo
Figure 4-12: 2nd-loop implementation
The second challenge is the in-band E1 cancellation. In the CT SMASH architecture, if in-band STF 2 is delay-less unity-gain, the
2 nd-loop
output subtraction cancels
the in-band E1 . The delay-less unity-gain STF within the signal bandwidth can be
65
approximated by a blue feedforward path as shown in Figure 4-12.
In general, a feedforward path in the CT AE modulator is implemented from the
input of the loop filter to the input of the quantizer. If this method is applied in the
proposed CT 3-1 SMASH AE modulator, both the input and the output of Q1, as
well as the DAC 3 output need to be applied to the input of Q2 through additional
paths. To avoid such additional complexity, the same effect as the feedforward is
achieved by the resistor RMASH in series with the integrating capacitor CMASH for
the It-order 2 nd-loop, as shown in Figure 4-12. This provides very close to unity-gain
with almost zero delay within the signal bandwidth. Then, the output of the SMASH
architecture within the signal bandwidth is represent by:
=
VSMASH, In-Band
~
Q1
(1 - STF2 ) - E1 - NTF1 - NTF2 E2/2
STF1 - U + NTF1
STF1 .U - NTF1 NTF2 - E2 /2
(4.7)
Output
Q2
Q1 Input
+
-
-T2
+
--Tds
z
To the
get-loop
'-LK
Z
(a)
01 output
Q2
Q1 Input
+
+-
s
+
f
dl
Td2
z
To the
st-loop
(b)
Figure 4-13: 2 nd-loop implementation: (a) with a feedforward path, (b) without a
feedforward path
66
To verify the effect of the feedforward path, the 2nd-loop is implemented without
the feedforward path. Figures 4-13(a) and (b) show the
2
nd-loop
with and without
the feedforward path. In each case, regardless of the feedforward path, the path from
the output to the input of Q2 is identical. Thus NTF 2s of two cases are identical, but
STF 2 of the case (b) has a delay within the signal bandwidth due to the absence of
the feedforward path.
1nl2 I
-
98-
-
96-
-
wlo FF + Gain-of-2
wlo FF + Gain-of-1
-
ft0
-
w/ FF + Gain-of-2
w/FF + Gain-of-1
.
100 F
z
0Y 94U)
.......9290
88
0
..........I
I
0.5
1
I
I
I
1.5
2
2.5
Input Frequency (Hz)
II
3
3.5
4
X107
Figure 4-14: SQNR results with and without a feedforward path at different input
frequencies
Figure 4-14 shows the SQNR results for both cases from the simulations. With
the feedforward path, the additional reduction of E 2 by the gain-of-2 block is fully
effective, providing additional 6dB SQNR improvement.
In contrast, without the
feedforward path, the SQNR improvement by the gain-of-2 block is limited to 2dB due
to the imperfect cancellation of E 1 . These results show that, due to the feedforward
path, in-band El is nearly fully canceled as in an ideal MASH architecture and E2
can be reduced further by the gain and attenuation blocks.
67
68
Chapter 5
Prototype Implementation
5.1
5.1.1
Circuit Implementation
CT 3-1 SMASH AE Modulator
CQrr
Rzi
Cim Rn
Cim
VVol
V IN
S15-level
-_V
C
R
Z'm
z~oD
1
Off-chip
Ii
CLKI
C
DAC2
let-looo
1/2
7-19vel
=1
D2
2"d-loop
Figure 5-1: Overall schematic
Figure 5-1 shows the overall schematic of the CT 3-1 SMASH AE modulator.
69
The 1 -loop consists of a 3rd-order feedforward loop filter, DAC 1 and DAC 1', and a
15-level quantizer. Three RC integrators are used for the 3rd-order loop filter. The
2nd-loop
consists of a Gm-C integrator implemented by an OTA with an embedded
LPF (for analog delay), a series R-C load, DAC 2 , DAC 3 , and a 7-level quantizer.
For the 1M-loop quantization noise extraction, an OTA with an embedded LPF
and DAC 2 are utilized. In order to match the output delay of Q1, the input of Qi is
delayed inside the OTA by the LPF. The transconductance of the OTA and DAC 2
values are chosen to provide the gain-of-2 between two loops. For the
2 nd-loop
output
injection into the 1St-loop, unlike the previous block diagram shown in Figure 4-8,
each loop output is directly injected into the It-loop through DAC, and DAC 1' as
an analog adder in order to avoid the delay associated with a digital adder [18]. The
DAC 1' currents are half that of DAC, due to the gain-of-2 at the input of the 2nd-loop.
The differential full-scale of the input signal is 3.16 Vp-p which is determined by
the sum of the total current values of DAC1 and DAC 1'. This is because when the
input signal swing exceeds the full-scale range of
Q1,
the 2nd-loop extends the range
of the modulator. Both quantizers have the same step size of 40 mV. The actual chip
outputs are the two quantizer outputs (D 1 and D 2 ). These two outputs are combined
off chip to generate the final output, DOUT. An external 7.2GHz clock is divided by
2 and 4 on chip to generate 1.8GHz clock signals with all the required phases for the
quantizers and the DAC drivers. Figure 5-2 shows the overall timing diagram. In
order to compensate DAC driver and DAC switch propagation delays, the clocks of
DAC drivers arrive earlier as shown in Figure 5-2.
Another key part of the CT 3-1 SMASH AE modulator implementation is the ELD
compensation. In the CT AE modulator, the ELD exists due to the unavoidable delay in the quantizer for the regeneration time of the quantizer, the DAC propagation
delay and the finite UGBW of opamps. The uncompensated ELD degrades the overall
performance, especially the stability of the AE modulator [69]. For the ELD compensation, several methods have been proposed [42]. Among these methods, the most
popular technique is to add the feedback path from the output to the input of the
quantizer in order to provide a zero-order path [43]. Conventionally, this zero-order
70
1/1.8GHz
. 556ps
.
Ts
CLK Q1
CLK Q2
CLK DAC 2
CLK DAC 3
DAC 2 Output
DAC 3 Output
'
CLK DAC1
CLK DAC 1
DAC, Output
DAC,' Output
(34Ts
Figure 5-2: Overall timing diagram
path is implemented by additional DACs, such as differentiated DACs [1J as shown in
Figure 5-3. However, the conventional method is not optimal in the CT 3-1 SMASH
AE modulator, because there are two outer-feedback paths from two different quantizers. Therefore, two additional DACs are necessary for the zero-order path and they
require corresponding power, area, and complicated clock routing paths.
To overcome this issue, the proposed CT 3-1 AE modulator employs a lead path
for the ELD compensation. To remove additional DACs, the zero-order path is implemented by using the existing outer-feedback DACs, DAC 1 and DAC 1 ' as shown in
Figure 5-4. Due to CINT1 and Rzi of the first opamp, the output of the first opamp
71
C wn C w
15-lvel
O ff -chip
-
C~wM
VIN -ifW
Rirm
q
Ci
Rn
DoUT'
1/
C
/2
+
Rim
DAC2
---
7-16vel
D2
RK~kSNZ-1/2
CLK
CTs
Figure 5-3: Additional DACs for the zero-order path
- -VIN
ln
Rum
15-level
.
Off-chip
Z-1/2
r -------- I
-DOU
!
CLK
........ .... ...
RR
Zero
let-order path
lit + 2"d-order path
2"d + 3"d-order path
-1/2
DAC2
+
1/2
7-level
a
Rm
CMD-
CLK
Figure 5-4: All feedforward paths using outer-feedback DACs
72
D2
has both integrated 1st-order and zero-order components.
The output of the first
opamp is added at the output of the loop filter through the capacitor adder of the
third opamp (CFF1 and CINT3). Therefore, Rzi and the feedforward path through
CFF1
and CINT3 provide the zero-order path. Higher order paths are shown in Fig-
ure 5-4. To find the correct loop filter coefficients with Rz 1 , the impulse response
matching method [55] was utilized. The value of Rz 1 was increased until the impulse
response from the actual loop filter was well matched to the ideal impulse response.
The value of Rzi is dependent on parasitic effects on the actual circuits, and was set
to 30% of the input resistance RINT1 in the prototype. Other loop filter coefficients
and integrator gain-bandwidth (GBW) requirements are also determined through the
impulse response matching method to implement the desired NTF. Rz 3 is approximately 1% of RINT3 and is utilized to tweak impulse responses with the given finite
GBW of the third integrator. The target NTFs for the Is' and the
2 nd
loops are as
follows:
NTF
(z- 1)(z 2- 1.982z + 1)
(z - 0.6664)(z 2 - 1.525z + 0.6608)
(5.1)
z-1
z
.
The overall NTF of the CT 3-1 SMASH AE modulator is given by NTF1 .NTF 2
The limited coefficient variation of the ELD compensation path does not degrade
the in-band performance, and only changes the out-of-band shape
[69].
is no Rzi sensitivity issue. Figure 5-5 shows the NTF 1 change due to
Thus, there
30% Rzi
variation. The variation of the in-band rms gain is within 1%. The out-of-band shape
is, however, affected. With +30% Rzi variation, the maximum NTF1 Hinf value is
changed from 1.5 to 1.97. However, from the simulations, there was no noticeable
stability issue.
The impulse response matching method is practical especially for high-speed CT
AE modulator design, since coefficients from this method already consider all nonnegligible parasitic effects. Furthermore, this method can be easily applied to the
post-layout simulations with extracted layouts which have more parasitic effects in
general. In this work, all loop filter coefficients and integrator GBW requirements were
73
1---------------
--
-0%
. -20
-------
- -
-
- -
--
Variation
-+30%
Variation
-30% Variation
-
0
-
20
-40
------------u.
-60
----------
------------
------------
------------
-80
-
-100,
C
0.1
0.2
0.3
0.4
Normalized Frequency (flfs)
0.5
Figure 5-5: 1st-loop NTF change due to +30% Rzi variation
continuously updated after any major changes through several iterative post-layout
simulations using the impulse response matching method to implement the desired
NTF. To compensate up to
25% variation from each of resistors and capacitors, all
capacitors are implemented by digitally switched binary capacitor arrays. The final
parameter values are shown in Table 5.1.
Table 5.1: Component parameters
Value
Parameter
Value
Parameter
1.45pF
CINT1
400Q
RINT1
RINT2
833Q
CINT2
1.2pF
RINT3
16.5Ki
8.7KQ
CINT3
800fF
CFF1
120Q
220Q
2.5Kg
CFF2
180fF
100fF
CMASH
100fF
RR
Rz1
RZ3
RMASH
The four major thermal noise sources are the input resistor RINT1, DAC 1 , DAC1',
74
the opamp in the first integrator. The thermal noise from DAC
1
and DAC 1' depends
on the amplitude of the input signal to the modulator, since they use a tri-level
current-steering topology [70] which will be explained further in Section 5.1.3. The
DAC unit cell in the zero-state (among plus, minus, and zero-states) is disconnected
from the loop filter, and it does not add the thermal noise to the modulator. Most
DAC unit cells are in the zero-states with a very small input signal which only changes
one output of mid-level comparators in
Qi.
On the contrary, with a full-scale input,
all DAC unit cells have either plus or minus-states and are connected to the loop filter.
Thus, the thermal noise from DAC, and DAC 1' is lowest, one of DAC1 unit cells and
one of DAC 1 ' unit cells are connected to the loop filter with a small input. The
thermal noise from DAC 1 and DAC 1' is highest, when all DAC 1 and DAC 1 ' unit cells
are connected to the loop filter with a full-scale input signal. Therefore, two different
thermal noise signal-to-noise ratios (SNRs) were targeted due to the thermal noise
difference from DAC, and DAC 1 '. The target SNR is calculated as:
SNR
=
10 log10
Input Full-Scale
(5.2)
PTotal Thermal Noise
For full-scale and very small input signals, the target thermal noise SNRs were 84dB
and 89dB, respectively. The
RINT1
value was set to 400Q to achieve both the thermal
noise and power consumption targets. Noise simulations show that
RINT1
contributes
40% or 13% of the total thermal noise with a small or full-scale input signal, respectively. DAC 1 and DAC 1' contribute 47% or 83% of the total thermal noise with with
a small or full-scale input signal, respectively. The opamp in the first integrator contributes 7% or 2% of the total thermal noise with with a small or full-scale input
signal, respectively.
5.1.2
Amplifiers
In this section, a hybrid opamp frequency compensation topology and corresponding
UGBW maximization technique are proposed for three RC integrators in the
loop [71].
1 "-
This frequency compensation is compared with two common frequency
75
compensation topologies: Miller-compensation (MC) and feedforward-compensation
(FFC) topologies. The opamp design for integrators with this frequency compensation
is presented. In addition, the OTA design with the embedded LPF is illustrated.
Sampling frequencies over 1GHz become necessary for modern CT A E modulators,
as required signal bandwidths increase. With high sampling frequencies, unintentional
internal delays from blocks in the CT AE modulator cannot be ignored, since they
are comparable to the sampling period. One of the main sources of internal delays is
the RC integrator delay, directly related to the GBW of the integrator loop transfer
function [41]. To reduce this delay, a high GBW is required. The loop gain of the
RC integrator is given by A(s)F, where A(s) is the open-loop transfer function of the
opamp and F is the feedback factor of the integrator. F is given by:
F
where
RINT
SCINT +RINT
RINT, CINT,
sRINTCINT
-
1
+
sRINTCINT
_
(5.3)
aINTfS
1+
I
aINTfs
and aINT are the integrator resistor, capacitor, and scaling factor,
respectively. aINTfS is 1/RINTOINT. In general, aINTfS27r is lower than the UGBW
of the opamp which is higher than fs.
Therefore, the GBW of the integrator is
directly related to the UGBW of the opamp.
For a high GBW integrator, a high
UGBW opamp is necessary.
Gain
A DC
R
R C
1n >_
P)
V
R o2C,
C,
+--------.--
!ah
/
J'
Maximum
achievable
OdB
Freq
_l
-
-
P2
--
(a)
Figure 5-6:
response
Two-stage opamp without compensation:
(b)
P1
(a) topology, (b) frequency
If stability is ignored, a maximum UGBW may be achieved when there is no
76
frequency compensation.
For example, Figure 5-6 shows the maximum achievable
UGBW of a two-stage opamp under given opamp parameters.
the first and the second stage outputs are pi
=
-1/R
1
When the poles at
Cp1 and P2
=
-1/Ro2CL,
respectively, the UGBW is approximated by:
UGBWmax ~ vAZ x P, =
ADCP1P2 =
gm1gm 2
CP1CL
(5.4)
This UGBW will be used as a base line. Although this topology provides the maximum UGBW, the PM is insufficient, since both pi and P2 are below the UGBW.
MC and FFC opamp topologies have generally been used in recent CT AE modulators. The frequency response characteristics of theses two topologies are reviewed
first and the UGBW limits of two topologies are presented.
Rz Cc
TOut
V
-9.
V
>-9m,
in
R I,C
R,
CL
Figure 5-7: MC topology
The MC topology is shown in Figure 5-7. A compensating capacitor and a nulling
resistor are added. The main idea of the MC topology is to split the poles by using
the Miller compensating capacitor. After compensation, the dominant pole is lowered
while the non-dominant pole is pushed out to a high frequency. Meanwhile, the nulling
resistor helps to eliminate the right-half-plane zero or to move this zero to the lefthalf-plane (LHP). In Figure 5-7, if Cp 1 is ignored, the MC opamp transfer function is
77
given by:
VOUT
gmigm 2 Ro1Ro2 [1 - SCC
VOUT1
1+ as + bs
VIN
2
2
1 - Rz
9m2(5.5)
a = Ro 1Cc + Ro2(CL + Cc) + RzCc + gm 2 Ro1Ro2 Cc
b = RolRo2CCL + Ro2RZCcCL
When gm2 RoiRo2 >> Rol, Ro2 and Rol >> Rz, the two poles and one zero are given by
P1 = -1/gm 2 RoiRo2 CC, P2 = -gm2/CL, and z, = 1/CC(1/gm2 - Rz). P2 is commonly
set to about twice the UGBW or higher in order to obtain a reasonably high PM.
Rz is set to a value slightly larger than 1/gm2 in order to move the zero to high
frequencies in the LHP. In this case, P2 and z, are located above the UGBW, and the
UGBW is approximated by ADC X pi=gmi/Cc, where ADC is the DC gain. Cc can
then be selected by comparing the UGBW and P2.
IP2 | = 2 x UGBW - gm2 =
CL
2
x
Cc
C 2g
CL
9m2
If Rz is slightly larger than 1/gm 2 , the PM is above 600: PM
tan- 1 (UGBW/zi) = 63.40 + tan-1 (gmfRz -
(5.6)
90'-tan-(UGBW/P 2 1)-
gml/gm2).
The main disadvantage of the MC topology is that the UGBW gmi/Cc, is considerably lower than UGBWmaX,
gmlgm2/Cp1CL, since 21Cpi is generally larger than
1/Cc as shown below.
UGBW _ C1
Cc
-C
2
Cc 2CL
UGBWmax x
C0
(5.7)
Moreover, from Equation 5.6, high gm2 is necessary for the MC topology to avoid
large Cc and correspondingly low UGBW and slew rate for given CL.
The FFC topology without an additional capacitor is analyzed in Figure 5-8. The
FF path is typically implemented by using the existing current for
m2
[26]. This path
is, therefore, considered as a power-free path. The overall frequency response of the
FFC topology is obtained by adding two frequency responses from the two-stage and
78
Gain
...........
V.'
g1
g,,,2
UGBW12
uaB
or
AdR
1-
I'
-
V
Case 1
uu vW 12
FF path UGBW1f
Case 2
UGBWIf>
FTa ath
2-stage path UGBW 12
2-s1age pa
Overal-
..---..-- FF path
- - - 2-stage path
UGB~f %',Freq
UJGBW1f
',
Figure 5-8: Two cases of the FFC topology
the FF paths. There are two possible cases based on the zero location. The first case
is when the zero is located above the overall UGBW. This means that UGBW of the
two-stage path (UGBW12) is higher than that of the FF path (UGBWlf). The second
case is when the zero is located below the overall UGBW, so UGBW1f is higher than
UGBW12. For a sufficient PM, the desired frequency response of the FFC topology
is that of the second case, because the zero location below the overall UGBW helps
to increase a PM. It is, however, difficult to locate the zero below the overall UGBW
with the given parameters only. This is easily shown by comparing UGBW12 and
UGBW1f, given by UGBW12 =
/gmlgm2/C1CL and UGBW1f = gmlf/CL. Since
Cp, is smaller than CL and the same bias current is used for
9m2
and gmlf, UGBW12
is typically higher than UGBW1f. Since the zero beyond the UGBW cannot provide
a sufficient PM, this zero needs to move below the overall UGBW. For this, there
are two options as shown in Figure 5-9: (1) adding additional capacitance at the first
stage output to increase effective CP1, or (2) adding a compensating capacitor around
the second stage, which is a combination of the MC and the FFC topologies.
The first option intentionally reduces UGBW12 =
79
V/gmlgm2/C1CL,
such that
gulff
V1.
V. v,-
-9.
-9.
R
c +c..
R.2
R. it~~
iCL
V
-g,.
-g.1
(a)
~
'V
Cj
o
R_
C
(b)
Figure 5-9: FFC topologies: (a) option 1, (b) option 2
UGBW1f > UGBW12. The zero is thereby located below the overall UGBW, and the
overall UGBW becomes UGBW1f = gmif/CL. By locating the zero at UGBW/1.7 or
lower, the PM can be above tan-1 (1.7) ~ 60'. In the second option, the compensating
capacitor splits the two-stage path poles as in the MC topology. Its transfer function
is given by:
VOUT_ g
1
[
+I C (gg2
1+ as + bS 2
m2 Ro 1 Ro 2
VIN
(5.8)
a = Ro1 Cc + Ro2(CL + CC) + 9m 2 Ro1 Ro 2 Cc
b = RolRo2CCCL
If gmlf is made slightly larger than gml, the overall UGBW becomes gmi/Cc. The
PM is also similar to that of the MC topology, except for a different zero location.
The PM is expressed as:
PM = 63.4'
+ tan-1 ((gmlf -
gml)/gm2).
Both options
guarantee enough PMs, but the overall UGBWs are always lower than UGBW max=
Vgmlgm2/Cp1CL.
Now, a feedforward-Miller-compensation with pole-zero cancellation (FFMC-PZ)
topology is proposed for achieving the maximum UGBW and adequate PM. Figure 510(a) presents the FFMC-PZ topology with Rz added for pole-zero cancellation.
Unlike the previous sections, Cpl is not ignored for accurate analysis.
Equation 5.9 gives the transfer function based on Figure 5-10(a). Assumptions are
80
Gain
Rz(C)
CI
( -g.
Ro
C P;
-------------------A i
V
Ro2
------
---
UGBW
FFMC
I
w/o compensation
2
P3
(b)
(a)
'
z2
.
| | |req
zI p
p1
Figure 5-10: FFMC-PZ: (a) topology, (b) frequency response
V 0 UT _
gmlgm2RolRo2
[I - sc
1
-
Rz
+gmlfRo2
1 +
VIN
2
[1+s(RoiCc + Ro1Cp1+ RzCc) +s RoiRzCcCp1]
as + bs 2
+ c8
3
(5.9)
a = R. 1 (Cp 1 + Cc) + R.2(CL + Cc) + RzCc + gm 2 Rol Ro 2 Cc
b = Ro1Ro2(CplCL + CCCL + Cp1Cc) + RzCc(Ro1Cp1 + RO2CL)
c = Ro1R.2RzCP1CCCL
made to simplify Equation 5.9 and extract poles and zeros: (1) gm 2 Roi, gm 2 Ro2 > 1,
(2) CL > Cpl (3) Rol > Rz, (4)
Ro 2 CL >
RZCp1 , and (5) gm2 RZCC > Cpi. Also,
gmlf is set to gmi for simplification. Different values can be used for gmlf without
changing the overall effectiveness. Then, Equation 5.9 is simplified as follows:
VOUT
gm1gm2Ro1Ro2[1
+ S (gm2RZCC+Cp1
9m2
1 + as + bs, + cs3
VIN
+ s2RzCcC11
9gm2
(5.10)
Since z, is located at much lower frequencies than z 2 , zi and z 2 are easily extracted
from Equation 5.10.
-
zi' ~
1
z2
81
9m2
pl
-Cp1
(5.11)
The dominant pole, pi, is expressed as:
P1 ~ -
(5.12)
1
gm2 Ro, Ro2 CC
The remaining poles, P2 and P3 , are given by:
Cc+ C1
C + C 11CL
P2, P3 ~+
-
(5.13)
4grn2
-2RzCcCp 1
From Equation 5.13, P2 X P3 is expressed as gm2/RzCpCL.
Based on these pole
and zero locations, the frequency response of the FFMC-PZ topology is shown in
Figure 5-10(b).
An important aspect is the location of the non-dominant poles and the zero. If
P2
and zi are approximately equal, the effects from P2 and z, are canceled. The fre-
quency response of the FFMC-PZ topology below the UGBW is, therefore, primarily
determined by the two poles, pi and P3. This helps to achieve UGBW max, which
is shown by deriving the UGBW from the pole and zero locations. To derive this
UGBW, the gain at zi, A 1, is calculated first, since the UGBW is VA 1 p 2p 3 as shown
in Equation 5.4. A 1 is calculated using pi and z, based on Equations 5.11 and 5.12
as follows: A 1 = ADO x pi/zi - gmiRz. The UGBW is, therefore, expressed as:
UGBW =
A 1 p2 pP2P33
gmgm2
CPlCL
UGBWmax
(5.14)
(.4
This result shows that the FFMC-PZ topology has the UGBW equal to UGBWmax,
when P2, P3, and z, are below the UGBW. The difference between this topology and
that in Figure 5-6 is that P3 is located higher than the original P2, giving a better
PM. Additionally, the FF path generates another zero, z2 , above the UGBW. If P3
is located at 4/5 xUGBW and z 2 is located at 5/2xUGBW, the PM becomes 60' as
.
given by: 90' - tan- 1 (5/4) + tan- 1 (2/5) ~ 60
There are nine parameters for the FFMC-PZ topology as shown in Figure 5-10:
gmi, gm2,
gmif, Rol, Ro2 , Rz, Cpl, CL, and Cc. If gmi, Rol, Ro 2 , Cpl, and CL are
given based on the design and power specifications,
82
gm2, 9mlf,
Cc, and Rz must be
selected for appropriate compensation with the maximum UGBW and adequate PM.
The process to choose these four parameters is as follows:
1. gmlf is set to gm 1
2. gm2 is determined by putting z 2 at approximately 5/2xUGBW for an adequate
PM
3. Cc is set to a x CL (a ~ 1/3 to 2/3)
4. By sweeping Rz, Rz is determined to locate P3 at 4/5x UGBW for a PM of 600
5. If a PM is not enough, increase Cc and find Rz again
gmif does not need to be set to gmi, as long as gmif/CL is lower than
gmlgm2/Cp1CL.
Since the FFMC-PZ compensation does not require that P2 and P3 are beyond the
crossover frequency, small
and Cc values can be used.
9m2
This saves power and
mitigates the slewing problem.
For the three RC integrators in the 1"-loop in the prototype, two-stage amplifiers
with the FFMC-PZ frequency compensation are used in order to maximize GBWs
with adequate PMs and low power. The amplifier schematic is shown in Figure 5-11.
Differential inputs are applied to Mia,
Mlb, M5a,
and
M5b.
The frequency response
is determined by the Miller capacitor (Cc) and the nulling resister (Rz) in the standard two-stage path (Mi, and
through
M 5a
and
M5b,
Mlb
through
M 4a
and
M4b,),
and the single-stage path
providing optimized pole-zero locations. The single-stage path
shares the bias current with the 2nd-stage of the two-stage path
M5b,)
(M4,, M4b, M5a,
and
[71]. The 15t-stage output common-mode (CM) is fixed locally, and the
2 nd-
stage output CM is fixed by a CMFB amplifier and M 7 . The closed-loop bandwidths
of the first, second, and third integrators with all loading effects, are 1.94, 1.17, and
1.28fs, respectively. The integrators consume 14.8, 2.2, and 10mW, respectively.
Figure 5-12 shows the OTA with an embedded LPF for the 2nd-loop.
Since the
LPF is located inside the active block, there is no direct loading effect of the LPF on
the inputs of Q, and
2 nd-loop.
connected transistors
(M 2 a
and
The additional capacitors, CD's and existing diodeM2b)
work together as the LPF to delay the signal.
83
VDD
H
M3a
I~
M3b
M2b
-
M 2a
j
M4b
M4a
OUTN
OUTp
Cc
[-
M5a
Rz
IN,
-1
Rz
Mib
Mia
VB19
INN-
M5b
Ms
Oj M 7
-
VCM
OUTp
I-
Cc
OUTN
Figure 5-11: Two-stage amplifier in the l -loop
The delay is determined by the time constant
ductance of
M2a
and
M2b.
CD/Gm,D
where
Gm,D
is the transcon-
The degeneration resistor RGm between the sources of
input transistors provides linear transconductance for the OTA. The output CM is
fixed by a CMFB through the 2"d-stage bottom transistors
values of
M6a,-M6d
(M 6 a-M 6 d).
All current
are programmable to verify the robustness of the time constant
variation. The current programmability makes the transconductance G mD adjustable
independent of the transconductance of the OTA. Therefore the delay can be adjusted
without altering the loop filter transfer function.
84
VDD
CD
GmD mD
GmD
mD
M3a
VB3
3
VOUTVoT-
M.
VIN+d
M1
Mab
M2
M2a
M4a
CD
~
RGm
Mb
VB3
V1N.
M1
VB2
PVIN-
Mob
VOUT+
Vo -r
5C
M6d
M
V21
M6a
M4b
Mac
CMFB
Figure 5-12: OTA in the
C
Qauntizer1
.
o---p--r----or--j j -14-----j
Z6;
[O
-L ve
CT
N P
QNN
3
VREF[1 :
+
Db[7:13
:DFF
Db[O:13]
]
zLO6
INz
Dz[0:6]
CDJ[-:3]
4CIb
Zb[O: ] .
n..................
---
6
DFF
Dzb[O:6]
Db[0:13]
IOUT2P
INpb[O:6]
INN b [ 6 ] PDMA C
CLK2 D [ :1 3 ]
Qz[0:61] :
Figure 5-13:
5.1.3
DAC 2 Driver
O01]TiLvlQa[0:13]
4NP
VRE[F
l31
NNb OffsetCAL[
.,....................
2 nd-l o o p
[O6]
IOUT2 N
~ [06
DAC2
D[7:13]
INb
IpO6
INZ[0:6]1NO
U 2
Quantizer 1 to DAC 2 path
Quantizer to DAC Path
Figure 5-13 shows the path from
Qi
to DAC 2 . The quantizer consists of comparators
and a trn-level encoder. The offset-calibrated comparator has 4 inputs: two for input
voltages and two for reference voltages from a resistor ladder.
The thermometer
outputs of 14 comparators, CO[[:131 and COb[0:131, are encoded to drive the tn-level
current-steering DACs chosen to reduce the number of DAC unit cells [701. Unlike a
85
general bi-level DAC which has one of two states (plus or minus), in this topology,
a DAC unit cell has one of three states (plus, minus, or zero). In the zero-state,
a DAC unit cell is disconnected from the loop filter and does not affect the output
current. Therefore, 7 DAC unit cells realize 15 levels (-7, ... ,
,- .-, +7).
Although
input signals for plus and minus-states can be directly obtained from the comparator
outputs, input signals for the zero-state must be generated by a tri-level encoder.
These quantizer outputs are connected to D flip-flops (DFFs), which drive NMOS
and PMOS elements of DAC 2 . Each element of DAC 2 consists of 7 unit cells. Three
inputs of the NMOS element are D[7:13], Db[6:01, and Dz[0:61. Notice that only one
of inputs of a unit cell is active at any time and the other two inputs are inactive.
Complementary inputs are applied to the PMOS element.
VDD
18a
17a
Mrb
CO
COb
Ma
MCal
6bCO
IN
REFNd
a
Mab
FREFp
-INN
CLKD
Mib CLKD
1
M2b
M 3 bw
CLK-I
M4b
M4a
Figure 5-14: Comparator schematic
The comparator is a 4-input StrongArm sense amplifier as shown in Figure 5-14.
Two input transistors Mi, and Mib are connected to the loop filter, and the other
two input transistors M2a and M2b are connected to a resistor ladder for reference
voltages. The voltage difference between inputs and references causes the different
current strength and rail-to-rail outputs from the cross-coupled inverters (M5a, M5b,
86
M6 a,
and M6b). Two additional small transistors MUa and M3b, in parallel with input
transistors, are used for offset calibration.
The gate voltages of these transistors
come from a separate 3-bit resistor ladder for reference voltages. To eliminate the
dependency on the previous state, comparator outputs and drain nodes of input
transistors are reset by M7a, M7b, M8a, and Msb during the low phase of the clock.
The CM kick-back to the loop filter is reduced by NMOS capacitors driven by a
slightly delayed clock [72]. A decoupling capacitor is added at each node of resistor
ladders to minimize the kick-back.
The combination of a double-tail sense amplifier [73] and symmetric slave latch [74]
is used for a DFF structure [3]. A double-tail sense amplifier provides fast regeneration
to rail-to-rail outputs during the active phase. Since both outputs become low during
the inactive phase in this sense amplifier, they are followed by a symmetric slave latch
to hold its outputs. Since this symmetric slave latch generates two complementary
outputs with the same delay, this DFF can drive the DAC cells directly.
A non-
return-to-zero pulse shape is used for all DACs to reduce the jitter sensitivity.
5.1.4
DACs and Their Calibration
The schematics of four DACs' unit cells are shown in Figure 5-15. All four DACs
use a tri-level current-steering topology and have both PMOS and NMOS elements.
DAC 1 , DAC 2 , DAC 1 ', and DAC 3 have 8, 7, 4, and 3 unit cells, respectively for the
15-level and 7-level quantizers. DAC 1 and DAC 1 ' have one extra unit cell (7+1 and
3+1) each, for current-copier based calibration
[45].
Each element of DAC 1 and DAC 1' consists of a cascoded-mirror (Mia and M 2
in the NMOS element), current copier circuits (Mlb, Ccopier,, and three transmission
gates) and four switches (M3a-M3d) operated in the triode region, three of which are
for tri-level inputs and the other for calibration. The four inputs come from DAC
drivers and only one of inputs is active at any time. Since any non-linearity in the
outer-feedback DACs, DAC 1 and DAC1', degrades the performance of the AE modulator, it is important to calibrate mismatches among unit cells of DAC 1 and DAC 1'.
Most popular calibration techniques are dynamic element matching (DEM) [37], ana87
1.5V
INCb
Ccopier2
INc
INc
VB4
1.5V
6a Menb
-
VB31
VREF1I
RF
M5
M4a
INNb-
M4c
M4b
INzb
INPb
1.2V
INcbi
VCM
IREF1
IOUTP
IREF2
INPI
INz
INNI
Mab
MWa
VBd
VB2
M2
Mia
Maf
S
M 2a
cbVIF
_
VB1-
1.2V-0
INPb
INzb
10 UTN
vCM
INd
MaC4
4
INNb
INP
M 3C
Mab
I03a
M4
el
IOUTN
M4
VB3j
VCM
INz
INN
IOUTP
VCM -0
M2C
M2b
MI
I1
mLINQ
I qC
Copiedr1
INeb
(b)
(a)
Figure 5-15: DAC unit-cell schematics: (a) DAC 1 and DAC 1', (b) DAC 2 and DAC 3
log calibration [45], and digital calibration [4, 31, 46]. In this work, current copier
based calibration [45] was chosen. This calibration is suitable with high sampling frequencies over 1GHz, since complicated circuits that can cause extra ELD delays are
not required and complex DEM shufflers for tri-level DACs in [70] are not necessary.
Figure 5-16 shows the configuration when one of DAC, NMOS element unit cells
is connected to the current copier reference cell (in blue) along with the DAC 1 NMOS
driver. Tri-level input signals for 7 unit cells come from the DAC 2 driver. Meanwhile,
the selection logic block in the DAC 1 driver chooses one of 8 unit cells to calibrate
based on the output of 8 shift registers. The tri-level inputs (INp[0], INN [01, and
88
DAC
0
UTNl
IOUT,
VCM
C..2
M7a
M7b
UN C
IREF
o.95IREF
3NP
a]
[0]Mc
MN
M
Mab
0 N dV]
Mac
Mad
VCM
M2
M5
M1b6cO
M4* Cfll1
r
Mi
M
Ceopie
N-e[0]
INc[0]
I
I
C
DAC 1 NMOS Driver
Sz[1:7]
From Dz[0:6]
DAC 2 Db[6:0]
Driver D[7:13]
LK
FromS4O:71
-
VD
SN[:7]
SP[1:7]
Sc[1:7] Sp[0:7]
SN[0:7]
0-
CLKnaC
KA
- INP[0:7]
DFF
[]
CN[O
P[]
8 Shift
Registers
Sc[0]
.
DFF
Sc[O 7
Selection
Logic
Block
DFF
-INN[0:7]
-
lNz[0:7]
-INc[0:7]
Figure 5-16: DAC, NMOS element connecting to a current copier reference cell and
DAC 1 driver for an NMOS element.
INz[O]) of the selected unit cell (DAC 1 [0) become low and the input for calibration
(INc[]) becomes high. The DACi driver input signals from the DAC 2 driver are
applied to other 7 unit cells (DACi[1:7]) through the selection logic block and the
inputs for calibration (INc[1:7]) become low. The frequency for current copying is
chosen at fs/1024. Since the transition in the selection logic block occurs before the
active edge of CLKDAC, there is no glitch from the unit cell rotation. On the actual
measured spectra, there is no noticeable spur at fs/1024.
Once one of unit cells is selected, this unit cell is taken off line from the loop filter
89
and connected to the current copier reference cell to refresh its current value, as shown
in Figure 5-16. Based on the mismatch between M la and M 4 , the Mib gate voltage is
decided through the feedback loop, because M la and Mlb must provide current IREF
from the current copier reference cell.
In next rotation cycle, transmission gates
disconnect the feedback loop and Mlb gate voltage is stored on Ccopier. Although the
gate voltage of each unit cell is different, since all unit cells copy one global reference
current, the current mismatch from mirrors (Mila and M 4 ) is calibrated. Therefore,
there is no strict mismatch requirement between mirrors. DAC 1 and DAC 1 ' have their
own current copier circuits, providing 14.5-bit and 13.4-bit accuracies respectively.
To achieve these accuracies, there are several issues. First, although a mismatch
requirement between mirrors is relaxed, the mismatch may cause a gate voltage variation of Mlb.
This gate voltage variation is reduced by the opamp gain, but the
small variation is still seen at the positive input node of the opamp. Then, it causes
slightly different reference current due to the finite output impedance from M 6a and
M7a.
Since the current copier reference circuit must provide a very accurate current
value to all unit cells, this current variation needs to be reduced based on the target
accuracy. In this prototype, up to 2% mismatch between mirrors (M la and M 4 ) was
able to be calibrated without performance degradation. The second issue in this calibration is noise. The noise from the feedback loop is stored at Ccopier and increases
the random current variation of the DAC cells. To reduce this noise, the GBW of
this feedback loop is reduced by using Miller compensation in the opamp. The third
issue is leakage and charge injection on Ccopier. Although Mlb needs to provide the
accurately fixed amount of current, the current value from Mlb drops because of the
charge leakage on Ccopier when the unit cell is disconnected from the current copier
reference cell. Also, every time a unit cell is disconnected from the reference cell, a
charge injection is introduced from the switches. To address this issue, complementary switches and large capacitors (2pF for DAC 1 and 0.8pF for DAC1 ') are used.
The second and third issues can be mitigated with proper current allocation between
Mia and Mlb. In this prototype, Ml, and Mlb nominally provide 95% and 5% of
total current. Transconductance of Mlb can be reduced dramatically and alleviate
90
the second and third issues [451.
In addition to the matching requirement of the DAC cells, there is also current
matching requirement between the two outer feedback DACs. The coefficient ratio
between DAC 1 and DAC 1' must be 2:1 for accurate cancellation of E 1 . From simulations, 10-bit matching was sufficient for 90dB modulator SNDR. Using a single
global reference current source, the two reference current transistors for the DAC1
and DAC 1 ' calibration circuits are sized to generate a 2:1 ratio with 10-bit accuracy.
Each element of DAC 2 and DAC 3 consists of a mirror (M, in the NMOS element),
three cascode switches (M2a-M2c) and associated switch drivers as shown in Figure 515(b).
Since the outputs of DAC 2 and DAC 3 are connected to the input of Q2
instead of the virtual ground of the RC integrator, cascode switches are employed.
Since DAC 2 and DAC 3 unit cells have relaxed accuracy targets (6.4-bit and 5.6-bit
respectively for 90dB modulator SNDR), calibration is not necessary.
5.2
Layout
In this section, the overall floor plan and the layouts of core blocks are presented.
Figure 5-17 shows the die photograph of the entire chip.
The overall size is
3mmx2mm. The bottom part of the chip is the analog core of the prototype. The
pins along the bottom edge are connected to the analog core. Next to the analog
core, large decoupling capacitors are provided for all power supply lines. The size of
each decoupling capacitor was decided based on the simulations in order to minimize
the ripples on the power supply lines and maintain the modulator performance. The
sizes of these capacitors are between 100pF and 450pF. On top of the analog core,
digital blocks such as SRAM and register bank are located.
Figure 5-18 shows the die photograph of the analog core.
The overall size is
0.34mm 2 . All power supplies, input signals, clock signals come from the pins below
the analog core. An external 7.2GHz clock is divided by 2 and 4 on chip to generate
all the required clock phases for the quantizers and the DAC drivers. As shown in
Figure 5-18, this clock generator is located in the middle of the layout and distribute
91
Figure 5-17: Die photograph of the entire chip
clock signals to four DACs and two quantizers through clock buffer chains. These
clock buffer chains not only consume a large amount of power, but also complicate
Figure 5-18: Die photograph of the analog core
92
1 GmC
Integrator
DAC3 DP*-
Q2
al
Q1
DAC2 Dr
3 R
Integ ra
DAC2
I
DACI Dr
DACI
DAC3
DACI1 Dr
DAC1'
At~
Current Copier Circuits
Figure 5-19: Overall floor plan
the layout, because these high frequency clock signal paths feeds clock noise to analog
paths, if they are too close. Therefore, it is necessary to reduce the number of DACs.
The ELD compensation approach using the lead path simplifies the clock routing
paths by removing additional DACs. The empty spaces are generally filled out by
decoupling capacitors for local bias circuits.
Figure 5-19 shows the overall floor plan. The I" and
2"
loop filters are located
in the middle. The driver for DAC 2 is located close to Q, to reduce the number of
buffers.
Likewise, the drivers for DAC 3 and DAC 1 ' are located close to Q2.
Figure 5-20: Layout of the modulator
93
Each
DFF in the DAC driver directly drives its own DAC without buffers. Current copier
circuits at the bottom calibrate DAC 1 and DAC 1 '.
The layout of the modulator is
shown in Figure 5-20.
Figure 5-21: Layout of two loop filters
The layouts for the two loop filters are shown in Figure 5-21. For symmetry, the
half of the opamp is implemented as one cell first and then this cell is mirrored to
complete the whole opamp. Also, the half of the loop filter including resistors and
capacitors is mirrored to the other side. Since any changes on the half cells update
the other half cell immediately, this technique helps to reduce mistakes that can cause
non-symmetry. The overall size of the loop filters is 360um x 240um.
Figure 5-22 shows the layout of Q1. Q, consists of comparators, tri-level encoder,
resistor ladders for the input reference voltages and the calibration reference voltages.
Although 14 comparators are sufficient to realize 15 levels, two dummy comparators
are added at both edges in order for 14 core comparators to be equally affected by
94
Figure 5-22: Layout of Quantizer 1
process gradients.
Comparators are followed by the tni-level encoder to drive the
DACs. In both resistor ladders, each tap has a large decoupling capacitor (>2pF)
to minimize the kick-back.
The overall sizes of Qi and Q2 are 17Oumx63um and
11Iumx9Oum, respectively.
Figure 5-23: Layout of DAC 1
Figure 5-23 shows the layout of DAC 1 , which is most critical among all DACs.
Two dummy DAC unit cells are added at both edges as well. The overall size is
210umx85um.
95
Figure 5-24: Layout of DAC 1 NMOS element
Figure 5-24 shows the NMOS element of the DAC 1 . Each part of the NMOS
element is outlined by different colors.
Figure 5-25 shows DAC 1 drivers and DAC 1 . As mentioned before, DAC 1 drivers
are located right next to DAC 1 to remove additional buffers and reduce the delay.
Figure 5-26 shows the NMOS mirrors in the current copier circuit to generate
the 2:1 current ratio with 10-bit accuracy for DAC 1 and DAC 1 '. This accuracy is
achieved by scaling up transistors. The unit cells are scrambled to minimize gradient
effects as shown in the table. 0 and X represent the unit cells of DAC 1 and DACi',
respectively. The overall size of the red dashed box is 135um x 63um.
96
Figure 5-25: Layout of DAC 1 drivers and DAC 1
0
0
0
x
0
0
0
x
0
0
0
x
0
0
0
0
x
0
0
x
0
x
0
x
0
x
0
0
x
0
Figure 5-26: Layout of NMOS mirrors in the current copier circuit
97
X
0
0
X
X
0
0
0
0
0
X X
0
0
X
0
0
0
X X
0
0
0
0
X
0
0
X
X
0
98
Chapter 6
Prototype Characterization
This section shows measurement results from the actual prototype. To optimize the
performance fully, quantizer offset calibration is done before the measurement. In the
quantizer offset calibration mode, two pins for the positive and negative inputs of the
modulator are connected to the two quantizer inputs directly and two loop filters are
disabled. Next, DC input signals are applied to the pins. The DC values are the same
as one set of the reference voltages from the resistor ladder. Then, one of comparators
PCB
Chip
65
Balun
A-M
8
4
D
D2
l6
OU3
fs=1.8GHz
9
'a
fs/2
128
32
28
161
6-Lon
fs/8
fs/32
6
fs/32
56
0
56
fs/64
egister
Banks
7.2GHz CLIK
Input
Bandpass
Filter ICoupler
0
SPI
Buffers
181fHybrid00
4-12.4GHz
Signal Source
81150A
Clock Source
83752A
Figure 6-1: Measurement setup
99
Logic Analyzer
16902A
in the quantizer has the same input and reference voltages. Due to this comparator, if
there is no quantizer offset, the quantizer output toggles between two adjacent digital
values during the transient simulation. The averaged quantizer output becomes very
close to the digital value corresponding to the reference voltage from the resistor
ladder. However, if there is a quantizer offset, a discrepancy between the averaged
quantizer output and the reference voltage exists. This discrepancy can be reduced
by using the 3-bit calibration code explained in Section 5.1.3. Each comparator in the
quantizer is calibrated with different DC inputs step by step. After the calibration, the
chip is ready to be characterized. There is no manual calibration process for DACs,
since they are automatically calibrated by analog background calibration using the
current copiers.
6.1
Test Environment
Figure 6-1 shows the measurement setup to characterize the test chip. Inside the chip,
two thermometer output codes (D 1 and D 2 ) from the two quantizers are encoded to
4-bit and 3-bit binary outputs. The output rates are reduced by 32 through three
serial-to-parallel blocks to store 224-bit outputs on an SRAM. Finally, the SRAM data
are send out through a logic analyzer (Agilent 16902A). A single-ended input signal
Table 6.1: Package information
Package Type
Body Size
Die Size
Via/Via Land Diameter
Number of Solder Balls
Die Thickness
Wire Loop Height
Solder Ball Diameter
Solder Ball Height
PBGA
15x15mm 2
3.094x2.014mm 2
200/300um
300
330um
0.7/0.8 x 10-3inch(Pd-Cu) /0.8 x 10- 3 inch (Au)
170um/370um
275um
210um
Distance to PCB
6x 10-3inch
Wire Diameter
100
is generated from the signal source (Agilent 81150A) through bandpass filters (TTE).
The balun (Coilcraft WB2010-SML) on the printed circuit board (PCB) converts
this signal to differential signals for the modulator. An external 1800 hybrid coupler
(Krytar 4040124) converts a single-ended 7.2GHz clock signal from the clock source
(hp 83752A) to differential clock signals.
Inside the chip, these differential clock
signals are converted to a single-ended signal again by a clock buffer. After that, this
clock signal is divided by 2 and 4 on chip to generate all the required clock phases.
Since the clock frequency is high, extensive simulations with a package model were
necessary to verify the performance. The signal nets from the bond pads to the solder
balls on the PCB were modeled by the high frequency structural simulator (HFSS).
Through the HFSS, s-parameters were extracted and could be included in Cadence to
run simulations. First, whether differential 7.2GHz clock signals can be delivered to
the clock buffer without significant attenuation was checked. Also, the ripples on the
power supply lines with this model were checked. Finally, the overall performance of
the modulator was verified. Table 6.1 shows the package information.
Figure 6-2 shows the PCB for the measurement. A single-ended input signal is
connected to one of two sub-miniature version A (SMA) connectors. One is connected
to the balun and the other is connected to the differential amplifier (ADL5565) on
the PCB. The differential amplifier is used for DC inputs to calibrate the quantizer
at the beginning of the measurement. 7.2GHz differential clock inputs are directly
connected to the chip. The data from the SRAM are read out through output buffers
and a logic analyzer. A PC communicates with the chip through a serial peripheral
interface (SPI). A 26MHz auxiliary clock is used for an SPI. All power supplies for
the chip come from low-dropout (LDO) regulators. Also, each LDO regulator has
its own jumper to be able to use an external power supply instead.
Each LDO
regulator output has a decoupling capacitor greater than luF. The PCB is powered
by a 12V/2A adapter. Figure 6-3 shows the measurement rack.
101
Figure 6-2: PCB for the measurement
Figure 6-3: Test environment
102
0
Without Calibration
:
--+--
-
-
---
------------------
--o
SFDR: 57.2dBc
With Calibration
-40 ---- SNDR: 74.9dB
SFDR: 89.3dBc
HD2: -92.4dBFS
-60
HD: -94.8dBFS
HD4: -92.5dBFS
-
SNDR: 53.3dB
-20
-80
-----.---.
..
2-100
-120
- ------- -:1
-140 5
IC
J
106
10 F
Frequency(Hz)
~
108
10
Figure 6-4: Measured 16384-point FFT spectrum with a -3.1dBFS input signal at
5.93MHz
6.2
SNR, SNDR, and SFDR
Experimental data are obtained using a 1.3V external power supply for all blocks except the outer DACs, instead of 1.2V, in order to avoid occasional quantizer metastability and an insufficient headroom encountered during testing. The DACs are powered from an external 1.5V as designed.
The measured 16384-point fast Fourier
transform (FFT) spectra with and without the analog background DAC calibration
is shown in Figure 6-4 with a -3.1dBFS input at 5.93MHz. After the DAC calibration, the SNDR and the spurious-free dynamic range (SFDR) are improved by 21.6dB
and 32.1dBc, respectively. Within the signal bandwidth, the harmonics are well suppressed by the background DAC calibration, providing SFDR of 89.3dBc dominated
by the second harmonic.
Figure 6-5 shows the SNR and SNDR vs. input amplitude at 5.93MHz. A peak
SNDR of 74.9dB and SNR of 76.8dB at -3.1dBFS and -0.5dBFS, respectively, as
well as a DR of 85dB are achieved, corresponding to Schreier and Walden FOMs of
172.9dB and 177fJ/step, respectively.
103
80
SN R
7 0 -- --O-SNDR
------------- ---------------------------- ---------------------
-------------
--------------------------6 0 ----------------------------------------- ------------- ---------- j-------------- ------ --------------10-%
5 0 ------------- ------------- ------------- -------------------------- ----- ----------------- -------------- ------------
z
--------------------------- -------------- -----------40 ------------- ............. ------------- ------------- ----- .....
-
%.00
ca
z
CO)
------------------- ------------- ------------- ---------------------------3 0 ------------- ------------- ------------- -----
Peak SNDR: 74.9dB
------------------------------2 0 -------------
-3.1dBFS
Peak SNR: 76.8dB (a)-0.5dBFS
1 0 ---------------------------------------------------------------------------------------------------------DR::85dB
-80
-70
-60
-50
-40
-30
Input Amplitude (dBFS)
-20
-10
0
Figure 6-5: Measured SNR/SNDR based on different input amplitudes
80
30MHz
------------ ------------- ------------- ------------Hz
-0-40M
70
50M Hz
--------------I--------60 ------------------------------------------------------------------------------50 ------------- ------------- ------------- I
--------------- ------ --------------------------------- ------------
z
0)
--------------------------- ------------
-
40 ------------- ------------- ------------- ------ ----- r
30 ------------- ------------- ------- ------------------- -------------- ------------- ------------- -----------20 ------------- ------ ---------
-------------- ------------- --------------------------- ------------
10 ------ ----- ------------- ------------- I--------------- ------------- ------------- ------------- -----------0
-70
-60
-50
-40
-30
-20
-10
Input Amplitude (dBFS)
Figur e 6-6: Measured SNDR results at 30, 40 and 50MHz
104
0
0
....
........
...-.
. --L:I.1
-20-
W
-91.5dBFS 0 46MHz
-89.4dBFS @ 29MHz.-91.9dBFS 17MHz @
-102.2dBFS @ 4MHz
IMD = 83.1dBc
-=-8dBc
IMD 3
-00
0- - ------ --
--- --
--
--
- -
----
---L ------
-
--
----
-100
-1 20
-- + -
-.+
-- ---
-- ..
------
--------
---
--
10
107
Frequency (Hz)
108
(a)
..................----------
- - -------------------
-90.6dBFS 0 29MHz
-89.5dBFS @17.5MHz
0 11.5MHz@
-40
CO -0-90.5dBFS
-104.8dBFS @ 2MHz
-.-.-.-.---
-2 0
-60
-
82.2d-c
IMD2 = 82.2dBc
3
--
-
--- --
-
..".....I-----...I...1--
=81.ldBc
-
-
-
0
....
-1 0 0----------
.
80
-120
10
10
108
Frequency (Hz)
(b)
Figure 6-7:
Measured two tone test results with -8.4dBFS inputs:
(a) at 21 and
25MHz, (b) at 13.5 and 15.5MHz
Figure 6-6 shows the measured SNDR vs. input amplitude at input frequencies
of 30, 40, and 50MHz.
At high input frequencies, it was discovered that the first
integrator had an insufficient headroom. Increasing the power supply voltage to 1.3V,
as previously indicated, improved the headroom slightly. However, the peak SNDR
reduction at high input frequencies is still present. This was the result of an oversight
105
in the design of not observing the first integrator output at high frequencies, and can
be easily addressed by proper scaling. Peak SNDRs of 74.1, 73.5, and 71.4dB, are
achieved at 30, 40, and 50MHz respectively.
6.3
Intermodulation Distortion
Figure 6-7 shows two tone test results. In Figure 6-7(a), with -8.4dBFS inputs at 21
and 25MHz, the second and third intermodulation distortions (IMD 2 and IMD 3 ) of
83.1 and 81dBc are achieved, respectively. In Figure 6-7(b), with -8.4dBFS inputs at
13.5 and 15.5MHz, IMD 2 and IMD 3 of 82.2 and 81.1dBc are demonstrated, respectively. Similar results were achieved, at different input frequencies, within the signal
bandwidth.
6.4
Signal Transfer Function
10
........ ---------------
..........
-15
--I--.......
-20 ------10
I
]------10
Frequency (Hz)
10
10
Figure 6-8: Measured STF
The measured STF is shown in Figure 6-8. There are out-of-band peaks at 127
and 425MHz.
The second peak of 6dB is larger than the first peak of 3.6dB. As
discussed before, the maximum peak is smaller than the peak in a CT single-loop
feedforward 4th-order modulator, which is generally greater than 10dB for the SQNR
of 100dB. Also, the maximum peak is located at a much higher frequency compared
106
to the signal bandwidth, 50MHz, which makes it easier to suppress.
Figure 6-9: Power breakdown
6.5
Power Consumption
Figure 6-9 shows the power breakdown of the CT 3-1 SMASH AE modulator. There
are five different power supply lines on the actual chip: the loop filter, quantizers,
DACs, DAC drivers and clock buffers. The clock generator, buffers, and DAC drivers
consume 34% of the total power. This is because the distance from the clock generator
to the modulator is on average 600um as shown in Figure 5-18. Thus, a large number
of strong buffers are required to make rising and falling edges very sharp in order
to reduce noise due to jitter. For the same reason, the latches in the DAC drivers
consume a large amount of power. This power portion can be reduced significantly
107
Table 6.2: Comparison with sate-of-the-art;>50MHz CT AE modulators
Process (nm)
fs (GHz)
BW (MHz)
DR (dB)
Peak SNR (dB)
Peak SNDR (dB)
Power (mW)
Area (mm2 )
FOM1 (dB)
FOM 2 (fJ/step)
This work
28
1.8
50
85
76.8
74.9
80.4
0.34
172.9
177
[3]
45
4
125
70
65.5
65
256
0.9
156.9
704.7
[6]
65
4
75
79
N/A
N/A
750
5.5
159
N/A
[7]
45
6
60
65
61.5
60.6
20
0.49
159.8
190.4
[11]
28
3.2
53
88
83.1
71.4
235
0.9
171.6
726
[17]
20
2.184
80
73
70
67.5
23
0.1
168.4
74.2
with a better floor plan and optimized design without strong clock buffers and DAC
drivers.
6.6
Comparison
Table 6.2 compares this work to the previous state-of-the-art CT AE modulators
with signal bandwidths 50MHz or greater. FOM1 and FOM 2 are Schreier and Walden
FOMs, respectively, defined as:
FOM = DR + 10logio(BW/P)
FOM2 = P/(2. BW - 2 (SNDR-1.76)/6.02)
(6.1)
(6.2)
This work was implemented in a 28nm LP process. The achieved signal bandwidth is
50MHz at a 1.8GHz sampling frequency. The peak SNR and SNDR of this modulator
are 76.8dB and 74.9dB, respectively. The measured DR is 85dB. The achieved Schreier
and Walden FOMs are 172.9dB and 177fJ/step, respectively. The SFDR comparison
is not shown in this table, because many publications do not report their SFDR
numbers. However, based on the reported FFT spectra from the previous works,
none of these works achieved the SFDR of 89.3dBc. This work achieves the best
108
Schreier FOM, peak SNDR and SFDR with the lowest sampling frequency.
109
110
Chapter 7
Conclusions
7.1
Thesis Contribution
This dissertation has investigated the design of wide-band, high-resolution, and powerefficient CT AE modulators for modern wireless applications. There are two main
key contributions of this thesis
The first contribution is to investigate and implement the architecture of the CT
3-1 SMASH AE modulator. Although the DT SMASH architecture achieves a decent
noise-shaping capability, it has a limited signal bandwidth due to the inherent sampling frequency limitation of the DT implementation. The CT SMASH architecture
provides a much higher signal bandwidth for given UGBWs of opamps as well as
relaxed anti-assailing requirements. As a result, the signal bandwidth of 50MHz is
achieved, which is 80 times wider than that of the DT SMASH AE modulator [18].
Moreover, with the wider signal bandwidth, the CT SMASH architecture provides
an enhanced SQNR. Unlike a normal CT MASH architecture, the quantization noise
leakage from the Is'-loop is no longer a bottleneck, since digital filters matched to
analog transfer functions are not required for in-band quantization noise cancellation.
In addition, the CT SMASH architecture cancels the in-band quantization from the
l"-loop. Furthermore, when the feedforward loop filter is used for the 1 -loop due for
power efficiency, the CT 3-1 SMASH architecture has benefits compared with the 4
h-
order single-loop feedforward architecture. Since the 3rd-order feedforward loop filter
111
is on the signal path of the CT 3-1 SMASH architecture, the out-of-band STF peak
is lower than the peak from the 4th-order single-loop feedforward architecture. Also,
a larger input is allowable for the CT 3-1 SMASH architecture compared with the
single-loop 4th-order feedforward architecture.
This thesis identifies two challenges
from the implementation of the CT 3-1 SMASH architecture and solutions to them.
For the extraction of the quantization noise from the 1It-loop, the CT input signal
of the quantizer is delayed by a simple LPF instead of a fast and accurate S/H circuit. Unlike the previous DT SMASH architecture, the in-band STF of the
2
"d-loop
is made approximately delay-less unity-gain to cancel the in-band quantization noise
from the
1 St-loop.
The second contribution is to present several circuit techniques which enable the
CT 3-1 SMASH AE modulator to achieve the requirements for modern wireless applications.
The lead path on the first integrator through existing outer feedback
DACs compensates the ELD and removes the additional DACs, which require more
power consumption, area, and complicated clock routing paths. The new frequency
compensation technique for opamps is also presented to maximize the GBWs of RC
integrators with sufficient PMs and low power. Also, an OTA with the embedded
LPF is used to delay the CT input signal of the quantizer, to simplify the circuitry,
and to avoid loading of the quantizer input signal. A tri-level current steering topology is employed to reduce the number of DAC cells. To generate the tri-level codes
and drive DACs, proper designs of quantizers, tri-level encoders and DAC drivers are
presented. Finally, four DACs with different types of switches are shown. In order to
improve the linearity of outer feedback DACs, a current copier technique is employed
as an analog background calibration. As a result, the prototype fabricated in 28nm
CMOS achieves DR of 85dB, peak SNDR of 74.9dB, SFDR of 89.3dBc and Schreier
FOM of 172.9dB over a 50MHz bandwidth at a 1.8GHz sampling frequency, which
represents the best peak SNDR, SFDR, and Schreier FOM at the lowest sampling
frequency.
112
7.2
Future Work
Although the prototype implemented in this thesis has shown excellent results, there
are still many opportunities for improvements.
In this thesis, aggressive quantization noise suppression is achieved for a DR 85dB
or higher. The target SQNR was 100dB. The final resolution is determined by quantization noise, thermal noise, jitter noise, and distortion from the circuits.
In this
work, the main strategy was to allow higher thermal noise, jitter noise, and distortion from the circuits by reducing quantization noise aggressively. However, through
the accurate noise and power budget allocation, it may be possible that less aggressive quantization noise suppression can achieve desired resolution while using a lower
sampling frequency and Hinf, resulting in less power consumption and better stability.
The NTFs from the cascaded architectures such as the SMASH architecture are
worthy of further research. Unlike the NTFs from single-loop AE modulators, the
NTFs from the cascaded architectures have more freedom to choose the pole and zero
locations. This freedom may provide benefits from NTFs with more optimized pole
and zero locations, beyond the stability advantage from low-order local loop filters.
The analog delay implementation using an LPF can be utilized for other applications, if the target delay is much smaller than the reciprocal of the signal frequency.
From the post-layout simulations, a peak SNR of 80dB was achieved. However,
the measured peak SNR is 76.8dB. The 3.2dB degradation may be the result of the
non-linearity of the OTA. Since the OTA receives a large signal when the input of the
2nd-loop is large, the linearity of the OTA becomes poor. Therefore, a new approach
to extract the quantization noise from the 1"t-loop may improve the peak SNR.
In this prototype, the size of the current copier circuits for NMOS and PMOS is
not small as shown in Figure 5-18. This is because the mirror transistors are scaled
to achieve a 2:1 ratio with 10-bit accuracy between DAC 1 and DAC 1' which have
different unit cells. This issue can be addressed if an identical DAC unit cell is used
for DAC 1 and DAC 1'.
If two identical DAC unit cells are combined as one cell for
DAC 1 , then one global current reference can be used for current copier circuits of
113
both DACs. Therefore, the mirror matching issue disappears and the layout size can
shrink.
Finally, the total power consumption may be reduced significantly. As shown in
Figure 5-18, due to the sub-optimal floor plan, the routing distances between core
digital blocks are long. Therefore, a large number of strong buffers are required to
make rising and falling edges very sharp to reduce noise due to jitter. These buffers,
especially from the clock generator to digital blocks, can be removed with a more
compact floor plan. Moreover, based on further analysis and simulations, it may be
possible to relax the rise and fall times of the buffers and the DAC drivers, without
suffering increased noise due to jitter. If the requirements of rising and falling times
are relaxed, power can be saved further.
114
Bibliography
[1] G. Mitteregger, C. Ebner, S. Mechnig, T. Blon, C. Holuigue, and E. Romani,
"A 20-mW 640-MHz CMOS Continuous-Time EA ADC With 20-MHz Signal
Bandwidth, 80-dB Dynamic Range and 12-bit ENOB," IEEE Journal of SolidState Circuits, vol. 41, no. 12, pp. 2641-2649, Dec. 2006.
[2] W. Yang, W. Schofield, H. Shibata, S. Korrapati, A. Shaikh, N. Abaskharoun,
and D. Ribner, "A 100mW 1OMHz-BW CT AE Modulator with 87dB DR and
91dBc IMD," in IEEE International Solid-State Circuits Conference Digest of
Technical Papers, pp. 498-631, Feb 2008.
[3] M. Bolatkale, L. Breems, R. Rutten, and K. Makinwa, "A 4 GHz ContinuousTime AE ADC With 70 dB DR and -74 dBFS THD in 125 MHz BW," IEEE
Journal of Solid-State Circuits, vol. 46, no. 12, pp. 2857-2868, Dec. 2011.
[4] P. Witte and M. Ortmanns, "Background DAC Error Estimation Using a Pseudo
Random Noise Based Correlation Technique for Sigma-Delta Analog-to-Digital
Converters," IEEE Transactions on Circuits and Systems I: Regular Papers,
vol. 57, pp. 1500-1512, July 2010.
[5] P. Shettigar and S. Pavan, "A 15mW 3.6GS/s CT-AE ADC with 36MHz bandwidth and 83dB DR in 90nm CMOS," IEEE Journal of Solid-State Circuits,
pp. 156-158, Feb. 2012.
[6] H. Shibata, R. Schreier, W. Yang, A. Shaikh, D. Paterson, T. Caldwell, D. Alldred, and P. W. Lai, "A DC-to-1 GHz Tunable RF AE ADC Achieving DR=74
dB and BW=150 MHz at f0=450 MHz Using 550 mW," IEEE Journal of SolidState Circuits, vol. 47, pp. 2888-2897, Dec 2012.
[7] V. Srinivasan, V. Wang, P. Satarzadeh, B. Haroun, and M. Corsi, "A 20mW
61dB SNDR (60MHz BW) lb 3rd-order continuous-time delta-sigma modulator
clocked at 6GHz in 45nm CMOS," in IEEE International Solid-State Circuits
Conference Digest of Technical Papers, pp. 158-160, Feb 2012.
[8] Y.-S. Shu, J.-Y. Tsai, P. Chen, T.-Y. Lo, and P.-C. Chiu, "A 28fJ/conv-step
CT AE modulator with 78dB DR and 18MHz BW in 28nm CMOS using a
highly digital multibit quantizer," in IEEE International Solid-State Circuits
Conference Digest of Technical Papers, pp. 268-269, Feb 2013.
115
[9] T. Caldwell, D. Alldred, and Z. Li, "A Reconfigurable AE ADC With Up to
100 MHz Bandwidth Using Flash Reference Shuffling," IEEE Transactions on
Circuits and Systems I: Regular Papers, vol. 61, pp. 2263-2271, Aug 2014.
[10] R. Rajan and S. Pavan, "Design Techniques for Continuous-Time AE Modulators
With Embedded Active Filtering," IEEE Journalof Solid-State Circuits, vol. 49,
pp. 2187-2198, Oct 2014.
[11] Y. Dong, W. Yang, R. Schreier, A. Sheikholeslami, and S. Korrapati, "A
Continuous-Time 0-3 MASH ADC Achieving 88 dB DR With 53 MHz BW in 28
nm CMOS," IEEE Journal of Solid-State Circuits, vol. 49, pp. 2868-2877, Dec
2014.
[12] D.-Y. Yoon, S. Ho, and H.-S. Lee, "15.1 An 85dB-DR 74.6dB-SNDR 50MHZ-BW
CT MASH AE modulator in 28nm CMOS," in IEEE International Solid-State
Circuits Conference Digest of Technical Papers, pp. 272-273, Feb 2015.
[13] C. Cutler, "Transmission System Employing Quantization," U.S. Patent No. 2
927 962, 1960.
[14] H. Inose, Y. Yasuda, and J. Murakami, "A Telemetering System by Code Modulation -A -E modulator," IRE Transactions on Space Electronics and Telemetry,
vol. SET-8, no. 3, pp. 204-209, Sept. 1962.
[15] X. Chen, Y. Wang, Y. Fujimoto, P. Lo Re, Y. Kanazawa, J. Steensgaard, and
G. Temes, "A 18 mW CT AE modulator with 25 MHz bandwidth for next generation wireless applications," in IEEE Custom Integrated Circuits Conference,
pp. 73-76, Sept 2007.
[16] B. Murmann, "ADC Performance Survey 1997-2014,"
http://www.stanford. edu/ murmann/adcsurvey.html.
[Online]. Available:
[17] S. Ho, C.-L. Lo, J. Ru, and J. Zhao, "A 23 mW, 73 dB Dynamic Range, 80 MHz
BW Continuous-Time Delta-Sigma Modulator in 20 nm CMOS," IEEE Journal
of Solid-State Circuits, vol. 50, pp. 908-919, April 2015.
[18] N. Maghari, S. Kwon, and U.-K. Moon, "74 dB SNDR Multi-Loop Sturdy-MASH
Delta-Sigma Modulator Using 35 dB Open-Loop Opamp Gain," IEEE Journal
of Solid-State Circuits, vol. 44, no. 8, pp. 2212-2221, Aug. 2009.
[19] W. Bennett, "Spectra of quantized signals," Bell Syst. Tech. J., vol. 27, pp. 446472, Jul. 2008.
[20] B. Widrow, "A Study of Rough Amplitude Quantization by Means of Nyquist
Sampling Theory," IRE Transactions on Circuit Theory, vol. 3, no. 4, pp. 266276, Dec. 1956.
116
[21] A. Sripad and D. Snyder, "A necessary and sufficient condition for quantization
errors to be uniform and white," IEEE Transactions on Acoustics, Speech and
Signal Processing, vol. 25, no. 5, pp. 442-448, Oct. 1977.
[22] R. Gray, "Quantization noise spectra," IEEE Transactions on Information Theory, vol. 36, no. 6, pp. 1220-1244, Nov. 1990.
[231 Y. Tsividis, "Integrated continuous-time filter design - an overview," IEEE Journal of Solid-State Circuits, vol. 29, pp. 166-176, Mar 1994.
[241 J. de la Rosa, "Sigma-Delta Modulators: Tutorial Overview, Design Guide, and
State-of-the-Art Survey," IEEE Transactions on Circuits and Systems I: Regular
Papers, vol. 58, pp. 1-21, Jan 2011.
[251 R. van Veldhoven, "A tri-mode continuous-time EA modulator with switchedcapacitor feedback DAC for a GSM-EDGE/CDMA2000/UMTS receiver," in
IEEE International Solid-State Circuits Conference Digest of Technical Papers,
pp. 60-477, Feb 2003.
[261 L. Breems, R. Rutten, R. van Veldhoven, and G. van der Weide, "A 56 mW
Continuous-Time Quadrature Cascaded EA Modulator With 77 dB DR in a
Near Zero-IF 20 MHz Band," IEEE Journal of Solid-State Circuits, vol. 42,
no. 12, pp. 2696-2750, Dec. 2007.
[27] S. Ouzounov, R. van Veldhoven, C. Bastiaansen, K. Vongehr, R. van Wegberg,
G. Geelen, L. Breems, and A. van Roermund, "A 1.2V 121-Mode CT AE Modulator for Wireless Receivers in 90nm CMOS," in IEEE InternationalSolid-State
Circuits Conference Digest of Technical Papers, pp. 242-243, Feb 2007.
[28] S.-J. Huang and Y.-Y. Lin, "A 1.2V 2MHz BW 0.084mm2 CT AE ADC with
-97.7dBc THD and 80dB DR using low-latency DEM," in IEEE International
Solid-State Circuits Conference Digest of Technical Papers, pp. 172-173, Feb
2009.
[29]
K. Reddy and S. Pavan, "A 20.7mW continuous-time AE modulator with 15MHz
bandwidth and 70 dB dynamic range," in IEEE European Solid State Circuits
Conference, pp. 210-213, Sept. 2008.
[30] M. Park and M. Perrott, "A 78 dB SNDR 87 mW 20 MHz Bandwidth ContinuousTime AE ADC With VCO-Based Integrator and Quantizer Implemented in 0.13
um CMOS," IEEE Journal of Solid-State Circuits, vol. 44, pp. 3344-3358, Dec
2009.
[31]
J. Kauffman, P. Witte, J. Becker, and M. Ortmanns, "An 8.5 mW ContinuousTime AE Modulator With 25 MHz Bandwidth Using Digital Background DAC
Linearization to Achieve 63.5 dB SNDR and 81 dB SFDR," IEEE Journal of
Solid-State Circuits, vol. 46, pp. 2869-2881, Dec 2011.
117
[32] H. Chae, J. Jeong, G. Manganaro, and M. Flynn, "A 12mW low-power
continuous-time bandpass AE modulator with 58dB SNDR and 24MHz bandwidth at 200MHz IF," in IEEE International Solid-State Circuits Conference
Digest of Technical Papers, pp. 148-150, Feb 2012.
1331
K. Reddy, S. Rao, R. Inti, B. Young, A. Elshazly, M. Talegaonkar, and P. Hanumolu, "A 16-mW 78-dB SNDR 10-MHz BW CT AE ADC Using ResidueCancelling VCO-Based Quantizer," IEEE Journal of Solid-State Circuits, vol. 47,
pp. 2916-2927, Dec 2012.
[34] P. Witte, J. Kauffman, J. Becker, Y. Manoli, and M. Ortmanns, "A 72dB-DR AE
CT modulator using digitally estimated auxiliary DAC linearization achieving
88fJ/conv in a 25MHz BW," in IEEE InternationalSolid-State Circuits Conference Digest of Technical Papers, pp. 154-156, Feb 2012.
[351 C.-Y. Ho, C. Liu, C.-L. Lo, H.-C. Tsai, T.-C. Wang, and Y.-H. Lin, "15.2 A
4.5mW CT self-coupled AE modulator with 2.2MHz BW and 90.4dB SNDR
using residual ELD compensation," in IEEE International Solid-State Circuits
Conference Digest of Technical Papers, pp. 274-275, Feb 2015.
[36] 0. Shoaei, "Continuous-time delta-sigma A/D converters for high speed applications," Ph.D. dissertation, Carleton Univ., Ottawa, ON, 1995.
[37] R. Schreier and G. C. Temes, "Understanding Delta-Sigma Data Converters,"
New York: Wiley, 2004.
[38] E. vanderZwan and E. Dijkmans, "A 0.2-mW CMOS EA modulator for speech
coding with 80 dB dynamic range," IEEE Journal of Solid-State Circuits, vol. 31,
pp. 1873-1880, Dec 1996.
[39] S. Kulchycki, R. Trofin, K. Vleugels, and B. Wooley, "A 77-dB Dynamic Range,
7.5-MHz Hybrid Continuous-Time/Discrete-Time Cascaded EA Modulator,"
IEEE Journal of Solid-State Circuits, vol. 43, no. 4, pp. 796-804, Apr. 2008.
[40] J. Cherry and W. Snelgrove, "Excess loop delay in continuous-time delta-sigma
modulators," IEEE Transactions on Circuits and Systems II: Analog and Digital
Signal Processing, vol. 46, no. 4, pp. 376-389, Apr. 1999.
[41] M. Ortmanns, F. Gerfers, and Y. Manoli, "Compensation of finite gainbandwidth induced errors in continuous-time sigma-delta modulators," IEEE
Transactions on Circuits and Systems I: Regular Papers, vol. 51, pp. 1088-1099,
June 2004.
[42] M. Keller, A. Buhmann, J. Sauerbrey, M. Ortmanns, and Y. Manoli, "A Comparative Study on Excess-Loop-Delay Compensation Techniques for ContinuousTime Sigma-Delta Modulators," IEEE Transactions on Circuits and Systems I:
Regular Papers, vol. 55, no. 11, pp. 3480-3487, Dec. 2008.
118
[43]
S. Yan and E. Sanchez-Sinencio, "A continuous-time sigma-delta modulator with
88-dB dynamic range and 1.1-MHz signal bandwidth," IEEE Journal of SolidState Circuits, vol. 39, no. 1, pp. 75-86, Jan. 2004.
[44] J. Cherry and W. Snelgrove, "Clock jitter and quantizer metastability in
continuous-time delta-sigma modulators," IEEE Transactions on Circuits and
Systems II: Analog and Digital Signal Processing, vol. 46, no. 6, pp. 661-676,
Jun. 1999.
[45]
D. Groeneveld, H. Schouwenaars, H. Termeer, and C. Bastiaansen, "A selfcalibration technique for monolithic high-resolution D/A converters," IEEE
Journal of Solid-State Circuits, vol. 24, pp. 1517-1522, Dec 1989.
[46] X. Wang, U. Moon, M. Liu, and G. Temes, "Digital correlation technique for
the estimation and correction of DAC errors in multibit mash AE ADCs," IEEE
International Symposium on Circuits and Systems, vol. 4, pp. IV-691-IV-694
vol.4, 2002.
[47] M. Ortmanns and F. Gerfers, "Continuous-Time Sigma-Delta A/D Conversion:
Fundamentals, Performance Limits and Robust Implementations," New York:
Springer, 2006.
[48] Y. Geerts, M. Steyaert, and W. Sansen, "Design of Multi-Bit Delta-Sigma A/D
Converters," Norwell, MA: Kluwer, 2002.
[49] J. Cherry and W. Snelgrove, "Continuous-Time Delta-Sigma Modulators for
High-Speed A/D Conversion," Norwell, MA: Kluwer, 2000.
[50] R. S. S. R. Norsworthy and G. C. Temes Delta-Sigma Data Converters: Theory,
Design, and Simulation., vol. Wiley-IEEE Press, 1997.
[51] R. Schreier, "The Delta-Sigma Toolbox Version 7.3," [Onlinej. Available:
http://www.mathworks.com/matlabcentral/fileexchange/19.html.,2000.
[52]
A. Thurston, T. Pearce, and M. Hawksford, "Bandpass implementation of the
sigma-delta A-D conversion technique," in International Conference on Analogue
to Digital and Digital to Analogue Conversion, pp. 81-86, Sep 1991.
[53] 0. Shoaei, "Continuous-time delta-sigma A/D converters for high speed applications," Ph.D. dissertation, Carleton Univ., Ottawa, Canada, 1996.
[54] F. M. Gardner, "A Transformation for Digital Simulation of Analog Filters,"
IEEE Transactions on Communications, vol. 34, pp. 676-680, Jul 1986.
[55] S. Pavan, "Systematic Design Centering of Continuous Time Oversampling Converters," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 57,
pp. 158-162, March 2010.
119
[56] R. Adams and R. Schreier, "Stability theory in EA modulators," in DeltaSigma Data Converters: Theory, Design and Simulation, S. R. Norsworthy, R.
Schreier, and G. C. Temes, Eds. :IEEE Press, 1997, ch. 4.
[57] K.-H. Chao, S. Nadeem, W. Lee, and C. Sodini, "A higher order topology for
interpolative modulators for oversampling A/D converters," IEEE Transactions
on Circuits and Systems, vol. 37, pp. 309-318, Mar 1990.
[58] M. Hovin, A. Olsen, T. Lande, and C. Toumazou, "Delta-sigma modulators using
frequency-modulated intermediate values," IEEE Journalof Solid-State Circuits,
vol. 32, pp. 13-22, Jan 1997.
[59] A. Iwata, N. Sakimura, M. Nagata, and T. Morie, "The architecture of delta
sigma analog-to-digital converters using a voltage-controlled oscillator as a multibit quantizer," IEEE Transactionson Circuits and Systems II: Analog and Digital
Signal Processing, vol. 46, pp. 941-945, Jul 1999.
[60] K. Lee, J. Chae, M. Aniya, K. Hamashita, K. Takasuka, S. Takeuchi, and
G. Temes, "A Noise-Coupled Time-Interleaved Delta-Sigma ADC With 4.2 MHz
Bandwidth, 98 dB THD, and 79 dB SNDR ," IEEE Journal of Solid-State Circuits, vol. 43, no. 3, pp. 204-209, Dec. 2008.
[61] K. Matsukawa, K. Obata, Y. Mitani, and S. Dosho, "A 10 MHz BW 50 fJ/conv.
continuous time AE modulator with high-order single opamp integrator using
optimization-based design method," in Symposium on VLSI Circuits, pp. 160161, June 2012.
[62] T. Hayashi, Y. Inabe, K. Uchimura, and T. Kimura, "A multistage delta-sigma
modulator without double integration loop," in IEEE International Solid-State
Circuits Conference Digest, of Technical Papers, vol. XXIX, pp. 182-183, Feb.
1986.
[631 Y. Matsuya, K. Uchimura, A. Iwata, T. Kobayashi, M. Ishikawa, and
T. Yoshitome, "A 16-bit oversampling A-to-D conversion technology using tripleintegration noise shaping," IEEE Journal of Solid-State Circuits, vol. 22, no. 6,
pp. 921-929, Dec. 1987.
[641 Y.-S. Shu, J. Kamiishi, K. Tomioka, K. Hamashita, and B.-S. Song, "LMS-Based
Noise Leakage Calibration of Cascaded Continuous-Time AE Modulators," IEEE
Journal of Solid-State Circuits, vol. 45, no. 2, pp. 368-379, Feb. 2010.
[651 J. Sauerbrey, J. Garcia, G. Panov, T. Piorek, X. Shen, M. Schimper, R. Koch,
M. Keller, Y. Manoli, and M. Ortmanns, "A configurable cascaded continuoustime AE modulator with up to 15MHz bandwidth," in IEEE European Solid
State Circuits Conference, pp. 426-429, Sept. 2010.
[66] L. Breems, R. Rutten, and G. Wetzker, "A cascaded continuous-time EA Modulator with 67-dB dynamic range in 10-MHz bandwidth," IEEE Journal of SolidState Circuits, vol. 39, no. 12, pp. 2152-2160, Dec. 2004.
120
[67] L. Breems and J. Huijsing, "Continuous-Time Sigma-Delta Modulation for A/D
Conversion in Radio Receivers," Norwell, MA: Kluwer, 2001.
[68] V. Dhanasekaran, M. Gambhir, M. Elsayed, E. Sanchez-Sinencio, J. SilvaMartinez, C. Mishra, L. Chen, and E. Pankratz, "A 20MHz BW 68dB DR CT
AE ADC based on a multi-bit time-domain quantizer and feedback element," in
IEEE InternationalSolid-State Circuits Conference Digest of Technical Papers,
pp. 174-175, Feb 2009.
[69] W. Gao, 0. Shoaei, and W. Snelgrove, "Excess loop delay effects in continuoustime delta-sigma modulators and the compensation solution," in IEEE International Symposium on Circuits and Systems, vol. 1, pp. 65-68, Jun 1997.
[70] K. Nguyen, A. Bandyopadhyay, B. Adams, K. Sweetland, and P. Baginski, "A
108dB SNR 1.1mW Oversampling Audio DAC with a Three-Level DEM Technique," in IEEE InternationalSolid-State Circuits Conference Digest of Technical
Papers, pp. 488-630, Feb 2008.
[71] D. Y. Yoon, H.-S. Lee, and J. Gealow, "Power-efficient amplifier frequency compensation for continuous-time delta-sigma modulators," in IEEE International
Midwest Symposium on Circuits and Systems, pp. 562-565, Aug 2013.
172]
Y.-S. Shu, "A 6b 3GS/s 11mW fully dynamic flash ADC in 40nm CMOS with
reduced number of comparators," in Symposium on VLSI Circuits, pp. 26-27,
June 2012.
[73] D. Schinkel, E. Mensink, E. Klumperink, E. van Tuijl, and B. Nauta, "A
Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time,"
in IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 314-605, Feb 2007.
[74] B. Nikolic, V. G. Oklobdzija, V. Stojanovic, W. Jia, J. K.-S. Chiu, and M. MingTak Leung, "Improved sense-amplifier-based flip-flop: design and measurements," IEEE Journal ofSolid-State Circuits, vol. 35, pp. 876-884, June 2000.
121