TMB 2004 Design Table of Contents UCLA High Energy Physics Version 2.02

TMB 2004 Design UCLA High Energy Physics Version 2.02 June 10, 2004 Table of Contents CHANGES FROM TMB2001 ..................................................................................................................................................... 3 LIST OF FIGURES ..................................................................................................................................................................... 4 LIST OF TABLES....................................................................................................................................................................... 4 TMB OVERVIEW .................................................................................................................................................................... 5 CATHODE LCT ALGORITHM............................................................................................................................................. 6 CFEB Demultiplex ............................................................................................................................................................ 6 Triad Decode ..................................................................................................................................................................... 6 Layer Staggering................................................................................................................................................................ 6 DiStrip OR......................................................................................................................................................................... 6 Pattern Cell Envelope ........................................................................................................................................................ 6 Priority Enocoding............................................................................................................................................................. 6 DiStrip Patterns.................................................................................................................................................................. 6 DMB Active FEB Signal ................................................................................................................................................... 6 Best 2 LCTs ....................................................................................................................................................................... 6 CLCT Bend Patterns.......................................................................................................................................................... 7 Drift Delay ......................................................................................................................................................................... 7 CLCT Format..................................................................................................................................................................... 7 ALCT+CLCT MATCHING ALGORITHM .......................................................................................................................... 8 Matching Logic.................................................................................................................................................................. 8 LCT Duplication................................................................................................................................................................ 8 LCT Quality....................................................................................................................................................................... 8 MPC Format ...................................................................................................................................................................... 8 VME REGISTERS.................................................................................................................................................................... 9 Addressing Modes ............................................................................................................................................................. 9 Base Address ..................................................................................................................................................................... 9 Register Addresses........................................................................................................................................................... 10 Register Definitions ......................................................................................................................................................... 13 TTC Commands: ............................................................................................................................................................. 43 Embedded Logic Analyzer Scope Channels:................................................................................................................... 44 TMB BOARD STATUS OPERATIONS............................................................................................................................... 47 ID Registers ..................................................................................................................................................................... 47 Digital Serial Numbers .................................................................................................................................................... 47 Power Supply ADC ......................................................................................................................................................... 47 Clock Delays.................................................................................................................................................................... 47 RAT Module Status ......................................................................................................................................................... 48 JTAG Chains ................................................................................................................................................................... 48 DMB READOUT..................................................................................................................................................................... 49 Full-Readout and Local-Readout Format: ....................................................................................................................... 49 Long Header-only Format: .............................................................................................................................................. 50 Short Header-only Format: .............................................................................................................................................. 50 Header Word Descriptions: ............................................................................................................................................. 51 Sample TMB Raw Hits Dump:........................................................................................................................................ 58 TMB SIGNAL SUMMARY ................................................................................................................................................... 59 CCB ................................................................................................................................................................................. 59 Page 1 of 83 06/11/04 1:58 PM ALCT............................................................................................................................................................................... 60 DMB ................................................................................................................................................................................ 61 CFEB ............................................................................................................................................................................... 61 MPC................................................................................................................................................................................. 62 RPC.................................................................................................................................................................................. 63 VME ................................................................................................................................................................................ 63 JTAG ............................................................................................................................................................................... 63 LEDs................................................................................................................................................................................ 64 TMB Total I/O Count ...................................................................................................................................................... 65 TMB2001 CONNECTORS..................................................................................................................................................... 66 TMB Connector Summary............................................................................................................................................... 66 J0-J4 CFEB0-CFEB4 Connectors.................................................................................................................................... 67 J5 ALCT Cable1 Connector (Receiver)........................................................................................................................... 68 J6 ALCT Cable2 Connector (Transmitter) ...................................................................................................................... 69 J1-J6 SCSI-II 50-Pin Connector Pin Convention............................................................................................................. 70 J7 Xilinx LVDS Xilinx X-Blaster Connector .................................................................................................................. 71 P1 Backplane VME64x J1/P1 Connector ........................................................................................................................ 72 P2A Backplane CCB+DMB Connector........................................................................................................................... 73 P2A Backplane CCB+DMB Connector Continued ......................................................................................................... 74 P2B Backplane DMB Connector ..................................................................................................................................... 75 P3A Backplane MPC Connector ..................................................................................................................................... 76 P3B Backplane RPC+ALCT Connector .......................................................................................................................... 77 Backplane Pin Diagram ................................................................................................................................................... 78 Front Panel Connector Locations..................................................................................................................................... 79 PCB Shunts...................................................................................................................................................................... 80 CCB Front Panel.............................................................................................................................................................. 81 REVISION HISTORY............................................................................................................................................................ 83 Page 2 of 83 06/11/04 1:58 PM Changes from TMB2001 Old TMB2001 New TMB2004 FPGA Xilinx XCV1000E Xilinx XC2V4000 EPROMs 2 x 18V04 4 x 18V04 Clock Delays 2 x PHOS4, 10 channels Voltage Regulators Voltage Protection +3.3V,+1.8V Not tested for rad tolerance Zener 3 x 3D3444, 12 channels with duty cycle correction +1.8V,+1.5V/+1.2V Tested rad tolerant MOSFET RPC Not implemented ALCT Cables Front panel entry RAT2004 Transition Module Receives 4 RPC link boards RAT2004 Transition Module and front panel entry Page 3 of 83 06/11/04 1:58 PM List of Figures Figure 1 TMB Overview .............................................................................................................................5 Figure 2: 50-Pin PCB Connector (Female) ...............................................................................................70 Figure 3: 50 Pin Cable Connector (Male)..................................................................................................70 Figure 4: 50 Pin PCB Connector Pin Convention .....................................................................................70 List of Tables Table 1: CCB Signal Summary .................................................................................................................59 Table 2: ALCT Signal Summary...............................................................................................................60 Table 3: DMB Signal Summary ................................................................................................................61 Table 4: CFEB Signal Summary ...............................................................................................................61 Table 5: MPC Signal Summary.................................................................................................................62 Table 6: RPC Signal Summary..................................................................................................................63 Table 7: VME Signal Summary ................................................................................................................63 Table 8: JTAG Signal Summary................................................................................................................63 Table 9: TMB Front Panel LEDs...............................................................................................................64 Table 10: TMB Total I/O Count................................................................................................................65 Table 11: TMB2001 Connector Summary ................................................................................................66 Table 12: J0-J4 CFEB0/4-to-TMB Connectors.........................................................................................67 Table 13: J5 ALCT Cable1 Connector [J10 on ALCT board] .................................................................68 Table 14: J6 ALCT Cable2 Connector [J11 on ALCT board] ..................................................................69 Table 15: J8 Xilinx LVDS X-Blaster Connector.......................................................................................71 Table 16: P1 VME64x Connector .............................................................................................................72 Table 17: P2A Backplane CCB+DMB Connector ....................................................................................73 Table 18: P2B Backplane DMB Connector...............................................................................................75 Table 19: P3A Backplane MPC Connector ...............................................................................................76 Table 20: P3B Backplane RPC+ALCT Connector ...................................................................................77 Page 4 of 83 06/11/04 1:58 PM TMB Overview Figure 1 TMB Overview CFEB0 CFEB1 CFEB2 CFEB3 CFEB4 24 x80MHz 40MHz clock 24 x80MHz D16 40MHz clock A24+GA5 46 x40MHz 24 x80MHz 46 x40MHz 40MHz clock 24 x80MHz VME CLCT + TMB Logic 40MHz clock 44 x40MHz 40MHz clock 40MHz clock CCB DMB 4 x40MHz 24 x80MHz 32 x80MHz 40MHz clock 1 x80MHz MPC 28x80MHz+1x10MHz ALCT RPC 15x80MHz+5x10MHz 40MHz clock 40 x80MHz n 8 PROM 1 3 A2 JTAG Page 5 of 83 06/11/04 1:58 PM Cathode LCT Algorithm (documentation incomplete 6/9/2004) CFEB Demultiplex (documentation incomplete 6/9/2004) Triad Decode (documentation incomplete 6/9/2004) Layer Staggering (documentation incomplete 6/9/2004) DiStrip OR (documentation incomplete 6/9/2004) Pattern Cell Envelope (documentation incomplete 6/9/2004) Hit pattern LUTs for 1 layer: - = don't care, xxx= any one or more ½-strips hit Default Cell Envelope Key on Ly3 ------------hs 0123 LUT ly0 xxx- FEFE ly1 xxx- FEFE ly2 xxx- FEFE ly3 -x-- CCCC ly4 xxx- FEFE ly5 xxx- FEFE Priority Enocoding (documentation incomplete 6/9/2004) DiStrip Patterns (documentation incomplete 6/9/2004) DMB Active FEB Signal (documentation incomplete 6/9/2004) Best 2 LCTs (documentation incomplete 6/9/2004) Page 6 of 83 06/11/04 1:58 PM CLCT Bend Patterns (documentation incomplete 6/9/2004) Hit pattern LUTs for 1 layer: - = don't care, x=one ½-strip hit, xx= one hit or the other or both ½-StripID=0123 Layer0 --xLayer1 --xLayer2 -xxLayer3 -x-Layer4 xx-Layer5 x--Pattern 7 -------------hs 0123 LUT ly0 -x-- CCCC ly1 -x-- CCCC ly2 -x-- CCCC ly3 -x-- CCCC ly4 -x-- CCCC ly5 -x-- CCCC LUT (look-up table contents) F0F0 F0F0 FCFC CCCC EEEE AAAA Pattern 6 -------------hs 0123 LUT ly0 x--- AAAA ly1 x--- AAAA ly2 xx-- EEEE ly3 -x-- CCCC ly4 -x-- CCCC ly5 -x-- CCCC Pattern 5 -------------hs 0123 LUT ly0 --x- F0F0 ly1 --x- F0F0 ly2 -xx- FCFC ly3 -x-- CCCC ly4 -x-- CCCC ly5 -x-- CCCC Pattern 4 -------------hs 0123 LUT ly0 -x-- CCCC ly1 -x-- CCCC ly2 -x-- CCCC ly3 -x-- CCCC ly4 --x- F0F0 ly5 --x- F0F0 Pattern 3 -------------hs 0123 LUT ly0 -x-- CCCC ly1 -x-- CCCC ly2 -x-- CCCC ly3 -x-- CCCC ly4 x--- AAAA ly5 x--- AAAA Pattern 2 -------------hs 0123 LUT ly0 x--- AAAA ly1 x--- AAAA ly2 xx-- EEEE ly3 -x-- CCCC ly4 -xx- FCFC ly5 --x- F0F0 Pattern 1 -------------hs 0123 LUT ly0 --x- F0F0 ly1 --x- F0F0 ly2 -xx- FCFC ly3 -x-- CCCC ly4 xx-- EEEE ly5 x--- AAAA Drift Delay (documentation incomplete 6/9/2004) CLCT Format (documentation incomplete 6/9/2004) Page 7 of 83 06/11/04 1:58 PM ALCT+CLCT Matching Algorithm (documentation incomplete 6/9/2004) Matching Logic (documentation incomplete 6/9/2004) LCT Duplication (documentation incomplete 6/9/2004) // Fill in missing ALCT if CLCT has 2 muons, missing CLCT if ALCT has 2 muons wire no_alct = !alct0_vpf; wire no_clct = !clct0_vpf; wire wire one_alct = alct0_vpf && !alct1_vpf; one_clct = clct0_vpf && !clct1_vpf; wire wire two_alct = alct0_vpf && alct1_vpf; two_clct = clct0_vpf && clct1_vpf; wire wire dupe_alct = one_alct && two_clct; dupe_clct = one_clct && two_alct; wire wire [MXALCT-1:0] [MXCLCT-1:0] alct_dummy = clct0_real[18:17] << 11; clct_dummy = 0; // Inserts clct bxn into // frame for clct_only events wire wire [MXALCT-1:0] [MXALCT-1:0] alct0 = (no_alct ) ? alct_dummy : alct0_real; alct1 = (dupe_alct) ? alct0_real : alct1_real; // Substitute dummy alct wire wire [MXCLCT-1:0] [MXCLCT-1:0] clct0 = (no_clct ) ? clct0_real : clct0_real; clct1 = (dupe_clct) ? clct0_real : clct1_real; // Do not = alct0_vpf || clct0_vpf; = alct1_vpf || clct1_vpf; // First muon exists // Second muon exists wire first_vpf wire second_vpf LCT Quality (documentation incomplete 6/9/2004) assign first_nlayers = (alct_first_quality + 3) + clct_first_nhit; assign second_nlayers = (alct_second_quality + 3) + clct_second_nhit; // Construct 1st LCT quality reg [3:0] lct_first_quality; always @(tmb_match or tmb_clct_only or tmb_alct_only or alct_first_amu or clct_first_hsds or first_nlayers) begin if (tmb_match && clct_first_hsds && first_nlayers >= 8) // ALCT & CLCT match, CLCT ½-strip pattern lct_first_quality = 4'b1011 + first_nlayers[3:0]-8; else if (tmb_match && !clct_first_hsds && first_nlayers >= 8)// ALCT & CLCT match, CLCT DiStrip pattern lct_first_quality = 4'b0110 + first_nlayers[3:0]-8; else if (tmb_clct_only && clct_first_hsds) lct_first_quality = 4'b0101; // CLCT no ALCT, CLCT ½-strip pattern else if (tmb_clct_only && !clct_first_hsds) lct_first_quality = 4'b0100; // CLCT no ALCT, CLCT DiStrip pattern else if (tmb_alct_only) lct_first_quality = 4'b0011; // ALCT only else if (tmb_match && alct_first_amu) lct_first_quality = 4'b0010; else if (tmb_alct_only && alct_first_amu) lct_first_quality = 4'b0001; else lct_first_quality = 4'b000; end MPC Format (documentation incomplete 6/9/2004) Page 8 of 83 06/11/04 1:58 PM VME Registers Addressing Modes TMB2001 responds to A24D16 VME addressing modes: Address Modifier 3916, A24 non-privileged mode Address Modifier 3D16, A24 supervisor mode It does not respond to byte-addressing modes, so all valid addresses must be even numbers. Base Address TMB2001s “base address” bits A[23:19] select which TMB is being addressed by the VME crate controller. The base address is determined either by 5 VME-slot Geographic Address bits or by the Local Address set by two on-board hexadecimal rotary switches. Shunt SH62 selects between Geograpic [1-2] and Local [2-3] modes. A[23:19] = VME Crate Slot Geographic Address, (Slot= 2 to 21)10 SH62 [1-2] A[23:19] = Hexadecimal Switch Address SW2x16+SW1 SH62 [2-3] Multiple TMBs can be addressed simultaneously using a Global Address: A[23:19] = 2610 Addresses all TMBs in parallel A[23:19] = 2710 Address all peripheral crate modules The Hardware Bootstrap Register has a special mode where it can use the Local Address set by the hexadecimal rotary switches as its Global Address Page 9 of 83 06/11/04 1:58 PM Register Addresses Address Register Name Description ADR_BOOT Hardware Bootstrap Register 00 02 04 06 ADR_IDREG0 ADR_IDREG1 ADR_IDREG2 ADR_IDREG3 ID Register 0 ID Register 1 ID Register 2 ID Register 3 08 0A 0C ADR_VME_STATUS ADR_VME_ADR0 ADR_VME_ADR1 VME Status Register VME Address read-back VME Address read-back 0E 10 12 ADR_LOOPBK ADR_USR_JTAG ADR_PROM Loop-back Register User JTAG PROM 14 16 18 1A 1C 1E ADR_DDDSM ADR_DDD0 ADR_DDD1 ADR_DDD2 ADR_DDDOE ADR_RATCTRL 3D3444 State Machine Register + Clock DCMs 3D3444 Delay Chip 0 3D3444 Delay Chip 1 3D3444 Delay Chip 2 3D3444 Delay Chip Output Enables RAT Module Control 20 22 24 26 ADR_STEP ADR_LED ADR_ADC ADR_DSN Step Register Front Panel +On-Board LEDs ADCs Digital Serials 28 2A 2C 2E ADR_MOD_CFG ADR_CCB_CFG ADR_CCB_TRIG ADR_CCB_STAT TMB Configuration CCB Configuration CCB Trigger Control CCB Status 30 32 34 36 38 3A 3C 3E ADR_ALCT_CFG ADR_ALCT_INJ ADR_ALCT0_INJ ADR_ALCT1_INJ ADR_ALCT_STAT ADR_ALCT0_RCD ADR_ALCT1_RCD ADR_ALCT_FIFO ALCT Configuration ALCT Injector Control ALCT Injected ALCT0 ALCT Injected ALCT1 ALCT Sequencer Control/Status ALCT LCT0 Received by TMB ALCT LCT1 Received by TMB ALCT FIFO RAM Status 40 ADR_DMB_MON DMB Monitored signals Hexadecimal Add to Base 70000 Page 10 of 83 06/11/04 1:58 PM 42 44 46 48 ADR_CFEB_INJ ADR_CFEB_INJ_ADR ADR_CFEB_INJ_WDATA ADR_CFEB_INJ_RDATA CFEB Injector Control CFEB Injector RAM address CFEB Injector Write Data CFEB Injector Read Data 4A 4C 4E 50 52 54 56 58 5A 5C 5E 60 62 64 66 ADR_HCM001 ADR_HCM023 ADR_HCM045 ADR_HCM101 ADR_HCM123 ADR_HCM145 ADR_HCM201 ADR_HCM223 ADR_HCM245 ADR_HCM301 ADR_HCM323 ADR_HCM345 ADR_HCM401 ADR_HCM423 ADR_HCM445 CFEB0 Ly0,Ly1 Hot Channel Mask CFEB0 Ly2,Ly3 Hot Channel Mask CFEB0 Ly4,Ly5 Hot Channel Mask CFEB1 Ly0,Ly1 Hot Channel Mask CFEB1 Ly2,Ly3 Hot Channel Mask CFEB1 Ly4,Ly5 Hot Channel Mask CFEB2 Ly0,Ly1 Hot Channel Mask CFEB2 Ly2,Ly3 Hot Channel Mask CFEB2 Ly4,Ly5 Hot Channel Mask CFEB3 Ly0,Ly1 Hot Channel Mask CFEB3 Ly2,Ly3 Hot Channel Mask CFEB3 Ly4,Ly5 Hot Channel Mask CFEB4 Ly0,Ly1 Hot Channel Mask CFEB4 Ly2,Ly3 Hot Channel Mask CFEB4 Ly4,Ly5 Hot Channel Mask 68 6A 6C 6E ADR_SEQ_TRIG_EN ADR_SEQ_TRIG_DLY0 ADR_SEQ_TRIG_DLY1 ADR_SEQ_ID Sequencer Trigger Source Enables Sequencer Trigger Source Delays Sequencer Trigger Source Delays Sequencer Board + CSC ID 70 72 74 76 78 7A 7C ADR_SEQ_CLCT ADR_SEQ_FIFO ADR_SEQ_L1A ADR_SEQ_OFFSET ADR_SEQ_CLCT0 ADR_SEQ_CLCT1 ADR_SEQ_TRIG_SRC Sequencer CLCT Configuration Sequencer FIFO Configuration Sequencer L1A Configuration Sequencer Counter Offsets Sequencer Latched CLCT0 Sequencer Latched CLCT1 Sequencer Trigger Source Read-back 7E 80 82 84 ADR_DMB_RAM_ADR ADR_DMB_RAM_WDATA ADR_DMB_RAM_WDCNT ADR_DMB_RAM_RDATA Sequencer RAM Address Sequencer RAM Write Data Sequencer RAM Word Count Sequencer RAM Read Data 86 ADR_TMB_TRIG TMB Trigger Configuration / MPC Accept 88 8A 8C 8E ADR_MPC0_FRAME0 ADR_MPC0_FRAME1 ADR_MPC1_FRAME0 ADR_MPC1_FRAME1 MPC0 Frame 0 Data sent to MPC MPC0 Frame 1 Data sent to MPC MPC1 Frame 0 Data sent to MPC MPC1 Frame 1 Data sent to MPC Page 11 of 83 06/11/04 1:58 PM 90 92 94 96 ADR_MPC_INJ ADR_MPC_RAM_ADR ADR_MPC_RAM_WDATA ADR_MPC_RAM_RDATA MPC Injector Control MPC Injector RAM address MPC Injector RAM Write Data MPC Injector RAM Read Data 98 9A ADR_SCP_CTRL ADR_SCP_RDATA Scope control Scope read data 9C 9E A0 A2 A4 ADR_CCB_CMD ADR_BUF_STAT ADR_SRLPGM ADR_ALCT_FIFO1 ADR_ALCT_FIFO2 CCB TTC Command Generator Buffer Status SRL LUT Program ALCT Raw hits RAM Control ALCT Raw hits RAM data A6 A8 AA ADR_ADJCFEB0 ADR_ADJCFEB1 ADR_ADJCFEB2 CFEB Adjacent hs Mask lsbs CFEB Adjacent hs Mask msbs CFEB Adjacent ds Mask AC AE B0 B2 B4 ADR_SEQMOD ADR_SEQSM ADR_SEQCLCTM ADR_TMBTIM ADR_LHC_CYCLE Sequencer Trigger Modifiers Sequencer Machine State Sequencer CLCT msbs TMB Timing for ALCT*CLCT coincidence LHC Cycle period, Maximum BXN+1 B6 B8 BA BC BE C0 C2 C4 C6 C8 CA CC ADR_RPC_CFG ADR_RPC_RDATA ADR_RPC_RAW_DELAY ADR_RPC_INJ ADR_RPC_INJ_ADR ADR_RPC_INJ_WDATA ADR_RPC_INJ_RDATA ADR_RPC_BXN_DIFF ADR_RPC0_HCM ADR_RPC1_HCM ADR_RPC2_HCM ADR_RPC3_HCM RPC Configuration RPC Sync Mode Read Data RPC Raw Hits Delay RPC Injector Control RPC Injector RAM Addresses RPC Injector Write Data RPC Injector Read Data RPC BXN Differences RPC0 Hot Channel Mask RPC1 Hot Channel Mask RPC2 Hot Channel Mask RPC3 Hot Channel Mask Page 12 of 83 06/11/04 1:58 PM Register Definitions Adr 7000016 ADR_BOOT 15 14 13 12 11 R=tdo R=ready free free /fpga vme_en 10 /en_fpga reset_alct Hardware Bootstrap Register 9 8 7 6 5 4 hard reset TMB hard reset ALCT JTAG source vme/fpga sel3 sel2 sel1 3 2 1 0 sel0 tck tms tdi Bit Dir Signal [ 0] [ 1] [ 2] [ 3] [ 4] [ 5] [ 6] [ 7] [ 8] [ 9] [10] [11] [12] [13] [14] [15] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R jtag_vme1 (tdi) jtag_vme2 (tms) jtag_vme3 (tck) sel_vme0 sel_vme1 sel_vme2 sel_vme3 vme/usr_en hard_reset_alct_vme hard_reset_tmb_vme /en_fpga_reset_alct /fpga_vme_en unassigned unassigned vme_ready jtag_vme0 (tdo) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x 0 vme tdi vme tms vme tck 00XX ALCT JTAG Chain 01XX TMB Mezzanine FPGA + FPGA PROMs Chain 10XX TMB User PROMs JTAG chain 11XX TMB FPGA User JTAG chain 1=JTAG sourced by Bootstrap Register, 0= from FPGA 1=Hard reset to ALCT FPGA 1=Hard reset to TMB FPGA 0=Allow TMB FPGA to hard reset ALCT 0=Allow TMB FPGA to issue VME commands Available for future use Available for future use 1=FPGA vme logic indicates ready vme tdo [14] [15] W W unassigned unassigned - No connection on PCB No connection on PCB Default Description Page 13 of 83 06/11/04 1:58 PM Adr 00 15 14 0 ADR_IDREG0 13 12 11 0 0 Bits Dir [03:00] [07:04] [12:08] [15:13] R R R R month msd2 Typical ga2 month msd1 Dir [07:00] [15:08] R R month msd0 month lsd3 Typical year digit3 1 year digit3 0 fvers3 4 3 2 1 0 fvers2 fvers1 fvers0 ftype3 ftype2 ftype1 ftype0 10 9 month lsd2 month lsd1 ID Register 1 8 7 month lsd0 day msd3 6 5 4 3 2 1 0 day msd2 day msd1 day msd0 day lsd3 day lsd2 day lsd1 day lsd0 Description DD Firmware Version Day (BCD) MM Firmware Version Month (BCD) ADR_IDREG2 13 12 11 year digit3 2 ga0 5 Firmware type, C=Normal CLCT/TMB, D=Debug loopback Firmware version code Geographic address for this board Unassigned 14 04 Adr 04 15 14 ga1 6 Description ADR_IDREG1 13 12 11 Bits year digit3 3 ga3 C D 15 0 Adr 02 15 14 month msd3 ga4 10 ID Register 0 9 8 7 10 year digit2 3 year digit2 2 ID Register 2 9 8 7 year digit2 1 year digit2 0 year digit1 3 6 5 4 3 2 1 0 year digit1 2 year digit1 1 year digit1 0 year digit0 3 year digit0 2 year digit0 1 year digit0 0 Bits Dir Typical Description [15:00] R 2002 YYYY Firmware Version Year (BCD) ADR_IDREG3 13 12 11 10 ID Register 3 9 8 7 rev code 13 rev code 10 Adr 06 15 14 rev code 15 rev code 14 Bits Dir [15:00] R rev code 12 rev code 11 Typical rev code 9 rev code 8 rev code 7 6 5 4 3 2 1 0 rev code 6 rev code 5 rev code 4 rev code 3 rev code 2 rev code 1 rev code 0 Description Firmware Revcode (as stored in raw hits header) Page 14 of 83 06/11/04 1:58 PM Adr 08 15 14 ADR_VME_STATUS 13 12 11 10 TMB ready iack local/ geo Bits Dir [04:00] [05] [06] [07] [08] [09] [10] [11] [12] [13] [14] [15] R R R R R R R R R R R R Adr 0A 15 14 a15 a14 acfail sysreset Typical sysfail VME Status Register 9 8 7 6 5 sysclk ds1 as lword gap 4 3 2 1 0 ga4 ga3 ga2 ga1 ga0 Description Crate slot Geographic Address Crate slot Geographic Address Parity VME signal lword VME signal as VME signal ds1 VME signal sysclk VME signal sysfail VME signal sysreset VME signal acfail VME signal iack 1=Address mode set to local, 0=Geographic 1=TMB reports ready to boot register ADR_VME_ADR0 13 12 11 10 VME Address Read-Back 9 8 7 6 5 4 3 2 1 0 a13 a9 a4 a3 a2 a1 lword a12 a11 a10 a8 a7 a6 a5 Bits Dir Typical Description [15:00] R a[15:0] VME Address captured at last write cycle {a[15:1},lword} Adr 0C 15 14 ADR_VME_ADR1 13 12 11 10 TMB ready iack local/ geo acfail sysreset sysfail VME Address Read-Back 9 8 7 6 5 sysclk ds1 as lword gap Bits Dir Typical [07:00] [13:08] [15:14] R R R VME Address captured at last write cycle am[5:0] VME Address modifier 0 Unassigned 4 3 2 1 0 ga4 ga3 ga2 ga1 ga0 Description a[23:16] Page 15 of 83 06/11/04 1:58 PM Adr 0E 15 14 0 ADR_LOOPBK 13 12 11 0 0 0 10 0 0 Bits Dir Signal [00] [01] [02] [03] [04] [05] [06] [07] [08] [09] [15:10] R R R/W R R R R R R R R cfeb_oe alct_loop alct_scsi_rear alct_oe rpc_loop rpc_oe dmb_loop dmb_oe gtl_loop gtl_oe -- Adr 10 15 14 tdo usr 0 gtl_ oe gtl_ loop Default 1 0 1 0 0 0 0 0 0 0 0 ADR_USR_JTAG 13 12 11 10 0 Loop-Back Control Register 9 8 7 6 5 4 0 0 0 dmb_ oe dmb_ loop rpc_ oe 2 1 0 alct_ oe alct_ scsi_ rear alct_ loop cfeb_ oe Description 1=CFEB output enable 0=No ALCT loop-back 1=ALCT source=SCSI, 0=RAT module 0=ALCT driver enable No RPC Loop-back RPC driver enable 0=No DMB loop-back 0=DMB driver enable 0=No GTL loop-back 0=Enable GTL outputs Unassigned User JTAG Register 9 8 7 6 5 0 rpc_ loop 3 sel3 usr 0 sel2 usr 4 3 2 1 0 sel1 usr sel0 usr tck usr tms usr tdi usr Bits Dir Signal Description [00] [01] [02] [06:03] [14:07] [15] R/W R/W R/W R/W R/W R tdi_usr tms_usr tck_usr sel_usr[3:0] User JTAG Chain TDI (output from FPGA) User JTAG Chain TMS User JTAG Chain TCK User JTAG Chain Select, 0=ALCT,1=Mez,2=UserPROMs,3=UserChain Unassigned User JTAG Chain TDO (input to FPGA) Adr 12 15 14 0 prom_ src tdo_usr ADR_PROM 13 12 11 prom1 ce prom1 oe prom1 clk 10 prom0 ce Bits Dir Signal [07:00] [08] [09] [10] [11] [12] [13] [14] [15] R/W R/W R/W R/W R/W R/W R/W R/W R/W prom_led[7:0] prom0_clk prom0_oe prom0_ce prom1_clk prom1_oe prom1_ce prom_src -- User PROMs Register 9 8 7 6 5 prom0 oe prom0 clk Default CD 0 0 1 0 0 1 0 0 prom_ led7 prom_ led6 prom_ led5 4 3 2 1 0 prom_ led4 prom_ led3 prom_ led2 prom_ led1 prom_ led0 Description PROM data bus shared with On-Board LEDs PROM 0 clock PROM 0 output enable PROM 0 /chip_enable PROM 1 clock PROM 1 output enable PROM 1 /chip_enable Data bus 0=on-board LEDs, 1=enabled PROM Unassigned Page 16 of 83 06/11/04 1:58 PM Adr 14 15 14 rpc lock dcc lock ADR_DDDSM 13 12 11 10 mpc lock tmb1 lock alctd lock alct lock Bits Dir Signal [00] [01] [02] [03] [04] [05] [06] [07] [08] [09] [10] [11] [12] [13] [14] [15] R/W R/W R/W R/W R/W R/W R R R R R R R R R R ddd_start_vme ddd_clock ddd_adr_latch ddd_serial_in ddd_serial_out ddd_auto_start ddd_busy ddd_verify lock_tmb_clock0 lock_tmb_clock0d lock_tmb_clock1 lock_alct_clock lock_alct_clockd lock_mpc_clock lock_dcc_clock lock_rpc_clock Adr 16 ADR_DDD0 Bits Dir Signal [03:00] [07:04] [11:08] [15:12] R/W R/W R/W R/W delay_ch0[3:0] delay_ch1[3:0] delay_ch2[3:0] delay_ch3[3:0] Adr 18 ADR_DDD1 Bits Dir Signal [03:00] [07:04] [11:08] [15:12] R/W R/W R/W R/W delay_ch4[3:0] delay_ch5[3:0] delay_ch6[3:0] delay_ch7[3:0] Adr 1A ADR_DDD2 Bits Dir Signal [03:00] [07:04] [11:08] [15:12] R/W R/W R/W R/W delay_ch8[3:0] delay_ch9[3:0] delay_ch10[3:0] delay_ch11[3:0] 3D3444 State Machine Control + DCM Lock Status 9 8 7 6 5 4 3 2 1 0 tmb0d lock tmb0 lock Default 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 ddd verify dddsm busy auto start serial from serial to ddd adr latch ddd clock ddd start Description Start DDD State Machine DDD manual-mode clock DDD manual-mode address latch Serial data to DDD chain Serial data from DDD chain DDD State Machine autostart state DDD State Machine busy DDD data read back verified OK TMB clock 0 DCM locked TMB clock 0d DCM locked TMB clock 1 DCM locked ALCT rxclock DCM locked ALCT rxclockd DCM locked MPC clock DCM locked DCC clock DCM locked RPC clock DCM locked 3D3444 Chip 0 Delays, 1 step = 2ns Default 8 1 2 0 Description ALCT tx clock, 8 steps = 16ns delay ALCT rx clock DMB tx clock RPC tx clock 3D3444 Chip 1 Delays, 1 step = 2ns Default 0 0 0 7 Description TMB1 Clock MPC Clock DCC Clock (CFEB duty cycle correction) CFEB 0 clock 3D3444 Chip 2 Delays, 1 step = 2ns Default 7 7 7 7 Description CFEB 1 clock CFEB 2 clock CFEB 3 clock CFEB 4 clock Page 17 of 83 06/11/04 1:58 PM Adr 1C 15 14 0 0 [11:00] [15:12] 10 cfeb 4 cfeb 3 0 R/W R/W Adr 1E 15 14 0 ADR_DDDOE 13 12 11 0 0 0 0 0 Dir Signal [0] [1] [2] [3] [4] [15:5] R/W R/W R/W R/W R/W R/W rpc_sync rpc_posneg rpc_lptmb rpc_free_tx[0] rat_dsn_en -- 0 0 10 /tmb hard alct clken /alct hard Bits Dir Signal [00] [01] [02] [03] [04] [05] [06] [07] [08] [09] [10] [11] [12] [15:13] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W step_alct step_dmb step_rpc step_cfeb step_run cfeb_clock_en0 cfeb_clock_en1 cfeb_clock_en2 cfeb_clock_en3 cfeb_clock_en4 alct_clock_en /alct_hard_reset_en /tmb_hard_reset_en -- cfeb 0 dcc mpc 0 0 0 0 0 0 0 0 tmb1 3 2 1 0 rpc tx dmb tx alct rx alct tx Bit(n)=1=Enable DDD output channel n Unassigned RAT Module Control 8 7 6 5 9 Default ADR_STEP 13 12 11 0 cfeb 1 0FFF 0 Bits Adr 20 15 14 cfeb 2 ddd_oe[11:0] Unassigned ADR_RATCTRL 13 12 11 10 0 3D3444 Chip Output Enables 9 8 7 6 5 4 0 0 0 4 3 2 1 0 rpc dsn en rpc free rpc lptm rpc posneg rpc sync Description 1=RPC 80MHz sync pattern mode 1=shift RPC data ½ cycle in RAT FPGA + dsn Not used (for matching rpc_tx array) Unassigned 1=Enable RAT dsn readout Unassigned Clock Single-Step + Hard Resets 9 8 7 6 5 4 3 cfeb4 clken cfeb3 clken Default 0 0 0 0 0 1 1 1 1 1 1 1 1 0 cfeb2 clken cfeb1 clken cfeb0 clken step run step cfeb 2 1 0 step rpc step dmb step alct Description Step ALCT clock Step DMB clock Step RPC clock Step CFEB clock 0=run mode, 1=step clocks 1=enable CFEB0 clock 1=enable CFEB0 clock 1=enable CFEB0 clock 1=enable CFEB0 clock 1=enable CFEB0 clock 1=enable ALCT clock 1=disable ALCT hard reset 1=disable TMB hard reset Unassigned Page 18 of 83 06/11/04 1:58 PM Adr 22 15 14 led bd7 led bd6 ADR_LED 13 12 11 10 led bd5 led bd2 led bd4 led bd3 Front Panel + On-Board LED Register 9 8 7 6 5 4 3 2 led bd1 led bd0 VME NL1A NMAT INVP L1A CLCT 1 0 ALCT LCT Bits Dir Signal Color Description [00] [01] [02] [03] [04] [05] [06] [07] [08] [09] [10] [11] [12] [13] [14] [15] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W led_fp_lct led_fp_lct led_fp_clct led_fp_l1a led_fp_invp led_fp_nmat led_fp_nl1a led_fp_vme led_bd0 led_bd1 led_bd2 led_bd3 led_bd4 led_bd5 led_bd6 led_bd7 Blue Green Green Green Amber Amber Red Green Blue Green Green Green Green Green Green Red LCT TMB matched ALCT+CLCT ALCT found a muon CLCT found a muon L1A level 1 accept INVP invalid pattern after CSC drift NMAT no match after ALCT or CLCT triggered NL1A no L1A after trigger VME power-up = on, off=vme access flash Buffer busy[0] Buffer busy[1] Buffer busy[2] Buffer busy[3] Buffer busy[4] Buffer busy[5] Buffer busy[6] Buffer busy[7] Adr 24 15 14 0 ADR_ADC 13 12 11 0 0 0 0 Bits Dir Signal [00] [01] [02] [03] [04] [05] [06] [07] [08] [09] [10] [15:11] R R R R R R R/W R/W R/W R/W R/W R/W vstat_5p0v vstat_3p3v vstat_1p8v vstat_1p5v /t_crit adc_dout adc_sclock adc_din /adc_cs smb_clk smb_data -- 10 9 smb data smb clk ADC + Power Comparator Register 8 7 6 5 4 3 ADC /cs ADC din ADC sclock ADC dout /tcrit V1.5 2 1 0 V1.8 V3.3 V5.0 Typical Description 1 1 1 1 1 0 0 0 1 0 1 0 1 = 5.0V power supply OK 1 = 3.3V power supply OK 1 = 1.8V power supply OK 1 = 1.5V power supply OK 1 = FPGA and Board Temperature OK Voltage monitor ADC serial data receive Voltage monitor ADC serial clock Voltage monitor ADC serial data transmit Voltage monitor ADC chip select Temperature monitor ADC serial clock Temperature monitor ADC serial data, open drain Unassigned Page 19 of 83 06/11/04 1:58 PM Adr 26 15 14 0 RAT DSN Data ADR_DSN 13 12 11 10 RAT DSN Busy RAT DSN Start RAT DSN Init RAT DSN Write Bits Dir Signal [00] [01] [02] [03] [04] [05] [06] [07] [08] [09] [10] [11] [12] [13] [14] [15] R/W R/W R/W R R R/W R/W R/W R R R/W R/W R/W R R R/W tmb_sn_start tmb_sn_write tmb_sn_init tmb_sn_busy tmb_sn_data mez_sn_start mez_sn_write mez_sn_init mez_sn_busy mez_sn_data rat_sn_start rat_sn_write rat_sn_init rat_sn_busy rat_sn_data - Adr 28 15 14 mez done ddd auto 0 Mez DSN Data Mez DSN Busy Default ADR_MOD_CFG 13 12 11 10 power up Digital Serial Numbers 9 8 7 6 5 led flash rate 1 led flash rate 0 Bits Dir Signal [00] [01] [02] [03] [04] [9:5] [11:10] [12] [13] [14] [15] R/W R/W R/W R/W R/W R RW RW R R R led_fp_src_vme led_fp_cylon led_flash_on_stop led_bd_src_vme led_bd_cylon cfeb_exists led_flash_rate[1:0] power_up ddd_autostart mez_done 0 0 0 0 0 0 0 0 0 0 Mez DSN Init Mez DSN Write Mez DSN Start 4 3 2 1 0 TMB DSN Data TMB DSN Busy TMB DSN Init TMB DSN Write TMB DSN Start Description TMB Digital serial SM start TMB Digital serial write pulse TMB Digital serial Init pulse TMB State DSN State Machine busy TMB State DSN read data Mez Digital Serial State Machine start Mez Digital Serial Write pulse Mez Digital Serial Init pulse Mez State DSN State Machine busy Mez State DSN read data RAT Digital Serial State Machine start RAT Digital Serial Write pulse RAT Digital Serial Init pulse RAT State DSN State Machine busy RAT State DSN read data Unassigned TMB Module Configuration 9 8 7 6 5 4 cfeb4 exists cfeb3 exists Default 0 0 1 0 0 1F 0 cfeb2 exists cfeb1 exists cfeb0 exists bdled cylon 3 2 1 0 bdled vme fpled flash fpled cylon fpled vme Description 1=Front Panel LEDs sourced from VME register 1=FP LED Cylon mode, cool 1=Flash Front Panel LEDs on TTT stop_trigger 1=On-Board LEDs sourced from VME register 1=BD LED Cylon mode, cool CFEB(n) instantiated in this firmware version LED flash rate in Flash-on-stop mode Unassigned Power-up FF 1=3D3444 auto-start enabled 1=Mezzanine FPGA loaded from PROM Page 20 of 83 06/11/04 1:58 PM Adr 2A 15 14 ADR_CCB_CFG 13 12 11 10 adb pulse async alct hard reset adb pulse sync tmb hard reset tmb resout 2 tmb resout 1 Bits Dir Signal [00] [01] [02] [03] [04] [05] [06] [08:07] [11:09] [12] [13] [14] [15] R/W R/W R/W R/W R/W R/W R/W R R R R R R ccb_ignore_rx ccb_disable_tx ccb_int_l1a_en /ccb_status_oe_vme alct_status_en clct_status_en l1accept_vme tmb_reserved[1:0] tmb_reserved_out[2:0] tmb_hard_reset alct_hard_reset alct_adb_pulse_sync alct_adb_pulse_async ADR_CCB_TRIG 13 12 11 10 l1a delay vme7 l1a delay vme5 l1a delay vme4 tmb resout 0 tmb res1 Default Adr 2C 15 14 l1a delay vme6 CCB Configuration 9 8 7 6 l1a delay vme3 l1a delay vme2 0 0 0 1 1 1 0 tmb res0 l1a vme 5 4 3 2 1 0 clct status en alct status en /ccb status oe int l1aen disabl tx ignore rx Description 1=Ignore Received CCB backplane inputs 1=Disble tranmistted CCB backplane outputs 1=Enable internal L1A emulator 1=Enable ALCT+CLCT status to CCB front panel 1=Enable ALCT status GTL outputs 1=Enable CLCT status GTL outputs 1=fire ccb_l1accept oneshot Future use Future use Reload TMB FPGA Reload ALCT FPGA ALCT synchronous test pulse ALCT asynchronous test pulse CCB Trigger Control 9 8 7 6 5 l1a delay vme1 Bits Dir Signal [00] [01] [02] [03] [04] [05] [06] [07] [15:08] R/W R/W R/W R/W R/W R/W R/W R/W R/W alct_ext_trig_l1aen clct_ext_trig_l1aen seq_trig_l1aen alct_ext_trig_vme clct_ext_trig_vme ext_trig_both ccb_allow_extbypass -l1a_delay_vme l1a delay vme0 Default 0 0 1 0 0 0 0 0 7516 0 ccb exttrig bypas ext trig both 4 3 2 1 0 clct ext trg vme alct ext trg vme seq trig l1aen clct ext trg l1aen alct ext trg l1aen Description 1=Request ccb l1a on alct ext_trig 1=Request ccb l1a on clct ext_trig 1=Request ccb l1a on sequencer trigger 1=Fire alct_ext_trig oneshot 1=Fire clct_ext_trig oneshot 1=clct_ext_trig fires alct + alct fires clct_trig, DC 1=Allow clct_exttrig_ccb when ccb_ignore_rx=1 Unassigned Internal L1A delay (not same as sequencer L1A) Page 21 of 83 06/11/04 1:58 PM Adr 2E 15 14 ccb bx0 ADR_CCB_STAT 13 12 11 10 ccb bcntrs ccb res4 ccb res3 ccb res2 ccb res1 Bits Dir Signal [07:00] [08] [13:09] [14] [15] R R R R R ccb_cmd[7:0] ccb_clock40_enable ccb_reserved[4:0] ccb_bcntres ccb_bx0 Adr 30 15 14 0 0 0 ccb res0 alct res in4 alct res in3 9 Signal [00] [01] [02] [03] [06:04] [11:07] [15:12] R/W R/W R/W R/W R/W R/W R/W cfg_alct_ext_trig_en cfg_alct_ext_inject_en cfg_alct_ext_trig cfg_alct_ext_inject alct_seq_cmd[2:0] alct_reserved_in[4:0] -- 0 0 0 0 0 0 Bits Dir Signal [00] [01] [02] [07:03] [15:08] R/W R/W R/W R/W R/W alct_clear alct_inject_mux alct_sync_clct alct_inj_delay[7:0] -- 4 3 2 1 0 ccb cmd6 ccb cmd5 ccb cmd4 ccb cmd3 ccb cmd2 ccb cmd1 ccb cmd0 Description alct res in1 alct res in0 Default ADR_ALCT_INJ 13 12 11 10 5 ALCT Configuration 8 7 6 5 alct res in2 Dir ccb cmd7 6 CCB Command word from TTC 1=TMB 40MHz clock from CCB enabled Future use Bunch counter reset from CCB (backplane) Bunch crossing 0 from CCB (backplane) 1 Bits Adr 32 15 14 ccb clock en Default ADR_ALCT_CFG 13 12 11 10 0 CCB Status 9 8 7 1 0 0 0 0 0 0 alct seq cmd2 alct seq cmd1 4 3 2 1 0 alct seq cmd0 assert alct ext inj assert alct ext trg alct ext inj en alct ext trg en Description 1=Enable alct_ext_trig from CCB 1=Enable alct_ext_inject from CCB 1=Assert alct_ext_trig 1=Assert alct_ext_inject ALCT Sequencer command ALCT Reserved for future use Unassigned ALCT Injector Control 9 8 7 6 5 4 3 2 1 0 inject delay 4 inject delay 1 inject delay 0 link inject w clct start inject clear alct 0 0 Default 0 0 0 816 0 inject delay 3 inject delay 2 Description 1=Blank ALCT received data 1=Start ALCT injector State Machine 1=Link ALCT injector with CLCT inject command Injector delay Unassigned Page 22 of 83 06/11/04 1:58 PM Adr 34 15 14 0 ADR_ALCT0_INJ 13 12 11 10 0 0 1st bxn 1 1st bxn 0 1st key 6 ALCT0 1st Muon To Inject 9 8 7 6 5 4 1st key 5 Bits Dir Signal [00] [02:01] [03] [10:04] [12:11] [15:13] R/W R/W R/W R/W R/W R/W alct_first_valid alct_first_quality[1:0] alct_first_amu alct_first_key[6:0] alct_first_bxn[1:0] -- Adr 36 15 14 0 0 0 2nd bxn 0 2nd key 6 2nd key 5 Dir Signal [00] [02:01] [03] [10:04] [12:11] [15:13] R/W R/W R/W R/W R/W R/W alct_second_valid alct_second_quality[1:0] alct_second_amu alct_second_key[6:0] alct_second_bxn[1:0] -- 0 0 0 0 0 Bits Dir Signal [00] [02:01] [04:03] [08:05] [15:09] R R R R R alct_cfg_done seq_status[1:0] seu_status[1:0] reserved_out[3:0] -- 1st key 1 1st key 0 2nd key 4 3 st 1 amu 2nd key 3 1 2 0 6110 1 0 0 1 1st qualty 0 0 1st vpf Description 2nd key 2 2nd key 1 2nd key 0 3 nd 2 amu 2 2nd qualty 1 1 2nd qualty 0 0 2nd vpf Description Valid pattern flag Pattern quality Accelerator muon flag Injected ALCT1 key wire-group Injected ALCT1 bunch crossing number Unassigned ALCT Sequencer Control/Status 9 8 7 6 5 4 3 res out 3 2 1st qualty 1 Valid pattern flag Pattern quality Accelerator muon flag Injected ALCT0 key wire-group Injected ALCT0 bunch crossing number Unassigned Default ADR_ALCT_STAT 13 12 11 10 0 1 3 0 7 1 0 1st key 2 ALCT1 2nd Muon To Inject 9 8 7 6 5 4 Bits Adr 38 15 14 1st key 3 Default ADR_ALCT1_INJ 13 12 11 10 2nd bxn 1 1st key 4 res out 2 res out 1 res out 0 seu stat 1 seu stat 0 2 1 0 seq stat 1 seq stat 0 alct cfg done Typical Description 1 0 0 0 0 ALCT FPGA Configuration done ALCT Sequencer status ALCT Single-event-upset status Future use Unassigned Page 23 of 83 06/11/04 1:58 PM Adr 3A 15 14 0 ADR_ALCT0_RCD 13 12 11 10 0 0 1st bxn 1 1st bxn 0 1st key 6 ALCT 1st Muon Received by TMB 9 8 7 6 5 4 3 1st key 5 Bits Dir Signal [00] [02:01] [03] [10:04] [12:11] [15:13] R R R R R R alct_first_valid alct_first_quality[1:0] alct_first_amu alct_first_key[6:0] alct_first_bxn[1:0] -- Adr 3C 15 14 0 0 0 1st key 3 1st key 2 1st key 1 1st key 0 2nd bxn 0 2nd key 6 2nd key 5 Dir Signal [00] [02:01] [03] [10:04] [12:11] [15:13] R R R R R R alct_second_valid alct_second_quality[1:0] alct_second_amu alct_second_key[6:0] alct_second_bxn[1:0] -- 1 0-3 0 0-111 0-3 0 alct data17 alct data16 2 1st qualty 1 1 1st qualty 0 0 1st vpf Valid pattern flag Pattern quality Accelerator muon flag Injected ALCT0 key wire-group Injected ALCT0 bunch crossing number Unassigned 2nd key 4 2nd key 3 2nd key 2 2nd key 1 2nd key 0 nd 2 amu 2 2nd qualty 1 1 2nd qualty 0 0 2nd vpf Typical Description 1 0-3 0 0-111 0-3 0 Valid pattern flag Pattern quality Accelerator muon flag Injected ALCT1 key wire-group Injected ALCT1 bunch crossing number Unassigned Adr 3E ADR_ALCT_FIFO ALCT FIFO RAM Status (Split with Adr A2 ADR_ALCT_FIFO1 and A4 ADR_ALCT_FIFO2) 15 14 13 12 11 10 9 8 7 6 5 4 0 1 amu ALCT 2nd Muon Received by TMB 9 8 7 6 5 4 3 Bits alct wdcnt 10 st Typical Description ADR_ALCT0_RCD 13 12 11 10 2nd bxn 1 1st key 4 alct wdcnt 9 alct wdcnt 8 alct wdcnt 7 alct wdcnt 6 alct wdcnt 5 alct wdcnt 4 alct wdcnt 3 alct wdcnt 2 3 2 1 0 alct wdcnt 1 alct wdcnt 0 alct RAM done alct RAM busy Bits Dir Signal Description [00] [01] [12:02] [14:13] [15] R R R R R alct_raw_busy alct_raw_done alct_raw_wdcnt[10:0] alct_raw_rdata[17:16] -- ALCT raw hits FIFO busy writing ALCT data ALCT raw hits ready for VME readout ALCT raw hits word count stored in RAM ALCT raw hits data MSBs Unassigned 0 Page 24 of 83 06/11/04 1:58 PM Adr 40 15 14 0 ADR_DMB_MON 13 12 11 10 0 0 2nd bxn 1 2nd bxn 0 2nd key 6 DMB Monitored Signals 9 8 7 6 5 2nd key 5 Bits Dir Signal [02:00] [03] [08:04] [11:09] [15:12] R R R R R dmb_cfeb_calibrate[2:0] dmb_l1a_release dmb_reserved_out[4:0] dmb_reserved_in[2:0] dmb_rx_ff[3:0] Adr 42 15 14 inj start inj mask 3 inj mask 2 2nd key 3 2nd key 2 2nd key 1 4 2nd key 0 3 nd 2 amu 2 2nd qualty 1 1 2nd qualty 0 inj mask 1 inj mask 0 9 inj febsel 4 0 0 0 0 0 CFEB Injector Control 8 7 6 5 inj febsel 3 inj febsel 2 inj febsel 1 inj febsel 0 4 3 2 1 0 mask all cfeb4 mask all cfeb3 mask all cfeb2 mask all cfeb1 mask all cfeb0 Dir Signal Default Description [04:00] [09:05] [14:10] [15] R/W R/W R/W R/W mask_all[4:0] inj_febsel[4:0] injector_mask[4:0] inj_trig_vme 111112 0 111112 0 1=Enable, 0=Turn off all CFEBn inputs 1=Select CFEBn for RAM read/write Enable CFEBn for injector trigger Start pattern injector 0 0 ADR_CFEB_INJ_ADR CFEB Injector RAM Address 13 12 11 10 9 8 7 6 5 4 3 2 1 0 inj adr 7 inj ren 0 inj wen 2 inj wen 1 inj wen 0 inj adr 6 inj adr 5 inj adr 4 Bits Dir Signal [02:00] [05:03] [13:06] [15:14] R/W R/W R/W R/W inj_wen[2:0] inj_ren[2:0] inj_rwadr[7:0] -- Adr 46 15 14 inj wdata 15 inj wdata 14 2nd vpf DMB calibration DMB test DMB future use DMB future use DMB received Bits Adr 44 15 14 0 Typical Description ADR_CFEB_INJ 13 12 11 10 inj mask 4 2nd key 4 inj adr 3 inj adr 2 inj adr 1 Default 0 0 0 0 inj adr 0 inj ren 2 inj ren 1 Description 1=Write enable injector RAMn (Ly01,23,45) 1=Read enable Injector RAMn Injector RAM read/write address Unassigned ADR_CFEB_INJ_WDATA CFEB Injector Write Data 13 12 11 10 9 8 7 6 5 4 inj wdata 13 inj wdata 12 inj wdata 11 inj wdata 10 Bits Dir Signal [07:00] [15:08] R/W R/W inj_wdata[7:0] inj_wdata[15:8] inj wdata 9 inj wdata 8 inj wdata 7 Default 0 0 inj wdata 6 inj wdata 5 inj wdata 4 3 2 1 0 inj wdata 3 inj wdata 2 inj wdata 1 inj wdata 0 Description Triad bit for addressed Tbin Ly0 (or 2,4) Triad bit for addressed Tbin Ly1 (or 3,5) Page 25 of 83 06/11/04 1:58 PM Adr 48 15 14 inj rdata 15 ADR_CFEB_INJ_RDATA CFEB Injector Read Data 13 12 11 10 9 8 7 6 5 4 inj rdata 14 inj rdata 13 inj rdata 12 inj rdata 11 inj rdata 10 Bits Dir Signal [07:00] [15:08] R R inj_rdata[7:0] inj_rdata[15:8] Adr 4A 15 14 ly1 distrip 7 ly1 distrip 6 ly1 distrip 4 inj rdata 8 inj rdata 7 Default ADR_HCM001 13 12 11 ly1 distrip 5 inj rdata 9 ly1 distrip 3 0 0 inj rdata 5 inj rdata 4 3 2 1 0 inj rdata 3 inj rdata 2 inj rdata 1 inj rdata 0 Description Triad bit for addressed Tbin Ly0 (or 2,4) Triad bit for addressed Tbin Ly1 (or 3,5) CFEB0 Ly0,Ly1 Hot Channel Mask 9 8 7 6 5 4 3 10 ly1 distrip 2 inj rdata 6 ly1 distrip 1 ly1 distrip 0 ly0 distrip 7 ly0 distrip 5 ly0 distrip 4 ly0 distrip 3 2 1 0 ly0 distrip 2 ly0 distrip 1 ly0 distrip 0 Bits Dir Signal [07:00] [15:08] R/W R/W cfeb0_ly0_hcm[7:0] cfeb0_ly1_hcm[7:0] Adr 4C ADR_HCM023 R/W cfeb0_ly2_hcm[7:0] R/W cfeb0_ly3_hcm[7:0] CFEB0 Ly2,Ly3 Hot Channel Mask 111111112 1=Enable DiStrip[7:0] Layer 2 111111112 1=Enable DiStrip[7:0] Layer 3 ADR_HCM045 R/W cfeb0_ly4_hcm[7:0] R/W cfeb0_ly5_hcm[7:0] CFEB0 Ly4,Ly5 Hot Channel Mask 111111112 1=Enable DiStrip[7:0] Layer 4 111111112 1=Enable DiStrip[7:0] Layer 5 [07:00] [15:08] Adr 4E [07:00] [15:08] Adr 50 15 14 ly1 distrip 7 ly1 distrip 6 Default ly0 distrip 6 ADR_HCM101 13 12 11 ly1 distrip 5 ly1 distrip 4 ly1 distrip 3 1=Enable DiStrip[7:0] Layer 0 1=Enable DiStrip[7:0] Layer 1 CFEB1 Ly0,Ly1 Hot Channel Mask 9 8 7 6 5 4 3 10 ly1 distrip 2 111111112 111111112 Description ly1 distrip 1 ly1 distrip 0 ly0 distrip 7 ly0 distrip 5 ly0 distrip 4 ly0 distrip 3 2 1 0 ly0 distrip 2 ly0 distrip 1 ly0 distrip 0 Bits Dir Signal [07:00] [15:08] R/W R/W cfeb1_ly0_hcm[7:0] cfeb1_ly1_hcm[7:0] Adr 52 ADR_HCM123 R/W cfeb1_ly2_hcm[7:0] R/W cfeb1_ly3_hcm[7:0] CFEB1 Ly2,Ly3 Hot Channel Mask 111111112 1=Enable DiStrip[7:0] Layer 2 111111112 1=Enable DiStrip[7:0] Layer 3 ADR_HCM145 R/W cfeb0_ly4_hcm[7:0] R/W cfeb0_ly5_hcm[7:0] CFEB1 Ly4,Ly5 Hot Channel Mask 111111112 1=Enable DiStrip[7:0] Layer 4 111111112 1=Enable DiStrip[7:0] Layer 5 [07:00] [15:08] Adr 54 [07:00] [15:08] Default ly0 distrip 6 111111112 111111112 Description 1=Enable DiStrip[7:0] Layer 0 1=Enable DiStrip[7:0] Layer 1 Page 26 of 83 06/11/04 1:58 PM Adr 56 15 14 ly1 distrip 7 ly1 distrip 6 ADR_HCM201 13 12 11 ly1 distrip 5 ly1 distrip 4 ly1 distrip 3 CFEB2 Ly0,Ly1 Hot Channel Mask 9 8 7 6 5 4 3 10 ly1 distrip 2 ly1 distrip 1 ly1 distrip 0 ly0 distrip 7 ly0 distrip 5 ly0 distrip 4 ly0 distrip 3 2 1 0 ly0 distrip 2 ly0 distrip 1 ly0 distrip 0 Bits Dir Signal [07:00] [15:08] R/W R/W cfeb2_ly0_hcm[7:0] cfeb2_ly1_hcm[7:0] Adr 58 ADR_HCM223 R/W cfeb2_ly2_hcm[7:0] R/W cfeb2_ly3_hcm[7:0] CFEB2 Ly2,Ly3 Hot Channel Mask 111111112 1=Enable DiStrip[7:0] Layer 2 111111112 1=Enable DiStrip[7:0] Layer 3 ADR_HCM245 R/W cfeb2_ly4_hcm[7:0] R/W cfeb2_ly5_hcm[7:0] CFEB2 Ly4,Ly5 Hot Channel Mask 111111112 1=Enable DiStrip[7:0] Layer 4 111111112 1=Enable DiStrip[7:0] Layer 5 [07:00] [15:08] Adr 5A [07:00] [15:08] Adr 5C 15 14 ly1 distrip 7 ly1 distrip 6 Default ly0 distrip 6 ADR_HCM301 13 12 11 ly1 distrip 5 ly1 distrip 4 ly1 distrip 3 1=Enable DiStrip[7:0] Layer 0 1=Enable DiStrip[7:0] Layer 1 CFEB3 Ly0,Ly1 Hot Channel Mask 9 8 7 6 5 4 3 10 ly1 distrip 2 111111112 111111112 Description ly1 distrip 1 ly1 distrip 0 ly0 distrip 7 ly0 distrip 5 ly0 distrip 4 ly0 distrip 3 2 1 0 ly0 distrip 2 ly0 distrip 1 ly0 distrip 0 Bits Dir Signal [07:00] [15:08] R/W R/W cfeb3_ly0_hcm[7:0] cfeb3_ly1_hcm[7:0] Adr 5E ADR_HCM323 R/W cfeb3_ly2_hcm[7:0] R/W cfeb3_ly3_hcm[7:0] CFEB3 Ly2,Ly3 Hot Channel Mask 111111112 1=Enable DiStrip[7:0] Layer 2 111111112 1=Enable DiStrip[7:0] Layer 3 ADR_HCM345 R/W cfeb3_ly4_hcm[7:0] R/W cfeb3_ly5_hcm[7:0] CFEB3 Ly4,Ly5 Hot Channel Mask 111111112 1=Enable DiStrip[7:0] Layer 4 111111112 1=Enable DiStrip[7:0] Layer 5 [07:00] [15:08] Adr 60 [07:00] [15:08] Adr 62 15 14 ly1 distrip 7 ly1 distrip 6 Default ly0 distrip 6 ADR_HCM401 13 12 11 ly1 distrip 5 ly1 distrip 4 ly1 distrip 3 1=Enable DiStrip[7:0] Layer 0 1=Enable DiStrip[7:0] Layer 1 CFEB4 Ly0,Ly1 Hot Channel Mask 9 8 7 6 5 4 3 10 ly1 distrip 2 111111112 111111112 Description ly1 distrip 1 Bits Dir Signal [07:00] [15:08] R/W R/W cfeb4_ly0_hcm[7:0] cfeb4_ly1_hcm[7:0] ly1 distrip 0 ly0 distrip 7 Default 111111112 111111112 ly0 distrip 6 ly0 distrip 5 ly0 distrip 4 ly0 distrip 3 2 1 0 ly0 distrip 2 ly0 distrip 1 ly0 distrip 0 Description 1=Enable DiStrip[7:0] Layer 0 1=Enable DiStrip[7:0] Layer 1 Page 27 of 83 06/11/04 1:58 PM Adr 64 [07:00] [15:08] Adr 66 [07:00] [15:08] ADR_HCM423 R/W cfeb4_ly2_hcm[7:0] R/W cfeb4_ly3_hcm[7:0] CFEB4 Ly2,Ly3 Hot Channel Mask 111111112 1=Enable DiStrip[7:0] Layer 2 111111112 1=Enable DiStrip[7:0] Layer 3 ADR_HCM445 R/W cfeb4_ly4_hcm[7:0] R/W cfeb4_ly5_hcm[7:0] CFEB4 Ly4,Ly5 Hot Channel Mask 111111112 1=Enable DiStrip[7:0] Layer 4 111111112 1=Enable DiStrip[7:0] Layer 5 Adr 68 15 14 0 ADR_SEQ_TRIG_EN 13 12 11 10 0 0 0 0 0 Bits Dir Signal [00] [01] [02] [03] [04] [05] [06] [07] [08] [09] [15:10] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W clct_pat_trig_en alct_pat_trig_en match_pat_trig_en adb_ext_trig_en dmb_ext_trig_en clct_ext_trig_en alct_ext_trig_en vme_ext_trig ext_trig_inject all_cfebs_active -- Adr 6A 15 14 adb delay 3 Sequencer Trigger Source Enables 9 8 7 6 5 4 3 alct ext trig en all cfebs active ext trig inject Default Description 1 0 0 0 0 0 0 0 0 0 0 vme trig clct ext trig en adb ext trig en adb ext trig en adb delay 2 adb delay 1 adb delay 0 alct aff delay 2 alct aff delay 1 Bits Dir Signal [03:00] [07:04] [11:08] [15:12] R/W R/W R/W R/W alct_trig_width[3:0] alct_pre_trig_dly alct_pat_trig_dly[3:0] adb_ext_trig_dly[3:0] 1 0 alct pat trig en clct pat trig en pat trig en 1=Allow CLCT pattern triggers (CLCT Active FEB) 1=Allow ALCT pattern triggers (ALCT Active FEB) 1=ALCT*CLCT pattern triggers 1=Allow ADB external triggers from CCB 1=Allow DMB external triggers 1=Allow CLCT external triggers (scintillator) from CCB 1=Allow ALCT external triggers from CCB 1=Initiate Sequencer trigger (write 0 to recover) 1=Change clct_ext_trig to fire pattern injector 1=Make all CFEBs active when triggered Unassigned ADR_SEQ_TRIG_DLY0 Sequencer Trigger Source Delays 13 12 11 10 9 8 7 6 5 4 3 alct aff delay 3 2 alct*clct alct aff delay 0 alct pretrig delay Default 3 0 (2) 0 1 alct pretrig delay 2 alct pretrig delay 1 alct pretrig delay 0 alct width 3 2 1 0 alct width 2 alct width 1 alct width 0 Description ALCTCLCT Pre-trigger window width ALCT Pre-trigger delay for ALCT*CLCT Delay alct_pat_trig (active feb flag from ALCT) Delay adb_ext_trig from CCB Page 28 of 83 06/11/04 1:58 PM Adr 6C 15 14 0 ADR_SEQ_TRIG_DLY1 Sequencer Trigger Source Delays 13 12 11 10 9 8 7 6 5 4 3 0 0 0 alct ext delay 3 alct ext delay 2 alct ext delay 1 Bits Dir Signal [03:00] [07:04] [11:08] [15:12] R/W R/W R/W R/W dmb_ext_trig_dly[3:0] clct_ext_trig_dly[3:0] alct_ext_trig_dly[3:0] -- Adr 6E 15 14 0 0 Default clct ext delay 1 clct ext delay 0 run id 1 run id 0 Signal [04:00] [08:05] [12:09] [15:13] R/W R/W R/W R/W board_id[4:0] csc_id[3:0] run_id[3:0] -- nph patrn 2 csd id 2 Default 21 5 0 0 ADR_SEQ_CLCT 13 12 11 10 drft delay 0 csd id 3 nph patrn 1 nph patrn 0 Bits Dir Signal [03:00] [06:04] [09:07] [12:10] [14:13] [15] R/W R/W R/W R/W R/W R/W triad_persist hs_thresh[2:0] ds_thresh[2:0] nph_pattern[2:0] drift_delay[1:0] pretrig_halt csd id 1 csd id 0 board id 4 ds thresh 1 0 dmb ext delay 0 3 2 1 0 board id 3 board id 2 board id 1 board id 0 Board ID = VME Slot Geographic Adr CSC Chamber ID number Run ID number Unassigned ds thresh 0 Default 5 4 4 4 2 0 1 dmb ext delay 1 Description Sequencer CLCT Configuration 9 8 7 6 5 4 ds thresh 2 2 dmb ext delay 2 Delay dmb_ext_trig from DMB Delay clct_ext_trig (scintillator) from CCB Delay alct_ext_trig from CCB Unassigned 10 run id 2 dmb ext delay 3 Description run id 3 Dir pretrig halt 1 7 7 0 clct ext delay 2 Sequencer Board + CSC Ids 9 8 7 6 5 4 Bits drft delay 0 clct ext delay 3 ADR_SEQ_ID 13 12 11 0 Adr 70 15 14 alct ext delay 0 hs thresh 2 hs thresh 1 hs thresh 0 3 2 1 0 triad persist 3 triad persist 2 triad persist 1 triad persist 0 Description Triad One-Shot Persistence (5=150ns) ½-Strip Pre-trigger threshold Di-Strip Pre-trigger threshold Minimum pattern hits for a valid pattern CSC Drift delay, number 25ns clock periods Pretrigger and halt until unhalt arrives Page 29 of 83 06/11/04 1:58 PM Adr 72 15 14 0 ADR_SEQ_FIFO 13 12 11 10 0 0 fifo pretrig 4 fifo pretrig 3 fifo pretrig 2 Sequencer FIFO Configuration 9 8 7 6 5 4 fifo pretrig 1 Bits Dir Signal [02:00] R/W fifo_mode[2:0] 1 [07:03] [12:08] [15:13] R/W R/W R/W fifo_tbins[4:0] fifo_pretrig[4:0] -- 7 2 0 Adr 74 15 14 0 Default ADR_SEQ_L1A 13 12 11 0 0 l1a intern l1a windo 3 10 l1a windo 2 Bits Dir Signal [07:00] [11:08] [12] [15:13] R/W R/W R/W R/W l1a_delay[7:0] l1a_window[3:0] l1a_internal -- Adr 76 15 14 bxn offset 11 bxn offset 10 bxn offset 8 bxn offset 7 bxn offset 6 Bits Dir Signal [03:00] [15:04] R/W R/W l1a_offset[3:0] bxn_ofset[11:0] fifo tbins 4 fifo tbins 3 fifo tbins 2 fifo tbins 1 3 2 1 0 fifo tbins 0 fifo mode 2 fifo mode 1 fifo mode 0 Description FIFO Mode: 0=no CFEB raw hits full header 1=all CFEB raw hits full header 2=local CFEB raw hits full header 3=no CFEB raw hits short header 4=no CFEB raw hits no header Number FIFO time bins to read out Number FIFO time bins before pretrigger Unassigned Sequencer L1A Configuration 9 8 7 6 5 4 l1a windo 1 l1a windo 0 Default ADR_SEQ_OFFSET 13 12 11 10 bxn offset 9 fifo pretrig 0 12810 3 0 0 l1a delay 7 l1a delay 6 l1a delay 5 l1a delay 4 3 2 1 0 l1a delay 3 l1a delay 2 l1a delay 1 l1a delay 0 Description Level1 Accept delay from pretrig status output Level1 Accept window width after delay Generate internal Level 1, overrides external Unassigned Sequencer Counter Offsets 9 8 7 6 5 4 bxn offset 5 bxn offset 4 Default 0 0 bxn offset 3 bxn offset 2 bxn offset 1 bxn offset 0 3 2 1 0 l1a offset 3 l1a offset 2 l1a offset 1 l1a offset 0 Description L1A counter preset value BXN offset at reset Page 30 of 83 06/11/04 1:58 PM Adr 78 15 1st cfeb 1 14 1st cfeb 0 ADR_SEQ_CLCT0 Sequencer Latched CLCT0 (LSBs) (Split with Adr B0 ADR_SEQCLCTM) 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bend pat 0 hits pat 1 hits pat 0 1st vpf 1st key 4 1st key 3 1st key 2 1st key 1 1st key 0 hs/ds pat 3 shape pat 2 shape pat 1 Bits Dir Signal Typical Description [00] [03:01] [06:04] [07] [08] [13:09] [16:14] [18:17] [19] [20] R R R R R R R R R R clct_first_valid clct_first_nhit[2:0] clct_first_pat[2:0] clct_first_pat[3] clct_first_pat[0] clct_first_key[4:0] clct_first_cfeb[2:0] clct_first_bxn[1:0] sync_err bx0_local 1 4-6 0-7 0-1 0 0-3110 0-4 0-3 0 0 Adr 7A 15 2nd cfeb 1 14 2nd cfeb 0 shape pat 0 hits pat 2 Valid pattern flag Hits on pattern: 0 to 6 Pattern shape 0 to 7 1=½-Strip, 0=Di-Strip Bend direction (=pattern lsb with current pattern set) Key ½-strip (Di-Strips point to lower ½-Strip) Key CFEB ID Bunch crossing number Sync error BXN=0 on this TMB ADR_SEQ_CLCT1 Sequencer Latched CLCT1 (LSBs) (Split with Adr B0 ADR_SEQCLCTM) 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bend pat 0 hits pat 1 hits pat 0 2nd vpf 2nd key 4 2nd key 3 2nd key 2 2nd key 1 2nd key 0 hs/ds pat 3 shape pat 2 shape pat 1 Bits Dir Signal Typical Description [00] [03:01] [06:04] [07] [08] [13:09] [16:14] [18:17] [19] [20] R R R R R R R R R R clct_second_valid clct_second_nhit[2:0] clct_second_pat[2:0] clct_second_pat[3] clct_second_pat[0] clct_second_key[4:0] clct_second_cfeb[2:0] clct_second_bxn[1:0] sync_err bx0_local 1 4-6 0-7 0-1 0 0-3110 0-4 0-3 0 0 shape pat 0 hits pat 2 Valid pattern flag Hits on pattern: 0 to 6 Pattern shape 0 to 7 1=½-Strip, 0=Di-Strip Bend direction (=pattern lsb with current pattern set) Key ½-strip (Di-Strips point to lower ½-Strip) Key CFEB ID Bunch crossing number Sync error BXN=0 on this TMB Page 31 of 83 06/11/04 1:58 PM Adr 7C 15 14 0 ADR_SEQ_TRIG_SRC Sequencer Trigger Source Read-back 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 Bits Dir Signal [00] [01] [02] [03] [04] [05] [06] [07] [15:07] R R R R R R R R R/W clct_pat_trig_en alct_pat_trig_en match_pat_trig_en adb_ext_trig_en dmb_ext_trig_en clct_ext_trig_en alct_ext_trig_en vme_ext_trig -- Adr 7E 15 14 dmb wdata 17 1 0 0 0 0 0 0 0 0 dmb reset dmb wr dmb adr 11 dmb adr 10 Dir Signal [11:00] [12] [13] [15:14] R/W R/W R/W R/W dmb_adr[11:0] dmb_wr dmb_reset dmb_wdata[17:16] Adr 80 15 14 adb ext trig en dmb adr 9 dmb adr 8 dmb adr 7 Default 0 0 0 0 dmb adr 6 dmb adr 5 dmb wdata 12 2 1 0 alct*clct alct pat trig en clct pat trig en pat trig en 4 3 2 1 0 dmb adr 4 dmb adr 3 dmb adr 2 dmb adr 1 dmb adr 0 Description Raw hits RAM VME read/write address Raw hits RAM VME write enable Raw hits RAM VME address reset Raw hits RAM VME write data MSBs ADR_DMB_RAM_WDATASequencer RAM Write Data 13 12 11 10 9 8 7 6 5 4 dmb wdata 13 adb ext trig en CLCT pattern triggered sequencer ALCT pattern triggered sequencer ALCT*CLCT pattern triggered sequencer ADB external triggered sequencer DMB external triggered sequencer CLCT (CCB scintillator) external triggered sequencer ALCT (CCB) external triggered sequencer VME triggered sequencer Unassigned ADR_DMB_RAM_ADR Sequencer RAM Address 13 12 11 10 9 8 7 6 5 dmb wdata 16 dmb wdata 14 vme trig 0 clct ext trig en Typical Description Bits dmb wdata 15 0 alct ext trig en dmb wdata 11 dmb wdata 10 Bits Dir Signal [15:00] R/W dmb_wdata[15:0] dmb wdata 9 dmb wdata 8 dmb wdata 7 Default 0 dmb wdata 6 dmb wdata 5 dmb wdata 4 3 2 1 0 dmb wdata 3 dmb wdata 2 dmb wdata 1 dmb wdata 16 Description Raw hits RAM VME write data (msb in adr 76) Page 32 of 83 06/11/04 1:58 PM Adr 82 15 14 0 ADR_DMB_RAM_WDCNTSequencer RAM Word Count 13 12 11 10 9 8 7 6 5 4 dmb rdata 17 dmb busy dmb wdata 16 dmb wdcnt 11 dmb wdcnt 10 Bits Dir Signal [11:00] [13:12] [14] [15] R R R R dmb_wdcnt[11: 0] dmb_rdata[17:16]; dmb_busy -- Adr 84 15 14 dmb rdata 15 dmb wdcnt 8 dmb wdcnt 7 Default 0 0 0 0 dmb wdcnt 6 dmb wdcnt 5 dmb wdcnt 4 dmb rdata 14 dmb rdata 13 dmb rdata 12 dmb rdata 11 dmb rdata 10 Dir Signal [15:00] R dmb_rdata[15:0] Adr 86 15 14 0 dmb rdata 8 Default ADR_TMB_TRIG 13 12 11 10 0 dmb rdata 9 mpc mpc reserved reserved 1 0 mpc accept 1 0 3 2 1 0 dmb wdcnt 3 dmb wdcnt 2 dmb wdcnt 1 dmb wdcnt 0 Description Raw hits RAM VME word count Raw hits RAM VME read data MSBs Raw hits RAM VME Unassigned ADR_DMB_RAM_RDATA Sequencer RAM Read Data 13 12 11 10 9 8 7 6 5 4 Bits 0 dmb wdcnt 9 dmb rdata 7 dmb rdata 6 dmb rdata 5 dmb rdata 4 3 2 1 0 dmb rdata 3 dmb rdata 2 dmb rdata 1 dmb rdata 16 Description Raw hits RAM VME read data (msb in adr 7A) TMB Trigger Configuration / MPC Accept 9 8 7 6 5 4 3 2 mpc accept 0 Bits Dir Signal [01:00] [02] [03] [04] [08:05] [10:09] [12:11] [15:13] R/W R/W R/W R/W R/W R R R/W tmb_sync_err_en[1:0] tmb_allow_alct tmb_allow_clct tmb_allow_match mpc_rx_delay[3:0] mpc_accept[1:0] mpc_reserved[1:0] -- mpc delay 3 Default 112 0 1 1 7 0 mpc delay 2 mpc delay 1 mpc delay 0 allow clct+alct match allow clct only allow alct only 1 0 sync err en 1 sync err en 0 Description Allow sync_err to MPC for either muon Allow ALCT-only L1A (not used in current version) Allow CLCT0-only L1A Allow ALCT+CLCT match pre-trigger MPC accept response delay MPC accept latched after delay MPC reserved latched after delay Unassigned Page 33 of 83 06/11/04 1:58 PM Adr 88 15 14 st 1 vpf ADR_MPC0_FRAME0 MPC0 Frame0 Data Sent to MPC 13 12 11 10 9 8 7 6 5 4 3 lct 1st q 2 lct 1st q 3 lct 1st q 1 lct 1st q 0 clct 1st hsds clct 1st pat 2 clct 1st pat 1 clct 1st pat 0 alct 1st wg 6 alct 1st wg 5 Bits Dir Signal Typical Description [06:00] [09:07] [10] [14:11] [15] R R R R R alct_first_key[6:0] clct_first_pat[2:0] clct_first_hsds lct_first_quality[3:0] first_vpf 0-11110 4-6 0-1 8 1 Adr 8A 15 14 csc id 3 ADR_MPC0_FRAME1 MPC0 Frame1 Data Sent to MPC 13 12 11 10 9 8 7 6 5 4 3 csc id 2 csc id 1 csc id 0 tmb bx0 local alct 1st bxn 0 sync err clct 1st key 7 clct 1st bend clct 1st key 6 clct 1st key 5 Dir Signal Typical Description [07:00] [08] [09] [10] [11] [15:12] R R R R R R clct_first_key[7:0] clct_first_bend sync_err alct_first_bxn[0] clct_first_bx0_local csc_id[3:0] 0-15910 0 0 0-1 0-1 1-9 Adr 8C 15 14 2 vpf alct 1st wg 3 clct 1st key 4 clct 1st key 3 lct 2nd q 2 lct 2nd q 1 lct 2nd q 0 clct 2nd hsds clct 2nd pat 2 clct 2nd pat 1 1 0 alct 1st wg 1 alct 1st wg 0 2 1 0 clct 1st key 2 clct 1st key 1 clct 1st key 0 CLCT first muon key ½-strip CLCT first muon bend direction BXN does not match at BX0 ALCT first muon bunch crossing number 1=TMBs bxn[11:0]==0 CSC chamber ID ADR_MPC1_FRAME0 MPC1 Frame0 Data Sent to MPC 13 12 11 10 9 8 7 6 5 4 3 lct 2nd q 3 2 alct 1st wg 2 ALCT first key wire-group CLCT first pattern number CLCT 1=1/2-Strip Pattern, 0=DiStrip Pattern LCT first muon quality First valid pattern flag Bits nd alct 1st wg 4 clct 2nd pat 0 alct 2nd wg 6 alct 2nd wg 5 alct 2nd wg 4 alct 2nd wg 3 2 1 0 alct 2nd wg 2 alct 2nd wg 1 alct 2nd wg 0 5 Bits Dir Signal Typical Description [06:00] [09:07] [10] [14:11] [15] R R R R R alct_second_key[6:0] clct_second_pat[2:0] clct_second_hsds lct_second_quality[3:0] second_vpf 0-11110 4-6 0-1 8 1 ALCT second key wire-group CLCT second pattern number CLCT 1=1/2-Strip Pattern, 0=DiStrip Pattern LCT second muon quality Second valid pattern flag Page 34 of 83 06/11/04 1:58 PM Adr 8E 15 14 csc id 3 ADR_MPC1_FRAME1 MPC1 Frame1 Data Sent to MPC 13 12 11 10 9 8 7 6 5 4 3 csc id 2 csc id 1 csc id 0 tmb bx0 local alct 2nd bxn 0 sync err clct 2nd key 7 clct 2nd bend clct 2nd key 6 clct 2nd key 5 Bits Dir Signal Typical Description [07:00] [08] [09] [10] [11] [15:12] R R R R R R clct_second_key[7:0] clct_second_bend sync_err alct_second_bxn[0] clct_second_bx0_local csc_id[3:0] 0-15910 0 0 0-1 0-1 1-9 Adr 90 15 14 0 ADR_MPC_INJ 13 12 11 0 0 mpc reserv 1 mpc reserv 0 10 mpc accept 1 Bits Dir Signal [07:00] [08] [09] [11:10] [13:12] [15:14] R/W R/W R/W R R R/W mpc_nframes[7:0] mpc_inject ttc_mpc_inj_en mpc_accept[1:0] mpc_reserved[1:0] -- Adr 92 15 14 mpc adr 7 5 0 1 0 mpc nfram 6 mpc nfram 5 mpc adr 5 mpc adr 4 mpc adr 3 mpc adr 2 Dir Signal [03:00] [07:04] [15:08] R/W R/W R/W mpc_wen[3:0] mpc_ren[3:0] mpc_adr[7:0] Adr 94 15 14 mpc adr 1 mpc wdata 4 mpc wdata 2 mpc adr 0 3 2 1 0 mpc nfram 3 mpc nfram 2 mpc nfram 1 mpc nfram 0 Description mpc ren 3 0 0 0 Bits Dir Signal [15:00] R/W mpc_wdata[15:0] mpc wdata 1 mpc wdata 0 mpc ren 2 mpc ren 1 mpc ren 0 3 2 1 0 mpc wen 3 mpc wen 2 mpc wen 1 mpc wen 0 Description Select RAM to write Select RAM to read Injector RAM read/write address mpc wdata 3 Default 0 0 clct 2nd key 0 Number frames to inject 1=Start MPC test pattern injector 1=Enable injector start by TTC command MPC accept stored at injector RAM address MPC reserved stored at injector RAM address Unassigned Default mpc wdata 3 1 clct 2nd key 1 4 ADR_MPC_RAM_WDATA MPC Injector RAM Write Data 13 12 11 10 9 8 7 6 5 4 mpc wdata 5 2 clct 2nd key 2 mpc nfram 4 ADR_MPC_RAM_ADR MPC Injector RAM Address 13 12 11 10 9 8 7 6 5 4 mpc adr 6 mpc wdata 6 mpc nfram 7 Default Bits mpc wdata 7 mpc inject clct 2nd key 3 CLCT second muon key ½-strip CLCT second muon bend direction BXN does not match at BX0 ALCT second muon bunch crossing number 1=TMBs bxn[11:0]==0 CSC chamber ID MPC Injector Control 9 8 7 6 5 mpc accept 0 clct 2nd key 4 mpc wdata 2 mpc wdata 1 mpc wdata 0 3 2 1 0 mpc wdata 3 mpc wdata 2 mpc wdata 1 mpc wdata 0 Description MPC Injector RAM write data Page 35 of 83 06/11/04 1:58 PM Adr 96 15 14 mpc rdata 7 ADR_MPC_RAM_RDATA MPC Injector RAM Read Data 13 12 11 10 9 8 7 6 5 4 mpc rdata 6 mpc rdata 5 mpc rdata 4 mpc rdata 3 mpc rdata 2 Bits Dir Signal [15:00] R mpc_rdata[15:0] Adr 98 15 14 radr 7 radr 5 radr 4 radr 3 radr 2 Dir Signal [00] [01] [04:02] [05] [06] [07] [15:08] R/W R/W R/W R/W R R R/W scp_runstop scp_force_trig scp_ram_sel[2:0] scp_auto scp_waiting scp_trig_done scp_radr[7:0] Adr 9A 15 14 scp ch 14 mpc rdata 3 mpc rdata 2 mpc rdata 1 radr 0 3 2 1 0 mpc rdata 3 mpc rdata 2 mpc rdata 1 mpc rdata 0 0 MPC Injector RAM read data Scope Control 9 8 7 6 radr 1 mpc rdata 0 Description 0 ADR_SCP_CTRL 13 12 11 10 radr 6 mpc rdata 0 Default Bits scp ch 15 mpc rdata 1 trig done Default waitin for trigger 5 4 3 2 1 auto ram sel 2 ram sel 1 ram sel 0 force Description 0 0 0 0 1=Run, 0=Stop 1=Force a trigger (set 0,1,0 in 3 writes) RAM bank to read / last RAM adr if scp_auto=1 Sequencer readout mode 1=insert in DMB data Scope waiting for trigger Scope triggered, ready for readout Scope data read address ADR_SCP_RDATA 13 12 11 10 Scope Read data 9 8 7 6 5 4 3 2 1 0 scp ch 13 scp ch 9 scp ch 5 scp ch 4 scp ch 3 scp ch 2 scp ch 1 scp ch 0 scp ch 12 scp ch 11 scp ch 10 scp ch 8 scp ch 7 scp ch 6 Bits Dir Signal Description [15:00] R scp_data[15:0] See channel assignments on page 44 Adr 9C 15 14 ccb cmd 7 ADR_CCB_CMD 13 12 11 10 ccb cmd 6 run stop ccb cmd 5 ccb cmd 4 ccb cmd 3 ccb cmd 2 CCB TTC Command Generator (Internal) 9 8 7 6 5 4 3 2 ccb cmd 1 Bits Dir Signal [00] [01] [02] [03] [05:04] [07:06] [15:08] R/W R/W R/W R/W R R/W R/W vme_ccb_cmd_enable vme_ccb_cmd_strobe vme_ccb_data_strobe ccb cmd 0 Default vme_ccb_subaddr_strobe 0 0 0 0 fmm_state[1:0] vme_ccb_cmd[7:0] 0 0 0 fmm state 1 fmm state 0 subadr strobe data strobe 1 0 brcst strobe dis con ccb Description 1=Disconnect CCB backplane ccb_cmd[7:0] 1=Assert internal ccb_cmd brcst strobe 1=Assert internal ccb_cmd data strobe 1=Assert internal ccb_cmd sub-adr strobe FMM machine state Unassigned TTC command to generate Page 36 of 83 06/11/04 1:58 PM Adr 9E 15 14 buffer busy 7 buffer busy 6 ADR_BUF_STAT 13 12 11 10 buffer busy 5 buffer busy 4 buffer busy 3 buffer busy 2 Buffer Status 9 8 7 buffer busy 1 buffer busy 0 peak busy 3 6 5 4 3 2 1 0 peak busy 2 peak busy 1 peak busy 0 nbusy 3 nbusy 2 nbusy 1 nbusy 0 Bits Dir Signal Description [03:00] [07:04] [15:08] R R R buf_nbusy[3:0] buf_nbusy_peak[3:0] buf_busy[7:0] Number of buffer busy Peak buffer usage List of busy buffers Adr A0 15 14 0 ADR_SRLPGM 13 12 11 0 0 0 0 Bits Dir Signal [04:00] [09:05] [10] [15:11] R R R R srl_hsq[4:0] srl_dsq[4:0] srl_resq - Adr A2 15 10 srl dsq 4 resq 0 srl dsq 3 srl dsq 2 Default 0 srl dsq 1 5 4 3 2 1 0 srl dsq 0 srl hsq 4 srl hsq 3 srl hsq 2 srl hsq 1 srl hsq 0 Description CFEB ½-Strip SRL serial data out CFEB Di-Strip SRL serial data out Resolver SRL serial data out Unassigned ADR_ALCTFIFO1 ALCT Raw Hits RAM Control (Split with Adr 3E ADR_ALCT_FIFO0 and Adr A4 ADR_ALCT_FIFO2) 14 0 SRL LUT Program 9 8 7 6 13 0 0 12 11 10 9 8 7 6 5 4 3 2 1 0 0 alct radr 10 alct radr 9 alct radr 8 alct radr 7 alct radr 6 alct radr 5 alct radr 4 alct radr 3 alct radr 2 alct radr 1 alct radr 0 alct raw reset Bits Dir Signal [00] [11:01] [12] [15:13] R/W R/W R/W R/W alct_raw_reset alct_raw_radr[10:0] alct_raw_sync -- Adr A4 Default 0 0 0 0 Description Reset ALCT raw hits FIFO controller ALCT raw hits RAM address to read 1=Sync alct FIFO write to TMB readout Unassigned 15 14 ADR_ALCTFIFO2 ALCT Raw Hits RAM data (LSBs) (Split with Adr 3E ADR_ALCT_FIFO0 and Adr A2 ADR_ALCT_FIFO1) 13 12 11 10 9 8 7 6 5 4 3 2 alct fifo 15 alct fifo 14 alct fifo 13 alct fifo 12 alct fifo 11 alct fifo 10 Bits Dir Signal [15:00] R alct_raw_rdata[15:0] alct fifo 9 alct fifo 8 Default alct fifo 7 alct fifo 6 alct fifo 5 alct fifo 4 alct fifo 3 alct fifo 2 1 0 alct fifo 1 alct fifo 0 Description ALCT FIFO data (msbs in adr_alct_fifo) Page 37 of 83 06/11/04 1:58 PM Adr A6 15 14 hs 15 ADR_ADJCFEB0 13 12 11 10 hs 14 hs 13 hs 12 hs 11 hs 10 Bits Dir Signal [15:00] R/W adjcfeb_mask_hs[15:0] Adr A8 15 14 hs 31 hs 29 hs 28 hs 27 hs 26 Bits Dir Signal [15:00] R/W adjcfeb_mask_hs[31:16] Adr AA 15 14 0 0 0 1 0 hs 2 hs 1 hs 0 1 0 hs 16 hs 22 hs 21 0 adjcfeb_mask_ds[7:0] - ADR_SEQMOD 13 12 11 10 ds 7 ds 6 ds 5 4 3 2 1 0 ds 4 ds 3 ds 2 ds 1 ds 0 Description 1=Enable DiStrip for adjecent CFEB hit in aff Unassigned Sequencer Trigger Modifiers 9 8 7 6 5 4 L1A no tmb L1A tmb trig Bits Dir Signal Default [03:00] [04] [05] R/W R/W R/W clct_flush_delay[3:0] clct_turbo ranlct_enable 1 0 0 [06] [07] [08] [09] [10} [11] [12] [13] [15:14] R/W R/W R/W R/W R/W R/W R/W R R/W wr_buf_required valid_clct_required l1a_allow_match l1a_allow_notmb l1a_allow_nol1a l1a_allow_alct_only scint_veto_clr scint_veto_vme -- 1 1 1 0 0 0 0 0 hs 19 1=Enable ½-Strip for adjecent CFEB hit in aff 0 8116 0 hs 20 Description CFEB Adjacent ds Mask 9 8 7 6 5 R/W R/W 0 hs 23 F000 [07:00] [15:08] 0 Description hs 17 0 L1A tmb nol1a hs 3 2 hs 24 Default L1A alct only hs 4 hs 18 Signal Clear scint veto hs 5 1=Enable ½-Strip for adjecent CFEB hit in aff Default 0 hs 6 hs 25 Dir Scint veto state hs 7 CFEB Adjacent hs Mask (MSBs) 9 8 7 6 5 4 3 Bits Adr AC 15 14 hs 8 000F ADR_ADJCFEB2 13 12 11 10 0 2 hs 9 Default ADR_ADJCFEB1 13 12 11 10 hs 30 CFEB Adjacent hs Mask (LSBs) 9 8 7 6 5 4 3 valid clct requir wr buf requir ranlct clct turbo 3 2 1 0 flush timer 3 flush timer 2 flush timer 1 flush timer 0 Description Trigger sequencer flush state timer Trigger sequencer turbo mode! (no raw hits) 1=Enable OSU random LCT generator Requires external trigger mode + pat thresh=7 Require wr_buffer available to pre-trigger Require valid CLCT after drift delay Readout allows tmb trig pulse in L1A window Readout allows notmb trig pulse in L1A window Readout allows tmb trig pulse outside L1A wind Allow ALCT-only events to readout at L1A Clear scintillator veto FF Scintillator veto FF state Unassigned Page 38 of 83 06/11/04 1:58 PM Adr AE 15 14 0 ADR_SEQSM 13 12 11 stack udf stack ovf stack empty stack full 10 read sm 4 Sequencer Machine State 9 8 7 6 5 read sm 3 read sm 2 read sm 1 read sm 0 tmb sm 2 4 3 2 1 0 tmb sm 1 tmb sm 0 clct sm 2 clct sm 1 clct sm 0 Bits Dir Signal Description [02:00] [05:03] [10:06] [11] [12] [13] [14] [15] R R R R R R R R clct_sm[2:0] tmb_sm[2:0] read_sm[4:0] stack_full stack_empty stack_ovf stack_udf -- CLCT Trigger machine state TMB Match machine state Readout machine state Readout stack full Readout stack empty Attempt to push new even when stack full Attepmt to pop stack when empty Unassigned Adr B0 15 14 0 0 0 ADR_SEQCLCTM Sequencer CLCT (MSBs) (Split with Adr 78 ADR_SEQCLCT0 and Adr 7A ADR_SEQCLCT1) 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 2nd clct 20 2nd clct 19 2nd clct 18 2nd clct 17 2nd clct 16 1st clct 20 1st clct 19 2 1st clct 18 1 1st clct 17 0 1st clct 16 Bits Dir Signal Description [04:00] [09:05] [15:10] R R R clct_first[20:16] clct_second[20:16] -- First CLCT MSBs (see 78 ADR_SEQCLCT0) Second CLCT MSBs (see 78 ADR_SEQCLCT0) Unassigned Adr B2 15 14 0 ADR_TMBTIM 13 12 11 0 0 0 0 10 0 Bits Dir Signal [03:00] [07:04] [11:08] [15:12] R/W R/W R/W R/W alct_delay[3:0] clct_width[3:0] mpc_tx_delay[3:0] -- 0 TMB Timing for ALCT*CLCT Coincidence 9 8 7 6 5 4 3 2 0 clct width 3 0 Default 1 3 0 0 clct width 2 clct width 1 clct width 0 alct delay 3 alct delay 2 1 0 alct delay 1 alct delay 0 Description Delay ALCT for CLCT match window CLCT match window width MPC transmit delay Unassigned Page 39 of 83 06/11/04 1:58 PM Adr B4 15 14 0 ADR_LHC_CYCLE 13 12 11 10 0 0 0 lhc cycle 11 lhc cycle 10 Bits Dir Signal [11:00] R/W lhc_cycle[11:0] [15:12] R/W -- Adr B6 15 14 0 0 read bxn 1 read bxn 0 read bank 1 Dir Signal [03:00] [04] [08:05] [10:09] [13:11] [15:14] R/W R/W R/W R/W R R/W rpc_exists[3:0] rpc_read_enable rpc_bxn_offset[3:0] rpc_bank[1:0] rpc_rbxn[2:0] -- rdata 15 rdata 13 rdata 12 lhc cycle 7 3564 rdata 11 rdata 10 Bits Dir Signal [15:00] R rpc_rdata[15:0] lhc cycle 6 lhc cycle 5 bxn offset 3 bxn offset 2 F 1 0 0 0 bxn offset 1 4 3 2 1 0 read enable rpc3 exists rpc2 exists rpc1 exists rpc0 exists Description Bit (n) = 1 = RPC(n) Exists, F=all 4 exist 1=Include Existing RPCs in DMB Readout RPC BXN offset RPC bank address, for reading rdata sync mode RPC rdata[18:16] msbs for sync mode, adr 1E Unassigned rdata 9 rdata 8 - rdata 7 rdata 6 rdata 5 rdata 4 Bits Dir Signal [03:00] [07:04] [11:08] [15:12] R/W R/W R/W R/W rpc0_delay[3:0] rpc1_delay[3:0] rpc2_delay[3:0] rpc3_delay[3:0] rpc2 delay 0 Default 1 1 1 1 rdata 2 rdata 1 0 rdata 0 RPC RAM read data for sync mode rpc3 delay 1 rpc2 delay 1 rdata 3 Description rpc3 delay 3 rpc2 delay 2 lhc cycle 0 RPC Raw Hits Sync Mode Read Data, See Adr 1E 9 8 7 6 5 4 3 2 1 Default rpc2 delay 3 0 lhc cycle 1 5 ADR_RPC_RAW_DELAY RPC Raw Hits Data Delay 13 12 11 10 9 8 7 6 5 4 rpc3 delay 0 1 lhc cycle 2 bxn offset 0 Adr BA 15 14 rpc3 delay 2 lhc cycle 3 Description RPC Configuration 9 8 7 6 read bank 0 lhc cycle 4 Maximum bxn+1 3564(hDEC) for LHC 924(h39C) for beam test Unassigned Default ADR_RPC_RDATA 13 12 11 10 rdata 14 lhc cycle 8 0 Bits Adr B8 15 14 lhc cycle 9 Default ADR_RPC_CFG 13 12 11 10 read bxn 2 LHC Cycle Period, Maximum BXN Count 9 8 7 6 5 4 3 2 rpc1 delay 3 rpc1 delay 2 rpc1 delay 1 rpc1 delay 0 3 2 1 0 rpc0 delay 3 rpc0 delay 2 rpc0 delay 1 rpc0 delay 0 Description RPC0 Raw hits data delay RPC1 Raw hits data delay RPC2 Raw hits data delay RPC3 Raw hits data delay Page 40 of 83 06/11/04 1:58 PM Adr BC 15 14 0 ADR_RPC_INJ 13 12 11 inj rdata 18 0 inj rdata 17 inj rdata 16 RPC Injector Control 9 8 7 6 5 10 inj wdata 18 inj wdata 17 Bits Dir Signal [00] [01] [02] [06:03] [07] [10:08] [13:11] [15:14] R/W R/W R/W R/W R/W R/W R R/W rpc_mask_all injector_mask_rat injector_mask_rpc inj_delay_rat[3:0] rpc_inj_sel rpc_inj_wdata[18:16] rpc_inj_rdata[18:16] -- Adr BE 15 14 inj adr 7 inj adr 6 inj adr 3 inj adr 2 rpc_inj_wen[3:0] rpc_inj_ren[3:0] inj_rwadr[7:0] 2 1 0 mask rpc mask rat mask all Description 1=Enable RPC Inputs from RAT, 0=disable all 1=Enable RAT for injector fire 1=Enable RPC injector RAM for injector fire CFEB/RPC injectors wait for RAT 1=Enable injector RAM write RPC injector write data MSBs, see adr C0 RPC injector read data MSBs, see adr C0 Unassigned inj adr 0 inj ren 3 Default 0 0 0 inj ren 2 inj ren 1 inj wdata 13 inj wdata 12 inj wdata 11 inj wdata 10 inj wdata 9 Bits Dir Signal [15:00] R/W rpc_inj_wdata[15:0] inj wdata 8 inj rdata 12 inj wdata 7 Default inj rdata 11 inj rdata 10 0 Bits Dir Signal [15:00] R rpc_inj_rdata[15:0] inj rdata 9 inj rdata 8 Default - 3 2 1 0 inj wen 3 inj wen 2 inj wen 1 inj wen 0 1=Write enable injector RAMn 1=Read enable Injector RAMn Injector RAM read/write address inj wdata 6 inj wdata 5 4 3 2 1 0 inj wdata 4 inj wdata 3 inj wdata 2 inj wdata 1 inj wdata 0 Description RPC RAM write data LSBs (see adr BC msbs) ADR_RPC_INJ_RDATA RPC Injector Read Data 13 12 11 10 9 8 7 6 5 inj rdata 13 inj ren 0 Description ADR_RPC_INJ_WDATA RPC Injector Write Data 13 12 11 10 9 8 7 6 5 inj rdata 14 3 delay rat 0 inj adr 1 inj adr 4 R/W R/W R/W Adr C2 15 14 4 delay rat 1 inj adr 5 [03:00] [07:04] [15:08] inj rdata 15 delay rat 2 RPC Injector RAM Addresses 9 8 7 6 5 4 Signal inj wdata 14 1 0 1 0 0 0 0 delay rat 3 ADR_RPC_INJ_ADR 13 12 11 10 Dir inj wdata 15 inj sel Default Bits Adr C0 15 14 inj wdata 16 inj rdata 7 inj rdata 6 inj rdata 5 4 3 2 1 0 inj rdata 4 inj rdata 3 inj rdata 2 inj rdata 1 inj rdata 0 Description RPC RAM read data LSBs (see adr BC msbs) Page 41 of 83 06/11/04 1:58 PM Adr C4 15 14 rpc3 bxn diff3 ADR_RPC_BXN_DIFF RPC BXN Differences 13 12 11 10 9 8 7 6 5 rpc3 bxn diff2 rpc3 bxn diff1 rpc3 bxn diff0 rpc2 bxn diff3 rpc2 bxn diff2 Bits Dir Signal [03:00] [07:04] [11:08] [15:12] R R R R rpc0_bxn_diff[3:0] rpc1_bxn_diff[3:0] rpc2_bxn_diff[3:0] rpc3_bxn_diff[3:0] Adr C6 15 14 enable pad15 enable pad14 enable pad12 enable pad11 enable pad10 Bits Dir Signal [15:00] R/W rpc0_hcm[15:0] Adr C8 ADR_RPC1_HCM Bits Dir Signal [15:00] R/W rpc1_hcm[15:0] Adr CA ADR_RPC2_HCM Bits Dir Signal [15:00] R/W rpc2_hcm[15:0] Adr CC rpc2 bxn diff0 rpc1 bxn diff3 Default ADR_RPC0_HCM 13 12 11 10 enable pad13 rpc02 bxn diff1 ADR_RPC3_HCM Bits Dir Signal [15:00] R/W rpc3_hcm[15:0] - rpc1 bxn diff2 rpc1 bxn diff1 enable pad8 3 2 1 0 rpc0 bxn diff3 rpc0 bxn diff2 rpc0 bxn diff1 rpc0 bxn diff0 Description RPC bxn – Offset (in adr B6) RPC bxn – Offset (in adr B6) RPC bxn – Offset (in adr B6) RPC bxn – Offset (in adr B6) RPC0 Hot Channel Mask 9 8 7 6 5 enable pad9 4 rpc1 bxn diff0 enable pad7 Default FFFF enable pad6 enable pad5 4 3 2 1 0 enable pad4 enable pad3 enable pad2 enable pad1 enable pad0 Description Bit(n)=1=Enable RPC Pad(n), FFFF=enable all RPC1 Hot Channel Mask Default FFFF Description Bit(n)=1=Enable RPC Pad(n), FFFF=enable all RPC2 Hot Channel Mask Default FFFF Description Bit(n)=1=Enable RPC Pad(n), FFFF=enable all RPC3 Hot Channel Mask Default FFFF Description Bit(n)=1=Enable RPC Pad(n), FFFF=enable all Page 42 of 83 06/11/04 1:58 PM TTC Commands: Fast Control Bus ccb_cmd[5..0] Decoding Scheme Signal Code (hex) BX0 (*) L1 Reset (*) Hard_reset (*) Start Trigger Stop Trigger Test Enable Private Gap Private Orbit Tmb_hard_reset (*) Alct_hard_reset (*) Dmb_hard_reset (*) Mpc_hard_reset (*) Dmb_cfeb_calibrate0 (*) Dmb_cfeb_calibrate1 (*) Dmb_cfeb_calibrate2 (*) Dmb_cfeb_initiate (*) Alct_adb_pulse_sync (*) Alct_adb_pulse_async (*) Clct_external_trigger (*) Alct_external_trigger (*) Soft_reset (*) DMB_soft_reset (*) TMB_soft_reset (*) MPC_soft_reset (*) Send_bcnt[7..0] (*) Send_evcnt[7..0] (*) Send_evcnt[15..8] (*) Send_evcnt[23..16] (*) Inject patterns from TMBs Alct_adb_pulse (*) Inject patterns from MPCs Inject patterns from MS tmb_bxreset 1 3 4 6 7 8 9 A 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 30 31 32 Decoded by TMB Y Y Description Bunch Crossing Zero Reset L1 readout buffers and resynchronize optical links Reload all FPGAs from EPROMs Y Y Y Y Reload TMB FPGAs from EPROM Reload ALCT FPGAs from EPROM Reload DMB FPGAs from EPROM Reload MPC FPGAs from EPROM CFEB Calibrate Pre-Amp Gain CFEB Trigger Pattern Calibration CFEB Pedestal Calibration Initiate CFEB calibration (Hold next L1ACC and Pretriggers) Pulse Anode Discriminator, synchronous Pulse Anode Discriminator, asynchronous External Trigger All CLCTs External Trigger All ALCTs Initializes the FPGA on DMB, TMB and MPC boards Initializes the FPGA on a DMB Initializes the FPGA on a TMB Initializes the FPGA on a MPC Send Bunch_Counter[7..0] to ccb_data[7..0] bus Send Event_Counter[7..0] to ccb_data[7..0] bus Send Event_Counter[15..8] to ccb_data[7..0] bus Send Event_Counter[23..16] to ccb_data[7..0] bus Injects patterns from TMB’s internal RAM to MPC Generate sync and async anode discriminator pulses Injects patterns from MPC’s input FIFO to SP Injects patterns from MS input FIFO to Global Muon Trigger Reset TMB/ALCT BXN, do not reset L1A counters (*) – decoded by CCB Page 43 of 83 06/11/04 1:58 PM Embedded Logic Analyzer Scope Channels: Embedded Logic Analyzer Scope Channels Channel Signal ch00 ch01 ch02 ch03 ch04 ch05 ch06 ch07 ch08 ch09 ch10 ch11 ch12 ch13 ch14 ch15 sequencer pretrig active_feb_flag any_cfeb_hit any_cfeb_hsds wr_buf_busy wr_buf_ready clct_ext_trig_os alct_active_feb alct_pretrig_win first_really_valid clct_sm==xtmb tmb_discard discard_nobuf discard_invp discard_tmbreject 0 (no dmb readout) ch16 ch17 ch18 ch19 ch20 ch21 ch22 ch23 ch24 ch25 ch26 ch27 ch28 ch29 ch30 ch31 first_nhit[0] first_nhit[1] first_nhit[2] first_pat[3]hsds second_nhit[0] second_nhit[1 second_nhit[2] second_pat[3]hsds latch_clct0 latch_clct1 alct_1st_valid alct_2nd_valid alct_vpf_tp clct_vpf_tp clct_window_tp 0 (no dmb readout) ch32 ch33 ch34 ch35 ch36 ch37 ch38 ch39 ch40 ch41 ch42 ch43 ch44 ch45 ch46 ch47 sequencer pretrig mpc_frame_ff mpc_response_ff mpc_accept_tp[0] mpc_accept_tp[1] l1a_pulse_dsp l1a_window_dsp dmb_dav_mux dmb_busy hs_thresh[0] hs_thresh[1] hs_thresh[2] ds_thresh[0] ds_thresh[1] ds_thresh[2] 0( no dmb readout) Description Page 44 of 83 06/11/04 1:58 PM ch48 ch49 ch50 ch51 ch52 ch53 ch54 ch55 ch56 ch57 ch58 ch59 ch60 ch61 ch62 ch63 sequencer pretrig valid_clct_required buf_nbusy[0] buf_nbusy[1] buf_nbusy[2] buf_nbusy[3] 0 0 0 0 0 l1a_rx_counter[0] l1a_rx_counter[1] l1a_rx_counter[2] l1a_rx_counter[3] 0 (no dmb readout) ch64 ch65 ch66 ch67 ch68 ch69 ch70 ch71 ch72 ch73 ch74 ch75 ch76 ch77 ch78 ch79 sequencer pretrig bxn_counter[ 0] bxn_counter[ 1] bxn_counter[ 2] bxn_counter[ 3] bxn_counter[ 4] bxn_counter[ 5] bxn_counter[ 6] bxn_counter[ 7] bxn_counter[ 8] bxn_counter[ 9] bxn_counter[10] bxn_counter[11] 0 0 0 (no dmb readout) ch80 ch81 ch82 ch83 ch84 ch85 ch86 ch87 ch88 ch89 ch90 ch91 ch92 ch93 ch94 ch95 dmb seq_wdata[0] dmb seq_wdata[1] dmb seq_wdata[2] dmb seq_wdata[3] dmb seq_wdata[4] dmb seq_wdata[5] dmb seq_wdata[6] dmb seq_wdata[7] dmb seq_wdata[8] dmb seq_wdata[9] dmb seq_wdata[10] dmb seq_wdata[11] dmb seq_wdata[12] dmb seq_wdata[13] dmb seq_wdata[14] dmb seq_wdata[15] ch96 ch97 ch98 ch99 rpc0_bxn[0] rpc0_bxn[1] rpc0_bxn[2] rpc1_bxn[0] Page 45 of 83 06/11/04 1:58 PM ch100 ch101 ch102 ch103 ch104 ch105 ch106 ch107 ch108 ch109 ch110 ch111 ch112 ch113 ch114 ch115 ch116 ch117 ch118 ch119 ch120 ch121 ch122 ch123 ch124 ch125 ch126 ch127 rpc1_bxn[1] rpc1_bxn[2] rpc2_bxn[0] rpc2_bxn[1] rpc2_bxn[2] rpc3_bxn[0] rpc3_bxn[1] rpc3_bxn[2] 0 0 0 0 rpc0_nhits[0] rpc0_nhits[1] rpc0_nhits[2] rpc0_nhits[3] rpc1_nhits[0] rpc1_nhits[1] rpc1_nhits[2] rpc1_nhits[3] rpc2_nhits[0] rpc2_nhits[1] rpc2_nhits[2] rpc2_nhits[3] rpc3_nhits[0] rpc3_nhits[1] rpc3_nhits[2] rpc3_nhits[3] Page 46 of 83 06/11/04 1:58 PM TMB Board Status Operations (documentation incomplete 6/9/2004) ID Registers id_slot=15 id_rev =D id_type=C id_date=06/08/2004 id_rev =38CA=06/10/04 xc2v3000 VME Slot Firmware version Firmware Type Firmware Compile Date Firmware Revcode Digital Serial Numbers Digital Serial for TMB CRC=DC DSN=00000A237E7F MFG=01 OK Digital Serial for Mez CRC=BF DSN=000007E06194 MFG=01 OK Digital Serial for RAT CRC=52 DSN=00000AB39AAD MFG=01 OK Power Supply ADC TMB2004A Comparators 5.0V status=OK 3.3V status=OK 1.8V status=OK 1.5V status=OK Tcrit status=OK TMB2004A ADC +5.0 TMB +3.3 TMB +1.5 TMBcore +1.5 GTLtt +1.0 GTLref +3.3 RAT +1.8 RATcore +vref/2 +vzero +vref 5.004 3.221 1.488 1.492 1.004 3.221 1.797 2.047 0.000 4.095 V V V V V V V V V V 0.305 1.160 0.795 0.230 0.000 0.250 8.985 0.000 0.000 0.000 A A A A A A A A A A TMB2004A Temperature IC T tmb pcb 73.4 F T tmb fpga 95.0 F 23. 35. C C Tcrit=261./127. Tcrit=261./127. RAT2004A Temperature IC T rat pcb 68.0 F T rat xstr 69.8 F 20. 21. C C Tcrit=261./127. Tcrit=261./127. Clock Delays Current 3D3444 Delay Settings Ch0 8steps 16ns ALCT Ch1 1steps 2ns ALCT Ch2 2steps 4ns DMB Ch3 9steps 20ns RPC Ch4 0steps 0ns TMB1 Ch5 0steps 0ns MPC Ch6 0steps 0ns DCC Ch7 7steps 14ns CFEB0 Ch8 7steps 14ns CFEB1 Ch9 7steps 14ns CFEB2 ChA 7steps 14ns CFEB3 ChB 7steps 14ns CFEB4 tx rx tx tx rx rx tx tx tx tx tx tx clock clock clock clock clock clock clock clock clock clock clock clock Page 47 of 83 06/11/04 1:58 PM RAT Module Status RAT FPGA device 0 Idcode=20A10093 RAT PROM device 1 Idcode=05034093 RAT FPGA device 0 USERcode=FFFFFFFF RAT PROM device 1 USERcode=06032004 RAT USER1=E2A78220040603AB rs_begin B rs_version A rs_monthday 0603 rs_year 2004 rs_syncmode 0 rs_posneg 1 rs_loop 0 rs_rpc_clk 0 rs_rpc_en F rs_txok 0 rs_rxok 0 rs_locked 1 rs_locklost 0 rs_tcrit 1 rs_rpc_free 2 rs_unassigned 00 rs_end E JTAG Chains Chain 3210 00XX 01XX 10xx 1100 1101 Select Address (X=don't care) Base Function 0 ALCT 4 TMB Mezzanine FPGA+PROMs 8 TMB User PROMs C FPGA Monitor (for TMB self-test) D RAT Module FPGA+PROM Page 48 of 83 06/11/04 1:58 PM DMB Readout Full-Readout and Local-Readout Format: 1 3 e e e e e e n n n n n 1 m m m m 1 1 1 1 1 1 1 1 6B0C header Beginning Of Cathode Data event header Non-buffered event data clct header Cathode LCTs tmb header TMB match result mpc header MPC frames buf header Buffer status rpc header RPC status 6E0B header End of header block hits CFEB0 raw hits hits CFEB1 raw hits hits CFEB2 raw hits hits CFEB3 raw hits hits CFEB4 raw hits 6B04 Start of RPC raw hits marker hits RPC0 raw hits hits RPC1 raw hits hits RPC2 raw hits hits RPC3 raw hits 6E04 End of RPC raw hits marker 6E0C End of raw hits 2AAA Make word count x4 5555 Make word count x4 crc0 CRC22[10:0] crc1 CRC22[21:11] E0F End of Frame wordcount Total words in transmission (optional) (optional) (optional) (optional) (optional) (optional) (inserted only if needed) (inserted only if needed) (inclusive) ------ Word Count = 26(nheaders) + 1(E0B) + ncfebs*(6*ntbins) +1(B04) + nrpcs*(2*ntbins) +1(E04) +1(EOC) +2(2AAA 5555) +2(crc) +1(E0F) +1(wordcount) (if RPC readout enabled) (if RPC readout enabled) (if RPC readout enabled) (if needed to make word count multiple of 4) Page 49 of 83 06/11/04 1:58 PM Long Header-only Format: 1 3 e e e e e 1 1 1 1 1 1 6B0C header event header clct header tmb header mpc header buf header rpc header 6E0B 6E0C crc0 crc1 E0F wordcount Beginning Of Cathode Data Non-buffered event data Cathode LCTs TMB match result MPC frames Buffer status RPC status End of header block End of raw hits CRC22 CRC22 End of Frame Total words in transmission (inclusive) ------ 32 words = nheaders(26)+E0B+E0C+2crc+E0F+wdcnt Short Header-only Format: 1 3 1 1 1 1 6B0C header event header crc0 crc1 EEF frame wordcount Beginning Of Cathode Data Non-buffered event data CRC22 CRC22 End of Frame Total words in transmission (inclusive) ------ 8 words = 4headers+2crc+EEF+wdcnt Page 50 of 83 06/11/04 1:58 PM Header Word Descriptions: (documentation incomplete 6/9/2004) header00_[11:0] = 12'hB0C; header00_[14:12]= 3'b110; // Begining of Cathode record marker // Marker 6 header01_[4:0] = header01_[11:5] = header01_[14:12]= r_fifo_tbins[4:0]; {2'h0,r_febs_read[4:0]}; fifo_mode[2:0]; // Number of time bins per CFEB in dump // CFEBs read out for this event, 2 dummy for ALCT // Trigger type and fifo mode header02_[3:0] = header02_[7:4] = header02_[12:8] = header02_[14:13]= pop_l1a_rx_counter[3:0]; csc_id[3:0]; board_id[4:0]; l1a_type[1:0]; // Level 1 accepts received and pushed on L1A stack // Chamber ID number = (slot/2 or slot/2-1 if slot>12 at pup) // TMB2001 module ID number (= VME slot at power up) // L1A Pop type code: buffers, no buffers, clct/alct_only header03_[11:0] = header03_[13:12]= header03_[14] = pop_bxn_counter[11:0]; r_type[1:0]; 0; // Bxn pushed on L1A stack at L1A arrival // Record type: dump,nodump, full header, short header // Free header04_[4:0] header04_[7:5] header04_[8] header04_[13:9] header04_[14] r_nheaders[4:0]; r_ncfebs[2:0]; r_has_buf; fifo_pretrig[4:0]; 0; // Number of header words // Number of CFEBs read out // Event has buffer data // # Time bins before pretrigger; // Free header05_[3:0] = header05_[11:4] = header05_[12] = header05_[14:13]= r_l1a_tx_counter[3:0]; r_trig_source_vec[7:0]; r_trig_source_hsds; 0; // Level 1 accept event number at pretrig or alct_only // Trigger source vector // Trigger was hs or ds // Free header06_[4:0] = header06_[9:5] = header06_[13:10]= header06_[14] = r_active_feb_ff[4:0]; cfeb_exists[4:0]; run_id[3:0]; 0; // Active CFEB list sent to DMB // List of instantiated CFEBs // Run info // Free header07_[11:0] = header07_[12] = header07_[14:13]= r_bxn_counter_ff[11:0]; r_sync_err; 0; // Full Bunch Crossing number at pretrig // BXN sync error // Free header08_[14:0] = header09_[14:0] = r_clct0_tmb[14:0]; r_clct1_tmb[14:0]; // CLCT0 after drift lsbs // CLCT1 after drift lsbs header10_[5:0] = header10_[11:6] = header10_[12] = header10_[14:13]= r_clct0_tmb[20:15]; r_clct1_tmb[20:15]; r_clct_invp; 0; // CLCT0 after drift msbs // CLCT1 after drift msbs // CLCT0 had invalid pattern after drift delay // Free header11_[0] = header11_[1] = header11_[2] = header11_[4:3] = header11_[6:5] = header11_[10:7] = header11_[14:11]= r_tmb_match; r_tmb_alct_only; r_tmb_clct_only; r_tmb_bxn0_diff[1:0]; r_tmb_bxn1_diff[1:0]; r_tmb_match_win[3:0]; triad_persist[3:0]; // ALCT and CLCT matched in time // Only ALCT triggered // Only CLCT triggered // BXN difference for matched LCTs alct-clct // BXN difference for matched LCTs alct-clct // Location of alct in clct match window // CLCT Triad persistence header12_[14:0] header13_[14:0] header14_[14:0] header15_[14:0] r_mpc0_frame0_ff[14:0]; r_mpc0_frame1_ff[14:0]; r_mpc1_frame0_ff[14:0]; r_mpc1_frame1_ff[14:0]; // MPC muon 0 frame 0 LSBs // MPC muon 0 frame 1 LSBs // MPC muon 1 frame 0 LSBs // MPC muon 1 frame 1 LSBs = = = = = = = = = Page 51 of 83 06/11/04 1:58 PM header16_[0] = header16_[1] = header16_[2] = header16_[3] = header16_[5:4] = header16_[7:6] = header16_[10:8] = header16_[13:11]= header16_[14] = r_mpc0_frame0_ff[15]; r_mpc0_frame1_ff[15]; r_mpc1_frame0_ff[15]; r_mpc1_frame1_ff[15]; r_mpc_accept[1:0]; r_mpc_reserved[1:0]; hs_thresh[2:0]; ds_thresh[2:0]; 0; // MPC muon 0 frame 0 MSB // MPC muon 0 frame 1 MSB // MPC muon 1 frame 0 MSB // MPC muon 1 frame 1 MSB // MPC muon accept response // MPC reserved // ½-strip pretrigger threshold // DiStrip pretrigger threshold // Free header17_[0] header17_[5:1] header17_[8:6] header17_[9] header17_[10] header17_[11] header17_[12] header17_[13] header17_[14] = = = = = = = = = r_wr_buf_ready_ff; r_wr_tbin_adr_ff[4:0]; r_wr_buf_adr_ff[2:0]; r_buf_ovf; r_buf_full; r_buf_almost_full; r_buf_half_full; r_buf_empty; 0; // Write buffer is ready // Tbin address at pretrig // Address of write buffer at pretrig // Pretrig arrived when no buffer was free // All 8 buffers in use // Almost all buffers in use // Half of buffers in use // No buffers in use // Free header18_[3:0] header18_[11:4] header18_[12] header18_[13] header18_[14] = = = = = r_buf_nbusy[MXBUFB:0]; r_buf_busy[MXBUF-1:0]; pop_free[0:0]; stack_ovf_latch; 0; // Number of buffers busy // List of busy buffers // Unassigned // L1A stack overflow // Free header19_[0] = header19_[1] = header19_[2] = header19_[3] = header19_[4] = header19_[5] = header19_[10:6] = header19_[13:11]= header19_[14] = pop_tmb_trig_pulse; pop_tmb_alct_only; pop_tmb_clct_only; pop_tmb_match; pop_wr_buf_ready; pop_wr_buf_avail; pop_wr_tbin_adr[4:0]; pop_wr_buf_adr[2:0]; 0; // TMB response // Only ALCT triggered // Only CLCT triggered // ALCT*CLCT triggered // Write buffer ready at pretrig // Write buffer ready or not required at pretrig // Tbin address at pretrig // Address of write buffer at pretrig // Free header20_[3:0] header20_[7:4] header20_[11:8] header20_[12] header20_[13] header20_[14] r_discard_nowbuf_cnt[3:0]; r_discard_invp_cnt[3:0]; r_discard_tmbreject_cnt[3:0]; r_no_tmb_trig_pulse; r_no_mpc_frame_ff; r_no_mpc_response_ff; // pretrig but no wbuf available // invalid pattern after drift // tmb rejected event // no tmb_trig_pulse before timeout // no mpc_frame_ff before timeout // no mpc_response_ff before timeout header21_[3:0] = header21_[7:4] = header21_[11:8] = header21_[14:12]= alct_delay[3:0]; clct_width[3:0]; mpc_tx_delay[3:0]; 0; // Delay ALCT for CLCT match window // CLCT match window width // MPC transmit delay // Free header22_[3:0] = header22_[7:4] = header22_[10:8] = header22_[11] = header22_[14:12]= rpc_exists[3:0]; rd_rpc_list[3:0]; rd_nrpcs[2:0]; rpc_read_enable; 0; // RPCs connected to this TMB // RPC units included in read out // Number of RPCs in readout // RPC readout enabled // Free header23_[14:0] = header24_[14:0] = 8'h23; 8'h24; // Free // Free header25_[13:0] = header25_[14] = revcode[13:0]; 0; // Firmware version date code // Free = = = = = = Page 52 of 83 06/11/04 1:58 PM Revcode Algorithm: `define FIRMWARE_TYPE `define VERSION `define MONTHDAY `define YEAR `define FPGAID 04'hC 04'hD 16'h0610 16'h2004 16'h3000 // C=Normal CLCT/TMB, D=Debug PCB loopback version // Version ID // Version date // Version date // FPGA Type XC2Vnnnn assign revcode_vme[8:0] = (monthday[15:12]*10 + monthday[11:8])*32+ (monthday[7:4]*10 + monthday[ 3:0]); assign revcode_vme[11:9] = year[2:0]; assign revcode_vme[13:12] = fpgaid[15:12]; Decoding Revcode: adr = base_adr+6 status = vme_read(%ref(adr),%ref(rd_data)) id_rev = rd_data id_rev_day = ishft(id_rev , 0).and.'001F'x id_rev_month = ishft(id_rev, -5).and.'000F'x id_rev_year = ishft(id_rev, -9).and.'0007'x id_rev_fpga = ishft(id_rev,-12).and.'000F'x Page 53 of 83 06/11/04 1:58 PM DMB FIFO Data Format: Short-Header Mode Frame # No Write 0 1 2 3 4 5 6 7 No Write /wr first last FIFO Control 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ddu d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 B0C16 - - - - - TMB Data DDU 0 0 0 0 1 1 1 1 - 1 1 0 FIFO Mode l1a_type Res r_type DDU Code 1012 DDU Code 1012 DDU Code 1012 DDU Code 1012 - - - - - - - - CFEBs in Readout Tbins per CFEB Board ID CSC ID L1A Rx Number BXN Counter at L1A arrival 1 CRC22[10:0] TMB 1 CRC22[21:11] TMB EEF16 1 Word Count [10:0] TMB - Record Type Codes: r-type 0 1 2 3 Raw Hits No Full Local No Header Full Full Full Short (No buffer was available at pre-trigger) L1A Type Codes: l1a-type 0 Normal CLCT trigger with buffer data and L1A window match 1 ALCT-only trigger, no data buffers 2 L1A-only, no matching TMB trigger, no buffer data 3 TMB triggered, no L1A-window match, event has buffer data FIFO Modes: mode Raw Hits 0 No 1 All 5 CFEBs 2 Local 3 No 4 No (not usually read out) (not usually read out) (not usually read out) Header Full (If buffer was available at pre-trigger) Full (If buffer was available at pre-trigger) Full (If buffer was available at pre-trigger) Short No Page 54 of 83 06/11/04 1:58 PM DMB FIFO Data Format: Long Header-Only Mode Frame # No Write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 /wr first last FIFO Control 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ddu d14 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 B0C16 - - - - - TMB Data DDU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 FIFO Mode 23 24 25 26 27 28 29 30 31 No Write - - 0 0 0 0 1 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 1 - 0 0 0 0 0 0 1 1 1 1 - - - Invalid Pattern Triad Persistence[3:0] ALCT Match Time LCT1 BXN Difference LCT0 BXN Difference CLCT Only ALCT Only TMB Match Muon1 Frame0 [15] Muon0 Fram1 [15] Muon0 Frame0 [15] MPC Muon0 Frame0[14:0] (lsb) MPC Muon0 Frame1[14:0] (lsb) MPC Muon1 Frame0[14:0] (lsb) MPC Muon1 Frame1[14:0] (lsb) Res Res ds_thresh[2:0] Buf empty Reserved Res TMB Mpc rx timeout Buf ½ful Pop free hs_thresh[2:0] Buf full-1 POP Buf Adr TMB Mpc tx timeout TMB Trig timout mpc_tx_delay[3:0] Res 1 1 0 0 DDU Code 1012 DDU Code 1012 1 TMB 1 TMB DDU Code 1012 DDU Code 1012 - - Buf ovf - Write Buf Adr Discard: TMB Reject rpc read en Reserved 1 1 Buf full 1 TMB - mpc reserved Busy Buffer List POP Tbin Adr Reserved 0 0 0 0 0 0 0 0 0 0 1 - CFEBs in Readout Tbins per CFEB l1a_type Board ID CSC ID L1A Rx Counter Res r_type BXN Counter at L1A arrival Res # Tbins before pre-trig has # CFEBs # Header frames buf hs Reserved Trigger Source Vector L1A Tx Counter pretg Res Run ID CFEBs Instantiated Active CFEBs Sync Reserved BXN Counter at Pre-trigger Err Cathode LCT0[14:0] (lsb) Cathode LCT1[14:0] (lsb) Reserved Cathode LCT1[20:15] Cathode LCT0[20:15] 21 22 d13 #RPCs mpc accept[1:0] Muon1 Fram1 [15] Tbin Address at pretrig Buf ready # Buffers Busy POP Buf Avai POP Buf Ready Discard: Invalid Pattern POP TMB Match POP CLCT Only POP ALCT Only POP TMB Trig Discard: No buffer avail clct_width[3:0] alct_delay[3:0] RPC Readout[3:0] RPC Exits[3:0] 2316 (future RPC/TMB matching info) 2416 (future RPC/TMB matching info) Firmware Revcode E0B16 E0C16 CRC22[10:0] CRC22[21:11] E0F16 Word Count [10:0] - - - - Page 55 of 83 06/11/04 1:58 PM DMB FIFO Data Format: Full-Readout Mode Frame # No Write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 /wr first last FIFO Control 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ddu d14 d12 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 - d11 TMB Data DDU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 FIFO Mode B0C16 Begin Cathode Header CFEBs in Readout Tbins per CFEB l1a_type Board ID CSC ID L1A Rx Counter Res r_type BXN Counter at L1A arrival Res # Tbins before pre-trig has # CFEBs # Header frames buf Reserved Trigger Source Vector L1A Tx Counter Res Run ID CFEBs Instantiated Active CFEBs Sync Reserved BXN Counter at Pre-trigger Err Cathode LCT0[14:0] (lsb) Cathode LCT1[14:0] (lsb) Reserved Cathode LCT1[20:15] Cathode LCT0[20:15] - - 0 0 0 0 Res Reserved 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - - ALCT Match Time LCT1 BXN Difference LCT0 BXN Difference CLCT Only ALCT Only TMB Match Muon1 Frame0 [15] Muon0 Fram1 [15] Muon0 Frame0 [15] MPC Muon0 Frame0[14:0] (lsb) MPC Muon0 Frame1[14:0] (lsb) MPC Muon1 Frame0[14:0] (lsb) MPC Muon1 Frame1[14:0] (lsb) mpc reserved Reserved Buf empty Reserved Res TMB Mpc rx timeout Buf ½ful Pop free Buf full-1 TMB Mpc tx timeout TMB Trig timout Reserved Res 1 1 0 CFEB 0 CFEB 0 CFEB 0 CFEB 0 CFEB 0 CFEB 0 CFEB 0 CFEB 0 CFEB 0 CFEB 0 CFEB 0 CFEB 0 - Buf full Buf ovf Write Buf Adr Busy Buffer List POP Tbin Adr POP Buf Adr mpc accept[1:0] Muon1 Fram1 [15] Tbin Address at pretrig Buf ready # Buffers Busy POP Buf Avai POP Buf Ready POP TMB Match POP CLCT Only POP ALCT Only POP TMB Trig Discard: TMB Reject Discard: Invalid Pattern Discard: No buffer avail mpc_tx_delay[3:0] clct_width[3:0] alct_delay[3:0] RPC Readout[3:0] RPC Exits[3:0] Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - - Invalid Pattern 21 22 d13 rpc read en #RPCs 2316 (future RPC/TMB matching info) 2416 (future RPC/TMB matching info) Firmware Revcode E0B16 End Header Block Tbin 0 Ly0[7:0] Triad bits Tbin 0 Ly1[7:0] Tbin 0 Ly2[7:0] Tbin 0 Ly3[7:0] Tbin 0 Ly4[7:0] Tbin 0 Ly5[7:0] Tbin 1 Ly0[7:0] Tbin 1 Ly1[7:0] Tbin 1 Ly2[7:0] Tbin 1 Ly3[7:0] Tbin 1 Ly4[7:0] Tbin 1 Ly5[7:0] - Page 56 of 83 06/11/04 1:58 PM 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 292 293 294 295 opt opt 296 297 298 299 No Write 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 - CFEB 4 CFEB 4 CFEB 4 CFEB 4 CFEB 4 CFEB 4 1 1 0 RPC 0 RPC 0 RPC 0 RPC 0 RPC 0 RPC 0 RPC 0 RPC 0 RPC 0 RPC 0 RPC 0 RPC 0 RPC 0 RPC 0 RPC 3 RPC 3 1 1 0 1 1 0 Tbin 6 Tbin 6 Tbin 6 Tbin 6 Tbin 6 Tbin 6 - Tbin 0 RPC BXN Tbin 1 RPC BXN Tbin 2 RPC BXN Tbin 3 RPC BXN Tbin 4 RPC BXN Tbin 5 RPC BXN Tbin 6 RPC BXN Tbin 6 RPC BXN 0 0 DDU Code 1012 DDU Code 1012 1 TMB 1 TMB DDU Code 1012 DDU Code 1012 - - - 1 TMB - - Ly0[7:0] Ly1[7:0] Ly2[7:0] Ly3[7:0] Ly4[7:0] Ly5[7:0] B0416 Begin RPC Raw Hits (if RPC readout enabled) Pads[7:0] RPC Pads Pads[15:8] Pads[7:0] Pads[15:8] Pads[7:0] Pads[15:8] Pads[7:0] Pads[15:8] Pads[7:0] Pads[15:8] Pads[7:0] Pads[15:8] Pads[7:0] Pads[15:8] Pads[7:0] Pads[15:8] E0416 End RPC Raw Hits E0C16 End Cathode Data 2AAA16 (Optional to make word count multiple of 4) 555516 (Optional to make word count multiple of 4) CRC22[10:0] CRC22[21:11] E0F16 End TMB Readout Word Count [10:0] - - - Page 57 of 83 06/11/04 1:58 PM Sample TMB Raw Hits Dump: TMB internal pattern injector + RPC internal pattern injector 7-Time bins, full raw hits readout Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 Data=06B0C Data=013E7 Data=01592 Data=01CFA Data=005BA Data=01011 Data=003FF Data=01C7D Data=00BFD Data=04BFD Data=00514 Data=02881 Data=07F87 Data=01705 Data=077BD Data=01725 Data=0240F Data=00021 Data=00011 Data=00439 Data=00000 Data=00033 Data=00CFF Data=00023 Data=00024 Data=038CA Data=06E0B Data=00000 Data=00000 Data=00000 Data=00000 Data=00000 Data=00000 Data=00100 Data=00100 Data=00100 Data=00100 Data=00100 Data=00100 Data=00242 Data=00242 Data=00242 Data=00242 Data=00242 Data=00242 Data=00300 Data=00340 Data=00300 Data=00340 Data=00300 Data=00340 Data=00440 Data=00402 Data=00440 Data=00402 Data=00440 Data=00402 Data=00500 Data=00500 Data=00500 Data=00500 Data=00500 Data=00500 Data=00600 Data=00600 Data=00600 Data=00600 Data=00600 Data=00600 Data=01000 Data=01000 Data=01000 Data=01000 Data=01000 Data=01000 Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 Data=01100 Data=01100 Data=01100 Data=01100 Data=01100 Data=01100 Data=01242 Data=01242 Data=01242 Data=01242 Data=01242 Data=01242 Data=01300 Data=01340 Data=01300 Data=01340 Data=01300 Data=01340 Data=01440 Data=01402 Data=01440 Data=01402 Data=01440 Data=01402 Data=01500 Data=01500 Data=01500 Data=01500 Data=01500 Data=01500 Data=01600 Data=01600 Data=01600 Data=01600 Data=01600 Data=01600 Data=02000 Data=02000 Data=02000 Data=02000 Data=02000 Data=02000 Data=02100 Data=02100 Data=02100 Data=02100 Data=02100 Data=02100 Data=02242 Data=02242 Data=02242 Data=02242 Data=02242 Data=02242 Data=02300 Data=02340 Data=02300 Data=02340 Data=02300 Data=02340 Data=02440 Data=02402 Data=02440 Data=02402 Data=02440 Data=02402 Data=02500 Data=02500 Data=02500 Data=02500 Data=02500 Data=02500 Data=02600 Data=02600 Data=02600 Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 Data=02600 Data=02600 Data=02600 Data=03000 Data=03000 Data=03000 Data=03000 Data=03000 Data=03000 Data=03100 Data=03100 Data=03100 Data=03100 Data=03100 Data=03100 Data=03242 Data=03242 Data=03242 Data=03242 Data=03242 Data=03242 Data=03300 Data=03340 Data=03300 Data=03340 Data=03300 Data=03340 Data=03440 Data=03402 Data=03440 Data=03402 Data=03440 Data=03402 Data=03500 Data=03500 Data=03500 Data=03500 Data=03500 Data=03500 Data=03600 Data=03600 Data=03600 Data=03600 Data=03600 Data=03600 Data=04000 Data=04000 Data=04000 Data=04000 Data=04000 Data=04000 Data=04100 Data=04100 Data=04100 Data=04100 Data=04100 Data=04100 Data=04242 Data=04242 Data=04242 Data=04242 Data=04242 Data=04242 Data=04300 Data=04340 Data=04300 Data=04340 Data=04300 Data=04340 Data=04440 Data=04402 Data=04440 Data=04402 Data=04440 Data=04402 Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= Adr= 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 Data=04500 Data=04500 Data=04500 Data=04500 Data=04500 Data=04500 Data=04600 Data=04600 Data=04600 Data=04600 Data=04600 Data=04600 Data=06B04 Data=00000 Data=00000 Data=00100 Data=00000 Data=002CD Data=005AB Data=00301 Data=00100 Data=00402 Data=00200 Data=00503 Data=00300 Data=00604 Data=00400 Data=01000 Data=01000 Data=01100 Data=01000 Data=012AB Data=014EF Data=01301 Data=01200 Data=01402 Data=01200 Data=01503 Data=01200 Data=01604 Data=01200 Data=02000 Data=02000 Data=02100 Data=02000 Data=022EF Data=023CD Data=02301 Data=02300 Data=02402 Data=02300 Data=02503 Data=02300 Data=02604 Data=02300 Data=03000 Data=03000 Data=03100 Data=03000 Data=03223 Data=03201 Data=03301 Data=03400 Data=03402 Data=03400 Data=03503 Data=03400 Data=03604 Data=03400 Data=06E04 Data=06E0C Data=0DB37 Data=0DAE7 Data=0DE0F Data=0D92C Page 58 of 83 06/11/04 1:58 PM TMB Signal Summary CCB 1 Input 46 Inputs 46 Outputs LVDS 40MHz clock GTLP at 40MHz GTLP at 40MHz Table 1: CCB Signal Summary Signal Bits Dir Logic 1 1 In LVDS Total In In In In In In In In In In GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP Total 1 6 1 1 1 1 1 8 1 5 26 Function Clock Bus ccb_clock40 Fast Control Bus ccb_clock40_enable ccb_cmd[5..0] ccb_evcntres ccb_bcntres ccb_cmd_strobe ccb_bx0 ccb_l1accept ccb_data[7..0] ccb_data_strobe ccb_reserved[4..0] TMB Reload Bus: ALCT+CLCT+TMB FPGA Reload tmb_hard_reset tmb_cfg_done[8..0] alct_hard_reset alct_cfg_done[8..0] tmb_reserved[1..0] Total 1 9 1 9 2 22 In Out In Out In GTLP GTLP GTLP GTLP GTLP DAQ Special Purpose Bus [Used by DMB and TMB] dmb_cfeb_calibrate[2..0] dmb_l1a_release dmb_reserved_out[4..0] dmb_reserved_in[2..0] Total 3 1 5 3 12 In (In) In (In) GTLP GTLP GTLP GTLP Trigger Special Purpose Bus [Used by TMB only] alct_adb_pulse_sync alct_adb_pulse_async clct_external_trigger alct_external_trigger clct_status[8..0] alct_status[8..0] tmb_l1a_request tmb_l1a_release tmb_reserved_in[4..0] tmb_reserved_out[2..0] Total 1 1 1 1 9 9 1 1 5 3 32 In In In In Out Out Out Out Out In GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP Page 59 of 83 06/11/04 1:58 PM ALCT 29 Input s 20 Outputs 1 Output LVDS Multiplexed at 80 MHz LVDS Multiplexed at 80 MHz LVDS 40MHz clock Table 2: ALCT Signal Summary Signal Bits Pins Mux Dir Logic first_valid first_quality[1..0] first_amu first_key[6..0] second_valid second_quality[1..0] second_amu second_key[6..0] bxn[4..0] daq_data[13..0] /wr_fifo lct_special ddu_special first_frame last_frame seq_status[1..0] seu_status[1..0] active_feb_flag cfg_done reserved_out[3..0] tdo Total Inputs 1 2 1 7 1 2 1 7 5 14 1 1 1 1 1 2 2 1 1 4 1 57 0.5 1 0.5 3.5 0.5 1 0.5 3.5 2.5 7 0.5 0.5 0.5 0.5 0.5 1 1 0.5 0.5 2 1 29 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No In In In In In In In In In In In In In In In In In In In In In LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS Signal Bits Pins Mux Dir Logic ccb_brcst[7..0] brcst_str dout_str subadr_str bx0 ext_inject ext_trig level1_accept sync_adb_pulse seq_cmd[2..0] reserved_in[4..0] clock clock_en hard_reset async_adb_pulse jtag_select[1..0] tck tms tdi Total Outputs 8 1 1 1 1 1 1 1 1 3 5 1 1 1 1 2 1 1 1 33 4 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 1.5 2.5 1 1 1 1 2 1 1 1 21 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS Function Valid Pattern Flag, best muon Pattern Quality, best muon Accelerator Muon Flag, best muon Key Wire Group, best muon Valid Pattern Flag, 2nd best muon Pattern Quality, 2nd best muon Accelerator Muon Flag, 2nd best muon Key Wire Group, 2nd best muon Bunch Crossing Number DAQ data /Write_enable DAQ FIFO LCT Special Word Flag DAQ Special Word Flag First DAQ Frame Last DAQ Frame Sequencer Status Radiation SEU Status Active FEB Flag (ALCT pre-triggered) FPGA configuration done Future use JTAG tdo from ALCT Function CCB broadcast command ccb_brcst strobe ccb_dout strobe ccb_subaddr strobe Bunch Crossing Zero External Test Pattern Inject Command External Trigger Command Level 1 Accept Synchronous ADB Test Pulse Sequencer Command Future use 40MHz clock Clock enable FPGA Reload Command Asynchronous ADB Test Pulse JTAG Chain Select JTAG tck to ALCT JTAG tms to ALCT JTAG tdi to ALCT Page 60 of 83 06/11/04 1:58 PM DMB 3 Inputs 45 Outputs LVTTL at 40 MHz LVTTL at 40 MHz Table 3: DMB Signal Summary Signal Bits Dir Logic Function tmb_data[14:0] alct_data[14:0] tmb_ddu_special tmb_last_frame tmb_data_available /tmb_write_enable_fifo tmb_active_feb_flag tmb_active_feb[4…0] fifo_clock alct_ddu_special alct_last_frame alct_first_frame(dav) /alct_write_enable_fifo reserved_to_dmb Total Outputs 15 15 1 1 1 1 1 5 1 1 1 1 1 5 50 Out Out Out Out Out Out Out Out Out Out Out Out Out Out LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL TMB data[14:0] to DMB FIFO ALCT data [14:0] to DMB FIFO TMB DDU Special Word Flag TMB Last FIFO frame TMB Data Available TMB FIFO /write_enable TMB Active Front-End-Board Flag TMB Active FEB indicators[4..0] 40MHz FIFO storage clock [= tmb_clock] ALCT DDU Special Word Flag ALCT Last FIFO frame ALCT First FIFO frame, data available ALCT FIFO /write_enable Unassigned dmb_request_lct dmb_ext_trig dmb_fpga_pgm_done reserved_from_dmb Total Inputs 1 1 1 3 6 In In In In LVTTL LVTTL LVTTL LVTTL DMB requests active_feb_flag from TMB DMB external trigger to TMB DMB FPGA Program Done Unassigned CFEB 120 Inputs 5 Outputs LVDS data multiplexed at 80 MHz LVDS 40MHz clock Table 4: CFEB Signal Summary Signal Bits Pins Dir Logic Function cfeb0_ly[5..0]_tr[7..0] cfeb1_ly[5..0]_tr[7..0] cfeb2_ly[5..0]_tr[7..0] cfeb3_ly[5..0]_tr[7..0] cfeb4_ly[5..0]_tr[7..0] Total Inputs 48 48 48 48 48 240 24 24 24 24 24 120 In In In In In LVDS LVDS LVDS LVDS LVDS CFEB0 6 layers x 8 triads, 80MHz CFEB1 6 layers x 8 triads, 80MHz CFEB2 6 layers x 8 triads, 80MHz CFEB3 6 layers x 8 triads, 80MHz CFEB4 6 layers x 8 triads, 80MHz Signal Bits Pins Dir Logic Function cfeb0_lct_clock cfeb1_lct_clock cfeb2_lct_clock cfeb3_lct_clock cfeb4_lct_clock Total Outputs 1 1 1 1 1 5 1 1 1 1 1 5 Out Out Out Out Out LVDS LVDS LVDS LVDS LVDS CFEB 1 40MHz clock CFEB 2 40MHz clock CFEB 3 40MHz clock CFEB 4 40MHz clock CFEB 5 40MHz clock Page 61 of 83 06/11/04 1:58 PM MPC 1 Input 32 Outputs GTLP at 80MHz GTLP at 80MHz Second In Time First In Time Table 5: MPC Signal Summary Signal Bits Pins Dir Logic alct_first_key[6:0] clct_first_pat[2:0] clct_first_hsds lct_first_quality[3:0] first_vpf alct_second_key[6:0] clct_second_pat[2:0] clct_second_hsds lct_second_quality[3:0] second_vpf 7 3 1 4 1 7 3 1 4 1 3.5 1.5 0.5 2 0.5 3.5 1.5 0.5 2 0.5 Out Out Out Out Out Out Out Out Out Out GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP LCT 0 ALCT key wire-group LCT 0 CLCT pattern number LCT 0 CLCT ½-Strip flag LCT 0 Muon quality LCT 0 Valid pattern flag LCT 1 ALCT key wire-group LCT 1 CLCT pattern number LCT 1 CLCT ½-Strip flag LCT 1 Muon quality LCT 1 Valid pattern flag 0 0 8 1 1 1 1 4 8 1 1 1 1 4 4 0.5 0.5 0.5 0.5 2 4 0.5 0.5 0.5 0.5 2 Out Out Out Out Out Out Out Out Out Out Out Out GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP LCT 0 CLCT key ½-strip LCT 0 CLCT bend direction LCT 0 BXN does not match at BX0 LCT 0 ALCT bunch crossing number LCT 0 local BXN from CLCT CSC chamber ID LCT 1 CLCT key ½-strip LCT 1 CLCT bend direction LCT 1 BXN does not match at BX0 LCT 1 ALCT bunch crossing number LCT 1 local BXN from CLCT CSC chamber ID 64 32 Bits Pins Dir Logic Function lct0_accept lct1_accept 1 1 0.5 0.5 In In GTLP GTLP LCT 0 Accepted by MPC best 3 of 18 sort LCT 1 Accepted by MPC best 3 of 18 sort Total Input Signals 2 1 clct_first_key[7:0] clct_first_bend lct 0 sync_err alct_first_bxn[0] clct_first_bx0_local csc_id[3:0] clct_second_key[7:0] clct_second_bend lct 1 sync_err alct_second_bxn[0] clct_second_bx0_local csc_id[3:0] Total Input Signals Signal Time 1st 2nd Function 2:1 Multiplexing at 80 MHz 2:1 Multiplexing at 80 MHz Page 62 of 83 06/11/04 1:58 PM RPC 80 Inputs 0 Outputs 40MHz LVTTL [from receivers on transition module] Table 6: RPC Signal Summary Signal rpc0_seg[15..0] rpc0_bxn[2..0] rpc0_clock rpc1_seg[15..0] rpc1_bxn[2..0] rpc1_clock rpc2_seg[15..0] rpc2_bxn[2..0] rpc2_clock rpc3_seg[15..0] rpc3_bxn[2..0] rpc3_clock Total data bits Bits Dir Logic Function 16 3 1 16 3 1 16 3 1 16 3 1 In In In In In In In In In In In In LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL RPC Segment[15..0] Bunch Crossing Number [2..0] Clock from RPC Link Board RPC Segment[15..0] Bunch Crossing Number [2..0] Clock from RPC Link Board RPC Segment[15..0] Bunch Crossing Number [2..0] Clock from RPC Link Board RPC Segment[15..0] Bunch Crossing Number [2..0] Clock from RPC Link Board 80 VME 24 Inputs TTL Address 16 BiDir TTL Data Table 7: VME Signal Summary Signal address data control in control out Bits Dir Logic 24 16 In BiDir In Out TTL TTL TTL TTL Function VME Address[23..0] VME Data[15..0] VME Control Inputs VME Control Outputs JTAG 5 Inputs 1 Outputs LVDS LVDS Table 8: JTAG Signal Summary Signal tck tms tdi chain_select tdo Page 63 of 83 Bits Dir Logic 1 1 1 2 1 In In In In Out LVDS LVDS LVDS LVDS LVDS Function JTAG TCK JTAG TMS JTAG TDI Chain Select Address JTAG TDO 06/11/04 1:58 PM LEDs Table 9: TMB Front Panel LEDs 1 LED Color Function LCT Blue ALCT Green CLCT Green L1A Green ALCT vpf and CLCT vpf match within the 75ns ALCT window (see note1 below) ALCT active FEB flag (may not always be the same as ALCT valid pattern flag) CLCT active FEB flag Or any external trigger except ALCT Level 1 Accept arrived in L1A window INVP Amber NMAT Amber NL1A Red VME Green Invalid CLCT pattern after drift delay Pattern dropped below threshold, probably triggered on noise ALCT vpf or CLCT vpf arrived but did not match in ALCT window No Level 1 Accept arrived in L1A window after TMB triggered Constant flash rate = buffers full ON = TMB FPGA loaded successfully from PROM Flashes OFF when module addressed by VME NB: All external triggers (including scintillator and ALCT active FEB) create a dummy CLCT to force the TMB to read out raw hits. ALCT triggers can produce an LCT match if the ALCT active FEB is followed by an ALCT valid pattern flag. Page 64 of 83 06/11/04 1:58 PM TMB Total I/O Count Table 10: TMB Total I/O Count Bits Pins Dir Logic Connect To 1 26 4 12 7 240 57 6 2 80 24 16 5 2 26 4 12 7 120 29 6 1 40 24 16 5 In In In In In In In In In In In BiDir In LVDS GTLP GTLP GTLP GTLP LVDS LVDS LVTTL GTLP LVTTL TTL TTL LVTTL CCB CCB CCB CCB + 9 DMB + 9 TMB CCB + 9 TMB 5 CFEBs ALCT 1 DMB MPC RPC VME VME JTAG 480 292 Bits Pins Dir Logic Connect To 0 0 18 0 25 5 33 50 64 0 0 1 0 0 18 0 25 5 21 50 32 0 0 1 Out Out Out Out Out Out Out Out Out Out Out Out LVDS GTLP GTLP GTLP GTLP LVDS LVDS LVTTL GTLP LVTTL TTL LVTTL CCB CCB CCB CCB + 9 DMB + 9 TMB CCB + 9 TMB 5 CFEBs ALCT 1 DMB MPC RPC VME JTAG 196 152 Function Clock Bus Fast Control Bus TMB Reload Bus DAQ Special Purpose Bus Trigger Special Purpose Bus CFEB Comparators ALCT Module DMB commands MPC winner RPC Inputs VME Address VME Data JTAG Totals Function Clock Bus Fast Control Bus TMB Reload Bus DAQ Special Purpose Bus Trigger Special Purpose Bus CFEB Comparators ALCT Module DMB data MPC winner RPC Inputs VME data is BiDir JTAG Totals FPGA I/O Estimate: 392 in – 7 clock + 152 out = 537 Page 65 of 83 06/11/04 1:58 PM TMB2001 Connectors TMB Connector Summary Table 11: TMB2001 Connector Summary ID Pins J0 J1 J2 J3 J4 J5 J6 J7 P1 P2A P2B P3A P3B 50 50 50 50 50 50 50 10 160 125 55 55 125 Type SCSI-II SCSI-II SCSI-II SCSI-II SCSI-II SCSI-II SCSI-II Header VME64x Z-Pack 25x5 Z-Pack 11x5 Z-Pack 11x5 Z-Pack 25x5 Function CFEB0 Inputs + Clock Out CFEB1 Inputs + Clock Out CFEB2 Inputs + Clock Out CFEB3 Inputs + Clock Out CFEB4 Inputs + Clock Out ALCT Cable 1 Inputs ALCT Cable 2 I/O Xilinx LVDS X-Blaster I/O VME J1/P1 Bus I/O CCB + DMB I/O DMB I/O MPC I/O RPC Inputs + ALCT alternate I/O Page 66 of 83 06/11/04 1:58 PM J0-J4 CFEB0-CFEB4 Connectors Function: Receives 80MHz data from CFEBs. Transmits 40MHz clock. Connector Type: PCB: Cable: Shell: AMP 787190-5 AMP 749111-4 AMP 749889-3 [with latches] Table 12: J0-J4 CFEB0/4-to-TMB Connectors (This table uses Layer numbers Ly0-to-Ly5, Triad numbers Tr0-to-Tr7) Pair 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Pin 1+ 3+ 5+ 7+ 9+ 11+ 13+ 15+ 17+ 19+ 21+ 23+ 25+ 27+ 29+ 31+ 33+ 35+ 37+ 39+ 41+ 43+ 45+ 47+ 49+ 2468101214161820222426283032343638404244464850- Dir Logic In In In In In In In In In In In In Out In In In In In In In In In In In In LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS Multiplexed Signals Ly0Tr0 Ly0Tr2 Ly5Tr0 Ly5Tr2 Ly1Tr0 Ly1Tr2 Ly0Tr4 Ly0Tr6 Ly5Tr4 Ly5Tr6 Ly1Tr4 Ly1Tr6 Ly3Tr0 Ly3Tr2 Ly4Tr0 Ly4Tr2 Ly2Tr0 Ly2Tr2 Ly3Tr4 Ly3Tr6 Ly4Tr4 Ly4Tr6 Ly2Tr4 Ly2Tr6 LCT_Clock Ly1Tr7 Ly2Tr7 Ly1Tr5 Ly2Tr5 Ly5Tr7 Ly4Tr7 Ly5Tr5 Ly4Tr5 Ly0Tr7 Ly3Tr7 Ly0Tr5 Ly3Tr5 Ly1Tr3 Ly2Tr3 Ly1Tr1 Ly2Tr1 Ly5Tr3 Ly4Tr3 Ly5Tr1 Ly4Tr1 Ly0Tr3 Ly3Tr3 Ly0Tr1 Ly3Tr1 Page 67 of 83 06/11/04 1:58 PM J5 ALCT Cable1 Connector (Receiver) Function: Receives 80MHz data from ALCT. Connector Type: PCB: Cable: Shell: AMP 787190-5 AMP 749111-4 AMP 749889-3 [with latches] Table 13: J5 ALCT Cable1 Connector [J10 on ALCT board] Modified 4/12/01 to match ALCT2001 PCB. Stinking bad signal inversion = / Pair 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Inverted / / / / / / / / / / / / / Pin Dir + - 1+ 49+ 3+ 47+ 5+ 45+ 7+ 43+ 9+ 41+ 11+ 39+ 13+ 37+ 15+ 35+ 17+ 33+ 19+ 31+ 21+ 29+ 23+ 27+ 25+ 2504486468441042124014381636183420322230242826- Logic Multiplexed Signals First in Time In In In In In In In In In In In In In In In In In In In In In In In In In LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS first_valid first_amu first_quality0 first_quality1 first_key0 first_key1 first_key2 first_key3 first_key4 first_key5 first_key6 bxn0 bxn1 bxn2 daq_data0 daq_data1 daq_data2 daq_data3 daq_data4 daq_data5 daq_data6 lct_special seq_status0 seq_status1 ddu_special Second in Time second_valid second_amu second_quality0 second_quality1 second_key0 second_key1 second_key2 second_key3 second_key4 second_key5 second_key6 bxn3 bxn4 /wr_fifo daq_data7 daq_data8 daq_data9 daq_data10 daq_data11 daq_data12 daq_data13 first_frame seu_status0 seu_status1 last_frame Page 68 of 83 06/11/04 1:58 PM J6 ALCT Cable2 Connector (Transmitter) Function: Sends/Receives 80MHz data to/from ALCT. Connector Type: PCB: Cable: Shell: AMP 787190-5 AMP 749111-4 AMP 749889-3 [with latches] Table 14: J6 ALCT Cable2 Connector [J11 on ALCT board] Modified 4/12/01 to match ALCT2001 PCB. Stinking bad signal inversion / Pair 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 2 Inverted / / / / / / / / / / / / Pin Dir + - 1+ 49+ 3+ 47+ 5+ 45+ 7+ 43+ 9+ 41+ 11+ 39+ 13+ 37+ 15+ 35+ 17+ 33+ 19+ 31+ 21+ 29+ 23+ 27+ 25+ 2504486468441042124014381636183420322230242826- Logic Multiplexed Signals First in Time Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out In In In In LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS Second in Time tdi tms tck jtag_select0 jtag_select1 ccb_brcst0 ccb_brcst4 ccb_brcst1 ccb_brcst5 ccb_brcst2 ccb_brcst6 ccb_brcst3 ccb_brcst7 brcst_str1 subaddr_str dout_str bx0 ext_inject ext_trig level1_accept sync_adb_pulse seq_cmd0 seq_cmd2 seq_cmd1 reserved_in4 2 reserved_in0 reserved_in2 reserved_in1 reserved_in3 async_adb_pulse /hard_reset clock_en clock tdo reserved_out0 reserved_out2 reserved_out1 reserved_out3 active_feb_flag cfg_done Reserved cable input signals connect to ALCT FPGA user input pins Page 69 of 83 06/11/04 1:58 PM J1-J6 SCSI-II 50-Pin Connector Pin Convention Figure 2: 50-Pin PCB Connector (Female)3 (Looking into PCB Connector) ------------------------------------\ 25 1/ \ 26 50/ --------------------------------- Figure 3: 50 Pin Cable Connector (Male) (Looking into Cable Connector) ------------------------------------\1 25/ \ 50 26/ --------------------------------- Figure 4: 50 Pin PCB Connector Pin Convention 1 • 2 3 • 4 5 • • • 11 • 13 • 15 • 17 • 19 • 10 12 14 16 18 20 21 • • 3 • • • • 40 • 38 • 36 • 34 • 32 • • • • • • • • 26 • 47 • 45 • 43 • 41 • 39 • 37 • 35 • 33 • 31 • 29 • 27 • • • • 49 • 42 28 24 25 • 30 22 23 48 44 8 9 • 46 6 7 50 • • • Cable Side (Looking At Top of PCB) • Copied from CFEB design: http://www.physics.ohio-state.edu/~gujh/works/cmpdata.html Page 70 of 83 06/11/04 1:58 PM J7 Xilinx LVDS Xilinx X-Blaster Connector Function: Connects TMB2001 to LVDS x-Blaster for programming FPGAs and PROMs. The LVDS signals and voltage sources on this connector are not directly compatible with the standard Xilinx programming cable. JTAG chain select signals SEL[3:0] are TTL /. Connector Type: PCB: Cable: 3M 3316-5002 3M 3452-6600 16-pin right angle center key 16-pin center bump Table 15: J8 Xilinx LVDS X-Blaster Connector +TCK +TDO +TMS +3.3V +TDI +3.3V SEL0 (TTL) SEL2 (TTL) In Out In Out In In Out In 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 In Out In In In In In -TCK -TDO -TMS GND -TDI JTAG_EN(TTL) SEL1 (TTL) SEL3 (TTL) Page 71 of 83 06/11/04 1:58 PM P1 Backplane VME64x J1/P1 Connector Function: VME interface. Connector Type: PCB: Backplane: Address bits: 24 Data bits: 16 Geographic Address bits: 5 Harting 02-02-160-2101 Male Right-Angle Harting 02-01-160-2201 Female Table 16: P1 VME64x Connector Pin Row z Row a Row b Row c Row d 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 MPR GND MCLK GND MSD GND MMD GND MCTL GND RESP* GND RsvBus1 GND RsvBus2 GND RsvBus3 GND RsvBus4 GND RsvBus5 GND RsvBus6 GND RsvBus7 GND RsvBus8 GND RsvBus9 GND RsvBus10 GND D00 D01 D02 D03 D04 D05 D06 D07 GND SYSCLK GND DS1* DS0* WRITE* GND DTACK* GND AS* GND IACK* IACKIN* IACKOUT* AM4 A07 A06 A05 A04 A03 A02 A01 -12V +5V BBSY* BCLR* ACFAIL* BG0IN* BG0OUT* BG1IN* BG1OUT* BG2IN* BG2OUT* BG3IN* BG3OUT* BR0* BR1* BR2* BR3* AM0 AM1 AM2 AM3 GND SERCLK SERDAT GND IRQ7* IRQ6* IRQ5* IRQ4* IRQ3* IRQ2* IRQ1* +5VSTDBY +5V D08 D09 D10 D11 D12 D13 D14 D15 GND SYSFAIL* BERR* SYSRESET* LWORD* AM5 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A09 A08 +12V +5V VPC GND +V1 +V2 RsvU -V1 -V2 RsvU GAP* GA0* GA1* +3.3V GA2* +3.3V GA3* +3.3V GA4* +3.3V RsvBus11 +3.3V RsvBus12 +3.3V RsvBus13 +3.3V RsvBus14 +3.3V LI/I* +3.3V LI/O* +3.3V GND VPC Page 72 of 83 06/11/04 1:58 PM P2A Backplane CCB+DMB Connector Function: Sends and receives data to/from CCB, and carries some DMB signals. Connector Type: PCB: Backplane: AMP Z-Pack 125 (25 rows of 5 pins) female AMP 100145-1 AMP Z-Pack 125 (25 rows of 5 pins) male AMP ? Table 17: P2A Backplane CCB+DMB Connector Pin Dir Logic Signal Pin Dir Logic Signal A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 In In In In In In In In In In Out Out Out Out Out Out Out LVDS GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP ccb_clock40+ ccb_clock40_enable ccb_cmd0 ccb_cmb4 ccb_cmd_strobe ccb_data0 ccb_data4 ccb_reserved0 tmb_hard_reset alct_adb_pulse_sync clct_status0 clct_status4 clct_status6 alct_status3 alct_status7 tmb_reserved_in0 tmb_reserved_in4 In In In In In In In In In In Out Out Out Out Out Out In LVDS GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP ccb_clock40ccb_reserved4 ccb_cmd1 ccb_cmb5 ccb_bx0 ccb_data1 ccb_data5 ccb_reserved1 alct_hard_reset alct_adb_pulse_async clct_status1 clct_status5 alct_status0 alct_status4 alct_status8 tmb_reserved_in1 tmb_reserved_out0 In In In GTLP GTLP GTLP dmb_cfeb_calibrate0 dmb_reserved_out0 dmb_reserved_out4 In In (In)1 GTLP GTLP GTLP dmb_cfeb_calibrate1 dmb_reserved_out1 dmb_reserved_in0 Out Out Out LVTTL LVTTL LVTTL B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 Out Out Out LVTTL LVTTL LVTTL tmb_data0 tmb_data4 tmb_data8 tmb_data1 tmb_data5 tmb_data9 Pins C1 through C25 are connected to Backplane Ground Notes: 1) TMB can monitor signals to/from DMB, but can not assert them. Page 73 of 83 06/11/04 1:58 PM P2A Backplane CCB+DMB Connector Continued Table 17: P2A Backplane CCB Connector Continued Pin Dir Logic Signal D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 Out GTLP tmb_config_done In In In In In In In In Out Out Out Out Out Out In GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP ccb_cmd2 ccb_evcntres ccb_l1accept ccb_data2 ccb_data6 ccb_reserved2 tmb_reserved0 clct_external_trigger clct_status2 clct_status6 clct_status1 alct_status5 tmb_l1a_request tmb_reserved_in2 tmb_reserved_out1 In In (In)1 GTLP GTLP GTLP dmb_cfeb_calibrate2 dmb_reserved_out2 dmb_reserved_in1 Out Out Out LVTTL LVTTL LVTTL tmb_data2 tmb_data7 tmb_data11 Pin Dir Logic Signal E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 Out GTLP alct_config_done In In In In In In In In Out Out Out Out Out Out In GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP ccb_cmd3 ccb_bcntres ccb_data_strobe ccb_data3 ccb_data7 ccb_reserved3 tmb_reserved1 alct_external_trigger clct_status3 clct_status7 alct_status2 alct_status6 tmb_l1a_release tmb_reserved_in3 tmb_reserved_out2 (In)1 In (In)1 GTLP GTLP GTLP dmb_l1a_release dmb_reserved_out3 dmb_reserved_in2 Out Out Out LVTTL LVTTL LVTTL tmb_data3 tmb_data7 tmb_data11 Notes: 1) TMB can monitor signals to/from DMB, but can not assert them. Page 74 of 83 06/11/04 1:58 PM P2B Backplane DMB Connector Function: Sends and receives data to/from DMB. Connector Type: PCB: Backplane: AMP Z-Pack 55 (11 rows of 5 pins) female AMP 100161-1 AMP Z-Pack 55 (11 rows of 5 pins) male AMP ? Table 18: P2B Backplane DMB Connector Pin Dir Logic Signal A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 Out Out Out Out Out Out Out Out Out In Out LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL Pin Dir Logic D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 Out Out Out Out Out Out Out Out In Out Out LVTTL tmb_data14 LVTTL alct_data3 LVTTL alct_data7 LVTTL alct_data11 LVTTL tmb_ddu_special LVTTL tmb_active_feb_flag LVTTL tmb_active_feb3 LVTTL /alct_write_enable_fifo LVTTL res_from_dmb1 LVTTL res_to_dmb5 LVTTL res_to_dmb4 tmb_data12 alct_data1 alct_data5 alct_data9 alct_data13 tmb_data_available tmb_active_feb1 fifo_clock alct_last_frame res_from_dmb2 res_to_dmb2 Signal Pin Dir Logic C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 In In In In In In In In In In In Pwr Pwr Pwr Pwr Pwr Pwr Pwr Pwr Pwr Pwr Pwr Pin Dir Logic Signal B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 Out Out Out Out Out Out Out In In In Out LVTTL tmb_data13 LVTTL alct_data2 LVTTL alct_data6 LVTTL alct_data10 LVTTL alct_data14 LVTTL /tmb_write_enable_fifo LVTTL tmb_active_feb2 LVTTL dmb_request_lct LVTTL dmb_ext_trig LVTTL res_from_dmb3 LVTTL res_to_dmb3 Pin Dir Logic Signal E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 Out Out Out Out Out Out Out Out Out Out In LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL alct_data0 alct_data4 alct_data8 alct_data12 tmb_last_frame tmb_active_feb0 tmb_active_feb4 alct_ddu_special alct_data_available res_to_dmb1 dmb_fpga_pgm_done Signal Gnd VTT (+1.5V) Gnd VTT Gnd VTT Gnd VTT Gnd VTT Gnd Page 75 of 83 06/11/04 1:58 PM P3A Backplane MPC Connector Function: Sends and receives data to/from MPC. Connector Type: PCB: Backplane: AMP Z-Pack 55 (11 rows of 5 pins) female AMP 100161-1 AMP Z-Pack 55 (11 rows of 5 pins) male AMP ? Table 19: P3A Backplane MPC Connector See ADR_MPCx_FRAMEx on page 34 for signal assigments Pin Dir Logic A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 Out Out Out Out Out Out Out Out In GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP Pin Dir Logic D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 Out Out Out Out Out Out Out Out GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP Signal /mpc_out0 /mpc_out4 /mpc_out8 /mpc_out12 /mpc_out16 /mpc_out20 /mpc_out24 /mpc_out28 lct_winner Signal /mpc_out2 /mpc_out6 /mpc_out10 /mpc_out14 /mpc_out18 /mpc_out22 /mpc_out26 /mpc_out30 Pin Dir Logic B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 Out Out Out Out Out Out Out Out GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP Pin Dir Logic E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 Out Out Out Out Out Out Out Out GTLP GTLP GTLP GTLP GTLP GTLP GTLP GTLP Signal /mpc_out1 /mpc_out5 /mpc_out9 /mpc_out13 /mpc_out17 /mpc_out21 /mpc_out25 /mpc_out29 Signal /mpc_out3 /mpc_out7 /mpc_out11 /mpc_out15 /mpc_out19 /mpc_out23 /mpc_out27 /mpc_out31 Pins C1 through C11 are connected to Backplane Ground Page 76 of 83 06/11/04 1:58 PM P3B Backplane RPC+ALCT Connector Function: Sends and receives data to/from ALCT, and receives from RPC. Connector Type: PCB: Backplane: AMP Z-Pack 125 (25 rows of 5 pins) female AMP 100145-1 AMP Z-Pack 125 (25 rows of 5 pins) male AMP ? Table 20: P3B Backplane RPC+ALCT Connector Pin Signal Pin Signal Pin Signal A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 rpc_rx30 rpc_rx25 rpc_rx20 rpc_rx15 rpc_rx10 rpc_rx5 rpc_rx0 tdi smbrx rpc_in33 +3.3V alct_rx30 alct_rx25 alct_rx20 alct_rx15 alct_rx10 alct_rx5 alct_rx0 alct_clock alct_tx22 alct_tx17 alct_tx12 alct_tx7 alct_tx2 +1.8V C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 rpc_rx29 rpc_rx24 rpc_rx19 rpc_rx14 rpc_rx9 rpc_rx4 rpc_clock rpc_loop rpc_in37 rpc_in32 GND alct_rx29 alct_rx24 alct_rx19 alct_rx14 alct_rx9 alct_rx4 smbtx alct_clk_en alct_tx21 alct_tx16 alct_tx11 alct_tx6 alct_tx1 GND rpc_rx31 rpc_rx26 rpc_rx21 rpc_rx16 rpc_rx11 rpc_rx6 rpc_rx1 tms tdo rpc_in34 +3.3V alct_rx31 alct_rx26 alct_rx21 alct_rx16 alct_rx11 alct_rx6 alct_rx1 alct_oe alct_tx23 alct_tx18 alct_tx13 alct_tx8 alct_tx3 +1.8V Pin Signal Pin Signal D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 rpc_rx28 rpc_rx23 rpc_rx18 rpc_rx13 rpc_rx8 rpc_rx3 smb_clk posneg rpc_in36 GND alct_rx28 alct_rx23 alct_rx18 alct_rx13 alct_rx8 alct_rx3 hrst_rpc txoe alct_tx20 alct_tx15 alct_tx10 alct_tx5 alct_tx0 GND rpc_rx27 rpc_rx22 rpc_rx17 rpc_rx12 rpc_rx7 rpc_rx2 tck sync rpc_in35 +3.3V GND alct_rx27 alct_rx22 alct_rx17 alct_rx12 alct_rx7 alct_rx2 free_tx0 alct_loop alct_tx19 alct_tx14 alct_tx9 alct_tx4 +1.8V GND Page 77 of 83 06/11/04 1:58 PM Backplane Pin Diagram X1A X1B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 CLK+ Clock_Enable ccb_cmd0 ccb_cmd4 ccb_cmd_strobe ccb_data0 ccb_data4 ccb_reserved0 tmb_hard_reset alct_adb_pulse_sync clct_status0 clct_status4 clct_status8 alct_status3 alct_status7 tmb_reserved_in0 tmb_reserved_in4 dmb_cfeb_calibrate0 dmb_reserved_out0 dmb_reserved_out4 tmb_data0 tmb_data4 tmb_data8 ZPack125 X2A 1 2 3 4 5 6 7 8 9 10 11 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 tmb_data12 tmb_data16 tmb_data20 tmb_data24 tmb_data28 first_frame active_feb1 fifo_clock reserved_to_dmb2 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 1 2 3 4 5 6 7 8 9 10 11 lct_vpf lct_quality3 lct_quality7 lct_hs2 lct_hs6 lct_wg2 lct_wg6 lct_reserved0 lct_winner 1 2 3 4 5 6 7 8 9 10 11 X18B A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 ZPack125 X18C B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 tmb_data1 tmb_data5 tmb_data9 ZPack125 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 ZPack125 X2C B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 tmb_data13 tmb_data17 tmb_data21 tmb_data25 tmb_data29 write_enable active_feb2 dmb_request_lct reserved_from_dmb0 1 2 3 4 5 6 7 8 9 10 11 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 lct_quality0 lct_quality4 lct_quality8 lct_hs3 lct_hs7 lct_wg3 lct_accmu lct_reserved1 1 2 3 4 5 6 7 8 9 10 11 ZPack55 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 ZPack125 X1E 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 tmb_cfg_done_ ccb_cmd2 ccb_evcntres ccb_l1accept ccb_data2 ccb_data6 ccb_reserved2 tmb_reserved0 clct_external_trigger clct_status2 clct_status6 alct_status1 alct_status5 tmb_l1a_request tmb_reserved_in2 tmb_reserved_out1 dmb_cfeb_calibrate2 dmb_reserved_out2 dmb_reserved_in1 tmb_data2 tmb_data6 tmb_data10 ZPack125 X2D C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 1.5V 1 2 3 4 5 6 7 8 9 10 11 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 X3D 1 2 3 4 5 6 7 8 9 10 11 ZPack55 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 alct_cfg_done_ ccb_cmd3 ccb_bcntres ccb_data_strobe ccb_data3 ccb_data7 ccb_reserved3 tmb_reserved1 alct_external_trigger clct_status3 clct_status7 alct_status2 alct_status6 tmb_l1a_release tmb_reserved_in3 tmb_reserved_out2 dmb_l1a_release dmb_reserved_out3 dmb_reserved_in2 tmb_data3 tmb_data7 tmb_data11 ZPack125 X2E D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 tmb_data14 tmb_data18 tmb_data22 tmb_data26 ddu_special active_feb_flag active_feb3 reserved_to_dmb0 reserved_from_dmb1 ZPack55 ZPack55 X3C X18D C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 X1D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 dmb_cfeb_calibrate1 dmb_reserved_out1 dmb_reserved_in0 ZPack55 X18A ZPack125 CLKccb_reserved4 ccb_cmd1 ccb_cmd5 ccb_bx0 ccb_data1 ccb_data5 ccb_reserved1 alct_hard_reset alct_adb_pulse_async clct_status1 clct_status5 alct_status0 alct_status4 alct_status8 tmb_reserved_in1 tmb_reserved_out0 ZPack55 X3B ZPack55 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 ZPack125 X2B ZPack55 X3A 1 2 3 4 5 6 7 8 9 10 11 X1C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 10 11 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 tmb_data15 tmb_data19 tmb_data23 tmb_data27 last_frame active_feb0 active_feb4 reserved_to_dmb1 reserved_from_dmb2 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 lct_quality2 lct_quality6 lct_hs1 lct_hs5 lct_wg1 lct_wg5 lct_bxn1 lct_reserved3 ZPack55 X3E D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 lct_quality1 lct_quality5 lct_hs0 lct_hs4 lct_wg0 lct_wg4 lct_bxn0 lct_reserved2 1 2 3 4 5 6 7 8 9 10 11 ZPack55 X18E D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 ZPack125 Page 78 of 83 06/11/04 1:58 PM Front Panel Connector Locations -------------------------Front Panel Æ | ----^ | | | to 2.130” | Pin | one \/ ----Pin ^ one | | | to 2.130” | Pin | one \/ ----Pin ^ one | | | to 2.130” | Pin | one \/ ----Pin ^ one | | | to 2.130” | Pin | one \/ ----Pin ^ one | to 1.990” bottom | edge \/ ----Pin one | | Multipurpose connector goes here | | ---||. . | CFEB0 || . .| ||. . | || . .| ||. . | || . .| <- Pin 1 here (10.510) | ---| | ---||. . | || . .| ||. . | || . .| ||. . | || . .| <- Pin 1 here (8.380) | ---| | ---||. . | || . .| ||. . | || . .| ||. . | || . .| <- Pin 1 here (6.250) | ---| | ---||. . | || . .| ||. . | || . .| ||. . | || . .| <- Pin 1 here (4.120) | ---| | ---||. . | || . .| ||. . | || . .| ||. . | || . .| <- Pin 1 here (moved up from previous position 4/11/2001) | ---| | Optical output here | | ---------------------------------------- Page 79 of 83 06/11/04 1:58 PM PCB Shunts Table 20: PCB Shunts Shunt SH50 SH55 SH56 SH57 SH62 SH74 SH95 SH99 SH104 SH105 SH106 SH107 SH69-1 SH69-2 SH1081 SH1082 Module Clock VME VME VME VME JTAG VME Power VME VME VME VME Power Power VME VME 1-2 Normal Operation Position 2-3 Special Operations Select CCB 40MHz clock Select 40MHz on-board crystal Enable bootstrap global address SW1 SW2 Disable Enable bootstrap geographic address Disable Enable bootstrap VME logic Disable Select backplane as geographic address Select SW1-SW2 as geographic address JTAG chain select comes from X-blaster JTAG chain select comes from SW3 Enable CCB hard reset to clear bootstrap register Disable Select +3.3Vcc for U99+U101 delay chips Select +5Vcc Enable VME hard reset for TMB and ALCT Disable Enable CCB hard reset for TMB and ALCT Disable Enable ALCT hard reset by FPGA Disable Enable TMB hard reset by FPGA (self reset) Disable Disconnect +3.3V from U69 1.5Vregulator input Connect +3.3V to U69 1.5Vregulator input Select backplane as source of +1.5V Select U69 as source of +1.5V TMB hard reset pulse width set by CCB TMB hard reset pulse width 400ns one-shot ALCT hard reset pulse width set by CCB ALCT hard reset pulse width 400ns one-shot Page 80 of 83 06/11/04 1:58 PM CCB Front Panel CCB Input connector P10 Pin (+) 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 Pin (-) 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 Signal external_clock40 external_clock40_enable external_l1accept dmb_cfeb_calibrate[0] dmb_cfeb_calibrate[1] dmb_cfeb_calibrate[2] alct_adb_pulse_sync alct_adb_pulse_async clct_external_trigger alct_external_trigger tmb_l1a_request ccb_fp_reserved_in[0] ccb_fp_reserved_in[1] CCB Output connector P11 Pin (+) 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 Pin (-) 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 Signal clct_status[0] clct_status[1] clct_status[2] clct_status[3] clct_status[4] clct_status[5] clct_status[6] clct_status[7] clct_status[8] ccb_clock40 ccb_bx0 ccb_l1accept ccb_cmdstr ccb_fp_reserved_out[0] Test Point 391-1 391-2 391-3 391-4 391-5 391-6 391-7 391-8 391-9 TMB Assignment pretrig seq_busy invpat daqmb l1a_window l1a tmb tmb_flush nol1a_flush Description Sequencer pre-triggered Sequencer busy Invalid pattern after drift delay Dump to DMB in progress L1A window L1A (should be in L1A window) CLCT sent for TMB match TMB found no match or rejected trigger No L1A, Sequencer flushing event Page 81 of 83 06/11/04 1:58 PM CCB Output connector P12 Pin (+) 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 Pin (-) 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 Signal alct_status[0] alct_status[1] alct_status[2] alct_status[3] alct_status[4] alct_status[5] alct_status[6] alct_status[7] alct_status[8] Test Point 392-1 392-2 392-3 392-4 392-5 392-6 392-7 392-8 392-9 TMB Assignment alct_active_feb first_valid second_valid first_amu second_amu /wr_fifo(alct) alct_vpf clct_vpf scint_veto Description ALCT fast active AFEB First muon valid pattern flag Second muon valid pattern flag First accelerator muon flag Second accelerator muon flag ALCT /write enable raw-hit FIFO ALCT 1st Valid Pattern (TMB pipe) CLCT 1st Valid Pattern (TMB pipe) Scintillator Veto (clears via VME) Page 82 of 83 06/11/04 1:58 PM Revision History Version Date Action 1.00 1.01 1.02 1.03 1.04 2.01 2.01 2.02 07/12/03 10/29/03 03/15/04 03/16/04 04/15/04 05/19/04 06/09/04 06/10/04 Initial, copied from TMB2001 Replaced PHOS4 registers with DDD, update shunts table, rat signals updated Update 3D3444 registers, add RAT/RPC registers Move RAT register addy to match bdtest.v Copy from TMB2003 Add RPC Readout New registers B6-CC, 4 new header words, new raw hits format, started logic docs Add mpc_tx_delay, modify header 21,22 Page 83 of 83 06/11/04 1:58 PM

TMB 2004 Design Table of Contents UCLA High Energy Physics Version 2.02

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