by
MASSACHUSETTS INSTITUTE OF TECHNOLOGY
JUL 15 2014
@
.
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An On-Chip Input Driver for a High-Voltage SAR ADC by
Submitted to the Department of Electrical Engineering and Computer Science on May 9, 2014, in partial fulfillment of the requirements for the degree of
Master of Science in Electrical Engineering and Computer Science
Abstract
This thesis describes the design of a novel on-chip input driver for a SAR ADC. The driver achieves performance gains relative to off-chip alternatives by being integrated into the signal path of the ADC between the sampling switches and sampling capacitor. This placement allows for auto-zeroing the offset of the driver and reducing flicker noise. Additional performance benefits are possible because the driver can be optimized for the specific load and timings of the ADC. The most important benefit of an on-chip input driver is that it simplifies the design process for the ADC user by eliminating the external op-amp and reducing the constraints on the external filter by reducing input current load. Design simplicity is especially important to users in high-voltage SAR ADC applications, so the input driver is designed for an
ADC with a 10.24 V input range and 15 V supply rails. This high-voltage input relaxes noise and headroom constraints, but makes device overvoltage a significant concern. The driver is designed in a BiCMOS process, and simulation results with a computer-modeled ADC are presented here. In these simulations, the driver achieves a THD of -124.7 dB at 2 kHz and a noise voltage spectral density of 5.5 nV/v Hz with a power consumption of 27.6 mW. The LT1469, an example of a state-of-the-art external input driver, has a THD of -123 dB at 2 kHz, a noise voltage spectral density of 5 nV/VHz, and a power consumption of 123 mW.
Thesis Supervisor: Micah G. O'Halloran
Title: Design Engineering Section Lead, Linear Technology
Thesis Supervisor: Charles G. Sodini
Title: LeBel Professor, Electrical Engineering
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First and foremost, I would like to thank Micah O'Halloran, my thesis supervisor at
Linear Technology. Micah was an outstanding supervisor who always found time to answer my questions and offer advice. He is responsible for much of my understanding of analog circuit design. Without his assistance and expertise, this project would not have been possible. I would also like to thank two other Linear engineers, Andrew
Thomas and Joe Sousa. Both were excellent sources of help and advice. Andrew in particular always had insightful answers to my toughest questions.
I am thankful to Prof. Charles Sodini, my faculty thesis advisor, for his help during the project, as well as his review of the thesis and suggestions for improvement. I am also appreciative of Prof. Sodini's advising throughout my MIT experience.
Finally, I would like to thank my parents, Kathy and Bob, for their love, support, and guidance. Without their parenting effort I would not be where I am or who I am today.
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1 Introduction
1.1 Background . . . . . . . . . . . . .
1.2 Project Motivation . . . . . . . . .
1.3 Approach .................
1.4 Thesis Organization . . . . . . . . .
2 Input Driver Circuit Design
2.1 Performance Goals . . . . . . . . .
2.2 Driver Circuit Design Summary . .
2.3 Low-Voltage Driver Core . . . . . .
2.4 Low-Voltage Rail Generator Circuit
2.5 Protection Devices . . . . . . . . .
2.6 Sample Switch. . . . . . . . . . . .
3 Simulation
3.1 ADC Test Bench . . . . . . . . . . .
3.2 Total Harmonic Distortion . . . . . .
3.3 Output Noise . . . . . . . . . . . . .
3.4 Power Consumption . . . . . . . . .
3.5 Gain Error and Integral Nonlinearity
3.6 Overvoltage . . . . . . . . . . . . . .
3.7 Summary . . . . . . . . . . . . . . .
. . . . . . . . . . . .
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43
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4 Conclusion 47
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1-1 Simplified schematic of SAR ADC . . . . . . . . . . . . . . . .
1-2 Equivalent circuit for the analog input of a typical SAR ADC
1-3 LTC2389 recommended external input driver . . . . . . . . . .
1-4 Simplified schematic of SAR ADC with input drivers.....
1-5
2-4
2-5
2-6
2-1
2-2
2-3
Input driver system diagram . . . . . . . . . . . . . . . . . . .
Full driver schematic . . . . . . . . . . . .
Low-voltage driver core schematic . . . . .
Driver core mirror schematic . . . . . . . .
Low-voltage rail generator schematic .
. .
Protection clamps . . . . . . . . . . . . . .
Simplified model of ADC sampling switch
3-1
3-2
3-3
3-4
3-5
Diagram of simulated ADC . . . . . . . .
. . . . . . . . . . . . . . .
4 0
DFT of ADC with input driver . . . . . . . . . . . . . . . . . . . . .
4 1
Input driver noise voltage spectral density . . . . . . . . . . . . . . .
4 2
Gain error and INL . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 4
Overvoltage testing waveforms . . . . . . . . . . . . . . . . . . . . . .
4 5
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30
31
34
36
38
14
15
16
19
22
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1.1 ADC recommended input drivers . . . . . . . . . . . . . . . . . . . . 17
3.1 Subcircuit current consumption and total driver power . . . . . . . . 43
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Successive-approximation-register analog-to-digital converters (SAR ADCs) are the most commonly used architecture for medium- to high-resolution ADC applications.
This widespread adoption stems from the fact that SAR ADCs achieve a combination of high accuracy, moderately fast conversion rates and low power consumption. SAR
ADC applications include data acquisition, medical instrumentation, communication, and industrial process control. In particular, within the industrial application space, there is an important niche for high-voltage, high-speed, low-noise, SAR ADCs. Ex- amples of popular ADCs with these characteristics include the LTC2338, LTC2328,
AD7671, AD7612 and AD7609 [1, 2, 3, 4, 5]. This thesis describes the design of an on-chip input driver for a high-voltage SAR ADC similar to the LTC2338, an 18-bit,
1 Msps, SAR ADC with a 10.24 V input range.
An important issue for modern SAR ADCs is input drive circuitry. An input driver is the link between an ADC and the analog signal it is processing. It allows the ADC sampling capacitor to settle to the value of the input voltage within the acquisition interval for a wide variety of application-specific signal impedances. Since the SAR algorithm makes the bit decisions for the digital output sequentially, SAR ADCs can only use a fraction of each sampling period for settling the sampling capacitor to the correct input voltage. Noise requirements dictate that this sampling capacitance
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must be relatively large, so making sure that it settles to the input voltage with sufficient accuracy requires a fast input driver. At the same time, this driver must be very low noise in order to avoid reducing the overall noise performance of the ADC.
The requirement for a fast input driver holds true even if the input signal is very low frequency. The internal sampling capacitors in a SAR ADC are typically reset between each conversion, so a pulse of current is drawn from the input every time the ADC samples, even if the input signal is DC. Figure 1-1 illustrates the relevant switches and capacitances connected to the input of the SAR ADC. The ADC in the figure has two inputs, positive and negative, with a sample capacitor for each input. During the acquisition period, which is the first part of each sampling period, these capacitors are connected to the inputs through the sample switches on one end and grounded on the other end. It is during this time, which is only a fraction of the sampling period, that the input drivers must settle the sample capacitors to the correct value. Next, during the conversion period, the sample capacitors are disconnected from the input and ground and reconnected to ground on one end and the DAC capacitors on the other. This connection transfers charge from the sample caps to the DAC, where it is used to perform the SAR algorithm during the conversion period and produce a binary output.
I/ On-Chip Bufers
Vin+
SAR
DAC
Sample Switches
Figure 1-1: Simplified schematic of the input switches and capacitances of a SAR
ADC
For the purposes of designing external input drivers, each analog input to a SAR
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ADC can be viewed as a switch in series with a resistor and a capacitor. Figure 1-2 shows the equivalent circuit for the analog input of a typical high-performance SAR
ADC [6]. The diodes on the input serve as ESD protection.
Vdd
pF
40 Ohm
Vdd
40 pF
40 Ohm
Figure 1-2: Equivalent circuit for the analog input of a typical SAR ADC
Currently, almost all SAR ADCs use external input drivers. For the LTC2389, the recommended input driver consists of an operational amplifier to supply the spikes of current demanded by the ADC during sampling, and a RC low-pass filter to limit the noise introduced by the driver amplifier. This combination of an operational amplifier and low-pass filter represents the typical input network for a SAR ADC. Figure 1-3 shows the recommended external input driver for the LTC2389. The driver op-amp is configured as a unity-gain buffer by connecting its output to its inverting input. This configuration creates a buffer amplifier with very high input impedance and very low output impedance. The main SAR ADCs that do not use external input drivers are
ADCs with multiple input channels, including the AD7609. For an ADC with eight input channels, using on-chip input drivers saves the user the cost of implementing eight external drivers.
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10
I nF-
LTC21,)389
10 Ohm 49.9 Ohm
Figure 1-3: LTC2389 ADC showing recommended external input driver
The two motivations for moving the input driver of a high-voltage SAR ADC onto the chip are simplicity and power savings. Design simplicity is an important concern for ADC users, and incorporating the driver onto the chip removes the need for an external amplifier and reduces the constraints on the external filter. Removal of the external amplifier is an obvious benefit, as it eliminates the process of selecting an amplifier and also saves money and board space. Ideally, designing an input filter for an ADC would be as simple as choosing a cutoff frequency above the highest frequency expected in the input signal and below the Nyquist frequency to reduce noise and avoid aliasing. However, with external input drivers, the design process is much more complicated. Now, the filter must be slow enough to filter out sufficient noise from the chosen amplifier while being fast enough to settle the ADC sampling capacitor to within the precision of the converter during each acquisition window. The resulting filter typically has a much higher cutoff frequency than the user would otherwise select in order to allow for settling of the sampling capacitor. Furthermore, design simplicity is more valued by users of high-voltage ADCs than users of low-voltage
ADCs. In general, an alternative to using a high-voltage ADC is to attenuate the input signal and use a normal, low-voltage ADC [6]. Users who desire simplicity or a low component count avoid this step by choosing a high-voltage ADC. Incorporating the ADC driver onto the chip thus gives the user even more of the simplicity they
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seek.
Power savings is also an important motivation behind designing an on-chip driver.
Surveying the currently available high-voltage SAR ADCS, the power consumption of the driver is often higher than that of the ADC. Table 1.1 lists several popular SAR
ADCs, their power consumption, their recommended input drive amplifiers, and the power consumption of their input drive amplifiers. Of the ADCs listed, the LTC2338 is most similar to the ADC for which the on-chip driver described in this thesis is designed. Both are 18-bit, 1 Msps, SAR ADCs with input range 10.24 V. The recommended driver for this ADC is the LT1469, which consumes 123 mW of power per amplifier for a total of 246 mW for the two analog inputs [7]. The ADC itself only consumes 50 mW of power. The fact that the amplifiers consume 83% of the total system power speaks to the difficultly of settling the sampling capacitor to 18-bit precision during the acquisition period without introducing excessive noise. Moving the driver amplifier onto the chip helps reduce power consumption for two reasons.
Primarily, the amplifier can be optimized for the specific load and timings of the
ADC with which it shares a chip. Although it is possible to choose an input amplifier that is tailored for high accuracy applications, such as the LT1469, these amplifiers must always be somewhat general purpose and usable with a wide range of loads.
Additionally, moving the input driver onto the chip means that the amplifier can be integrated with the ADC internals. In the input driver described in this thesis, the placement of the driver in the signal path allows a simpler source follower architecture to be used and reduces flicker noise through auto-zeroing.
ADC
Part
Number
LTC2338 18
LTC2328 18
AD7671 16
AD7612 16
AD7609 18
Number Number Sampling Input SNR THD Power Driver of Bits of Rate Range (dB) (dB) Con- Part
Chan- (sps) (V) sump- Num- nels tion ber
(mW)
1
1
1
1
8 iM iM iM
750k
200k
10.24 100 -115 50
10.24
95 -110 50
10
10
10
90
94
98
-100
-107
-107
112
205
100
LT1469
AD8021
1
Driver
Input
Volt-
5
2.1
Internal Drivers
Power
Consumption age Noise (mw per
(nV/v H-) amplifier)
123
187
Table 1.1: Current high-voltage SAR ADCs and their recommended input drivers
The two input drivers that best represent the current state-of-the-art are the
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LT1469, which is the external input driver used by the LTC2338 ADC, and the internal input drivers of the AD7609 ADC. Since the input drivers of the AD7609 are internal, it seems natural to use them as a baseline for comparison. However, two factors make this approach undesirable. First, the specifications of the AD7609 differ significantly from those of the ADC for which the driver described in this thesis is designed. The sample rate is 200 kHz, rather than 1 MHz, its THD is -107 dB rather than -115 dB, and its input bandwidth is 32 kHz rather than 7 MHz. Second, because the input drivers of the AD7609 are internal, their exact distortion, noise, and power consumption are not publicly available. These parameters can be estimated from the overall performance of the ADC, but not accurately enough to use as a baseline of comparison, particularly for power consumption. Consequently, the LT1469 is a better performance reference because its THD, noise, and power consumption are published in its datasheet, and it is the recommended driver of the LTC2338, which has a sample rate of 1 MHz and a THD of -115 dB.
This thesis describes the design of an on-chip input driver for an 18-bit, 1 Msps, SAR
ADC with a +10.24 V input range and t15 V supply rails designed in a BiCMOS process. Moving the input driver onto the chip allows it to be integrated into the
ADC signal path. Specifically, the driver is placed between the sample switches and the sample caps. This location of the driver within the signal path is the central innovation of this thesis. Figure 1-4 shows the position of the input drivers within the ADC; there are two drivers because each analog input requires its own driver. This placement serves to auto-zero the driver offset. During SAR ADC operation with an external input driver, the sample cap is charged to the value of the input voltage plus the offset voltage of the driver. Then the input driver is disconnected and the input cap is reconnected to ground, moving charge proportional to the input voltage plus the offset voltage onto the ADC DAC capacitors. Since the input driver offset appears in the DAC, this offset must be small enough to not affect the accuracy of
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the converter. This requirement is typically satisfied by using an op-amp configured with unity-gain feedback for the external input driver. When the input driver is moved directly in front of the sample capacitor, the sample cap is still charged to the value of the input voltage plus the offset voltage of the input driver. However, now, at the start of conversion, the input to the driver is- grounded rather than the input to the sample capacitor. This reconnection causes a change in voltage equal to the input voltage at the input of the driver and the same change in voltage at the output of the driver regardless of offset. Thus, charge proportional to just the input voltage and not the driver offset is transferred to the ADC DAC capacitors.
Even if the driver offset changes during the acquisition interval, this change will still be cancelled because only the final value of the offset matters when the input to the driver is grounded. Since the input offset of the driver does not appear on the DAC capacitors, driver architectures with non-zero offset, such as source followers, become potential options. A second benefit of this auto-zeroing technique is that it reduces flicker noise. Flicker noise, or 1/f noise, is the dominant noise component in MOS transistors at low frequencies. The magnitude of flicker noise varies inversely with its frequency, and it can be modeled mathematically as random slow changes in a transistor's threshold voltage. These slow threshold voltage changes appear in the offset of the driver, so they are reduced by auto-zeroing.
V1n
On-Ch BuffersA
SCmp e Caps
DAC
S m Swtches
Vi
Figure 1-4: Simplified schematic of the input switches and capacitances of a SAR
ADC showing the relative position of the input drivers
Integrating the input driver into the ADC signal path has been performed suc-
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cessfully
[9].
This technique places the driver within the successive approximation loop, first using the driver to charge the sample cap, then feeding each of the successive DAC outputs through the driver before they are processed by the comparator.
This process compensates for the non-linearity of the driver, and, like the driver presented in this thesis, is able to cancel flicker noise and other changes in driver offset.
However, other techniques for auto-zeroing driver offset, such as measuring the driver offset during one sample and subtracting it in the analog or digital domain during the next sample, would not be appropriate for the ADC that will be integrated with the input driver described in this thesis. This ADC incorporates a 'sleep mode' to reduce power consumption, in which the ADC partially shuts down during long pauses between conversions. If a driver required the offset from the previous conversion to cancel the offset in the next conversion, the first ADC output after waking up from sleep mode would be inaccurate.
The three most important performance measures of an input drive circuit are distortion, noise and power consumption. The overall goal of any ADC input drive circuit is to achieve low distortion and output noise to avoid compromising the linearity and signal-to-noise ratio of the ADC while keeping power consumption as low as possible. Given these goals, and also the lack of offset voltage constraints imposed
by the input driver placement, a source follower architecture is chosen for the input driver. The advantages of a source follower stem from its simplicity. Each device in the signal path of an amplifier contributes noise, so the fact that a source follower uses the minimum number of devices allows it to have low noise for a given power consumption. Additionally, using a source follower architecture avoids feedback. Feedback is a powerful tool in driver circuits, but it requires that stability be carefully accounted for under all circumstances. Feedback can be used to reduce the output impedance of an amplifier, a desirable outcome, but, in doing, so it can increase output noise by increasing noise bandwidth without reducing noise spectral density. The primary disadvantage of source followers is the large offset voltage they introduce, but, as stated previously, this issue is not a concern.
A source follower is an appealing choice for the input driver architecture, but a
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single MOS transistor would have to consume a prohibitive amount of power in order to meet the distortion constraint of the driver design. However, if the transistor drain voltage were held fixed relative to the gate voltage and the source current remained constant, then the only source of small-signal distortion would be coupling between the transistor and the substrate. This concept is used in the input driver design to improve linearity. It is implemented in the form of two rail generator circuits that each produces a fixed voltage relative to the input. The two rails track changes in the input as closely as possible, making the gate-to-drain voltage of the source follower nearly constant. Creating two rails that track the input voltage of the driver has the added benefit of allowing low-voltage devices to be used in the source follower.
The high-voltage BiCMOS process used for the input driver contains high-voltage
MOS transistors, low-voltage MOS transistors and low-voltage bipolar transistors.
The low-voltage transistors are desirable for the source follower because they have much smaller parasitic capacitances than the high-voltage transistors, improving the linearity of the driver. Figure 1-5 shows the overall system diagram of the input driver, with the low-voltage core driving the output and the two rail generators providing fixed voltage rails relative to the input to improve linearity. The cost of using lowvoltage devices in a high-voltage circuit is that they are susceptible to high-voltage transients during rapid changes in input voltage. Consequently, protection circuits are included in the input driver that guard against overvoltage of low-voltage devices.
This chapter provided background on SAR ADC input drivers, described the benefits of moving the input driver onto the chip in high-voltage applications, and previewed the design approach taken in the thesis. Chapter two describes the design of each of the sub-circuits included in the input driver. Next, chapter three describes the simulation techniques used to verify the design. Finally, chapter four summarizes the material covered in the thesis.
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Vin
Vdd (+ 15V)
~Core
Vss? (-15V)
Figure 1-5: System diagram of the input driver featuring high-voltage power rails, low-voltage rails that track the input voltage, and a source follower core.
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The three key performance metrics of the input driver- distortion, noise, and power consumption- each have corresponding metrics that allow them to be quantified. Distortion is quantified as total harmonic distortion, noise is quantified as either noise voltage spectral density or total output noise, and power consumption is already a numeric value. THD is a measure of the extent to which a system deviates from a perfectly linear one, in which a perfect sinusoidal input would produce a perfect sinusoidal output. It is calculated as the ratio of the root square sum of all harmonics of a signal to the magnitude of the fundamental of the signal.
THD = 20 log (2.1)
V
1
In the case of the input driver, it is measured as the distortion of the output of the driver when fed with a perfect sinusoidal input. THD is measured for both input drivers and ADCs. The THD of the ADC that will be integrated with the driver described in this thesis is close to that of the most similar ADC on the market, the
LTC2338. This ADC achieves a THD of -115 dB for a 2 kHz input sinusoid with magnitude 1 dB below full scale. When choosing an input driver for an ADC, it is important that the driver does not degrade the distortion performance of the ADC
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significantly. The recommended input driver for the LTC2338, the LT1469, has at
THD of -123 dB for a 2 kHz input sinusoid. This value represents a reasonable target for the THD of the thesis input driver, although a lower value is desirable.
Output noise is the random variations the driver adds to its output voltage. It can be measured in two ways. One is noise voltage spectral density, expressed as V/vHz.
This quantity is measured as the square root of the noise power per frequency at a given frequency.
N = Noise voltage spectral density (V/ IHz) = (2.2)
Another noise measurement is total output noise, which is the square root of the integral of noise power over all frequencies.
Vnoise,RMS
J
N 2 df (2.3)
The LTC2338 achieves a SNR of 100 dB, which corresponds to a total noise of 145 pV
RMS. Its recommended driver, the LT1469, achieves a noise voltage spectral density of 5 nV/VH-z. The LTC2338 does not require an external RC filter between the input driver and ADC because an RC filter is formed on-chip by an internal resistor and the sampling capacitor of the ADC. The bandwidth of this filter is 7 MHz. Since the flicker noise of the LT1469 is negligible, the total output noise contributed by the LT1469 can be calculated as the integral of the 5 nV/VHz noise voltage spectral density over the ADC input bandwidth, yielding a total output noise of 16 PV RMS. Noise in the integrated input driver presented in this thesis has different constraints than noise in the external input driver of the LTC2338. Since the output of the integrated driver is connected directly to the ADC sample capacitor, the noise bandwidth is determined
by the output resistance of the input driver and the value of the sample capacitor, resulting in a higher noise bandwidth than seen by an external input driver. Although it increases noise bandwidth, the integration of the driver into the signal path also reduces low-frequency noise such as flicker noise. Noise with frequency less than the
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sampling rate of the ADC appears as changes in the offset of the input driver, so they are reduced by the auto-zeroing action of the driver. As a result, flicker noise of the driver can be much higher than would be acceptable in an external input driver. In order to meet this requirement that flicker noise be negligible, external input drivers are required to consume extra power and additional constraints are placed on device sizes.
Two other relevant metrics are gain error and integral non-linearity. Gain error is a measurement of how accurately a DC input to the driver maps to a DC output once the offset has been removed. Specifically, gain error is the difference between the slope of the driver DC transfer function and an ideal slope of 1 V/V.
Gain error =
Voutmax Voutmin
V 1n,ma. - Vn,rin
(2.4)
Integral non-linearity also measures how well DC inputs to the driver map to DC outputs. It is the maximum deviation between output and input voltages that remains once offset and gain errors have been removed. Gain error is a linear error that relatively easy to correct, so a 4 LSB gain error is considered acceptable; for an 18 bit ADC with a 40.96 V input range, this corresponds to 30.5 ppm. INL values must be less than 1/2 LSB, or 78 pV, in order to not compromise ADC performance.
A final design goal that has an important effect on THD and INL is settling time.
The input settling time of the driver is the amount of time required after a sudden step in input voltage for the output voltage of the driver to settle within a small percentage of the new input voltage. One input settling requirement on the driver circuit is that it can settle the largest possible input step to within a fraction of an
LSB during the acquisition time of the ADC. The input of the driver is reset to ground during the conversion period, so the largest possible input steps are ground to +10.24
V and ground to -10.24 V. The input driver has the duration of the acquisition period to settle this input step. A second input step that the driver must be able to settle occurs when the driver input is grounded at the start of conversion. This step has the same magnitude as the previous steps, but the opposite direction. It also has different
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settling requirements than the previous steps. The ADC that will be integrated with the driver uses a proprietary technique to reduce the required settling accuracy to
1% during this window. Although the settling value is less strict, the input driver also has a shorter period in which to settle: one-third of the acquisition time. This settling requirement is unique to an input driver placed between the sampling switch and sample capacitor. For an ADC with an external input driver, the grounding of the input of the sample capacitor would be performed entirely by the sample switch with no involvement of the input driver. The result is that an extra time interval of
75 ns must be created at the beginning of the conversion period for the output of the driver to settle to ground.
Output settling time is also an important issue for the input driver. Since the output of the driver is directly connected to the ADC sample capacitor, the switching of the DAC capacitors during conversion perturbs the output voltage of the driver.
These temporary changes in output voltage occur because the sample capacitor voltage changes at each bit decision, and the input driver must supply the charge necessary to make these voltage changes. Much less time is available for output step settling than input step settling since 18 bit decisions must be made during the conversion period. Fortunately, because of a proprietary technique, the driver output does not need to fully settle during each bit decision window. Furthermore, because each subsequent bit decision in the SAR algorithm involves a smaller capacitor than the last, the magnitudes of the steps that must be settled become smaller as the conversion period progresses. As a result, the bit decisions that define the settling requirement of the driver are those that are early in the decision process and those that are have the most strict settling requirements.
2.2
Figure 2-1 shows the full schematic of the driver with the three main subcircuits labeled. The most important subcircuit is the low-voltage driver core, which provides the buffering action of the driver. The core includes a low-voltage cascode current
26

mirror to define its bias current. The core is sandwiched within another subcircuit, the low-voltage rails. These rails track in the input voltage, allowing low-voltage devices to be used in the core and improving driver linearity. The 'Vdd rail' provides a bias voltage that follows aboves the input voltage, while the 'Vss rail' provides a bias voltage that follows below the input voltage. Lastly, the protection devices prevent overvoltage in the driver during rapid changes in input voltage. Each of these subcircuits will be discussed in detail in the subsequent sections.
Vdd Rail Generator
Vdd Rail
MPI AP3
Vi
WN4
Low-voltage
Driver Core
CO
V
100
>
E
UN3MN2 V4N6
V UP2 Ir W9
0 du
03.
MN7 Ra
Vss-Rail
Generator
05
06
>1
UP5
Q1,
N10
Vn2
J1
MP
Cascode
Current
Mirror
7
>
>
V;,
JuP9
Vn~
>4
MPI1
Vi
Protbc tion
Devilce s
Figure 2-1: Full driver schematic with all subcircuits
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The low-voltage core for is responsible for all of the buffering capability of the input driver; all other sub-circuits serve to either improve the linearity of the core or protect the low-voltage components from overvoltage. Consequently, most of the supply current used by the driver is consumed by the core, and the performance of the core is the largest factor in determining the THD, output noise and settling time of the driver. As stated previously, a source follower architecture was chosen for the core because it reduces noise by minimizing the number of devices in the signal path and avoids feedback. Unfortunately, a simple MOS source follower cannot meet the driver requirements by itself. The main reason is that the available MOS transistors require a prohibitively high power consumption in order to make the source follower smallsignal output resistance low enough to meet the driver step settling requirements.
The output resistance of the source follower can be maximized by increasing width and drain current of the transistor and minimizing the length.
Ro
1 1
gnt A2nCox (WIL ) Id
(2.5)
However, even a wide MOS transistor with maximum current density and minimum length consumes too much current to be a viable option. Furthermore, a single MOS transistor experiences slew rate issues for rapid input steps in one direction. Given that the output load on the core is the sample capacitor of the ADC, if the source follower device is an NMOS transistor and the input voltage is abruptly stepped down, the transistor will temporarily turn off. Until the output voltage catches up to the input voltage, the rate of change in the output voltage will be limited by the bias current of the source follower divided by the output capacitance.
Since the MOS transistors available in the BiCMOS process require too high a bias current to achieve sufficiently low small-signal output resistance, it is desirable to replace them with bipolar transistors. The available bipolar transistors can easily attain low enough small-signal output resistance, and also have significantly lower
28

noise density than the MOS transistors. However, the base current drawn by the bipolar transistors prevents them from being used in a simple emitter follower configuration. This base current creates a variable current through the user's external input filter, compromising linearity and complicating the user's design. The solution is to use a MOS input stage combined with a bipolar output stage to achieve the extremely high input impedance of a MOS transistor and the low output impedance of a bipolar transistor. An architecture that achieves this arrangement is a MOS input transistor driving a BJT diamond buffer. Figure 2-2 shows the schematic of the low-voltage driver core with the MOS source follower and bipolar diamond buffer.
A diamond buffer is another name for a class AB output stage (Q1 and Q3) biased
by two diode-configured transistors (QO and Q2). Using a diamond buffer reduces the current required to achieve low output impedance because the overall output impedance equals the output impedances of Q1 and Q3 in parallel. Furthermore, a diamond buffer reduces the slew-rate issue encountered in the source follower circuit. Now, when the source follower transistor MNO shuts off, the source follower bias current only needs to charge the capacitance of the diamond buffer rather than the entire output capacitance. Stacking the source follower and diamond buffer saves power by sharing the current of the source follower and input leg of the diamond buffer. This sharing is especially important because the MOS transistor requires a high bias current in order to reduce noise.
An important part of the low-voltage driver core is the current mirror that biases the source follower and input leg of the diamond buffer. Figure 2-3 shows the schematic of the chosen mirror architecture. The purpose of the mirror is to buffer the I0 current reference that originates elsewhere in the circuit so that it can be used to provide the bias current for the source follower leg of the low-voltage driver core.
A basic MOS current mirror with a single output NMOS transistor and single input NMOS transistor for providing a bias voltage would be the simplest option, but this architecture has insufficient output resistance. This output resistance determines how much the bias current is affected by changes in the drain-to-source voltage of the mirror output transistor. If the bias current changes too much, then the distortion
29

Vin > MNO
00
02
01
ALVo U t
03
00
0
U)
Figure 2-2: Schematic for the low-voltage driver core performance of the driver is compromised.
One current mirror with more output resistance than a simple current mirror is a cascode current mirror. Switching to a cascode current mirror solves the output resistance problem, but introduces a new problem: headroom.
Although the ADC that will be integrated with the driver has a +10.24 V input range and t15 V supply rails, voltage headroom is still a concern. In order to achieve excellent THD, current source devices in the driver cannot be allowed to enter the triode region at all. Furthermore, 5% variations in the 15 V rails must be tolerated, so rail voltages can be as low as +14.25 V. Additionally, although the offset created
by the source follower and diamond buffer are cancelled out by auto-zeroing, the total
30

_0
>
0
MNO
00
MN2 MN4
MN1 MN3 MN5
Cn CO
Figure 2-3: Driver core mirror schematic voltage headroom used by the two stacked buffers is still very relevant to the circuit.
The headroom requirements of the driver when the input voltage is above zero volts are negligible because the diamond buffer is stacked below the NMOS source follower.
However, these requirements become tightly constraining when the input voltage is at its minimum value, -10.24 V. The total headroom requirement below the input voltage of the source follower and diamond buffer in Figure 2-2 is the
Vg, of MNO plus the V&,'s of QO and Q2. This totals to 2.37 V, which leaves only 1.64
V of headroom for the current mirror and bottom low-voltage rail generator circuit when the minimum input voltage of -10.24 V is subtracted from the maximum V,, voltage of -14.25 V.
Vheadroom
=
I
14.251 - | 10.241 |Vbe,QOI |Vbe,Q2| |Vgs,MNOI (2.6)
If two stacked, diode-connected, MOS transistor are used to provide the bias voltage in a cascode current mirror, the headroom requirement on the output is one
31

Vgs plus one overdrive voltage [10]. At the expense of an extra bias leg worth of power consumption, this headroom requirement can be reduced to slightly more than two overdrive voltages by level shifting the bias voltage provided by the diode connected transistors using a source follower. If the width of MN2 in Figure 2-3 is set to a certain multiple of the width of MNO, then the Vgs of MN2 can be set to the Vth of
MNO.
1gs,MN2 Vth,MNO Vth,MN4
(2.7)
If MNO, MN4, and MN5 have the same current density, then the voltage at the source of MN4 will be equal to the overdrive voltage of MN5, making the total headroom requirement two overdrive voltages. However, to ensure that MN5 is not pushed into triode region by threshold variations of any of the bias transistors, MN2 must be sized slightly larger than the calculated width, and the headroom requirement increases slightly as a result.
Although the low-voltage core contains the entire signal path of the input driver, it would be unable to attain low THD without a circuit to moderate the relative swings of surrounding nodes. Several devices in the core, shown in Figure 2-2, need voltage swings buffered in order to maintain linearity: the source follower MNO needs its drain-to-source voltage regulated, the output bipolar transistors Q1 and Q3 need their collector-to-emitter voltages regulated, and the current mirror output transistor needs its drain-to-source voltage regulated. One option for regulating these voltages is to control each of them individually, possibly using several cascode devices. However, these cascode devices would each require a bias voltage that tracked the input voltage.
If bias voltages that track the input must be created, a straightforward solution to the voltage regulation problem is to create two voltages that track the input, one above and one below, and connect all of the devices that require regulated voltages directly to these 'rails'. These low-voltage rails that follow the input with fixed offset reduce
THD by both preventing core device voltages from changing over the input voltage
32

range and allowing low-voltage devices with small parasitic capacitances to be used in the core.
Figure 2-4 shows schematics for the two circuits that generate the low-voltage rails. The circuit on the left creates a 'Vdd rail' that remains at a fixed voltage above the input and connects to the core at the drain of the source follower and collector of the NPN output transistor. The circuit on the right creates a 'V,, rail' that remains below the input and connects to the sources of the current mirror transistors and collector of the PNP output transistor. Fixed offset voltages relative to the input are created using source followers stacked with diode-connected bipolar transistors for additional offset. Bipolar transistors were chosen over MOS transistors because they have smaller capacitance when diode-connected. The V,, rail has more bipolar transistors in its stack than the Vdd rail because the V,, rail needs to have a larger offset in order to provide enough headroom for the source follower, diamond buffer, and current mirror of the core.
Given that a source follower is used to generate the offset voltages for the rails, the simplest method for providing a bias current to the rail generator is to use a current source connected to the end of the diode stack, where the output of the rail generator is located. However, this bias choice creates a slew rate issue. For instance, when the input is quickly stepped down, the output of the driver core attempts to settle the sampling capacitor to the same value, drawing current out of the capacitor through the PNP output transistor Q3. The source of this current draw is the current source biasing the V,, rail. Thus, the max slew rate of the output capacitor is limited by the bias current of the rail generator. In order to meet settling time requirements, this bias current would need to be very high at all times in order to be ready for slewing events.
An alternative approach that requires less power consumption is the one implemented in the driver, which involves simple feedback. The drain of the source follower transistor (MP3 or MN4) in the rail circuit of Figure 2-4 is connected to the source of another transistor of opposite gender (MN1 or MP6). The two transistors split a bias current which comes from a current mirror located where the source follower was
33

_0
-o
MP1
VddRoil
-P4
MP2
Q11
MP5
Vin
MP3
N1
Vin MN4
MN2
U)
U)
02
>137
-os
E
03
V)
U)
MN3
VssRail
MN5
04
MP6
MN6
Figure 2-4: Low-voltage rail generator schematic with Vdd rail on left and V,, rail on right previously connected directly to the rail (MN2 and MN3 or MP4 and MP5). The ratio of the split is determined by the current ratio of a mirror located at the end of the diode stack (MP1 and MP2 or MN5 and MN6). The output of this current mirror serves as the bias current for the source follower and diode stack, and the input comes from the opposite gender transistor (MN1 or MP6). The output transistor (MP1 or
MN5) is five times wider than the input (MP2 or MN6), so, under normal conditions,
5/6 of the bias current flows through the source follower and 1/6 flows through the current mirror input. However, when a large input step occurs and the source follower is forced off, all of the bias current flows through the opposite gender transistor
(MN1 or MP6) instead. This current flows through the input of the current mirror and is multiplied by five, allowing the current mirror to supply five times the total
34

bias current during slewing events. Adding an additional opposite gender transistor
(MN1 or MP6) with its gate-to-source voltage across the gate-to-drain voltage of the source follower (MP3 or MN4) also has the added benefit of reducing the dependency of the source follower gate-to-source voltage on the input voltage. Another important note is that the noise of the rail generator circuits is not an issue because the driver core has a high power supply rejection ratio.
An important consequence of employing low-voltage devices in the driver core is that they are vulnerable to overvoltage during rapid changes in input voltage. Even the high-voltage MOS transistors are not immune to overvoltage; although they can withstand 40 V from drain to source, they can only tolerate 5 V from gate to source.
When the driver input changes very rapidly, device overvoltage occurs because the other nodes in the driver circuit lag behind the input. If a node lags sufficiently far behind its neighbors, the transistors surrounding the node may break down. Figure
2-5 shows the protection clamps employed in the input driver. The clamps to the right of the figure are all simple three-legged clamps and provide most of the protective action. Each of these clamps has the same overall connection scheme- the gate is connected to the input, the source is connected to the node that requires clamping, and the drain is connected to one of the high-voltage rails. If a node in the driver circuit has a DC bias point that is at a lower voltage than the input, it is clamped using a PMOS transistor. For instance, the output voltage of the driver is always at a lower voltage than the input of the driver in steady-state conditions, so the output is clamped to the input using PMOS transistor MP4. This steady state offset ensures that the clamp is never on during regular driver operation, and that the only negative impact of the clamp on circuit performance is the extra capacitance it adds. However, when the input voltage falls suddenly, since the output voltage lags behind the input voltage, the input voltage may be temporarily lower than the output voltage. If this voltage difference exceeds the threshold voltage of MP4, MP4 will turn on and sink
35

current from the driver output to the negative rail, helping the output to keep up with the input and preventing an excessive voltage difference from developing between the two.
MP1 MP2 Vi MN2 Vin
MN3
MW1 >
E
>>
MP3
0
Vin MP4
V
>>
MP5 MP6
Figure 2-5: Protection clamps used to prevent overvoltage
The three most important nodes to clamp in the circuit are the two low-voltage rails and the output because these nodes surround the low-voltage core of the circuit, where the transistors are particularly vulnerable to overvoltage. Clamping for these nodes is provided by MN3, MP6 and MP4. The output clamp must be particularly large because the sampling capacitor on the output makes the output node slowest to change voltage, and the output transistors are two low-voltage bipolar transistors that can easily break down. The negative low-voltage rail, labeled 'VsslV' in Figure
2-5, is also an important and difficult node to clamp. Because of the headroom requirements of the source follower, diamond buffer, and mirror in the low-voltage core, the negative low-voltage rail must have a large offset from the input voltage.
This large offset means that the clamp on the rail only turns on when the rail is lagging far behind the input, making the clamp less effective. To compensate, an extra clamp that includes transistors MN1, MP1 and MP2 is added to assist in the clamping of the rail. This helper clamp turns on when the input voltage rises above the drain voltage of the source follower transistor in the negative rail generator circuit, labeled 'Vn2' in Figure 2-5. Since the 'Vn2' voltage is close to the input voltage, this clamp turns on much more easily than the primary negative rail clamp. The current
36

through MN1 is multiplied by ten using a current mirror formed by MP1 and MP2 and delivered to the negative rail. Additional clamps help increase the slew rate of other, less critical nodes. The 'Vn2' node is clamped by MN2, and its analog in the positive low-voltage rail is clamped by MP5. The final node that requires a protective clamp is the output of the current mirror in the driver core; this node is clamped by
MP3. The connections of the clamps to the full driver circuit are shown in Figure
2-1.
Although the protection clamps can prevent device overvoltage for very fast changes in input voltage, they cannot protect from arbitrarily fast changes in input voltage.
Extremely fast changes in input may originate from the mechanical connection of the supply voltage to the ADC input, possibly when the ADC is being tested by an automatic handler. Fortunately, since the driver is located on-chip, it is somewhat protected from these rapid input transients. The input sampling switch, which is located between the ADC input and driver circuit, has natural current-limiting functionality because the MOS transistors that comprise it enter saturation if the magnitude of the voltage across the switch is large enough. Designing the sampling switch is outside the scope of this thesis, so a simplified model of a typical high-voltage bidirectional switch is employed instead. The model, which is shown in Figure 2-6, includes properly simulated NMOS devices for the switching transistors, but avoids implementing the floating voltage sources that determine their gate voltages. The resistor located between the two transistors is included because it makes the onresistance of the switch more linear and easier to control, and prevents the body diodes of the transistors from turning on during slewing events. The current limiting function of the switch, combined with a capacitor on the input of the driver circuit, creates a network that limits the maximum rate of voltage change at the input to the driver circuit to 3 V/ns. This rate is chosen because it is the maximum rate that still allows the voltage clamps to comfortably protect the driver transistors.
37

+
Vi V2
g
Figure 2-6: Simplified model of one leg of the ADC sampling switch
38

Testing of the on-chip input driver was performed in simulation using Cadence Virtuoso. However, thorough testing of an ADC input driver requires an ADC. As a result, a semi-ideal simulated ADC was designed for testing purposes. The goal of this ADC is to simulate as accurately as possible the relevant features of the ADC that will be integrated with the driver while being simple enough to simulate quickly. Rapid simulation is achieved by implementing all of the ADC logic and control signals, as well as the comparator, in Verilog-A. The only parts of the ADC not implemented in
Verilog-A are the many switches and capacitors. Figure 3-1 shows a diagram of the testbench ADC. Although not shown in the figure, each of the capacitors in the DAC is connected to its respective control signal through a resistor in order to simulate switch impedance.
The testbench ADC has several features that make it a more stringent test of driver performance than the LTC2338 would be. The goal of the stricter requirements on the testbench is to provide design margin; if the input driver works with the testbench ADC, it is very likely to work with the target ADC. One difference is that the testbench ADC is 20-bit rather than 18-bit, reducing the settling time of each bit test slightly, but providing more information about the input driver performance. Another modification is that the testbench ADC runs faster than the ADC
39

Sample Switches
On-Chip Buffers
Vin +
Sample Caps (1 6 pF
DAC (20 Cops, 40 pF Total)
*
TIdeal
Vin-
-HI
T
Comparator
SAR Logic
Figure 3-1: Diagram of simulated ADC used to test input driver that will be integrated with the driver. While the target ADC runs at 1 Msps, the testbench ADC runs at 1.67 Msps. This figure corresponds to an acquisition time of
225 ns, 75 ns to settle the input driver after the input is grounded, and 300 ns for the 20 bit decisions. Driver performance over process and temperature corners has not been tested, but functioning with a higher-speed ADC will allow the driver to meet the settling requirement at high temperature and slow device corners. Lastly, although the positive and negative analog inputs still have a 10.24 V input range, the maximum and minimum output codes of the ADC correspond to 10.24 V rather than +20.48 V. Although this does not change the rigorousness of the tests, it allows one input driver to cover the full output range while the other input is grounded, speeding up simulation and allowing a driver to be analyzed alone.
The THD of the input driver is measured as the output THD of the testbench ADC with the input driver in the signal path as depicted in Figure 3-2. The THD of the input driver cannot be measured alone because its ability to settle the sampling capacitor and DAC capacitors during switching events is crucial for determining the distortion performance of the ADC. If the settling time of the input driver is too
slow, the THD of the driver-ADC system will be poor even if the driver is perfectly linear. Conversely, if the driver meets the settling time requirements, the THD of the
40

system will be nearly the same as that of the driver alone. To calculate the THD at approximately 2 kHz, a 2.034505 kHz sine wave with magnitude 1 dB below full scale is applied to the input of the ADC. This frequency is chosen because it allows for a
4096-point DFT to be taken from exactly five periods of the sine wave with no two samples having the same phase in the sinusoid. A magnitude 1 dB below full scale is standard for testing ADCs, and avoids the clipping that may occur for full-scale input voltages. Likewise, to calculate THD at 20 kHz, a 21.11589 kHz sine wave is used to compute a 1024 point DFT. The resulting THDs are -124.7 dB at 2 kHz and
-104.7 at 20 kHz. This 2 kHz THD is close to that of the LTC1469, which is -123 dB, suggesting that the THD is acceptable for driving the target ADC.
Input
Drver 2kHz
DFT
0 -
-50-
-200-
2
0
12 14 16 16
Frequency (H)
X 104
Figure 3-2: 4096-point DFT of ADC with input driver and 2.03 kHz, 9.13 V amplitude sinusoidal input
Unlike THD, output noise can be calculated directly from the driver circuit without involving the testbench ADC. Avoiding the ADC allows a frequency domain noise simulation to be performed rather than a transient one, since transient noise simulations are much slower. However, without the ADC, the auto-zeroing effect of the input driver is lost. This problem can be avoided by assuming that noise with fre-
41

quency below the sampling rate is auto-zeroed. This approximation is valid because only driver output variation that occur during the conversion period appear as noise, and the conversion period is less than the sampling period. With this constraint in mind, the maximum noise voltage spectral density simulated for the input driver is
5.5 nV/v Hz. Figure 3-3 plots the driver noise voltage spectral density as a function of frequency. This noise voltage density is slightly higher than that of the LT1469-
5 nV/v Hz. Unfortunately, this problem is exacerbated by the differing bandwidth requirements on the two circuits. Since the LT1469's output is filtered by the relatively slow 7 MHz input bandwidth of the LTC2338, its total output noise is only 16
pV RMS. In contrast, the integrated driver's bandwidth is around 30 MHz, causing the total output noise to be 39.8 pV RMS. This value is significantly greater than the output noise of the LT1469, but still less than the noise of the LTC2338, 145 [tV RMS.
When the output noise of the integrated driver is added to that of the LTC2338, the result is 150 pV RMS, which is only a 3.7% increase in RMS noise voltage.
Drie
Output
Noise Der. ity
.Frequency
10,
10
0 01 S 10 1
10
10
Frequ1(0)
Figure 3-3: Input driver noise voltage spectral density as a function of frequency.
Noise frequencies less than 1 MHz are auto-zeroed.
42

Low power consumption is the most attractive feature of the thesis input driver. Table
3.1 summarizes the bias currents of each driver subcircuit, then sums them to find a total driver power consumption of 27.6 mW with 15 V rails. This figure compares favorably to the LT1469, which requires 123 mW of power.
Subcircuit
Low-Voltage Core
Bias Current (pA)
350
Low-Voltage Core Mirror 70
Rail Generator Circuits 500
Clamps 0
Total Power: 27.6 mW
Table 3.1: Bias current consumption of each driver subcircuit and total driver power
The driver circuit meets the necessary gain error and INL requirements. Gain error is calculated by finding the output values at the limits of the input range and determining the slope error. These two boundary points are calculated as part of an equally-spaced 100-point series of input-output pairs that form the DC transfer function of the driver circuit. From Figure 3-4, the gain error of the input driver is 9.96 ppm. This gain error, along with the offset, is subtracted from the transfer function to find the INL, which has a max value of 11.2 pV. Since both of these values are calculated using an ADC configured for a maximum output range of 10.24 V, they both need to be multiplied by two to match the output range of the LTC2338. The result is 19.9 ppm gain error and 22.4 pV INL, which are less than the required values of 30.5 ppm and 78 [V. The sawtooth pattern in the INL with edges at 5.12 V, 0 V and -5.12 V suggests that the least well-settled bit decisions are the first two, which is reasonable because these two decisions cause the greatest perturbation in driver output voltage. Although these two bit decisions are the least well settled, they still settle to within 0.25%, which is four times better than the 1% settling required.
43

Drhr
DC Eror .
Input
Voltage 41L ,. input Votge
200
150
100
50
15
10
-0 uj
-100
-150
-200 z
_j
-15 -10
-5
Vin
0
U
(a)
5
10 15 -15 -10 -5
0
Vin
V
(b)
5 10 15
Figure 3-4: DC transfer function of driver showing 204 [V gain error function with gain error removed showing max INL of 11.2 [W (b).
(a), and transfer
Lastly, the input driver circuit needs to be verified for its ability to withstand rapid input voltage changes without transistor breakdown. The input voltage waveform in
Figure 3-5a performs this test. The test begins by stepping the input voltage between ground and 10.24 V, then stepping between
V and -10.24 V, then between ground and 15V, then between +15 V and -15 V. The transition time of these edges is 100 ns. Next, the pattern repeats with a transition time of 10 ns. Finally, the pattern repeats twice with a transition time of 1 ns. Any device overvoltages trigger simulation warnings during this test. In addition, the relevant voltages of the most vulnerable devices are confirmed to not approach too closely to breakdown. The highest-risk device is the clamp on the output of the driver circuit, since the output node lags the farthest behind the input during slewing. A plot of the V
9
, of this device is show in Figure 3-5b, demonstrating that this voltage is never less than 0.5 V from breakdown. Driver performance has not been tested under temperature and process variation, so this 0.5 V margin may not be sufficient to prevent device overvoltage in all situations. If corner simulation suggests that overvoltage is a possibility, power consumption may need to be increased to improve driver slew performance.
44

output Clamp
Vigs
Oerncltage Input Test
1P
CD
4 -
5
-10
0
100
200
300
Tme (US
400 500 600 0 100 200 300
Time (us'
400 500 600
700
(a)
(b)
Figure 3-5: Input voltage waveform for testing driver ability to handle slewing events
(a), and voltage of the most vulnerable node during the test (b).
Simulating the driver with a computer-modeled ADC yields promising results. The
ADC achieves THDs of -124.7 dB at 2 kHz and -104.7 at 20 kHz. Based on frequencydomain simulations, noise voltage spectral density is 5.5 nV/VHz and total output noise is 39.8 pV RMS. Total driver power consumption is 27.6 mW. Lastly, gain error and INL are within specification, with values of 19.9 ppm and 11.2 pV respectively.
However, these simulations are performed at room temperature with typical process parameters. In particular, one of the clamps is only 0.5 V away from overvoltage during slew event testing, so driver power consumption may need to increase if corner simulation further indicates potential for overvoltage.
45

46

The goal of this thesis was to design an on-chip input driver for a high-voltage SAR
ADC. The resulting driver achieves a THD of -124.7 dB at 2 kHz and a noise voltage spectral density of 5.5 nV/
IHz with a power consumption of 27.6 mW. At the expense of some noise performance, the integrated driver improves power efficiency relative to the LT1469, a comparable external input driver. The LT1469 has a THD of -123 dB at 2 kHz, a noise voltage spectral density of 5 nV/ Hz, and a power consumption of 123 mW. The core of the integrated driver is an NMOS source follower stacked with a BJT diamond buffer, both composed of low-voltage devices to reduce parasitic capacitances. This core is surrounded by two low-voltage rails that track the input voltage, serving to protect the low-voltage transistors in the core and improve their distortion performance. The entire circuit is protected by a set of clamps that prevent transistor breakdown during rapid changes in input voltage. However, the most important part of the input drive circuit is its integration into the ADC signal path rather than its architecture. The input driver is located between the sampling switch and sample capacitor in the ADC, effectively auto-zeroing the offset of the driver and reducing low-frequency noise. Testing of the driver was accomplished in simulation using an ADC circuit model. Once the real-world design and fabrication of this ADC is complete, silicon results could be obtained. A potential advancement for future versions of the driver is to make the it configurable by the user, perhaps
by adjusting bias currents to trade driver speed for low power consumption.
47

48

[1] Linear Technology Corporation. LTC2338-18 18-Bit, 1Msps, k10.24V True
Bipolar, Fully Differential Input ADC with 100dB SNR, 2013. LTC2338
Datasheet.
[2] Linear Technology Corporation. LTC2328-18 18-Bit, 1Msps, k10.24V True
Bipolar, Pseudo-Differential Input ADC with 95dB SNR, 2014. LTC2328
Datasheet.
[3] Analog Devices. 16-Bit, 1 MSPS CMOS ADC, April 2012. AD7671 Datasheet
Rev. C.
[4] Analog Devices. 16-Bit, 750 kSPS, Unipolar/Bipolar Programmable Input Pul-
SAR ADC, December 2012. AD7612 Datasheet Rev. A.
[5] Analog Devices. AD7609- 8-Channel Differential DAS with 18-Bit, Bipolar, Si-
multaneous Sampling ADC, February 2012. AD7609 Datasheet Rev. A.
[6] Linear Technology Corporation. LTC2389-18 18-Bit, 2.5Msps SAR ADC
with Pin-Configurable Analog Input Range and 99.8dB SNR, 2012. LTC2389
Datasheet.
[7] Linear Technology Corporation. Dual 90MHz, 22 V/us 16-Bit Accurate Opera-
tional Amplifier, 2000. LTC1469 Datasheet.
[8] Analog Devices. Low Noise, High Speed Amplifier for 16-Bit Systems, May 2006.
AD8021 Datasheet Rev. F.
[9] K. Doris, E. Janssen, C. Nani, A. Zanikopoulos, and G. van der Weide. A 480 mw 2.6 gs/s 10b time-interleaved adc with 48.5 db sndr up to nyquist in 65 nm cmos. Solid-State Circuits, IEEE J. Solid-State Circuits, 46(12):2821-2833,
December 2011.
[10] Behzad Razavi. Design of Analog CMOS Integrated Circuits, section 5.3, pages
144-145. McGraw-Hill, Avenue of the Americas, New York, first edition, 2001.
49