NEDO/OITDA National Project on Photonic Network
Technologies -Development of an Optical Label
Switching Node Prototype
Yoshiaki Nakano
Research Center for Advanced Science and
Technology (RCAST)
University of Tokyo
International Workshop on the Future of Optical Networking
Sunday 25th March 2007
Acknowledgement
NEDO, METI (Ministry of Economy, Trade
and Industry )
Optoelectronics Industry and Technology
Development Association, OITDA
KDDI R&D Labs
Fujitsu Limited
Mitsubishi Electric Co.
Hitachi Ltd.
Furukawa Electric Co. Ltd.
Asahi Glass Co. Ltd
NEC
Hitachi Cable Ltd.
Project Overview
Photonic transparent networking
Advantages: -Large capacity over Tbps
-Compactness and economy by eliminating port-by-port OEO
-Low power consumption by payload cut-through
-Scalability and flexibility by bit-rate/modulation-format transparency
Purpose of the project
-To develop key devices and components for realizing
the photonic transparent network
-To construct a node prototype based on the developed
devices and to do system demonstration
More Specifically…
Development of a switching node subsystem featuring:
-Finer granularity switching by a microsecond class fast optical matrix switch
-Autonomous decentralized routing by optical labels
-Highly intelligent and flexible processing of the optical label by a high-speed
electronic processor
-Bit rate and format free payload cut-through
-Contention resolution by wavelength conversion and deflection routing
-Low power and low CAPEX due to wavelength converter sharing
So as to provide most feasible photonic switching
solutions at the moment
Optical Burst/Packet Switching
Label
(address)
Edge
Node
Data
Data
aggregation
Core
Node
Core Node
Low bit
rate label
Electronic
processor
Control
Data
Label
Data
All-optical
switch
Optical label controls switching path
Payload is cut-through the core nodes without OEO
High-speed (~µs) reconfiguration
Only optical label is read electronically
low power consumption
bit-rate, format independent payload
high network efficiency
Architecture of the Proposed Node
6. Label Processor
3. WDM MUX/DEMUX
Arrayed
Electronic label
processor (FPGA)
1. Optical Switch
Amp
Source 
AWG EDFA
Destination 
Source 
Destination 
5. Arrayed Amplifiers
2. Wavelength Conv.
Wavelength converter
8x8
Optical
Switch
Optical label
Optical data
Electrical control
signal
Tunable laser 4. Tunable Laser
Components are ready to be assembled into OBS node prototype
Outline
The NEDO Photonic Network Project
Optical matrix switch
Wavelength converter
Tunable wavelength laser
Arrayed waveguide grating (AWG)
Er-doped waveguide amplifier (EDWA)
Research of photonic subsystems
Switch subsystem
Label processor
Optical burst switching (OBS) node
prototype
Optical Switch
Switching principle and structure
suitable for OBS
Fast EO-effect
Good scalability
PLZT： (Pb,La)(Zr,Ti)O3
Prototype 8x8 switch
OUTPUT
120mm
Prototype switch unit
PLZT beam deflectors
prism-shaped electrode
EO waveguide
Light
beam
lower
electrode
When voltage is applied, ref. index changes
due to EO-effect in a prism shape, allowing
deflection to off-axis angles
8x8 matrix switch A. Sugama et al, OFC2007, Paper OWV2
Wavelength Converter (1)
LSOA=2.4mm, w=0.6µm
■InP-based MZI-SOA WC chip
■ Dual 40Gb/s WC unit
■Pig-tailed module
Full C-band operation bandwidth, with low polarization
dependence realized in bulk InGaAsP core, monolithic
integrated MZI-SOA wavelength converter
MZI-SOA: Mach Zehnder interferometer semiconductor optical amplifier
Wavelength Converter (2)
phase adjust
λprobe =1535-1565nm
SOA
SOA
λprobe (40G-NRZ)
λsignal =1547nm
(a) λprobe =1535nm
(b) λprobe =1550nm
5ps/div.
(c) λprobe =1565nm
λsignal=1547nm
Fast Tunable Laser Diode (1)
0.5mm
2.5mm
Tunable laser array
IGAIN
MMI coupler
Booster SOA
ISOA
ITUNE
Laser
output
波長可変特性
tunability
Short gain section（~35µm） Wavelengthamplification
Active DBR gratings
ground electrode
InP substrate
T. Kurobe et al., OFC’07 paper OMS5
Fast Tunable Laser Diode (2)
ch1
ch3
ch5
ch7
波長(nm)
(nm)
Lasing Wavelength
1570
1560
ch2
ch4
ch6
ch8
DBR laser chip
isolator
PD
1550
1540
32nm
1530
1520
0
20
40
60
80
DBRDBR電流(mA)
Current (mA)
100
PD
lens triple beam
FP etalon
collimator splitter
TLD module with wavelength locker
Innovative packaging enabled use
of standard sized encasing with
high-precision wavelength locker
Dual TLD unit with drivers
Compact, Low Loss, Athermal AWG (1)
Typical temp controlled AWG
Athermal AWG
200～80cm3
70～40cm3
inner packaging
resin fixing
heater for temp. control
Target (size: <1/10)
Size：3.9cm3
21mm
Compact athermal
AWG module
41.6mm
Target：
size :<1/10 (below 8cm3)
loss:<4dB
crosstalk:<-30dB
Compact, Low Loss, Athermal AWG (2)
Characteristics
Loss [dB]
20
0℃
25℃
65℃
15
80mm
25
130mm
10
Center
wavelength shift:
< 0.03 nm/0-65oC
5
0
1541.5
1542.5
1543.5
Athermal, flat-top AWG
(200GHz spacing)
1544.5
Wavelength [nm]
Temperature dependence
Low loss, low temp. dependence simultaneously realized
by optimizing resin trenches
Flat-top type athermal AWG also developed
Optical Amplifier (EDWA) Array (1)
Bismuthate host glass based erbium-doped waveguide amplifiers (Bi-EDWA)
•Bismuthate thin film fabricated by sputtering, waveguide array by
photolithography and dry-etching
•Spiral waveguide layout for chip-area saving with long waveguide for sufficient
gain
15mm
1cm
1cm
11mm
15mm
8-ch Bi-EDW
Photograph of EDW chip
under pumping
8-ch WDM
couplers
8chfiber arrays
M. Ono et al.,OFC2006, Anaheim, p. OTuD3.
Optical Amplifier (EDWA) Array (2)
EDWA
10dB
10dB
Signal IN
Pump LD1
APC
Signal OUT
Signal MON
Pump LD2
AGC
Automatic high speed gain control circuit
Burst-mode operation needs auto-gain control (AGC)
AGC using feedback control of backward pump was
realized for all 8ch.
Optical Labeling Scheme
Optical label is read by O-E conversion and simple signal processing
Label is generated with same transmitter as payload by bit-serial subcarrier
BPSK format
Label supports bit inversion due to wavelength conversion by NRZI coding
Immediate reservation, explicit release for each optical burst
16bit 16bit
preamble
"1"
"0"
Subcarrier BPSK
1
1
or
0
0
"0"
1
0
or
0
1
"1"
DA
SA test ctrl
delimiter
CRC
logical inversion
NRZI coding
setup label
release label
10~40Gbps payload
variable length
Optical burst format
Optical Label Processor
CHCH-1
CHCH-2
CHCH-3
CHCH-4
CHCH-5
CHCH-6
CHCH-7
CHCH-8
RX
PD
TX
AMP
RX
PD
TX
AMP
RX
PD
TX
AMP
RX
PD
TX
AMP
RX
PD
TX
AMP
RX
PD
TX
AMP
RX
PD
TX
AMP
RX
PD
TX
SERDES
SERDES
Sw I/F
スイッチ制御I/F
FPGAFPGA-A
BUFFER
1
TLS制御I/F
TLS I/F
SERDES
SERDES
FPGAFPGA-A
BUFFER
2
FPGAFPGA-B
SERDES
SERDES
SERDES
SERDES
モニタ（デバック）
Mon I/F I/F
FPGAFPGA-A
INT
CLOCK
外部CLOCK入力
Ref Clk
3
CLOCK出力
Clk out
FPGAFPGA-A
4
SH4
CPU
100Mイーサネット
100M Eth.
Edge node
AMP
Hardware implementation of label
generation/ recognition using FPGA
Core router
Payload 10Gbps NRZ
8ch per system interface for switch and
TLD wavelength control
FPGA: field programmable gate array
Optical Switching Subsystem Prototype
EDFAx3
AWGx3
Label tester
EDFAx3
AWGx3
Label processor
LNx6
AWGx3
EDFAx3
EDWAx8
PLZT Switch
LD source
(ILX)
Clock Rec.
DCA
(Agilent)
APD+
Oscillo.
(Tektronix)
Power supply
For switch
Pol Controlx8
FDLx8
EDWAx8
Wavelength
Converterx2
TLSx2
EDFAx3
Edge node and core node each is constructed within a rack, with less than 2kW
power consumption
3day stable operation during exhibition (InterOpto’06, ECOC’06)
Live Exhibition of OBS
 InterOpto 2006 （July 11-14,
2006, Makuhari）
 ECOC 2006 （Sep 25-28, 2006,
Cannes）
Live exhibition of OBS at the OFC ’07 (March 27-29)
Booth #1261 OITDA (close to poster session area and coffee station)
Contention Resolution Experiment in Optical
Switching Subsystem
Burst
Gen.
Label
Processor
100µs/div
Label
Analyzer
Input 1(λ1)
λ1
LN
1
1
1’
3
λ1
LN
2
2
2’
4
3
3’
4
AWG
EDWA
4’
4x4 PLZT
Switch
λ2
λ3
5
Output1(λ1)
6
Output2(λ1)
λ
Output4(λ2)
conv
TLS
Destination = 1’
Output4(λ3)
Destination = 2’
80 µs
200 µs
Input
time
1
2
Output
3
4
5
6
11’
22’
11’
22’
time
12’
11’
21’
21’
22’
 conv.
 conv.
21’
Input 2(λ1)
12’
21’
12’
12’
11’
22’
10Gbps burst payload waveform
Dynamic switching, burst-by-burst
wavelength conversion are among the
basic functions that were demonstrated
in the prototype node using a 4x4 PLZT
switch.
Bit Error Rate Measurement for Mixed Bitrate
Contention Resolution
40Gbps
-4
-4
Bit Error Ratio (BER)
-5
-5
10Gbps
-6
-6
-7
-7
-8
-8
-9
-9
-4
9.95Gbps
-5
PRBS7
1552.5
-6
1554.1nm
Bit Error Ratio (BER)
PRBS (27-1) continuous bit-stream
Back-to-Back
Back-to-Back
39.81Gbps
SW+λ.Conv
SW+λ.Conv
PRBS7
SW+λ.Conv+SW
SW+λ.Conv+SW
1552.5
1554.1nm
-7
-8
-9
-10
-10
-10
-4
Back-to-Back
Back-to-Back
20ps/div
-11
-11
SW+λ.Conv -11
SW+λ.Conv
-5
-5
SW+λ.Conv+SW
SW+λ.Conv+SW
Eye after switching,
-12
-12
-12
-6
-6
wavelength (λ)conversion,
-36
-29 -26
-34 -23-32
-20 -17
-30
-29 -26 -23 -20 -17
switching again
-7
-7
Received Power [dBm]
Error-free-8performance is achieved
for both switching and contention
-8
-9
Error Ratio (BER)
-4
resolution,
-9 <4.8dBm , for 10Gbps: <1dBm
Penalty for 40Gbps:
Multi-hop Loop Experiment
DFB 1547.7nm
LN Mod
DFB 1549.3nm
LN Mod
DFB 1550.9nm
DCF
AOSW2
AOSW1
DGE
50km SMF
50:50
LN Mod
Label
Proc.
OSA
Label Rx
DCA
AOSW3
BPF
Clock Rec.
Func. Gen.
5km
SMF
AGCEDWA
4x4
PLZT
Matrix
Switch
4x4 PLZT matrix switch and flat-top AWGs with 200GHz spacing
50km SMF link with hop by hop dispersion compensation
Gated receiver at receiver
Port 2-port2’ switched ON/OFF inside the loop to see dynamic behavior of
the setup
Label Processing Errors after Multiple Hops
(Label error ratio) 
(No of received labels) - (Label errors)
(No of sent labels)
Lap0
Lap1
Lap2
Lap3
Lap4
Lap5
Lap6
Lap7
Lap8
Lap9
Lap10
Lap14
Error-free label processing was verified for at least 13hopes
Power transients are a limiting factor for cascading
Wavelength conversion reduce noise levels and enable up to 13
hops switching at 10Gb/s with wavelength conversion.
Multihop Switching with Wavelength Conversion
50km SMF + DCF




Lap0
Lap1
Lap2
Lap3
Lap4
Lap5
Lap6
Lap7
Lap8
Lap9
Lap10
Lap14
node
10Gbps
TX
A
W
G
0.8nm
OBPF
10Gbps
Rx
200GHz
spacing
Wavelength conversion reduce noise levels and enable up to 13
hops switching with wavelength conversion.
Further cascading may need retiming, due to accumulated jitter
Optical Burst Switching of Application Data
40Gbit/s edge node
40Gbit/s payload with
optical label
40Gbit/s
Optical label
10GbE
40Gbit/s payload
PC2
LAN-Sw1
LAN-Sw2
Edge1
Edge2
PC1
PC1 Edge1 OBS Core Edge2 PC2
Microsoft Netmeeting
video conference
across OBS node
prototype
optical burst with 40Gbit/s payload
carrying clients data demonstrated
Summary
Advanced devices developed in the NEDO-funded Photonic
Network Project have been introduced
PLZT matrix switch based on beam-deflection
Inherently bit-rate transparent, µs switching speed
MZI-SOA monolithic integrated wavelength converter
Supports up to 40Gbps
Fast tunable LD based on active short-cavity DBR array
Full C-band continuous tuning
Compact, athermal AWG
<0.03nm passband shift for 0-65℃
Compact 8ch EDWA array with AGC for bursty signals
Large gain (>19dB) over C-band
An OLS router prototype based on the developed components
Successfully demonstrated optical label based switching,
contention resolution, bit-rate transparency, cascadibility etc.