LASOR: Label Switched Optical Router
International Workshop on the Future of Optical Networking
March 5, 2006
Daniel J. Blumenthal
Optical Communications and Photonic Networks Group
Dept. of ECE
University of California, Santa Barbara
Danb@ece.ucsb.edu
LASOR research supported under DARPA/MTO DoD-N Program Award Number W911NF-04-9-0001
Technical Contributors
Calient Networks
R. Helkey, O. Jerphagnon, S. Yuan
Cisco Systems
D. Civello, P. Donner, G. Epps
JDS Uniphase
D. Al-Salameh, C. Coldren, G. Fish , A. Turukhin
Stanford University
N. Beheshti, Y. Ganjali, A. Goel, N. McKeown, T. Roughgarden
UCSB
J. Barton, S. Bjorlin, D. J. Blumenthal, J. E. Bowers, E. Burmeister, J. Chen,
M. Chun, L. A. Coldren, W. Donat, M. Davanco, R. Doshi, M. Dummer, E.
Hu, Z. Hu, L. Johansson, B. Koch, V. Lal, J. Mack, M. Masanovic, H. Park,
H. Poulsen, R. Rajaduray, S. Rangarajan, J. Summers, A. Tauke-Pedretti,
D. Wolfson, W. Zhao
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D. J. Blumenthal, ECOC 2005, Sept. 26-30,
Glasgow, Scotland
Project Overview
Project Start Date: 4/8/04
Project Duration: 4 Years
Funding Agency: DARPA/MTO
Program: DoD-N
Program Manager: Dr. J. Shah
Technical Team
ERP
ORAM
32/64 40G
Inputs
Today’s
Technology
32/64 40G
Outputs
Line
WC/
Regen
WDM Fiber
Transmission
System
1.28/2.56 Tbps
ODR Linecard
40G Packet
Add/Drop
Optical Router Node (ORN)
Electrical Router (ER)
D. J. Blumenthal, ECOC 2005, Sept. 26-30,
Glasgow, Scotland
1.28/2.56 Tbps
ODR Linecard
1.28/2.56 Tbps
ODR Linecard
40G WDM Line
Add/Drop
Reconfigurable Optical Backplane (ROB)
3
OH
Read
> 100 Tbps Nodes
Collaborators
USC (Willner)
Telcordia
Optical
Packet
Forwarding
Engine
Mux/DeMux
UCSB
Calient Networks
Cisco Systems
JDS Uniphase
Stanford University
2.56/5.12 Tbps Linecard
Router Architectures
Virtual Output Queue (Input Buffering)
FIFO (Single Input Queue)
FIFO
FIFO
FIFO
VOQ
Crossbar
Switch
•Simple Memory
•Simple Scheduler
•Performance limited
by head of line
blocking (HOB)
VOQ
Crossbar
Switch
VOQ
VOQ
FIFO
•More complex
memory than FIFO
(one queue per
output port for every
input port)
•More Complex
Scheduler than FIFO
• Performance not
limited by HOB
Scheduler
Scheduler
Distributed/Multistage
Linecard
Scheduler
Scheduler
Linecard
Scheduler
Linecard
Linecard
Linecard
Linecard
Linecard
Linecard
Scheduler
Scheduler
4
Linecard
Scheduler
Scheduler
Scheduler
D. J. Blumenthal, ECOC 2005, Sept. 26-30,
Glasgow, Scotland
Scheduler
•Scales to very
large number
of ports
Integrated Technologies
Basic Optical Data Router (ODR)
OLR/E
PED
Optical Label
Recovery/
Payload Envelope
Detect
5
Sync/
ORAM
40G
FTWC/
OLE/
OLW
32 x 32
(64 x 64)
AWGR
Electronic Routing Processor
D. J. Blumenthal, ECOC 2005, Sept. 26-30,
Glasgow, Scotland
40G
TWC
Array
Optical Packet Structure
Optical Packet
Optical
Header
(10Gbps
NRZ)
Optical
Payload
(40Gbps
RZ)
Payload (IP Packet)
Guard
Bands
6
Idlers
Guard
Band
D. J. Blumenthal, ECOC 2005, Sept. 26-30,
Glasgow, Scotland
[Optional]
Inter-packet gap
Optically Buffered ODR
Input A Time Domain
Local Reference
Clock
Output A Time Domain
Memory
Write
Delay
Set
Input A
PED
ORAM
Synchronizer
Buffer Size
Delay
Set
Input B
PED
Synchronizer
Buffer Size
Memory
Read
Memory
Write
ORAM
Memory
Read
Input B Time Domain
7
D. J. Blumenthal, ECOC 2005, Sept. 26-30,
Glasgow, Scotland
Output A
Optical Packet
Forwarding
Output B
Simulation Environment:
TCP over Input-Queued Switch
N. Beheshti, R. Rajaduray, N. McKeown
Flow 1
TCP
Sources
1
Port 1
Group1
8
Flow N
1
Port 32
Scheduler
Pre-existing:
8
ns2: Accurate discrete-event simulator for TCP networks
SIM: Accurate slotted-time simulator for switches/routers
New simulation environment
Ns2 with accurate switch/router simulator
Many TCP flows per input port multiplexed upstream.
Four Virtual Output Queues (VOQ) per input port
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D. J. Blumenthal, ECOC 2005, Sept. 26-30,
Glasgow, Scotland
Group4
Small Buffer
Simulation Results
32x32 CIOQ switch, 10Gb/s per port,
GiSLIP scheduler, Speedup = 2, very small buffers
120 flows per input port
IQ: 5 packets per VOQ
IQ: 10 packets per VOQ
OQ: 200 packets per output
120 flows per input port
OQ: 200 packets per output
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D. J. Blumenthal, ECOC 2005, Sept. 26-30,
Glasgow, Scotland
Optical Header Recovery and
Payload Envelope Detect
Basic Optical Data Router (ODR)
OLR/E
PED
Sync/
ORAM
40G
FTWC/
OLE/
OLW
Array
32 x 32
(64 x 64)
AWGR
Optical Label
Recovery/
Payload Envelope
Detect
Electronic Routing Processor
40G
TWC
Array
Burst Mode OL Recovery and PED
Fast locking (<20 bits @ 10Gbps)
Maintains clock for 384 bits after the end of packet
Low jitter payload envelope accurate to within 64ns
Optical Header Read/PED
OH Burst Mode CDR
Input: 10G optically
labeled 40G packet
OH Erase
TWEAM
MMIC Amplifier
TIA
10G PD
16ns
8ns
32ns 16ns
8ns
Recovered Label
B. Koch, Z. Hu,
UCSB
Input: 40G Packets
Output: PED
11
OH CDR
D. J. Blumenthal, ECOC 2005, Sept. 26-30,
Glasgow, Scotland
H. Poulsen, UCSB
40Gbps Wavelength Converter
Technology
Basic Optical Data Router (ODR)
OLR/E
PED
Optical Label
Recovery/
Payload Envelope
Detect
12
Sync/
ORAM
40G
FTWC/
OLE/
OLW
Array
32 x 32
(64 x 64)
AWGR
Electronic Routing Processor
D. J. Blumenthal, ECOC 2005, Sept. 26-30,
Glasgow, Scotland
40G
TWC
Array
40Gbps Monolithic Widely-Tunable
Differential Wavelength Converters
Gen. 1 : External Delay
V. Lal, M. L. Mašanović, J. A. Summers, L. A.
Coldren, and D. J. Blumenthal, "40Gbps Operation
of an Offset Quantum Well Active Region Based
Widely Tunable All-Optical Wavelength
Converter,“Optical Fiber Communication
Conference, Anaheim, California, 2005.
Chip Area =
2.5mm2
Gen. 2 : Integrated Input Differential Delay
J. A. Summers, V. Lal, M. L. Mašanović, L. A.
Coldren, and D. J. Blumenthal, "Widely-Tunable AllOptical Wavelength Converter Monolithically
Integrated with a Total Internal Reflection Corner
Mirror Delay Line for 40Gbps RZ Operation,"
Integrated Photonics Research and Applications
(IPRA '05), Paper IMC5, San Diego, California, April
11-13, 2005.
Chip Area =
3.8mm2
Gen. 3 : Compact Integrated Balanced Delay
V. Lal, J. A. Summers, M. L. Masanovic, L. A.
Coldren, and D. J. Blumenthal, “Novel Compact
InP-based Monolithic Widely Tunable
Differential Mach-Zehnder Interferometer
Wavelength Converter for 40Gbps Operation,”
Indium Phosphide and Related Materials, Opto-I
(IPRM '05), Glasgow, Scotland, May 8-12.
Chip Area =
2.4mm2
13
D. J. Blumenthal, ECOC 2005, Sept. 26-30,
Glasgow, Scotland
Differential MZI-SOA based
Wavelength Conversion at 40Gbps
Differential operation used to
overcome slow gain recovery
lifetimes
Input
Pulse
2
1
2
Switching window
1
CW signal power at
MZI output
Δt
V. Lal, M. L. Masanovic, J. A. Summers, L. A. Coldren, and D. J. Blumenthal, "40Gbps Operation of an Offset Quantum Well Active Region
Based Widely-Tunable All-Optical Wavelength Converter," presented at Optical Fiber Communication Conference,OFC 2005, Anaheim, CA.
14
D. J. Blumenthal, ECOC 2005, Sept. 26-30,
Glasgow, Scotland
40G Tunable Wavelength
Converters with Integrated Delay
World’s First Monolithic Integrated 40G Tunable All-Optical WC
On-chip delay lines using TIR mirrors for RZ operation
Optical preamplifiers
Optical power splitters and combiners
Mach-Zehnder interferometer optical wavelength converter
Tunable laser
Laser booster optical amplifier
PRBS 27-1
1553 in 1541 out
1553 in 1541 out
Input SOAs
0.8mm
λin
SG-DBR Laser Booster SOA
Power Penalty 5dB
λout
MZI SOAs
MZI Phase
2.9mm
λin
Input SOA
Booster SOAs
0.6mm
SG-DBR Laser
15
6.3mm
D. J. Blumenthal, ECOC 2005, Sept. 26-30,
Glasgow, Scotland
MZI SOAs
MZI Phase
λout
Packet Forwarding
Basic Optical Data Router (ODR)
OLR/E
PED
Optical Label
Recovery/
Payload Envelope
Detect
16
Sync/
ORAM
40G
FTWC/
OLE/
OLW
Array
32 x 32
(64 x 64)
AWGR
Electronic Routing Processor
D. J. Blumenthal, ECOC 2005, Sept. 26-30,
Glasgow, Scotland
40G
TWC
Array
PFC Chip and Module
Chip Area =
5.25 mm2
~10 ps Delay Line
Signal Power
Control SOAs
XPM SOA ’s
0.75 mm
7 mm
Pump Power
Control SOA
Signal Splitter
Fast Tunable Laser
Pump/Signal
Combiners
MZ Phase
Label Write
Phase Shifter
“Monolithic Widely Tunable Optical Packet Forwarding Chip in InP for All-Optical Label Switching with
40 Gbps Payloads and 10 Gbps Labels,” V. Lal, M. Mašanović, D. Wolfson, G. Fish, C. Coldren, and D.
J. Blumenthal, Accepted for presentation as Postdeadline Paper, ECOC 2005 Glasgow, Scotland.
17
D. J. Blumenthal, ECOC 2005, Sept. 26-30,
Glasgow, Scotland
PFC Packet λ-Conversion
and OH Re-Write
Dual SGDBR Signal
Booster SOAs
10ps Delay using deep-etched waveguide
Label Rewrite EAM
Input Signal Blanking EAM
SGDBR Tunable Flared Input Pre-amp
Laser
SOAs
1mm MZI SOAs
10G Optical Header Re-Write
Variable Length Packets and Dynamic
Forwarding + 100ns Guard Band
New 10G OL
WC 300ns 40G
Output λ1
iMix 7:4:1 -> 40B:570B:1500B
B
D
F
H
J
Input
A B CD E
F GH
I
J
New 10G OL
WC 114ns 40G
Output λ2
A
C
E
G
I
1500B
40B
100ns Guard
Band
570B
18
D. J. Blumenthal, ECOC 2005, Sept. 26-30,
Glasgow, Scotland
New 10G OL
WC 8ns 40G
Buffers
Basic Optical Data Router (ODR)
OLR/E
PED
Optical Label
Recovery/
Payload Envelope
Detect
19
Sync/
ORAM
40G
FTWC/
OLE/
OLW
Array
32 x 32
(64 x 64)
AWGR
Electronic Routing Processor
D. J. Blumenthal, ECOC 2005, Sept. 26-30,
Glasgow, Scotland
40G
TWC
Array
Optical Buffer (ORAM)
Recirculating buffers for on-chip,
integrated optical packet buffer with
dynamic control of storage time and
random read.
SOA gate matrix 2x2
switches have been
fabricated on the same
material platform as all
other program-wide InP
devices.
Prototypes meet all
specifications including
high extinction ratios, fast
switching, and error-free
operation at 40Gb/s.
20
E. Burmeister
D. J. Blumenthal, ECOC 2005, Sept. 26-30,
Glasgow, Scotland
Lookup and Forwarding
Basic Optical Data Router (ODR)
OLR/E
PED
Optical Label
Recovery/
Payload Envelope
Detect
21
Sync/
ORAM
40G
FTWC/
OLE/
OLW
Array
32 x 32
(64 x 64)
AWGR
Electronic Routing Processor
D. J. Blumenthal, ECOC 2005, Sept. 26-30,
Glasgow, Scotland
40G
TWC
Array
Electronic Control
OLR/PED
OH CDR
OH Erase
Input A
PF Board
Output A
• Label Blanker
• PFC Module
Input A
• PED
• OH CDR
PFC Module
Input B
• PED
• OH CDR
Output B
• Label Blanker
• PFC Module
Input B
22
D. J. Blumenthal, ECOC 2005, Sept. 26-30,
Glasgow, Scotland
2x2 Optical Data Router
(ODR) Demo
D. Wolfson, V. Lal, M. Masanovic, H. N. Poulsen, C. Coldren, G. Epps, D. Civello, P. Donner, and D. J.
Blumenthal, “All-optical asynchronous variable-length optically labeled packet switch operating at
40Gbps,” Accepted for presentation as Postdeadline Paper, ECOC 2005 Glasgow, Scotland.
23
D. J. Blumenthal, ECOC 2005, Sept. 26-30,
Glasgow, Scotland
Layer- 1 and Layer-2 Packet
Error Measurements
PRBS: Bit Error Rate
Minimum Measurable Packet Size
PRBS Sequence Length
Error Detection
Window
PRBS
Transmitter
PRBS
Transmitter
PRBS Data
Synchronization
~ 512 bits
User Defined Packets: Packet Throughput or Loss
Minimum Measurable Packet
User Defined Packet Streams†
Size
Data
Compare Received Packets to
Transmitted Packets
Data
Transmitter
Data
Receiver
PRBS Data
Synchronization
~ 16 bits
† Can be deterministic or user generated PRBS
24
To measure 10-9,
must collect 1010
to 1011 PRBS
data bits and
analyze over all
PRBS measured
in detection
windows
D. J. Blumenthal, ECOC 2005, Sept. 26-30,
Glasgow, Scotland
Packets
received
compared to
packets
transmitted to
measure %
throughput
2x2 ODR Functional Diagram
Input A
OHD/PED
Δoptical
OH Erase
Packet
Forwarding/
OH Write
Output A
•Analog Electrical
•10G NRZ Optical Header
•40G Payload Envelope
• New OH
• Digital Payload Envelope
• λ-select
• 10G Header Clock
•OH
Blanking
Burst Mode
10G CDR
• 10G Header Data
•Analog Electrical
•10G NRZ Optical Header
•40G Payload Envelope
OHD/PED
Input B
25
Δoptical
OH Erase
I2
O2
I3
O3
I5
• New OH
• Digital Payload Envelope
• λ-select
• 10G Header Clock
•OH
Blanking
Burst Mode
10G CDR
O1
I4
ERP
• 10G Header Data
I1
Packet
Forwarding/
OH Write
D. J. Blumenthal, ECOC 2005, Sept. 26-30,
Glasgow, Scotland
AWGR
O4
O5
I6
O6
I7
O7
I8
O8
Output B
Layer-2/3 Header &
PED Recovery
Header & PED Recovery
160
Detected (%)
140
Noise interpreted
as PED signals
Headers
PEDs
120
100%
100
80
-12 dBm < Pin < -3.5 dBm
60
40
20
-24
Forwarding and Label Re-Write
-20
-16
-12
-8
-4
0
Re-Written 10G Labels
Switched 40G Packets
Optical input power (dBm)
1500B
26
D. J. Blumenthal, ECOC 2005, Sept. 26-30,
Glasgow, Scotland
570B
40B
Layer-2/3 Results:
Payload Throughput
Output A (λ1)
Input iMix = 7:4:1
A
B CD E
F GH I
B
D
Output
λ1
570B
J
C
E
G
I
Input A
1500B
Output B (λ2)
Payload Throughput (%)
40B
H
J
A
95ns Guard Band
F
120
1550.12 nm (w/o switching)
1533.76 nm
1539.28 nm
100
Due to Tx/Rx bit
errors
80
60
~1 dB
40
20
0
1
2
3
4
5
6
Optical input power (dBm)
27
D. J. Blumenthal, ECOC 2005, Sept. 26-30,
Glasgow, Scotland
7
Ongoing Challenges
Asynchronous, variable length packet optical routing
DC balancing (both electrical and optical domain)
Higher density photonic integration + electronics
40G cascadability (node and link)
Fast wavelength switching
Optical packet buffer integration
Buffered ODR operation
Reduced guard bands
New techniques are being explored to move
functionality into the integrated photonic domain.
28
D. J. Blumenthal, ECOC 2005, Sept. 26-30,
Glasgow, Scotland
Summary
Reviewed the DARPA DoD-N LASOR Project
Described the ODR and linecard architecture
Progress on integrated technologies
Full packet forwarding function on a chip
Optical header recovery and payload envelope detect on
chip
Fast tunable 40Gbps wavelength converters
Demonstration of a 2x2 optical data router that
handles asychronous, variable length optically
labeled packets
Asynchronous burst mode control and lookup
electronics
Progress on optical packet buffers (ORAM) and
synchronizers
29
D. J. Blumenthal, ECOC 2005, Sept. 26-30,
Glasgow, Scotland