Enhancing Phase-Change Memory via DRAM Cache
Brian Pak, Lincoln Roop
Goals
Approach
•  Increase the lifetime of Phase-Change Memory by
reducing the number of writes to PCM
Ø  PCM cell write/erase endurance: ~107
Ø  Limits PCM from being sole main memory
•  Guaranteed lifetime for the worst case
(e.g. wear-out attacks)
Ø  Protects PCM lifetime with minimal performance
degradation
•  Introduce an extra level of indirection: DRAM Cache
•  More robust and wear-out-resistant cache
replacement policy
Ø  Access Density Decay (ADD) Policy
o  Keep track of the number of accesses per
block (A) – Access Density
§  A = (α x # Writes) + (β x # Reads),
where α = weightwrite, β = weightread
o  Decay access density by half for every
N instructions
PCM suffers wear-out problem
with multiple writes to the same
location
o  For eviction, a block with the least access
density is evicted to PCM
•  Employ wear-leveling to evenly distribute the writes
across PCM (when a block is evicted from the cache)
With DRAM write-back cache,
unnecessary writes to PCM
can be avoided
Experiments and Results
•  Experiment I
Ø  PCM Lifetime comparison
•  Experiment II
Ø  ADD Parameter (decay cycle) comparison
o  PCM Only
o  PCM + DRAM Cache (LRU)
o  PCM + DRAM Cache (ADD)
o  Decay Cycle: 200K, 500K, 1M, 2M instructions
•  Result
•  Result
Effect of Different Decay Cycle
2500
Comprison between ADD and LRU
1.2
1
0.8
0.6
DRAM Cache 1MB (ADD)
# Writes to PCM
# Writes to PCM Ratio to DRAM (LRU)
2000
1500
Shifting Attack (DRAM ADD 1MB)
1000
DRAM Cache 1MB (LRU)
ALL PCM
0.4
500
0.2
0
DRAM Cache 1MB (ADD)
DRAM Cache 1MB (LRU)
ALL PCM
0
403.gcc
1
1
1
Attack and Useful
1.00254399
1
0
Shifting Attack
0.059665871
1
3468.854893
462.libquantum
1
1
43.21399062
200K
500K
1M
Decay Cycle (# insns)
2M
10M