Author
Certified by
by
Peter Kyung-Moon Kim
Submitted to the Department of Electrical Engineering and Computer Science in Partial Fulfillment of the Requirements for the Degrees of
Master of Engineering in Electrical Engineering and Computer Science at the Massachusetts Institute of Technology
January 31, 2001
MASSACHUSETTS INSTITUTE
OF TECHNOLOGY
~ ~
Copyright 2001 Peter K. Kim. All rights reserved
LIBRARIES
The author hereby grants to M.I.T. permission to reproduce and distribute publicly paper and electronic copies of this thesis and to grant others the right to do so.
Certified by
Accepted by.
Department of Electrical Engineering and Computer Science
January 31, 2001
Professor Janies K. Roberge
Thesis Supervisor (MIT)
- -/>Ss
Kimo Tam
Inc.)
C. Smith
Chairman, Department Committee on Graduate Thesis

High Voltage Low-Power 6 and 8-Bit DACs for Liquid Crystal Display Driver Applications by
Peter Kyung-Moon Kim
Submitted to the
Department of Electrical Engineering and Computer Science
January 30, 2001
In Partial Fulfillment of the Requirements for the Degree of
Master of Engineering in Electrical Engineering and Computer Science
High performance 6 and 8-bit DACs implemented in a high voltage complementary bipolar process were designed and simulated. These DACs may be useful in applications such as LCD drivers where high voltage power supplies are common. In general, a DAC is composed of control logic, latches, decoders and current or voltage switching circuitry. The DACs were designed to have power dissipation of 750 pW or less, and can run at the speed of 2 MHz on +/- 5 V supply rails. Glitch impulses were also minimized to less than 10 nV-s in the final design. The output analog signal has a swing of +/- 1 V, and this swing can be adjusted by using an output amplifier with the desired gain. One sigma mismatch for TFR (resistors) and Vbe mismatch for transistors resulted in average INL error of 0.05LSB for the 6-bit DAC and 0. 1LSB for the 8-bit DAC.
Thesis Supervisor: James K. Roberge
Title: Professor of Electrical Engineering
2

Abstract
List of Figures ......................................................................................................................
List of Tables ......................................................................................................................
I. Introduction ....................................................................................................................
II. General LATCH and DAC Architectures ..................................................................... 12
A. LATCH ............................................................................................................
B. DAC ................................................................................................................. 14
III. LATCH Block .............................................................................................................. 18
IV. DAC Block ...................................................................................................................
A. Current Switching DAC ................................................................................... 24
B. Voltage Switching DAC ................................................................................... 25
C. Operational Am plifiers with Unity Gain Feedback .......................................... 28
1. Finite Gain Error ......................................................................................... 28
2. System atic Offset ........................................................................................ 30
3. Power Supply Error ..................................................................................... 37
D . Decoder ............................................................................................................ 37
V Output Analysis ...........................................................................................................
VI. M ism atch .................................................................................................................... 49
A. Resistor M ism atch ............................................................................................ 49
B. Vbe M ism atch .................................................................................................. 56
VII.Noise Analysis .............................................................................................................
A. Noise Contributions ......................................................................................... 59
B. Frequency Response Analysis .......................................................................... 65
C. Noise Division in Resistor String ..................................................................... 65
X. Conclusion ...................................................................................................................
XII.Bibliography ................................................................................................................
3

Figure 1.3
Figure 2.1
Figure 2.2
Figure 2.3
Figure 2.4
Figure 2.5
Figure 2.6
Figure 3.1
Figure 3.2
Figure 4.1
Figure 4.2
Figure 4.3
Figure 4.4
Figure 4.5
Figure 4.6
Figure 4.7
Figure 4.8
Figure 4.9
Figure 1.1
Figure 1.2
Figure 4.10
Figure 4.11
Figure 4.13
Figure 5.1
Figure 5.2
Figure 5.3
Figure 5.4
Block Diagram of General DAC..................................................................7
Overview of a typical signal path from Analog video input to the LCD panel................................................................. 10
AD8380 Dec Driver Functional Block Diagram ................................... 10
ECL Latch 1............................................................................................13
ECL Latch 2..........................................................................................
General Current Steering DAC Circuit .................................................
14
15
R-2R Current Steering DAC Architecture ............................................ 16
Voltage Switching DAC Architecture ................................................... 17
NJFET .....................................................................................................
17
4-Bit Stacked Latch String Block Diagram .......................................... 18
LATCH Block ............................................................................................
Current Switching DAC ........................................................................
20
24
Subranging 2 Stage Voltage Switching DAC Design #1 ....................... 26
NJFET Switch........................................................................................ 26
2 Stage Voltage Switching DAC Design #2........................................... 27
Unity Gain Feedback of Amplifier ....................................................... 28
Amp1 Architecture with Feedback ........................................................
Amp2 Architecture with Feedback ........................................................
29
30
Ampi Architecture with Class B Output Stage ..................................... 35
Ampi Architecture with Emitter Follower and Class B
Output Stage.......................................................................................... 36
Amp1 Architecture with only Emitter Follower
Output Stage..........................................................................................
ECL Decoder .........................................................................................
Actual Decoder Circuit ..........................................................................
37
38
41
Glitch Analysis...................................................................................... 44
6-Bit Ramp Response of Design #1..................................................... 45
6-Bit 1 LSB Ramp Response (Design #1)............................................ 46
6-Bit 1 LSB Glitched Response............................................................. 46
4

Figure 5.5
Figure 5.6
Figure 5.7
Figure 6.1
Figure 6.2
Figure 6.3
Figure 7.1
Figure 7.2
Figure 7.3
Figure 7.4
Figure 7.5
Figure 7.6
Figure 7.7
Figure 7.8
6-B it Full Sw ing ...................................................................................
6-Bit Ramp Response of Design #2......................................................
47
48
6-Bit 1 LSB Ramp Response (Design #2).............................................48
Resistor String DAC with Mismatch Gaussian Delta Sources .............. 50
Histogram of INL and DNL Error for 200 Simulations ............. 53
Vbe Mismatch for Input of Op-Amp ...................................................... 56
Noise Sources from Resistors .................................................................... 60
Noise Source Modeling for BJT ............................................................
Noise Source Modeling for Op-Amp....................................................
61
62
Noise Sources in the Op-Amp Architecture .......................................... 62
Frequency Response of Unity Gain Feedback Amplifier ...................... 66
Output Noise with Input=HIGH ............................................................
Output Noise with Input=MID ..............................................................
66
67
Output Noise with Input=LOW ............................................................ 67
5

Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Power and Resolution Performance of Various DACs.............................8
Performance Specifications of Various DAC Designs ........................... 42
Resistor M atching ................................................................................. 49
INL and DNL of 6-Bit DAC-1 Resistor String ...................................... 50
INL and DNL of 6-Bit DAC-Design #1 ................................................ 51
INL and DNL of 6-Bit DAC-Design #2 ................................................ 54
INL and DNL of 8-Bit DAC-Design #1 ................................................ 54
INL and DNL of 8-Bit DAC-Design #2 ................................................ 55
INL and DNL with Vbe Mismatch ........................................................ 57
6

Over the past few decades, the design and implementation of digital to analog converters
(DAC) have been growing as more systems turn to digital circuitry to do their computations.
Though the fundamental building block of a simple IC n-bit parallel DAC has been established
(Figure 1.1), the specific architecture of each building block is up to the designer. As newer and better transistor fabrication technology gets introduced, and as low power designs become more attractive, the design of each block may change significantly.
n-bit DAC n
-: ni
-: n
0 Vout or
Iout control logic
I ci k 2 clk1 l k
Figure 1.1 Block Diagram of General DAC Architecture
In Figure 1.1, the n-bit data bus input is latched twice before being converted to an analog signal. The double-latch arrangement allows the data bus to contain the complete word before being sent to the DAC block [Sheingold, 1986]. This prevents invalid data from arriving at the input of the DAC while the complete word is being assembled in the data bus. Notice that the second LATCH will only latch the data when the input word is completed from the first LATCH.
7

Thus, this ensures that only valid data gets sent to the input of the DAC block which performs the conversion.
The functionality of the control logic block is to interface to the outside world with the signals required by the latches. It may perform many different operations, such as level shifting the input data, or changing the input between TTL, ECL, CMOS, or other logic families. These signals are sent through the latches, and then to the DAC. The DAC block design has the most room for variable design and creativity. The two traditional basic designs are current switching and the voltage switching DACs.
The design implementation of the DAC IC is dependent on the performance desired from the DAC. For example, one may want a high speed, high resolution, high accuracy DAC that may trade off by pulling a large supply current, and thus have high power dissipation. Or one may want a low power DAC that trades off speed to attain the low power specification. There are many trade offs to be considered when designing a DAC and what one desires is determined by the specific application of that DAC.
The design of 6 and 8-bit low power DACs will be discussed in this paper. These DACs will be built on a high-voltage complementary bipolar (HVCB) process with power supply peak to peak range of 10 V to as high as 24 V, depending on the application. The bipolar process, in this application, has advantages over a MOS process. A few of the advantages are that the process must be high voltage and that bipolar transistors drive large capacitive outputs better than MOS transistors. With the 10 Vpp supply rails, the DACs described in this work will consume less than
1 mW of power. Table 1 shows the power specifications for many of the DACs in the market.
One can see from Table 1 that most 8-bit DACs dissipate at least 20 mW of power so a 1 mW specification will be a challenging goal. Device mismatches, parasitic effects, noise analysis and
8

other design issues that arise in building analog ICs will be considered. Because recent low power implementation of DACs has used a MOS process rather than a bipolar process, research on current technologies and designs were limited to a few IEEE papers and textbooks that have indirect relevancy to the topic at hand.
Table 1: Power and Resolution Performance of Various DACs
Manufacturer Part # Resolution Power (mW) Process
ADI
ADI
ADI
National
National
ADI
Harris
ADI
ADI
National
ADI
ADI
ADI
AD557
DAC-08
DAC-8408
DAC0800
DAC0830
AD561
HI5760
DAC-312
AD667
DAC14135
AD766
AD7111
AD1864
8-bit
8-bit
8-bit
8-bit
8-bit
10-bit
10-bit
12-bit
12-bit
14-bit
16-bit
17-bit
18-bit
75
33
20
33
20
76
165
225
300
185
120
450
225
Bipolar
Bipolar
CMOS
Bipolar
CMOS
Bipolar
BiCMOS
Bipolar
Bipolar
CMOS
BiMOS
CMOS
BiMOS
9

R
G
MGE
_/
LCD panel fnalog video in (RGB)
Figure 1.2 Overview of a typical signal path from Analog video input to the LCD panel
00.93
CLKi
STSO/CS
XFR
A10. 2)
A[.2
STSY
DYP
AD8380
CHANNELLTC
SELECTOR
10
2-STAGE
DAC
10
2-STAGE is DAC is 2--STAG
DAC to 2-STAGE to AC
BIRS STADAC
2-STAG
DAC
VREFHI
VREFLO
VI0
VIO4
VID
VID, vIol
V102
INV V1ID
Figure 1.3 AD8380 DecDriver Functional Block Diagram
A typical signal path of an analog RGB signal to the LCD panel is seen in Figure 1.2. As shown, the DecDriver drives the capacitive inputs of the LCD panel. For example, if the LCD panel is a 1028x1028 resolution display and there are 1028 DecDrivers driving each column, then at every update of the screen, each DecDriver needs to drive 1028 rows. If there are 516 DecDriv-
10

ers instead of 1028 driving the columns, then each driver controls 2 columns and needs to drive
2056 pixels at each update. Thus, a fast DecDriver is capable of driving a higher resolution LCD panel.
The AD8380 (Figure 1.3) shows a typical functional diagram of a DecDriver. Notice that the core of the design is the LATCH, DAC and output amplifiers. The application for a low power, low speed DecDriver would be for portable/handheld devices. These devices require low power operation because they run on batteries. Also, these devices usually have smaller display panels and require less resolution. Thus, a very high speed DecDriver is not required and speed can be traded off for power.
In Chapter 2, a discussion of possible design architectures for the LATCH and the DAC blocks will be considered. This will be followed by a discussion of the actual designs chosen for the LATCH block (Chapter 3) and the DAC block (Chapter 4). Chapter 5 will then discuss the simulated output performance and Chapter 6 will consider the mismatch effects. This will lead to the noise analysis for the DAC architectures in Chapter 7 and finally, the conclusion in Chapter 8 where major points of the thesis will be summarized.
11

2.1 LATCH
Emitter-coupled logic (ECL) is a widely used bipolar logic family. Figure 2.1 depicts a basic ECL Latch. TTL was not used for the LATCH block for a few reasons. TTL is a saturating logic family and thus, may slow down the circuit. Also, the Decoder in the DAC block is easily implemented using differential signals. Finally, using ECL allows the designer to easily reuse the current (as will be seen in this section) and conserve power dissipation.
There may be different variants to this structure, as will be discussed later, but the core of this design is common in all ECL latches, which is the criss-cross functionality between
and
2
.
This criss-cross architecture allows the circuit to hold the data when Q6 steers the current (i.e.
when LATCH is high) using positive feedback. During this hold state, Ic5 becomes negligible, so the data coming into D and DN will have no effect on the circuit. Thus, VON and VO are held at the voltages they were at when LATCH switched from LOW to HIGH and the signals are latched.
In the case where VON and VO have not settled to their final value when LATCH goes HIGH, the small difference output signal will be regenerated to full swing due to the feedback architecture.
When Q5 steers the I current, the latch becomes transparent and thus, incoming data is buffered.
All LOW and HIGH signals are differential signals because D/DN and LATCH/LATCHN are
ECL signals from previous stages.
There are some common mode requirements for the signals for this LATCH to function appropriately. One can see that when D is HIGH, VON is low (when LATCH is LOW). Thus, if we assume that forward biasing the base-collector junction by O.4V saturates the device,
D (HIGH) VON (LOW) must be greater less than 0.4 V. Similarly, in order to not saturate Q
5 and
Q
6
, LATCHN(HIGH) (D(LOW) Vbe) must be greater than 0.4 V.
12

In setting the value of I1, one needs to consider the speed/power and power/area trade-offs for this circuit. Decreasing current would slow the circuit down by decreasing slew rate at the output and also, increasing the RC time constant (because to get the same differential swing at the output with smaller current, RLOAD will have to increase in resistance). Decreasing I also forces us to make the chip bigger in area as the total resistance increases. Making current large would make the circuit faster but would increase power dissipation. In the design, I1 was chosen to be 2 gA, and so, to get a 300 mV output differential swing, RLOAD was set to 150 K1.
VCC,
RLOAD
VON ol0
.R_LORD
02 V
\__
LATCHN
03 04 D
05 06
LATCH
#I1
GND
Figure 2.1 ECL Latch 1
The latch in Figure 2.1 requires that VCC be high enough to support Vbe(Q3,4)
+ Vce,sat drop in order to operate (Vbe(Q3,4) + 2 Vce,sat if we replace Ii with a current mirror) without saturating any devices. High supply voltages are not ideal for low power circuits. In order to accommodate for this, some designers have chosen to use the circuit shown in Figure 2.2 [Razavi, 1994].
This circuit allows the designer to choose a lower VCC because there is at most (1 Vbe
+ 1 Vce,sat) drop from power to ground. It functions similarly to the circuit in Figure 2.1, as Q
1 and
Q
2 latch
13

the data when LATCHN is low. In this case, LATCH is HIGH (a value higher than D and DN) and steers most of I current. Thus, D/DN does not affect the output. Thus, this new latch requires LATCH/LATCHN differential signals to have a higher voltage in the ON state than the
D/DN signal, and a lower voltage OFF state. This is so that when LATCH is high, Q
5 will com- pletely rob I and when LATCH is low,
Q
6 will steal I2. The downside of this design is that it requires 2 current sources. As described by Razavi, this circuit is useful for low power supply applications but does not reduce the power dissipation for high power supply circuits. When VCC is larger than Vbe + Vce,sat, then power is wasted in the Razavi circuit and the latch in Figure 2.1 is a better choice in design.
VCC
D
RL RL
N3Q4 05
ID N LRTCH LRTCHNC
EDGND
06 Q1
(I2
02
Figure 2.2 ECL Latch 2
2.2 DAC
In building the DAC block using the bipolar technology, the common practice has been to use the binary current switching circuitry. A classic example of this can be found in AD56 1. This chip uses an R-2R ladder network to pull binary weighted currents through transistors and implements a switching network to access the currents at the output. The overall idea of this topology, as shown in Figure 2.3, is very simple. The current sources in this 6-bit DAC are binary weighed
14

as given by (2.1). If a switch is in it's off state, the current gets pulled from ground; otherwise, the current is driven from the resistor and the voltage output of the op-amp adjusts accordingly.
I= 2xI
2
2 2 x 1
3
1 2 x1 I
5
2X 1
6
(2.1)
Rf
Iref xRf + Vref
Figure 2.3 General Current Steering DAC Circuit
One can build an R-2R resistor ladder to perform this binary current functionality (Figure 2.4).
For a detailed explanation of how this structure establishes binary current, see Kennedy's paper
"On the Robustness of R-2R Ladder DACs". Generally, in Figure 2.4, when one looks to the right or look up from nodes 1 to 6, the same effective resistance is seen. For example, when one looks to the right of node 5, one sees 2R to the top and 2R to the right. This is true for any node. This causes the voltages in nodes 1 to 6 to be binary weighted, which allows one to pull binary currents through the resistors connected to the switches. This type of configuration is well suited for the bipolar process because the current steering can be readily implemented using ECL. Further discussion of trade-offs between this architecture and the voltage switching DACs will be presented in Section 4.
15

-r '.?1 ?R 2 R3
?R , ?5 2 6
-
;'R
+>Vout
Figure 2.4 R-2R Current Steering DAC Architecture
Another DAC implementation that is widely used performs the voltage switching technique (as opposed to the current switching technique described above). In this architecture, a reference voltage, VREF, gets divided into the number of levels required for the resolution wanted.
For example, in Figure 2.5, we see that VREF is divided into 8 levels to devise a 3-bit DAC (using
8 resistors of the same size). A decoder would be used to choose which of the 8 switches to turn on and the voltage chosen is followed through a buffer. This design is usually seen in MOS DAC designs because of the necessity of voltage switches with zero offset. But the HVCB the process that these DACs were designed on supports depletion-mode N-channel JFETs which can operate as switches if properly biased.
Similar to a MOSFET, a JFET has 3 regions of operation: cutoff, triode, and active. To operate in cutoff, VGS (see Figure 2.6) would need to be biased to a voltage less than Vp (the pinch off voltage of the NJFET). If V_GS and V_GD both are biased to a voltage greater than VP, then the NJFET is said to be in the triode region. Finally, if V_GS > V, and V_GD < VP, then the
NJFET is in the active region. In operating the NJFET as a zero offset pass transistor switch, one usually switch between the cutoff region (to turn off) and the triode region (to turn on).
16

VREF
R
R7/
R
R 3/
R /8
R
+ VOut
Figure 2.5 Voltage Switching DAC Architecture
D
V
-GD
J1
G
+
NL
WGS
V _ GS
S
Figure 2.6 NJFET
The basic components of a simple DAC design were discussed in this section. There has been much research done in the past where people cleverly manipulate these switching DACs to achieve a certain specification. These include structures such as multiple resistor string DACs, thermometer code DACs, etc. The design becomes more than trivial when trying to meet challenging specifications. This thesis will propose a design in which one may attain a very low power DAC built in a bipolar process in a high voltage (10 V peak-to-peak) setting.
17

A simple method of designing an 8-bit LATCH would be to simply make 8 latch circuits seen in Figure 2.1, each pulling it's own current, I. The power consumption for such a design is calculated to be 8 x I1 x Vcc. This methodology is ineffective when looking at the power consumption because each latch would require I1 current. As was mentioned in section 2.1, each latch needs Vbe + 2 Vce,sat from power to ground to function without saturating any devices but with Vec=10 V, there is room to stack many transistors without saturation. At room temperature, and Ic = 2 pA, Vbe was simulated to be about 0.73 V. With Vce,sat = 0.2 V, hypothetically, one can stack 8 LATCH blocks between 10 V. Thus, to conserve power and still perform the required 8- bit LATCH operation, the current being used in a single latch was reused to perform another latch operation. A block diagram of the functionality of a 4-bit LATCH system is seen in Figure 3.1. din vcc
Ilatch
+_j
'u
4
-
L a)U
U +-
-
-E
U
U o a) d2 d2 c13
12 l atch
1IL n vo2n we d4 d4n l atch
0
Vjj4n
I' vee
Figure 3.1 4-Bit Stacked Latch String Block Diagram
18

Each latch block in Figure 3.1 contains the circuit seen in Figure 2.1 without the current source. The node where the current source was tied is simply connected to the next latch block.
Thus, one current source is shared between 4 latches in Figure 3.1. The clock/latch level shifter shifts the clk input signal to the appropriate voltage level for each latch. Also, notice that all the input voltages need to be shifted accordingly. In other words, d4 needs to be at least 2 Vbe less than d3 for the fourth LATCH to operate without saturating.
The complementary signals at the output are also level shifted (Vol is at a higher voltage level than Vo
2
). This type of architecture fits well with the rest of the design. Adding another
LATCH block after this block would be simple because the level shifted output voltages connect right into the level shifted input of the next LATCH block. Also, as will be seen later, the level shifted output voltages fit well into the DECODER circuit that these voltages will eventually control because the DECODER inputs require level shifted voltages with differential signals.
Figure 3.2 shows the actual implementation for the LATCH block for the 6bit DAC. The level shifting for the clock/latch signal is done through a series of diode connected transistors
(Q
3
-
Q
9
). The purpose of the diodes is to simply shift the voltage down by a Vbe. Doing this many times gives a series of level shifted signals. The purpose of Q
9
_
11 may not be immediately obvious. The transistors are diode connected and function as level shifters. The signals VOl/VOiN need have a higher common mode voltage than VO2/VO2N (these signals connected directly to the decoder). Including these diodes allows the outputs to be at their appropriate common mode values.
The design shows two columns of LATCH blocks stacked on top of each other. Theoretically, 6 latches can be placed between -5 V and 5 V without saturating any devices, but that design
19

50K
150K OK
VC
CLK 010
9
Q13
04
LlN
05
L2N
06
L3N
07
L4N
08
L5N
014
L1
015
L2
016
L3
017
L4
018
L5
SAGND
5K
VEE
10K luP
10K luR
09
D yLRTCH Vp~
V 3
D
N
LATCH
0
N
U LATCH Vq
U
0
5Ko
2uA
010
011
LATCH
Vp2?
Vp 4
LRTCH
N Vp N
Vp 6
2 LATCH
N V9 N
024
5K
2uA
0
0
0
(14

was not chosen because the output voltages of the LATCH block needs to be at least 0 V. Thus, the voltages from -5 V and 0 V could not be used to stack more latches. The reason that the output needs to be greater than 0 V will become more apparent in the design of the decoder and the
DAC block.
It should be noted here that the differential signals being produced have a logic swing =
300 mV. For the differential emitter coupled pair seen in Figure 3.2 (Q
1
-Q
2
), calculations can be made to find the relationship between the differential input voltage and the collector currents through the transistors.
clk2
clk2n= Vid (3.1)
Vid Vbe l+ Vbe2= 0 (3.2)
=
S(
1 + (3.3)
VA = Early Voltage, Vth = Thermal Voltage (kT/q), Is = scaler current
Using (3.2) and (3.3), a relationship between Ici and Ic2 can be found as (ignoring Vce term):
-
Ic2 exp
V i
-_
( th)
Defining aF as ratio between emitter and collector currents:
(3.4)
1
-(Ie + = -(Ic +1c2) = c20
CF
(3.5)
Combining (3.4) and (3.5), the equations for the currents Ici and Ic2 in terms of the total current,
Ic20 and the differential input, Vid becomes:
21

IC = FIc20
1 + exp -7
(3.5)
Ic2
=
FIc20
1 + exp(\V)
(3.6)
Given these equations, substituting Vid =
0.3 V, Ic20 =
1 gA, and aF = 0.9934 (P for this process is approximately 150 at low frequencies) into (3.5), the value for Ici becomes 0.9934pA.
Thus, 99.34% of the current is being pulled by the "on" transistor. Most of the remaining current is pulled into the base of the "on" transistor. The "off' transistor has IC
= 8.4 pA. Using Vid of half it's value (0.15 V), QI would still pull 99.05% of Ic2o when turned on. Equations (3.5) and
(3.6) also show that IC will depend on temperature (because Vth = kT/q). For T = 70"C (which is the standard upper limit for commercial products) and Vid
= 0.3 V again, we see that the "on" transistor still pulls 99.34%. Even for T = 0
0
C, the "on" transistor has 99.34%. But, if we decrease Vid to 0. 15V and calculate the "on" transistor current for T = 70*C and T = 0"C, we do see a difference. For T = 70C, "on" transistor current steers 99.22% and for T = 0C, the current has 98.87%. Thus, although the current through the "on" transistor does change through temperature variations, the effect does not change the result of the output significantly.
The differential output signal (Vod) equation, derived from the fact that Vol = Vec Icl(150K) -
Ic
2 0
(50K) and Vo2 = Vc I2050K) - Ic20(50K) is
Vod = Vol Vo
2
= XFIc
2 0
(150kQ)tanh ( id (3.7)
Making Vid and Vod smaller would allow one to use smaller resistor sizes (i.e. making Vid
22

half the size allows one to decrease the load resistors from 150 ki to 75 k9). Also, because the voltages don't have to slew as much at the output, the chip could potentially be faster, but as will be seen in section 4.3, the speed limitation comes from the decoder where the voltages have to slew at least 2V at low current. The disadvantage of making Vid small is that the transistor that is
"on" will carry less of the bias current. Similar architectures to Figure 3.2 were used for the 8-bit
DAC and thus will not be discussed here.
23

4.1 Current Switching DAC
A voltage switching architecture was chosen in implementing the design of the 6 and 8 bit
DACs (Figure 2.5). In this section, a brief analysis of the current switching DAC will be discussed to compare the benefits and disadvantages between using the voltage switching DAC over the current switching DAC. This discussion will be followed by an analysis of the actual circuitry chosen for the design of the three 6-bit DAC topologies that were investigated. The 8-bit DACs follow closely the designs of the 6-bit DACs and thus, will not be discussed.
Figure 2.4 shows the design of the R-2R ladder used in the implementation of the current switching DAC. Figure 4.1 shows how the bipolar devices can be used steer the current from ground to the output. For this R-2R ladder to binary-weight the collector currents properly, the emitter nodes of
1 to
6 must all be at the same voltage. Thus, the bases of transistors Qi to
6 are all biased to the same node so that the emitters can all be at one Vbe below Vbias (as long as all the Vbe's are equal). The switches at the collectors of the transistors can be implemented using differential pairs.
6
LOGIC BUFFERS AND LEVEL SHIFTERS out
]
G ND bi£as
_ 5,p a
.
.
.
P ... P ... 9
9
Figure 4.1 Current Switching DAC
Shows how R-2R ladder and BJTs can be used to steer current from ground and output.
24

This R-2R methodology was not used mainly for one reason: it is difficult to obtain controlled nonlinearly with binary current switching methodology. In LCD driver applications, many times, the designer may want to produce a non-linear output. This is easy to do in voltage switching DACs (simply by varying the resistances of the resistors that are being switched).
4.2 Voltage Switching DAC
The simplest implementation of the 6-bit voltage switching DAC is a string of 64 resistors with switches at each node between the resistors. Figure 2.5 shows this design for a 4-bit DAC.
The design of the switches will be discussed in the Decoder section (4.3) and the design of the
Opamp will be discussed in the Operational Amplifier section (4.4).
Another voltage switching design used is seen in Figure 4.2. This subranging DAC design, when compared with the one string DAC, saves resistors, switches and transistors (in the decoder circuit) but these benefits come at the expense of the two extra buffers between the resistor strings. In this design, Amp 1 always buffers a voltage that is higher than the voltage that Amp
2 buffers. Thus, the current flows only in the down direction in the second resistor stage. Two switches from the first resistor string control the voltage across the second resistor string. For example, if the desired V
0 u is Vmin, then switches 15, 16, and 24 would be on. If the desired output is Vmax, then switches 1, 2 and 17 would be on. If the desired output is Vmid, then 7, 8 and 24 would be on. The voltage across the second resistor string is always the voltage across one resistor of the first resistor string.
The switches may be implemented as series JFET pass transistors (Figure 4.3). A decoder that controls the switches in the desired fashion will be discussed in Section 4.4.
25

vref( max)
1-
R1
3
R1
4
__
+
R2
17 mp
1
R2 ,s
R1
6
7
R1
8
9
R1
RI
10
11
12
13
Ri
14
15
16
RI
_
_
_R2
-24 is
R2 20
R2
21
R2 22
'
23 vref(min) Amp 2
+ vout
Figure 4.2 Subranging 2 Stage Voltage Switching DAC Design #1
The current in this design in the second resistor string flows downward from AmpI to Amp2.
to decoder
Figure 4.3 NJFET Switch
The resistors for the first string were chosen to have larger resistance than the resistors in the second string for many reasons. One reason is that the voltage across the first string is much larger than the voltage across the second string so to minimize current being pulled, R
1 must be larger than R
2
. Also, R
1 must be better matched than R
2 because it controls the higher order bits
26

and making Ri larger allows better matching. Matching considerations and resistor sizes will be analyzed in Section 6. For the 6-bit DAC, R
1 was chosen to be 40 ki and R
2 was 8 kL.
A similar design of the DAC in Figure 4.3 is seen in Figure 4.4. The difference between the two figures is that this new design pulls and pushes current up and down the second resistor string. One can think of this new switching mechanism as leap-frogging. When swinging Vout as a stair case from Vmin to Vmax, first Amp 2 would control the higher voltage, then Ampi, then back to Amp2, etc. In the stair case example, the "on" switches in the second stage would go from top to bottom, then bottom to top, etc. This leap frog has a few advantages over the uni-directional circuit as will be seen in Section 5. The main advantage is that this leap frogging method produces much smaller glitch impulses than the uni-directional circuit. Also, the leap frogging method keeps the circuit purely monotonic.
R1
R1
R1
R1
R1
R1
R1
R1
+
Amp
1
R2
R2 12
R2
13
R2
2
R2
14
1
R2 17
L
-+
>
17 vout vn
Amp
2
Figure 4.4 2 Stage Voltage Switching DAC Design #2
The current in this design in the second resistor string flows in both directions.
27

4.3 Operational Amplifiers with Unity Gain Feedback
Amplifier errors will contribute to integral nonlinearity (INL) and differential nonlinearity
(DNL) errors for this DAC. In Figure 4.4, if Ampi has an error of 10 mV, then the output will carry this error if switch 10 is on. Thus, it is optimal to minimize these errors. Because the design of the output amplifier was not part of the project, only errors due to Ampi and Amp2 will be discussed. Three errors that may be significant are gain error, systematic offsets, and power supply rejection ratio. All these effects will cause the buffer output to differ from it's input. These errors
(or portions of it, depending on which switch on the second stage is "on") will be directly seen at the output. If the errors of both Amps always have the same value, then the errors cancel each other out when determining the voltage across the second resistor string. The gain error has this property, but the systematic offset depends on the input voltage level and thus, the systematic offset errors do not cancel each other out. The optimal op-amp design was not pursued due to the scope of the project. Basic op-amp designs that functioned appropriately were chosen so that more focus would be made on the actual DAC design.
4.3.1 Finite Gain Error
In an ideal opamp with unity gain feedback (Figure 4.5), Vout = Vin. But, due to the finite gain of the amplifier, Vout = A/(1+A)Vin where A is the gain of the amplifier.
vout v
I n+
Figure 4.5 Unity Gain Feedback of Amplifier
28

If A is large, then Vout is close to Vin. If the offset due to finite gain is significant compared to an
LSB, the amplifier would need to be redesigned to have higher gain (i.e. using cascode circuitry).
03
IN 01
VCC--
02
04
EGND
Figure 4.6 Ampi Architecture with Feedback
The gain of this simple amplifier is calculated to be gm
1
(r.
4 j|ro
2
). With VAn' = 150 V and
VAp =50 V, the gain is approximately 2000. Given this estimation, Vout/Vin = A/(1+A) = 0.9995.
When Vin is maximum, this finite error will have the greatest effect on the output. So, setting Vin
= 1 V, the finite gain error produces an error that is 0.016 LSBs for 6-bit DAC and 0.064 LSBs for
8-bit DAC. But one should notice, an op-amp is used for both the top voltage and the bottom voltage of the resistor string (a possible Amp2 design is seen in Figure 4.7). Thus, both amplifiers should be taken into account when calculating the gain error due to finite gain because the combination of both amplifiers define the voltage across the string. Because the bottom amplifier will also produce a gain error, most of the gain error given by the top amplifier may be cancelled by the bottom one in determining the voltage across the resistor string. In effect, the sum of the gain errors will show up as a scale factor at the output, which can be easily fixed using an opamp.
29

VCC
110
01 Q4
|
GND
|
Figure 4.7 Amp2 Architecture with Feedback
4.3.2 Systematic Offset
The input offset of this simple amplifier greatly affects the INL and DNL errors of the DAC. The input offset voltage can be defined by and Q
4 will show up in this equation by affecting the currents through Q, and Q
2
)
Vos = Vbel-Vbe2 (4.1)
Vos = Vth x In [CX2
..
42 X Is11
(4.2)
These equations given above are approximately correct, given equal Vce's, but for systems whose transistors have significant Vce's, the equation for the current of that transistor can be better equated by
IVbe
IC = IsX( I+ C)Xe t (4.3)
30

Thus, the new equation for the input offset is
Vos = Vth x In
[Ic1 X s2
C
Vce21
Ic2 X Is xS1 + A~
(4.4)
In (4.4), Ici and Ic2 are determined, in the first order, by the collector currents of the current mirrors. But, a more careful analysis shows that Ici
= 1c3 + Ib3 + Ib4 which is approximately Ic3 +
2 1 b3 assuming Ib3 = Ib4. Also, Ic2 = c4 Ib2 if we replace the buffer with a wire (a discussion on why this is not a good design and other possible designs will be discussed later in this section).
These base currents play a significant role in determining the offset voltages. The LSB of a 6-bit
DAC (with +/- 1V swing) is 31.25 mV and for 8-bit DAC is 7.8 mV.
One final observation in the circuitry that affects the offset voltage is the affect of large
V e's of the current mirrors on their collector currents. From looking at Figure 4.6, one can see that Vce3 = Vbe3 and Vce4 may vary between (VCC Vce,sat) and (Vin,min + Vbe2). Thus, Q
4 has a much greater variation of Vce than Q
3 and this may affect the collector current matching. The final derived equation for the Vos is approximately
V = Vth x In osIS1
Is2
X Is3 x I
+
Vce
X Is4 x 1 + x 1+
V e x
1
+
2
)
V
) X (
1 +
VAP x 1 -n
(45)
Assuming that Is2 = Isi and Is3 = Is4, equation (4.5) can be written to be dependent on only
Vce, 0 , and VA. We have not yet taken into account the buffer in Figure 4.6. This buffer is required to isolate the high impedance node (Q
4
's collector) to the output stage.
In the 2 resistor string DAC that pulls current in the output string in one direction (Figure
31

4.2), the top amplifier needs to be able to source current and the bottom amplifier needs to sink current. As mentioned, the simple op amp shown in Figure 4.6 will not satisfy the requirements because the current is being sourced from Q
4 and creates a significant input offset error. The following circuit is a more promising design.
V IN Qi02
VCC
03
04
I1
GND
0
05 to res string
i stor
Figure 4.7 Ampi Architecture with Pseudo-Class A Output Stage
In this design, the emitter follower reduces the current being pushed from
Q
4
.
Similarly, a pull-transistor is added for the bottom op-amp. Transistor
Q
5 provides the push current for the output resistor string and the base current of
Q
2
.
Q
4 is now required to provide the base current of
Q
5 instead of the entire output string current. The new offset voltage given this circuitry (assuming perfect matching of transistors) is:
Vos = Vth x In
1+ (2_>(i-
3
SVAnx + P
V
A(4.6)
V+hen[
VAng)
+
+4.6
c
VAl)e fr
1 c5
4 i m
To get a first order approximation for the range of values for Vos estimates were made for
32

the variables in the above equation. Assuming Vbe to be 0.7 V, the following 6 estimates were made:
1.) Input voltage to the op-amp varies from 1 V to -1 V
2.) VAn= 150 V, VAp = -50 V
3.) Vce
3
= -0.7 V
-5.3 V < Vce4 < -3.3 V
4.) 4V<Vcei<6V
Vce
2
= 1.4V
5.) Ic5/1c4 = 10
6.) On= 150, Pp = 100
It is important to take notice that the transistors with the greatest absolute Vce values are in the denominator of (4.6). Given these values, we can calculate Vos from (4.6) to be between
-0.72 mV and 0.56 mV. With active loads, offset voltages usually are due to base currents of the load devices. But in our case, the base currents of the load device helps to minimize the offset voltage because it makes the denominator of (4.6) larger; in other words, the fact that Q4 has a large Vce (and thus has a higher collector current), is offset in part by the base current requirement of Q5. Also, the fact that Q1 has a large Vce is offset in part by the base currents of the active loads. Thus, the base currents of the active loads don't create a greater offset voltage but helps to minimize the offset voltage by cancelling some of the Vce mismatch errors.
Similar arguments can be made for the bottom op-amp. The offset voltage for Amp2 can be'given by the following equation:
33

1+ ce
2
) x + ce3
V = Vth x In
Vsn
1
+ Vcex + Je x
')X(IV
1+
(- c
( 'c4
1 3
(4.7)
From the list of 6 estimations made above, only numbers 3 and 4 need to be updated for this opamp.
3.) Vce
3
= 0.7V, 3.3V < Vce
4
< 5.3V
4.) -6V < Vcei < -4V, Vce
2
= -1.4V
Thus, the range of values for Vos for the pnp-input op-amp from (4.7) is 0.0725mV <Vos <
1.34mV. This offset voltage can be greater than the npn-input op-amp because the $ of an npn transistor is larger than the I of pnp transistor. Thus, the extra current being supplied to Q1 of the pnp-input circuit from the base currents of the active loads do not cancel the Vce mismatch error as much as the npn-input circuit (because the pnp-input circuit has npn active loads and thus, less base currents from the active loads).
In the DAC architecture where current is pulled in both directions at the second resistor string, the opamps need to be able to push and pull current. In order to do this, two different output circuitry possibilities will be discussed.
Method 1) Push-Pull (Class B) output stage
The architecture of the push-pull output stage is seen in the Figure 4.8 with unity gain feedback. The npn transistor sources any current required at the output and the pnp transistor sinks the current being pulled from the output. But, simply connecting this output stage to the output of the amplifier as seen in Figure 4.8 creates a problem when a unity gain feedback is implemented. When the output tries to sink current, the Q
6 turns on and brings collector of Q
2
34

approximately one Vbe below Vb2. This causes Q2 to go into saturation as the Vbc2 is forward biased.
VIN
03 04
01 Q2rsistor
01 020
,11
'UNU
Q5 to str ing
Figure 4.8 Ampi Architecture with Class B Output Stage
To account for this problem, one can add another stage between the amplifier and the output stage. One simple solution is to add an emitter-follower stage as seen in Figure 4.9. This stage has the advantage that one can control the current being pulled at this leg (almost independent of the current in the resistor string), and thus control the base current being taken by Q
7 from
Q
4
.
Thus, we can control this base current as mentioned in the previous section to minimize the
Vos.
35

VIN
03
01
.11
02
04
05
07
T12 I
61 tsistor
Sstring
Figure 4.9 Ampi Architecture with Emitter Follower and Class B Output Stage
Method 2) Emitter Follower
The emitter follower output stage shown in Figure 4.10 can also source and sink current to the output resistor string. When pushing current down, Q
5 needs to supply currents for the resistor string and the current source (I2). When the current is being pulled up, I2 sinks in the current from the resistor string and also pulls in the current from Q
5
.
If we minimize the current at the output to about a few micro-amps, then we can set the emitter follower current to pull about 6 pA.
Thus, at pull down stage, Q
5 supplies 8 gA and at sink current state, Q
5 supplies 4 pA. This architecture pulls a little less power than the circuit in Method 1 and has no obvious benefits over that circuitry. Thus, in the implementation, the emitter follower stage was chosen, though circuit in Method 1 would have performed just as well.
36

03
VIN 01
I
02t
Q4
05
WI2 resistor string
Figure 4.10 Ampi Architecture with only Emitter Follower Output Stage
4.3.3 Power Supply Error
The calculations for Vos done in the previous section assumes that the power supply remains constant at +/- 5 V. But it is not uncommon for the power supply to difffer from this value. It may have variations of over 1 V, and this will affect the amplifier errors. For example, from Figure 4.6, if VCC = 6 V instead of 5 V, then the Vce's of Q4 and Q1 both increase by 1 V while Vce's of Q2 and Q3 remain the same. Recalculating Vos as done in section 4.3.2 using (4.6) with VCC = 6V, Vos will be between -1.3 mV and -85 pV. If VCC = 4V, Vos would be between
1.2 mV and -0.085 mV. As described earlier, there are other possible amplifier designs that would improve the performance in diminishing the amplifier errors but the focus of this project was to analyze the core DAC circuit and not to design the best possible amplifier for the buffer circuit.
Thus, this simple amplifier was used.
4.4 Decoder
The decoder is used to control the switching mechanism of the NJFET devices in the resistor string. In the 6-bit, one resistor string, DAC, the decoder needs to be able to turn on one JFET at a time, depending on the data coming from the LATCH Block. In order to turn a JFET on, the
37

VGS needs to be above VP. The pinchoff voltage of a JFET on this high-voltage process is about
-2V. Also, because of the symmetry of the device, the source and the drain can be interexchanged. Thus, to keep the device off, both VGS and VGD need to be less than VP.
The circuitry for the ECL decoder is seen in Figure 4.11. It can be thought of as a tree where the current flows down one path, depending on the logic input. Thus, if both V
3 and V
4 were HIGH, then the current would flow down and end up in Q6. This current then needs to be turned into a voltage to control the gate of the JFET.
VCs
V4
01
04 V
02
3
05 06
Figure 4.11 ECL Decoder
The circuit needs to operate so that when the current is present, it pulls the VGS above VP.
Consider first the state when the current is not present. The gate voltage of the switch transistor needs to be pulled down V, below the lowest possible drain voltage in the resistor string
(Vref,LOW). For VP = -2 V and VrefLOW = 1 V, the gate voltage of the NJFETs must be at most
-3 V to turn the FETs off. This is true for every transistor on the resistor string and not only for the FET controlling the Vref,LOW node. One may think that the transistor connected to the
VrefHIGH (the most positive voltage in the resistor string) node needs to have a gate voltage pulled
38

down to VP below Vref,HIGH (-2 + 1 = -1 V) to force the transistor to turn off, but a more careful analysis show that this is untrue. Consider the case when switch 1 is off and switch 16 is on in
Figure 4.2. The drain voltage for all the transistors is VrefLOW (-1 V). Thus, if V
0
. for switch 1 was -I V, then VGD would be OV forcing the FET to turn on because of the drain and source for a
FET can be interexchanged. Thus, for all transistors, the off voltage must be less than VrefLOW +
VP. Now, consider the case when the transistor is to turn on. Again, we'll check the extreme cases where switch 1 and switch 16 turn on. When switchi turns on, the voltage at the gate must be at least Vref,HGH + Vp (-1 V). When switch 16 turns on, the voltage at the gate must be at least
Vref,LOW + Vp (-3 V). In the implementation, the transistors that switch 0 to 1 V in the first string were given an on voltage of 0.5V and the transistors that switch -1 to OV had on voltages of -1.5
V. The "on" voltage of the second string depends on the common mode voltage level of that string
(because the voltage output of Ampi and Amp2 change depending on the input). Thus, the "on" voltage is taken from within Ampi so that the "on" voltage can track the common mode voltage level.
The tree-like decoder, as described previously, flows a current down one path as described
by the input logic levels. But this current needs to be changed to a voltage to control the inputs to the FETs. Also, the voltage must be able to swing at least 3 volts to switch the transistors from one state to the other. For low power applications, simply inserting a resistor at the end of the tree is not reasonable. If one decides to run 2gV down the tree, to swing 3 V, the resistor needs to be
1 MC. The chip size will be greatly increased by adding these 32 large resistors.
Another circuit one can implement to create this large swing is seen in Figure 4.12 (which was the architecture chosen in the actual design). In this circuit,
Q
3 1 and Q
32
(and all other transistors along that row) function as pull up and pull down transistors. To see how the circuit works,
39

lets set I = 1 A and I2 = 0.5gA. As we know, I will flow down one path. But when it reaches the end of the tree, the bottom transistor will only desire to sink 0.5 pA. The rest of the current
(0.5 gA) will flow into the pull up transistor, Q
32
.
If the base of
Q
32 is set at Von + Vbe, then node
1 will be at Von when that node is desired to be turned on. In the case where no current flows down that node from I1, I2 will still desire the 0.5 gA and thus, will require Q
31 to provide this current. Thus, if we set the base of
Q
31 to be Voff + Vbe, then the node will be forced to Voff when that node is desired to be turned off. The implementation of this layout is much smaller than adding resistors because the transistors can be minimum size, and thus, very small.
The trade-off from this circuitry to the circuit with resistors is that at the bottom of every branch of the tree, we need to add a current mirror that sinks I2. Thus, if we branch off to 32 nodes, then we are pulling 32 x 12 amount of current and thus, 32xI
2 xVpp power. The only way to minimize this power is to minimize the I2 value, and choosing a value of 0.5 pA would give a power dissipation of 160 pW. But choosing such a small value for the current has it's disadvantages. To be safe, we will try to make the DAC to run at the speed of 2 MIHz. Thus, we can calculate the required current to swing 3 V from I = C dV/dt, where C is the capacitance seen at the node that is to slew. This capacitance is dominated by the collector to substrate capacitance of the transistors and will be approximated to about 50 fF for initial estimations. To run at 2 MHz, and with these given values for C and d, the current needs to be at least 0.3 pA. With I = 0.5 gA, the voltage can slew 3 V in 0.3 ps.
40

LTI(
.r
9*0 k=
I I
N
91
Go6
9T
N slit
Eli 01IT
~
9T4£I d
I
33A G
1
I fit
TA
-
1 : I I
N fT CT
10 z LZ
1*0
-t : I I
ZI TI
105 s0
TA N TA
- t : I I - If: I I I I - 1 : I
960 ~
I zI~1
*60
560
-r I
1 lA 0
Ito L60 r f71~T 77Th l~ K113
eT 6 zo cz
TA N
9
'
1011
9
10 TA N z G
60
5
10 61TLI
TA N
1 c Z
To ST go TA N LO
I
TA N
ZA N ZA N ZA ' N I ZA
0
I-
I-I
0
0
I-
0
0
I-
S90 so
R 1 A
N
TO
CA
TJI
J33A

5.0
Table 2: Performance Specifications of various DAC designs
# of BJTs
# of NJFETs
6-bit DAC string
6-bit DAC
1 resistor Design #1
8-bit DAC 6-bit DAC 8-bit DAC
Design #1 Design #2 Design #2
324
64
# of Resistors
(LATCH/DAC)
20/67
Total of Resistor Val- 2185K/ ues 340K
(LATCH/DAC)
Power Consumption 740 W
Total
Power Consumption 81.5pW
(Latch)
Power Consumption 658.5gW
(DAC)
1 LSB Settling Time 0.6gs
0.44gs/
0.56gs
142
24
20/22
2185K/
392K
537gW
92gW
445gW
0.35gs/
0.6gs
0.42gs/
0.45gs
249
48
27/38
3090K/
392K
754gW
106gW
645gW
0.4gs/1gs
0.43gs/
0.50gs
184
18
20/22
2185K/
496K
568pW
68gW
500gW
0.5gs
0.50gs/
0.55gs
264
34
27/38
3090K/
395K
749gW
95gW
654gW
0.35gs
0.50gs/
0.75gs
Full Scale Settling
Time
(falling/rising)
Glitch impulse
(1 LSB swing)
Glitch impulse
(Full Swing Fall/
Rise)
3.225nV-s 400pV-s/ 175pV-s/ 2.5nV-s
60pV-s/
128pV-s
45nV-s
62.5pV-s/
610pV-s
40nV-s
40pV-s/
100pV-s
10nV-s/
200pV-s
5nV-s/
3.25nV-s l00pV-s
Design #1:
Design #2:
Design as seen in Figure 4.2
Design as seen in Figure 4.4
Table 2 shows a summary of performance specifications for each DAC designed. In this section, the results from the simulations will be analyzed. Focus will be mainly on power, speed
42

and glitch impulses. Device mismatch analysis and noise analysis will be done in the next two sections.
Table 2 shows that the resistor count and transistor count for each DAC are similar, although the 8-bit DACs generally have more transistors and resistors than the 6-bit DACs. This is mainly due to the extra logic required in the decoder and the extra resistors in the voltage switching DAC architecture. But, it should be noted that most of the resistance comes, not from the DAC block, but from the LATCH block. This is because each LATCH outputs differential voltages of about 0.3 V. Because each LATCH is biased at 2 gA, each LATCH requires a pair of
150 kW resistors. For the 8-bit DAC, for the latches alone, this adds up to 2.4MI. The power consumption of the DACs are less than 1mW, with the 6-bit 2 string DACs near 0.5 mW. Most of the power dissipation does not come from the LATCH block but from the DAC block. As was discussed in section 4, the decoder dissipates most of the power in the DAC block.
The settling time for a 1 LSB swing and full swing were analyzed. These will determine the speed at which the DAC can be run. A 1 MHz requirement corresponds to a 1 ps settling time.
So, any word change at the input must settle at the output within 1 ps. As the table shows, most of the DAC variants settle around 1/2 gs. The table also shows two values for settling time for the 6- bit 1 way DAC and the 8-bit 1 way DAC. The first value corresponds to an LSB change when there is no voltage change across the second resistor string. The second value corresponds to an
LSB change when the switches in the first resistor string changes state, and thus, the voltage across the second resistor string changes. These values differ because the change of states in the first resistor string takes some finite time to affect the voltage across the second resistor string.
The calculation for the glitch impulse is done using the formula described in the Analog to
Digital Conversion Handbook. The positive rising glitch area is subtracted by the negative glitch
43

area. The net result is given the name "glitch impulse" and has the units V-s (Volt x seconds).
Equations (5.1) to (5.4) show the calculations for the glitch impulse for Figure 5.1. These glitches mostly arise from asymmetries in the on-to-off and off-to-on times of the voltages switches in the
DAC block [Analog-Digital Conversion Handbook, 1986]. mV
00
Figure 5.1 Glitch Analysis
G, = G,-G,
G,= ( 5ns xl1mV ) = 25 pV -s
= (nsx12mV) = 3OpV-s
(5.1)
(5.2)
(5.3)
G, = -5 pV -s (5.4)
Figure 5.2 shows the response of the 6-bit DAC to a digital ramp covering all codes.
There are large glitches at each 8th step at the output (steps where both the first and second resistor strings change switch states). To analyze these glitches, consider the circuit in Figure 4.2, when going through a step-ladder response as seen in Figure 5.2. The switches in the second string turn "on" in the upward direction. When switch 17 is reached, the next transistor that turns
"on" is the bottom transistor (switch 24). But the op-amps have not settled the voltages across the
44

second resistor string by the time the switches change states. Thus, switch 24 still sees the old voltage from the op-amp until the op-amp settles to a new value and the voltage output shows a downward glitch.
Figures 5.3 and 5.4 both show a 1 LSB ramp output response; the first shows where the switch only changes in the second resistor string and the second shows where there is a large glitch at a segment boundary. Figure 5.5 shows the full-scale step response of this architecture.
The settling times for each response are seen to be less than 1 gs.
------------------------------------------------------------- --------------- ---------------- 7 -------------------------------------------------- I
--------------- ----------------- --------------- --------------- ----------------- ----------------
I ---------------- ---------------- --------------- 4 : ------------ --------------- ... ---
--------------- ----------------- --------------- --------------- --------------- - --------------- --------------- ---------------- I I --------------- --------------- ---------- ----------------
-7 --------------- ------------------------------------------------------------------------------------
--------------- --------------- - ------------------------- ------------- ----------- ----------
-------------------------------- ------------------------------- ---------------- --------------- --------------- --------------- ---------------- --------------- ---
51 --------------- ---------------- --------------- --------------- --------------- - --------------- --------------- --------------- ---------------- -------
------------------- ----------- ----------
------------ ----------- ----------
----- ----- --------------- ---------------- ----------
L --------------- --------------- ---------------- --------------- --------------- --------------- - ------ -------- --------------- --------------- ---------------- ----------
--------------- ----------------- --------------- --------------- 1. --------------- T -------------------------------
---------------------------------- ------------------------------------------------- --------------- L ---------------
--------------- --------------- I
--------------- L ------------------------------- ------------------ ----------
C) ----------------------------------------------------- ------------ ----------------- -----------------------
3-
--------------- I
-----
---- ----------------- --------------- ---------------- ----------
---------------------------
------
------------------------------------------------------------------ --------------------- ----------- ------ -------- --------------- ---------------- --------------- --------------- ---------------- ----------
------------------------------------------------------------------------- -- -- ------------------ --------------- --------------- ---------------- --------------- --------------- ---------------- ----------
I ----------------- --------------- --------------- ---------------- ------
-------------------------------- --------------- ------------- --------------- ------------- ------- ----------- ----------
--------------- ---------------- ------------------- ------------------------ - ------------------------------- --------------- ---------------- --------------- --------------- ---------------- ----------
--------------- -------------------------- T
--- ----------- ------------------------------- I --------------- ---------------- --------------- T, --------------- 11
3-
0
------------------------------- -------------- -------------
----------
L --------------- --------------- ---------------- --------------- --------------- --------------- ---------------- ----------
--------------------- -- ---------- ------------------------------------------ ------------------------------------------------------------------------------- ------------------------------------------------
----------- -----
----------- -------------------- I
__L
::Y
-----------------------------
4
--------------- ---------------
_S
4e , 3
I ---------------- ---------------- --------------- --------------- -----------------
---
7 r--
JB
- so
3- _'L - 3-
IL
----------
Figure 5.2 6-bit Ramp Response of Design #1
45

E,
--------------- ------------------------------------------------------------------------------------------------ -------------------------------------------------
-------------------
------------------- ---------
--------- --------- ---------- L --------- --------- ---------
----
--------- --------- --------- ---------
-------------------------- ---------
I ---------- ---------- I
--------- ---------- ----
------- ----------- ------------- ----------------------------- --------- ------------------------------
-------------------- I ----------
---------- ----------
I
---------- ------------------- ---------
-700
-------------------- 4 ----------------------------------------------------- ------------ -------- -------
I ---------- --------- I ---------------------------------------------------- ------------ T -------- - ------- --------- ---------- ---------- ---------- I ---------- --------- ---------
--------- ------------------------------------------------- --------- -- --------------- ------- --------- --------- --------- ----------------------------- --
-70
-70
A I
---------- I --------- --------- I I --------- I
---------
--------- ------------------- --------- ------------------------ ----- --------
--------- ------------------- -------------------
-7 0
-7 -LA
E3
---------------- ----
--------- -------- --------- --------- ------------------------------------------ ------------------------------------------
---------
----- --------- ------------------- --
--------- -------
-7 -L 0
-7 3- M --------- I
----------
--------- --- --- I
L --------- --------- --------- --------- --------- --------- ---------
---- --------------------------------------- --------- ---------- ----------
----------- -----------------
-7 3-
-7 -L $3
-----------
-------- --------- ---------
---- -------------
-------------------------- --------- - --------- --------- ----------
I
-----------------------------------------------------------
--------- --------- --------- -------------------
-7 M 0 --------- 4
I ----------
-7 M n
-7
M A
--------- ---------- ---------
----------
L
--------- --------- I --------- I --------- I ---------
--------- 4 --------------------------------------------------------------
---------- --------- --------- --------- --------- --------- --------- --------- --------- ---------
-7--.5 -------------------- --------- --------- --------- --------- ------------------- --------- ---------- --------- --------- --------- --------- --------- --------- --------- --------- --------m 0 A
-- ----------------------------------------------- --------- ------------------- --------- --------- - --------- ------------------- ------------------- ------------------- -------------------
13 El m 0 .4 S E3 no S .
0 A m OF, M no5. m m 0 m E3 m C) .
.
a
:;t 0 E. a -a m 0 F. n m 0 E5 .
Ei
Figure 5.3 6-bit 1 LSB Ramp Response (Design #1)
5i
------------- ------------------------------- --------- ---------- -------------------- ---------- --------- ---------- --------------------
---------- --------------------
---------- -------------------- --------------------------------------------------------------
---------- ---------- --------- ---------- --------- - ---------
-7-70
'7 S 0
---------- -------------------- --------- ---------- ---------- --------- ---------- ---------
--------- ----------
--------- ---------- -------------------- ---------- -------------------
--------- --------------------------
---------- ----------
---------- ----------
----------
---------- --------- ----------
--- ----------- --------- ---------- ---------- --------- ---------- --------- ----------- --------------------
I
--- --------- ----------- ---------- --------- ----------
7 5) 0
---------- ----- --- ---------- --------- ---------- ---------- --------- -------------------- --------- ---------- --------- - -------- --------- ---------- ----------- --------- ----------
-
-
130 0
S 3-O
----------- ------ --
I --------- ----------- --------- -----------
----------
------ ----------- --------- ---------- ---------- --------- ----------
---------- ------ ----------------------- --------------------- ----------------------------------------- ----------- I ---------------------- -----------
S M 0 I
--------- ---------- ---------- --------- ----------- I ------------------------------ - --------- ---------------------- -----------
S Z3 0
4 --------------------- ---------- ---------- I
SA 0
IE3 S 0
---------- -------- ---------- --------- ---------- ---------- --------- ---------- --------- ----------
------- ----------------------------------------------------------------------------
----------- -------- --------------------------------------------- --------------------- --------------------------
---- r
-------------------- I --------- ---------- r --------------------
C 0 --------------------- ---------- ----------- --------------------- --------- ---------- --------- ---------- 4 ---- : ----------- : --------------------- - --------------------
13-70 a a o
E3 S? 0
--------- ------------------- -------------------------------------------- --------- ---------- -- -------
------------------ --------- ---------- ---------- --------- ----------
------------------------------------------- --------- ----------- ---------
I L --------- ---------- --------- ----------
C) C)
------------------------ ------------------- 4 --------- ---------------------- ----------- ----------- --------- --------------------- - -------------------- --------- ----------
S a_ 0 -----------------
---------- ---------- --------- -----------------------------
---------- --------- ---------- --------- -------------------- --------- ----------
V2 0
.> .4 0
---------- ------------ ------ --------- ---------- ---------- ---
---------- ---------
---------- --------- ----- ---- ------
---- --------- ---------- --------- ---------- ---------- --------- ----------
------------------------------- --------- 4 ---------- ----------- ----------------------------------------- --------- -----------------------
--------- ----------
---------------------
----------
---------- ---------- --------- ---------- ---- --- ----------- ---------- -------------------- ---------------------------------
---------------------
SPS O
------------ --- --------- ---------- ---------- ---------
--------- ---------- ----------- I
S Is 0 ---------- --------- ---------- -------
--------------------------- ------------ --------- ---------- -------------------- -------------------- ---------------------
L --------- ----------
SP-70 s's
-------------------------------- ---------
----------- ---------- I
--------- I ----------- --------- ---------- --------- - ---------
I
0 a_ es 5 a_ Is S .
3- a_ .5 -S
m 1-.5 5
I -------------------------------------------------------------- -------------------------- ----------------------------------------------
. a 3- 05 5 'a a_ -5 S :L 45 Ei . e5 3- 45 5, . -7 a- Is S a_ C S S?
Figure 5.4 6-bit 1 LSB Glitched Response
This glitch occurs when the switches in both the first and second resistor string changes states.
46

------------------------------------------------------------------ ----------------------------------------------------------------------------------------------------------------------
----------------------- --------- 4 --------------------- ------------ ----------- ----------- ---------
------------------------------------------
---------- ----- ---- ---------- --------- ---------- ---------- ---------- --------- ---------- ---------- ---------- ---------- --------- ---------- ----------
-7 ----------------------
----------
----------
-------- - ---------- --------- ---------- ---------- ---------- --------- ---------- ---------- ---------- ---------- --------- ---------- ----------
---------- --------------------- ----------
---------- --------- --------- ----------- ---------- -----------
1. ---------- I
---------- ---------
----------- ------- ------------------------ j ------------------------ ------- ---------- ---------------------------------------------- -----------------------
T
---------- ---------- ------------------------------
---------- ----------- ---------- ----------
----------------------------------------------------------------------- - - -------------------- --------------------- -------------------- ---------- ---------- ---------- --------- ---------- ----------
3- ----------------------- ------------------------------------------------------- ------------------------------------------------------------------- ---------------------------------------------------------------------
0 ---------- ---------- --------- ---------- ---------- ---------- --------- --------- ---------- ---------- ---------- --------- ---------- ---------- ---------- ---------- --------- ---------- ----------
3-1 ---------- -------------------- ---------- ---------- ---------- --------- - - ------- ---------- ---------- ---------- -------------------- ---------- ---------- ---------- -------------------- ----------
---------- ---------- --------- ---------- ---------- ---------- ---------- --- ----- ---------- ---------- ---------- -------------------- ---------- --------------------- --------- ---------- ----------
---------- ---------- --------- ---------- ---------- ---------- ---------- ----- --- ---------- ---------- ---------- --------- ---------- ---------- ---------- ---------- --------- ---------- ----------
I ----------- ------------ --------- - - ----- -- - ----- ----- ---------- ------------------------ -- - -- --- -----------------------
---------------------------------
S ---------- ---------- --------- ---------- ---------- ----------
---------- ---------- ---------- ----------
I --------- ----------
-----------
---------------------- ---------------------- ---------- -------------------------------- -
------ ---------- ----------
-7 ---------- ---------- --------- ---------- ---------- ---------- -------------------- ---------- ----------
---------- ------ ---------- ----------- -----------
---------
---------- ---------- --------- ---------- ---------- ---------- ---------- --------- ---------- ---------- ---------- -------
-------------------- L--------- I --------------------
---------------------------------------------
----------
----------- ----------- ---------- --------- 1.
----------
--- ---------- ---------- --------- ----------------------
3:
----------- ---------- --------- --------------------- ---------- --------- I --------- ----------
* --------- - --------- ---------- I---------- ---------- ------
----------
---------------------- ---------------------------------------------------------- ----------------------
--------------------- --------- - --------- -------------------------------- -------------------- ----------
M E3 S 0 ss 3- - M a--> :L 3- . :;2 0 S 3- S a_ 3- - M IE3 r :Z M, 3- M E3 , a :1L - M 93 S Z E. 3- - M E3 a A 3-
-3---Z
Figure 5.5 6-bit Full Swing
The input was given word change from all "FUGH" values to all "LOW" values at 1.285 ms.
The DAC architecture that sources and sinks current in the second resistor string (Figure
4.4) should not have the glitch problem seen above. Figure 5.6 shows the same ramp response of this circuit. As described in section 4, the "on" FETs in the second resistor string does not jump from top to bottom when moving ILSB but moves only to the next 'FET down. The glitch would be a much smaller glitch than the I -way current architecture because the voltage it drops to isn't significantly different from the initial voltage.
47

3- ;-- ( ---------------------------------- I
I --------------- -------------------------------- ---------------
--------------- --------- ---------------- -------------- ---------------- --------------- --------------- -------------- ---------------
---------------- -------------- ---------------- ------
--------------- ------------------------------- -------------------------------- --------------- -------------- ----
-7 ---------------
--------------- -------------- --------------- --------------- --------------- -------------- --------------- --------------- --------------- ------------ -- ------- ------------- -
---------------
--------------- -------------- --------------- --------------- -------------- --------------- ------------------------------- -------------------
--------------- ------------------------------ --------------- ------------------------------- -------------- ---------------
---------------- ---------
- -------------- ---------------- ------------- -
--------------- -------------- I ------------------------------- I - -- ------------------------------------ --------------- I
--------------- --------------- -------------- --------------- --------------- ---------------- -------------- ----------- -------------- --------------- -------------- --------------- I
3. --------------- --------------- -------------- ------------------------------- ----------------
-------------- .
---------------
-------------- -------------- --------------- --------------- --------------- ------
------- I --------------- -------------- -------------- -
3- --------------- --------------- ------------------------------ -----
------ ---------------------- --------------- --------------- -------------- -------------- ------------- -
--------------- --- ---------- --------------- --------- ---------------
--------------- --------------- --------------------------------------- -
-------- ------------------------------- --------------- --------------- ---------------------------------------------
-
- --------------- -------------- --------------- --------------- --------------- --------------- --------------- ------------- -
--------------- ---------------- -------------- -------------- I -------------- ---------------- -------------- I ---------------- ---------------- ----------- - -------------- -------------
S --------------- ---------------- -------------- ------- I ------------------------
----------------------------------- ---------------------- T -------------- -------------- -
------------------------------- ------ -- - ------------------------------- --------------- -------------- --------------- --------------- --------------- -------------- --------------- , ---------------
-7 -------------- ------------ -
-----------
---------- --------------- --------------- --------------- ------------------------------ ------------------------------- -------------- - -------------- ------------- -
- ---------------
---------------
---------- --------------- ---------------
--------------- --------------- ---------------
--------------- ------------------------------ --------------- --------------- -------------- --------------- --------------- --------------- ---------------
--------------- ------------- -
----------- --------------- -------------- --------------- --------------- --------------- -------------- --------------- --------------- --------------- -------------- --------------- -------------
S ------------------
L-- , -3- -- a
---------------- --------------- -------------
--- .1 -
----------- -2
Figure 5.6 6-bit Ramp Response of Design #2
E-. 11
E; C)
-------------------------------------------------- --- -- -- ----------------- ------------------- - ---- --------------- ----
--------------------------- ---------------------- -
- ---------- - ---------------------------------------
------------------- ------------------- ------------------- --------------------
--------------------------------- - ------------------- ---------------------------------------
-------------------
F. -7 C3 --------------------
F, -7 r ------------------- ------------------- ------------------- ------------------- ------------------- ------------- ------ ------------------- ------------------- ---------------------------------------
------------------- ------------------- ------------------- --------------------------------------- ---------- --------- ------------------- ------------------- ------------------- ------------------ff. IE3 -'5 ------------------- ---------------------------------------- -------------------------------- L -------- -------- - ------------------- ------------------- ---------------------------------------s C) ------------------- ------------------- -------------------- ------------------- j ff ------------------- ------------------- -- --------- --------------------------------------- - ----- ------------ ------------------- ------------------- --------- --------- -------------------
(5 C) ------------------- a -------------------------- ---- I -------------------- ----- -------------- L ------------------- ------------------- ------------------- -------------------
5 C E.
------------------- -------------------
------ ----------- ---- I
-- --------------- - ------------------- ------------------- ------------------- -------------------
3- C) ----------------------------------------------------------- ------------------- ------------- - ---------------- ------------------- ------------------- ------------------- ------------------t E3
------------------- ------------------- ------------------- --------------------------------------- ---------------------------------------
------------------- ------------------- -------------------
.2 C, -------------
--------------------
E3 M
------- ------------------------------------------- ------------------ ------------------- ------------------- --------------------
0 5i - 3- 2 E3
L--
2
I m 0
-a--
- :3
Is
! E3 E5 - .4 0 a E3 15 M 93 F. - -7 E3
Figure 5.7 6-bit I LSB Ramp Response
48

6.1 Resistor mismatch
For confidentiality reasons, the 3 sigma mismatch of thin film resistor (TFR) for this process will not be given. But, the percent mismatch for different resistor sizes can be calculated as seen in Table 3 using (6.1).
AR=
+A 2
(6.1)
AW = 0.004714, AL = 0.0824958
In simulating for mismatch effects for resistors, a Gaussian variable with a specific sigma was added to each resistor. For example, each resistor in the resistor ladders was given an extra value, whose value is determined randomly by a Gaussian variable of 0 mean and given sigma
(Figure 6.1). For a given sigma, the output was simulated 200 times and the average INL and
DNL values were extracted. Table 4 shows the results for the 1 resistor string 6-bit DAC. The average INL for 1 a (0.28%) is 0.018 LSB and average DNL is 0.0072 LSB.
Table 3: Resistor Matching
DAC resolution
6 bit (1 resistor string) 5 K
6 bit: Design #1 8 K
8 bit: Design #1
40 K
2 K
6 bit: Design #2
20 K
16 K
Resistor (A)
0.79
0.79
0.79
0.79
0.79
0.79
(x10-
3
)
L
(x10
3
) Mismatch
(1 sigma)
2.7
4.4
22
1.1
11
8.8
0.28
0.189
0.085
0.69
0.10
0.12
49

DAC resolution
8 bit: Design #2
Table 3: Resistor Matching
Resistor (Q) W (x10-
3
)
40 K
4 K
20 K
0.79
0.79
0.79
22
2.2
11
(x10
3
) Mismatch
(1 sigma)
0.085
0.35
0.10
-vCC del ta(R2 L§Q dol tn(R2
)
R delto(R R3
R delta(R4)
R.
dalta(R53R daltn(R6)
R
Lee
IF-out
Figure 6.1 Resistor string DAC with Mismatch Gaussian Delta Sources
0
0.1
0.5
1
5
10
0.28
R
Table 4: INL and DNL of 6-bit DAC-1 resistor string
AVG S.D. AVG S.D.
(INLMAX) (INLMAX) (DNLMAX) (DNLMJAX)
0.0053
0.0086
0.033
0.0563
0
0.0033
0.011
0.00032
0.0026
0.013
0
0.00043
0.002
0.305
0.617
0.018
0.0227
0.102
0.199
0.0062
0.0298
0.128
0.254
0.0072
0.00602
0.021
0.042
0.0012
50

0
0.1/0.1
0.1/1
0.1/10
0.5/1
0.5/5
0.5/10
1/0.1
1/1
1/5
5/1
5/5
10/10
0.085/0.189
CYRl /cR
2
(M
Table 5: INL and DNL of 6-bit DAC-Design #1
AVG S.D. AVG S.D.
(INLMAX) (INLMAX) (DNLMAX) (DNLMAX)
0.0061
0.020
0.0293
0.210
0.092
0.0143
0.229
0.181
0.1754
0.211
0.877
0.922
1.795
0.017
0
0.0087
0.0091
0.074
0.032
0.0418
0.080
0.077
0.065
0.070
0.360
0.390
0.726
0.0067
0.0011
0.010
0.019
0.163
0.051
0.0967
0.175
0.091
0.0945
0.125
0.459
0.500
1.012
0.0087
0
0.0069
0.0060
0.051
0.028
0.031
0.052
0.060
0.060
0.054
0.328
0.333
0.650
0.0053
Table 5 shows the resistor mismatch effects for the 2 string 6-bit DAC. Sigmas of different values were chosen for the first and second string to analyze the effects of varying degrees of mismatches. It is clear from the table above that mismatches in the first resistor string have a greater error effect than mismatches in the second resistor string. Thus, the resistors in the first resistor string must be more carefully matched. This is due to the fact that the resistors in the first resistor string control the higher order bits in the DAC. Similarly, Tables 6-8 show the resistor mismatch effects for 6-bit DAC Design #2, and 8-bit DACs (Design #1 and Design #2). The 1 cY mismatch
51

error is shown in the last row of each table. This was the value chosen for each DAC (68% of the yield will be under 1 a ). Table 5 shows that if the mismatch of R1 and R2 are maintained under
5 a , then the average INL error and the average DNL error are still small (less than 0.1 LSB).
Well over 99% of the yield will be within a 5 a mismatch.
Similarly, Tables 6-8 show that keeping the mismatch for the first resistor string small will minimize INL and DNL errors. Also, keeping the mismatches for both resistors less than 5 a will produce small errors in the circuit for all these designs (INL/DNL less than 1/2 LSB). Thus, it can be concluded that most (over 99%) of the yield will have small INL and DNL errors.
52

----------
7-
------- ---------- -------------------
----------- ---------- ----------
----------
----------------------- ----------
----------- ----------- ----------
----------------------- ----------
---------------------
----------- ---------
----------- ---------
----------- ---------
----------- ---------
-4 ---------- -
----------- --------
-----------------------------------
----------
----------
----------
------------ ---------- ---------
----------- ---------- ---------
----------- ---------- ---------
----------- ----------- ---------
------------ ---------- ---------
------------ ---------- ---------
- ---------
----------
---------- --------- - ---------
---------- --------- - ---------
---------- --------- - ---------
--------- - ---------
--------- --------- - ---------
--------- --------- - ---------
--------- --------- - ---------
--------- --------- - ---------
---------- --------
----------
------------- ----------- ---------- --------------------------------------------------------- ---------- ----------- ---------- -------
---------- ---------------------- ---------------------- ----------- ---------- ----------- ---------- ----------- ---------- -------
I ---------- ----------- ---------- ----------- ---------- ----------- ----------
I ------------ ----------
---------- ----------- ---------- ----------- ---------- ----------- ---------- ----------- ---------- ----------- ---------- -------
----------- ------------ L ------------ ------------- --
------------ ----------i r ------
4 ----------- ------------------------------- ----------- ---------- ----------- ---------- -------
------------- 4 ----------: -----------
----------- ---------- -------
------------------------------
I
------
----------
1
---------------------- --------------------------------- -------
---- ---------------------- ---------------------- ----------------------------
---
---------- ---------- ----------- ---------------------------------------------------------------------------------------
--------------------- ----------- ---------- ----------- -----------------------------------------------------------------
I ------------- L ---------- ----------- ---------- ----------- ----------
------------ ------------------------------------------------- r ------------ r ---
---------- ----------- ---------- ----------- ---------- ----------- ---------- ----------- ---------- -------
-------
----------- ---------- ----------- ----------
4 -------------
--- ---------I I ---------I --------- 7 ------
------- --------- -------------- -----------
-------
I
------- --- ---------
----------- ---------- ----------- ---------- -------
- --------------------- -----------
------- -------------- ----------- ---------- ----------- ------------------------------------------
------- --- ---------- ----------- ----------------------------------------------------------------
-------- -------------- --
------- - 4- ... ------Ir ---------- 11 ------ --11
------- -4- r ------------- --- -----------
I
I
---
---4 -------
!
---
C3 D U ---
-
----
------------ -------
I
------ -----------------------
--- -------
-----------
I ----------- I ---------
--I --------I -- ---------I I I ---i
----------------------------------------- ----------- ---------- ---------
---------- ---------- ---------- -------------------- ---------- ---------- ---------- ---------- ---------- ---------- ----------
---------- --------- ------------------- ---------- ---------- ------------------ -------4 ------
----------------------------------a 0 ---------------------- ------------------- ---------- ---------- --------
---------- ---------- ----------
----------
--------------------- ---------
---------- ---------- ----------
---------- ---------- ---------- --------
I ----------- ----------
---------------- ---
------ -------------
---------- ---------- --------------------
----------- ---------- -------------------t --------I --------I ----------I
---------- ---------- ----------
--------------------------------
3- 93 ---------- -----------------------
:3L 15 ---------- ---------- ----------
---------- ---------- ----------
---------- ---------- ---------a_ 0 ---------- ---------- ----------
------------- -------- ---- ---- ---- ------- ----- ------ ---- - ---- ---- --- -------- -------- -------- --- -------- --- -------- ----- -
--------- ---------- -
- ---------- ---------------------------------------------------------------------------------------
--------- ---------- ---------- - ---------- --------- ---------- ---------- ---------- ---------- ---------- ---------- ----------
--------- - -------- ---------- - ---------- -------------------I -- I
-------- - -------- ---------------------T ------------ ----------4- 4 ---------4 ----------4-
-------- - -------- - -------- - ---------- --------- ---------- ---------- ---------- --------- --------------------------------I
-------- - -------- - ----------------- ---------- ---------I ---------I ---- ---------I -
-------- - -------- - -------- ------------------------- ----------------- --- -------------------------------IE3:
---------- ---------- ----------
.S ---------- ---------
-------- - -------- - -------- --------- -------- --------- ---------- ---------- ---------- ---------- ----------
----------
---------- ---------- --------
--------------------- --------
-------- - -------- - --------
--------- -------- --------- --------
------- ---------- --------------------- ----------
-------- - -------- -------- -------- -------- --------- --------
-----------
A -- , S S -.5 ,
.
-7
-3---Z
-7 S a a -
.
5? SO - .
3- 0 2. 0 - S 3- 3- 1- 3- - 5 3- M
Figure 6.3 Histogram of INL and DNL Error for 200 Simulations
This simulation was run for the 6 bit DAC (Design #1). This particular simulation had sigma for
RI of 0.085% and sigma for R2 of 0.189%.
53

CR / CR
2
(
0
0.1/0.1
0.1/1
0.1/10
0.5/1
0.5/5
0.5/10
1/0.1
1/1
1/5
5/1
5/5
10/10
0.085/0.12
Table 6: INL and DNL of 6-bit DAC-Design #2
AVG S.D. AVG S.D.
(INLMAX) (INLMAX) (DNLMAX) (DNLMAX)
0.215
0.260
1.117
1.079
2.15
0.0187
0.0064
0.0215
0.035
0.255
0.114
0.166
0.279
0.208
0
0.0099
0.012
0.092
0.049
0.053
0.099
0.085
0.10
0.0965
0.55
0.515
1.06
0.0084
0.00275
0.0177
0.026
0.167
0.093
0.122
0.189
0.183
0.191
0.197
0.99
0.93
1.76
0.0151
0
0.0137
0.013
0.049
0.068
0.047
0.059
0.127
0.144
0.126
0.724
0.67
1.36
0.0116
Table 7: INL and DNL of 8-bit DAC-Design #1
0
0.1/0.1
0.1/0.5
0.1/5
0.5/1
0.5/5
CYR1/CYR2
AVG S.D.
R1R (INLMAX) (INL__MAX)
0.039
0.073
0.072
0.187
0.287
0.340
0
0.0197
0.020
0.057
0.102
0.095
AVG S.D.
(DNLMAX) (DNLMAX)
0.042
0.045
0.441
0.107
0.098
0.139
0
0.0186
0.0194
0.026
0.067
0.055
54

aRI/CTR
2 R
1/0.1
1/0.5
1/1
1/5
5/1
5/5
10/10
0.10/0.69
Table 7: INL and DNL of 8-bit DAC-Design #1
AVG S.D. AVG
(INLMAX) (INLMAX) (DNLMAX)
S.D.
(DNLMAX)
0.55
0.54
0.57164
0.586
2.737
2.813
5.421
0.076
0.194
0.19
0.213
0.183
1.051
0.98
2.15
0.0197
0.18
0.19
0.207
0.213
1.004
1.048
1.96
0.0462
0.12
0.134
0.138
0.128
0.677
0.69
1.64
0.0209
Table 8: INL and DNL of 8-bit DAC-Design #2
CYRI'/ R2
(9AVG S.D. AVG
(INLMAX) (INLMAX) (DNLMAX)
0
0.1/0.1
0.1/0.5
0.1/5
0.5/1
0.5/5
1/0.1
1/0.5
1/1
1/5
5/1
5/5
10/10
0.10/0.35
0.0217
0.066
0.067
0.206
0.313
0.375
0.599
0.610
0.587
0.645
3.097
3.038
5.99
0.065
0
0.024
0.021
0.071
0.117
0.116
0.225
0.230
0.200
0.225
1.205
1.111
2.245
0.022
0.012
0.040
0.038
0.106
0.179
0.198
0.371
0.369
0.355
0.379
1.922
1.834
3.830
0.039
S.D.
(DNLMAX)
0.17
0.262
0.264
0.258
0.244
1.401
1.312
2.760
0.026
0
0.027
0.026
0.025
0.135
55

6.2 Vbe Mismatch
In the buffer amplifiers of the two stage DACs, Vbe mismatches may create significant offset errors (these mismatches come from transistor mismatches during fabrication). Figure 6.4
shows that this mismatch effect can be modeled by placing the Gaussian variable at the base of the input transistor (QI). Ideally, the output voltage (vout) would follow the input voltage in unity gain feedback, but in the case where the vm is added, the output voltage will follow the input voltage minus the vm variable. For the forgoing analysis, Vm is taken to be 0 mean with standard deviation of 500 pV.
vin
Vm
4z + vout yind
Figure 6.4 Vbe Mismatch for input of Op-Amp
Vm is the Gaussian Vbe mismatch variable
Table 9 shows the results from the simulations of various DAC designs. Each DAC was simulated with and without resistor mismatches when Vbe mismatch was present. The effect of adding resistor mismatches along with Vbe mismatches to the circuit increases the INL error but does not affect average DNL error. A 500 mV mismatch approximately corresponds to 0.016
56

LSB error for the 6-bit DAC and 0.064 LSB error for 8-bit DAC. But these approximations do not take into account the internal input offset errors discussed in the previous section. Because the
INL and DNL are not significantly affected by the aVbe error, the yield implications are the same as described in the previous section (more than 99% of the yield will have INL and DNL less than
1/2 LSB).
albe = 500 "V
6bit
2 string, 1 way current
GR IaR2
0
6bit
2 string, 1 way current aRI = .085% aR2= .189%
6bit
2 string, 2 way current
aRI =UR2 =0
6bit
2 string, 2 way current
URI = .085% aR2 =.12%
8bit
1 way current aR =UR2
0
8bit
1 way current
CR I= 0.10% aR2 = 0.69%
Table 9: INL and DNL with Vbe mismatch
AVG S.D. AVG S.D.
(INLMAX) (INLMAX) (DNLMAX) (DNLMAX)
0.0175 0.0093 0.018 0.0120
0.0227
0.044
0.048
0.0716
0.0966
0.0095
0.0291
0.0297
0.0498
0.0397
0.018
0.0558
0.0607
0.0711
0.071
0.0126
0.0387
0.0395
0.054
0.050
57

Vbe
8bit
2 way current aYRl-a R
2
=0
8bit
2 way current
aRI = 0.10%
GR
2
= 0.35% v
Table 9: INL and DNL with Vbe mismatch
0(INLMAX)
AVG
0.119
0.1423
S.D. AVG S.D.
(INLMAX) (DNLMAX) (DNLMAX)
0.082 0.132 0.0955
0.0794 0.142 0.100
58

7.1 Noise Contributions
In designing a DAC, noise needs to be kept small so that the noise referred to the output will have minimal affect on the actual desired value. The word "small" is in comparison to the
LSB of the DAC. In the voltage switching design, most of the noise contribution at the output comes from the resistor strings, the NJFETs and the three operational amplifiers. The rest of the circuitry does not contribute much in terms of noise because they are in the form of ECL with differential voltage of 0.3 V.
Noise contribution for a resistor is mainly from the thermal noise. It's spectral density function is given by:
V(f) = 4kTR (7.1)
For resistor values in the range of 8K to 40K, the root spectral density ranges from
11.5 nV to 25.7 nV
. When considering these thermal noise contributions at the output, one needs to keep in mind that maximum noise contribution will be when the equivalent resistance seen at the input of the op-amp (in Figure 7.1) is greatest. The maximum equivalent resistance for a resistor string will be at midscale (when switch 3 is on) if all the resistor values were equal.
59

R1 ni
R2 n2
R3 n-3
R4
VCC
1
2
3
R5 n,5
R6 n6
5
6 v out
Figure 7.1 Noise Sources from Resistors
The switches in Figure 7.1 may also contribute to some noise at the output. A major source of noise is due to the fact that the channel in a FET (JFET or MOSFET) is resistive and thus exhibits thermal noise [Gray, 1993]. There is also a flicker noise contribution due to the drain-source current generator. When Vds < Vdsat (where Vdsat is the drain to source saturation voltage), these noise sources can be combined in the following equation:
2 4 742~ id(f) = 4kT
~
+
Vds
2Vdsat) (7.2)
Also, the shot noise due to gate leakage current can be represented by the following equation: i (f) = 2qI (7.3)
Because ID and IG are very small (ID is the base current of npn transistor input to the opamp on the order of 0.5 mA/$), the flicker noise and the gate shot noise are negligible. To calculate the contribution of the thermal noise, gm needs to be calculated. If the gn of the "on" FET device is small, then we can also ignore the thermal noise contribution. Because the device is
60

operating in the triode region when turned on, the gm is very small and thus, the thermal noise can be ignored.. The largest noise contribution from the FET will come from the gds term in (7.2).
From the simulation, gds for the "on" transistor was about 0.00052/. Given this value, 4kT(2/3 x gds) x (1.5 Vds/Vdsat) = 8.6 x 10-24 A
2
/Hz. Taking the square root of this value, we get for the noise contribution approximation: id(f) = 2.94 pA/ A/Jz .
In a bipolar transistor, noise contribution comes from the shot noise of the collector and base currents, the flicker noise of the base current, and the thermal noise of the base resistance
[Johns, 1997]. These are all modeled by (7.4) and (7.5).
V (f)= 4kT rb + (7.4)
The rb term refers to the thermal noise of the base resistance and the gm term is the input referred collector-current shot noise.
2 ~
Ii(f) = 2q(IB/+
KIB
B
I
C (7.5)
01
Iilf)
Figure 7.2 Noise Source Modeling for BJT
The 2qIB term refers to the base current shot noise, the KIB/f term refers to the flicker noise of base current and the IC term referred to the input referred collector current shot noise.
61

R
In-
Vn
+
Vn1( f]
Figure 7.3 Noise Source Modeling for Op-Amp
An Op-Amp needs three noise sources to model all the noise components [Johns 1997] as shown above in Figure 7.3. With a unity gain feedback, figure shows that:
V 2(f) = I (f)xR+ V2(f) (7.6)
Because of the unity gain feedback, the noise seen at the input is directly referred to the output.
The noise due to the In_ sources has no contribution to the output noise voltage because there is no feedback resistance. In order to find the values of Vn and In+, Figure 7.4 shows where the noise sources are in the op-amp architecture.
Vn1
I
03
In3
In4
Vns vrn 0
Vn2
Vout
In2
Vee
Figure 7.4 Noise Sources in the Op-Amp Architecture
62

The figure above will be used only as an approximation to get the first order value for the output referred noise. In reality, one would need to consider also the noise source of the current I but this value is usually small compared to the other noise sources [Johns, 1997]. First, the gain from each source needs to be found.
Vout
Vn1 out = gm1RO
Vn2
(7.7)
For V.
3 and V.
4
, the gain is dependent on the trans conductance of Q3. This is because in small signal, the Vn's approximately become the Vbe of Q3 and Q4 and give those transistors a non-zero small signal base to emitter voltage. Thus, the gain is the transconductance times the output resistance.
Vout Vout = gm
3
R
0 (7.8)
First, lets consider only the voltage noise sources seen in Figure 7.4. Assuming gm, = m2 and gm3 = gm
4
, (7.9) can be approximated as the output referred noise without the unity gain feedback.
)= 2(g
1
R
0
)
2 V
1
(f) + 2(gm
3
R)
2
V
2
3
(f) (7.9)
Referring the output noise back to the input, we divide by the gain which results in
V 2(f) = 2V
1
(f)+2V2 2
With the unity gain feedback, this input referred noise is also the output referred voltage noise.
Now, consider all the current noise sources seen in Figure 7.4. We can ignore In, because the value of 2q IP + C
2
1001 is very small. Even if we multiply this noise current by the input
63

resistance, the value is much smaller than Vn 2
(f). In other words, we can estimate Vno 2
(f) to be
Vn
2
(f) in equation (7.6), because In+ 2
(f) x R << Vn
2
(f). In3 and In4 can also be ignored because they create a Vbe for Q
3 and Q
4 of about In3 x 1/gm3, which is negligible when compared to Vn3-
The final noise source not yet considered, In2, becomes the In- source seen in Figure 7.3. Thus, n )= I,
2
(f)
(7.11)
It is useful to approximate these output referred noise values to get a sense of what the result of the simulations should return. So, considering the Vn sources, at low frequencies, the noise of one noise source would be approximately 21 nV/root(Hz) ignoring base resistance and using IC = 0.5 uA. Thus, Vnout(f) is approximately 41.3 nV/root(Hz) for one op-amp when considering only the voltage noise sources. When considering the noise due to the current noise source, we will ignore the flicker noise. If we are in the frequency range where 0 (f) is approximately constant (P c(f)/f(t) << 1), then we have 12(f) = 2q Ip + _
C
whose value is very
I IoI small value at low currents.
Output referred noise increases when $(f) decreases as shown in the current gain equation
=
1 + f f T
(7.12)
The cutoff frequency of 0 (f) is f = fT/Po. A common value for fT for the process being used is approximately 200 MHz at the appropriate low current levels. With I
of about 120, the cutoff frequency becomes about 1.7 MHz. As Figures 7.6-7.8 show, the output referred noise increases at about that frequency. But, we also see a drop at about 50 MIEIz. This drop is due to the fre-
64

quency response of the unity gain feedback amplifier.
7.2 Frequency Response Analysis
The gain of the amplifier is about gm1R
0 where R
0 is the parallel resistance of the output resistance of Q2 and Q4 (Figure 7.4). The dominant node with the greatest time constant (when multiplying the resistance at the node and the capacitance) is the high impedance node, which is labeled node 4. Thus, the dominant time constant is about ROCout- The unity gain frequency is then approximately gm,/Cout- Cout is simply the summation of the Ces capacitances of Q2 and Q4
(CCs capacitances are the dominant capacitances at node 4). Given CCs of about 15 fF and gm
1
=
1.9x1OA-5/ohm, the unity gain -3 dB frequency of the op-amp becomes approximately 100 MHz.
Figure 7.5 shows the -3 dB frequency to be about 70 MHz. Thus, the noise should be cut off at about this frequency in the simulation.
7.3 Noise Division in Resistor String
Figures 7.6-7.8 show three different plots of output referred noise for different input codes. The output referred noise will slightly depend on which switch in "on" in the second resistor string. Consider the case when switch 24 is "on" (from Figure 4.2), then the noise from Amp2
(AV
2
) will be directly fed into the output buffer. If switch 20 is "on", then the noise from Amp1
(AV
1
) and Amp2 will get divided along the resistor string and will produce an output referred noise that is smaller than the noise seen at the output of each amplifier. In other words, switch 23 will see A V
2
+ 1(AVI A V
2
) of the error, switch 22 will see A V
2
+ 2(AV
-
A V
2
), switch 21 will see A V
2
3
+ 3(AVI A V
2
), and so on until switch 17 sees A V
2
7
+ 7(AVI A V2). From section 6.2, if AV
1
=500gV and A V
2
=-500gV, then the maximum error from the Op-Amp is 500gV
65

at switch 24 which is 0.64 LSB.
3- ----------- ------------
----------- -------
-----------
S ----------- -------
---------------------------
-7
-----------
-----------
----------- -------
-------------------
----------I -------
----------- ------
----------- ------
T
--- - - - - - - - - - - - -- - - - - - - -- - - - - --- - -
----------- ------
.
----------- I -------
-------------------------------
-------------------------------------------- ----------------------------------- ---------- --------------------------
--------- -- ------ -j ------ j L -----'- ---------------- ---L
----- -- --- -- - ---- -- ----------- - ------ ------
Y T -------------------------------
4- - 4-
----------- ------
-------------------
-------------------
------------ ------
I ------ I I
-I.-,.-, ------------- -- ----
------------ -- ----
---------------- ------------ --- ----- -
-------------------
11
----------- ------ .
------------ r ------ T --- T 1. r .
-------------------------------- ----------- -------------------------- ---------------------- -------------------
------------ I
7-7-
------
----------- -------
-----------
----------- I T-1.
----------- ------
----------- ------- --------------------- --------------------- ----------
:3L Z3
- 3--a -----------
------------ I
3- C.
-3--7
------------
---------------
3- A
----------- I
I -------
---
T
------ I r ------ r ---- ............
----------- ------
-------------------- ------ 4-- --------
----------- 1. - --- I.- -- I
----------- ------- 1
------------ ------
------------ ----------------
---- ------- .........................
------ ----- ------
-------
-,r - r -----------
.............................
--------------------- r
T -------
------------------------------------------------
------------
3--S
------------------------------------ L - J- -L - I -------------- ------ 1- -l-
3- - -5
'r -1 , 1-1-- -
------------------------ --------------- r .................. ..........
4
I-L-L
I I I ---
------------ I
---------------
---------
3-
---------
------------
L ------
--------------
L
..........
-,L- Jj a- SO
Figure 7.5 Frequency response of Unity Gain Feedback Amplifier x-axis: Frequency, y-axis: dB
-L -7
7-1.-1-7-71 ------------ I
-7 E5 -------------------
----------- ------
----------------------
----------- ------
C) ----------------------------------------- ----------- ------
----------- ------
----------- ------
----------- -----------
---------------------------- ....... - , ----------- ------ ----------- ------
------- I -- ----- ------------------- ------------- ------
------------------
--------- 4-4 - -- -------- ------
------ ----------- ------ ---------------------
----------------------------------------
----------- ------
-------------------------
----------- ------ ------------- ------------ ------ ----------
--------------------------
T
----------- ------
------------------------------------ -
----------- ------ ---
.... ----------- ------ ----------- ------
------- ----
----------- ----------- --------- ---------------------------------
...................................
4 ........................
----------- ------------------------
.............................................. -,-4-T ----------- ------------------ -
-------------------------
4 4
------------------
----------- ------
-----------------------------
----------- ------ r
.......................... I ----
---
----------- 4 ---------------- ....... .......................... 4 4 ------ T
----------- 4 ----------------- i 4 --------- T ------------ ------- ---- 4-4-4-4-1 --------------
-4-4-4-4-4
4-4-4-4
------------------
I
----------- 4 ------ 4 ---- 4 ------ 4
------------ j ------ 4 ----
4 --- 4 ------ 4
----------- i ------ 4 i- f-4-4 f ------ I I ------
-4-4-1 ------------------
------- 4
1 -4-4-4- ----------- ' ------ 4 ----
---------------------------
.............
..... -4-4-i
------------- ------
------------------
------------------
----------- -----------
----------- ------ I
------------------------------------
---------------------- i
------- -------
-------------------
-----------
------------
--- ----------- f ------ i
------------------
------------------- --------
----------------------------------
....................... ........... ----------------------
------
---------------------------------
----------- I ------
..............................................
------------- ----------------
----------- ------
----------- ------
------------------
-------------------------
----------- ------
----------- ------
-----------
-------------------
----------- ------
----------- ------
----------- ------
---------
----------------------------
----------- ------
-------
----------- ------
----------- ------
-------------------------------------------
-
----------- ------
---------- ------
-----------------------------------------------------------
------------------
----------- ------
------ ---------
----------- ------ * ------------ ------- ------------ ------
----------- ------ ------
------------- ----------- ---------------------------
C> ------------------------ ---------
*
--------------------------------------------------------------------------------------------
------------------ -------------- ----------------- ----------- -------------------------------- ---------
------
---------------------------------
Figure 7.6 Output Noise with input = HIGH
From Figure 4.2, the "on" switch for this output for the second resistor ladder is switch 17. x-axis: Frequency, y-axis: V/Hz
66

E. -7 S
-------------------
------------------------
---------------------------------------
----------- ------
---------------------------------- ----------- ------- ........
------------------------------- ---------------------
-------------------
----------- ------
.............. ----------------------- ------ -------- ------------
S-7 S
----------- r ------
-------------------
T
----
E. M
----------- ------
S ---------------------------- -- so
----------- T ------ T---- -r--
----------- ------
----------------
----------- -----------------------
-------------
------
--------
I -------
---------- - ------
--------------------------------- r
----------- ------ ---------- * - -----
---------------------- --------- ------------------ -------------
-Q -7 S ----------- ------ ----------- ----------------------------
----------- ------
---------------------------
----------- ------ I ------- -------------- I
---------------------------------- L-L-L-L ------------- L --------
--------------------- -----------------------------------------------------------
-------------
-------- ------ ----------- --------
------------ ------
------------------
... ........ ---------------------------------
----------------- ------ ----- ------- j
-T T
-----------------------
------------
4
I
7 7 ----------I -
--------------------
J- I J ----------- ------
----------- ------
---------- - ------ ------- -.+ ------------------------------- -------------------------a -7
:2 -7
S ----------------------------- r-r-r
----------- ------
---------------------------
:3 0
----------- ------
----------- ------
------------------- r
-----------
----------- ------
----------------- ------
L -------
----------- -------
-------------- ------
-------------------------- 7 -----
---------- - ------ L --------
I
------
-------------------
----------------------------------------- ................ T ------
---------------------------- ------------------------------------------
-------------
- -------- ----------- ------
------------
--- ------------ ------ 1--t-1-1
----------- ------
----------- ------
-----------
-j.-.- ------------ -------
------ ---------------- -------
----------- ---------------------
-a M -----------------------
3--7
M 0
-----------------------
-----------
------
----------- ---------------
----------- ------
------------ ----- ----
---------- - ------
------
------ T-11-1
------------ ------
----------- ------
---------- ----------------------------------------------
-
I
------
-- ------- -------
3- S
----------- ------
I ------- ---------
-- T-- -T - ----------- ------ ---- --- --
----------- ------
----------- ------
----------- ------ ----
-- YTT ------------ ------
4---,4 ------------ ------ 4 ----
I ----
--------- 4 ------ 4
------------
3- - r.
------- L --- ----------------------------------- --------------------------------- ------------------------------------------
3- - IS 3--a
Figure 7.7 Output Noise when Input = NED
From Figure 4.2, the "on" switch in the second resistor string is switch 20.
x-axis: Frequency, y-axis: V/Hz
--------------------- T ------------------------------ ------------ ------- ------
. - 1.- -.11. -----------
------
I I - - -.1 - -.1 - 1.- -.1
------------ ------ ----
---------------------- ------------ T --- - -------------------------------a
E> -------------------------- ------------- ----------------- ------------ I I
E3 o ---------------------------- .............................................. ----------
-,-.L ----------
I ------
........ ...........
-------------------
---------- ----------- ------------ -------------------------
-7 ----------- ------
----------- ------ ----------- ------
-70 ----------- ------
4 ............ ----------- i ------ 4 --------
------------ ---------------------- - - ------------ ------ -------- -------------------- --
ES
-----------------------
------- r-.- ------------ ------ I L ---
------------- ------ I ----
----------- ------
----------- -- ------ ---- ---
- ----------------------- --
-----------
----------- j -----------
----------- ------
---------
-------------------------
----------- ------
----------- ------
-------------------------------- ------------------------------------ T---'.
---------- ------ -----------
---------- I
----------- ------
----------
4-
----
---------- -----------
-----------
-----------
---------- ------
-----------
-30
----------- ------ ---- ---
---------- ---------------
------------------
1- T ------------ ------
-------- --
T ------------ ------
------ -- - ------------ ------
----------- ------
--------------------------------
----------- -------- -1-
---------- -------
----------
1-1-6
---------- ----------------
-----------
------
....................
----------- ----- I --- 11 1-1-1-11-11-
-20
------------ ------- ------------ ------ ..........
-------------------
3- ------------- ----------- 4- 4- ----------- ------ ----------- ----------- --------
------------------
---------- ------
------------------------------------ --- -----
----------- ------ ------ I ------ ------------ ------
------------------- ----------------- -------
Figure 7.8 Output Noise when Input = LOW
From Figure 4.2, the "on" switch in the second resistor string is switch 24.
x-axis: Frequency, y-axis: V/Hz
67

High performance 6 and 8-bit DACs implemented in a high voltage complementary bipolar (HVCB) process were designed and simulated. These DACs may be useful in applications such as LCD drivers where high voltage power supplies are common. It's very low power dissipation, low INL/DNL, along with 2MHz bandwidth make these designs attractive for many applications.
The DACs were designed to have power dissipations of 750 pW or less on +/- 5 V power supplies. Glitch impulses were also minimized to less than 10 nV-s in the final design. One area of work may be continued is the circuit layout and parasitic effects of the circuit. Although the size of the circuit was considered in the design, one would need to lay out the circuit to see the actual die size. Also, parasitic capacitances may slow down the circuit, and those effects should be considered.
One area of interest may be to redesign this circuit in Bi-CMOS technology. The Decoder circuit, which consumes most of the power, could be redesigned in MOS so that it would dissipate much less power. The bipolar transistors can be still used for latch functions and op-amps (for high gain, speed and accuracy).
68

References
Analog-Digital Conversion Handbook, 3rd ed., D. H. Sheingold, Ed., Prentice-Hall, Englewood
Cliffs, New Jersey, 1986.
Analysis and Design of Analog Integrated Circuits, 3rd ed., Paul R. Gray and Robert G. Meyer,
John Wiley & Sons, Inc., New York, 1993.
Analog Integrated Circuit Design, David A. Johns and Ken Martin, John Wiley & Sons, Inc., New
York, 1997.
Kennedy, Michael Peter, "On the Robustness of R-2R Ladder DAC's," IEEE Trans. on Circuits
and Systems--Part I, vol. 47, pp. 109-116, February 2000.
Introduction to Junction Field-Effect Transistors, Sidney Soclof, Artech House, Norwood, MA,
1995.
Razavi, Behzad et. al., "Design Techniques for Low-Voltage High-Speed Digital Bipolar Circuits," IEEE Journal of Solid-State Circuits, vol. 29, pp. 332-339, March 1994.
Analog and switching circuit design: Using Integrated and Discrete Devices, Joseph Watson, A.
Hilger, Bristol, 1984.
69