Boise State University Electrical and Computer Engineering Department Instructor: Office: M

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Boise State University
Electrical and Computer Engineering Department
Course Syllabus for ECE 230L
Digital Systems Laboratory (1 semester credit hour)
Fall 2010
Instructor: Arlen Planting
Office: MET 227, Phone: (208) 426-4826, Email: [email protected]
Office Hours: Mon/Wed/Fri 2:30-3:30pm
Lab Assistants: James Hall, Andrew Landoch
Course Description:
Design, build, and test of small digital logic circuits using TTL gates, CMOS gates, flip-flops, registers,
counters, LED, infrared LEDs, and Xilinx Spartan 3 FPGA (XC3S200). Student is required to enroll in this
laboratory in the same semester with EE 230 Digital Systems.
Prerequisites: COMPSCI 117 or COMPSCI 125, Co-requisite: ECE230
Required text: No required text. Laboratory instructions are provided on course/laboratory webpage.
Laboratory Meeting Time:
Tuesday 9:15 AM to 11:55 AM
Laboratory Meeting Location:
Engineering/Tech Bldg 312 (ET 312)
Course/Laboratory Webpage: http://coen.boisestate.edu/smloo/ece230fall2010/
Laboratory Objectives:
After taking this laboratory, the students should be able to:
• Design and build the functions described by given specifications,
• Analyze and simulate the functions described by logic diagrams,
• Implement functions in logic gates (TTL and CMOS gates) and FPGA of given specifications,
• Develop circuits using combinational and sequential components, and
• Design, simulate, and implement state machine using Xilinx ISE, and BASYS 2 board.
Grading:
10 Laboratory Assignments/Reports 50%
Weekly Lab Quiz
10%
2 Hands-on Quizzes
20%
Final Project
20%
Grade determination: 100%-90% = A, 89%-80% = B, 79%-70% = C, 69%-60% = D, < 60% = F
Lab Quiz and Lab Report:
No pre-lab, but we will have weekly lab quiz. The Lab Report is a collaborative effort between you and your lab
partner. Reports are due by midnight on Friday of lab check-off.
Final Project:
See the course/laboratory website for project description. This project will not be completely defined. We will
go through a few negotiation sessions. You get to ask all the questions you want.
Schedule of Laboratory Assignments:
Week
1
Lab
0
Laboratory Topic
Details
Introduction
Xilinx ISE Tutorial
1
Basic and Tutorial: Introduction to
Digital Systems Laboratory
Introduction to discrete logic prototyping board, logic components,
and Xilinx ISE and ISE Simulator). Implement functions in logic
gates on discrete logic prototyping board with 7400 series chips.
3
2
Combinational Circuits: Universal
NAND
Build basic logic with just NAND and NOR. Design & Simulate
with Xilinx and ISE Simulator. Build circuits on Proto-Board with
7400 series chips.
4
3
Advanced Combinational Circuits: "Bad"
Logic Circuit Re-Design
Derive Boolean expression from existing circuit. Simplify output
equation. Re-design circuit of simplified equation.
5
4
Introduction to FPGA: Digilent BASYS 2
Work with busses and create custom chips.
6
5
Introduction to FPGA: Seven Segment
Display Driver
Derive Boolean expression from truth table. Design & Simulate in
Xilinx. Implement circuits and test their functionality with FPGA.
Adders & Subtracters: Arithmetic Unit
Modular Design. Design a 4-bit adder by using 1-bit full adder
modules. Build an adder/subtract unit with add/sub control bit.
Test on FPGA.
Lab Quiz #1
Derive: Truth Table, K-Map, Simplify Expressions, Design
Circuit, Timing Diagram/Simulation, Test on FPGA Platform.
2
7
6
8
9
5
Multiplexer, Encoder, Decoder:
Multiplexer and Decoders
Design simple MUXs & Decoders with logic gates. Implement
certain Boolean Expressions with MUXs and decoders.
10
6
Adders & Multipliers: Yet Another
Arithmetic Unit
Design 4-bit fast adders & multipliers. Multiplex signals from
multiple sources into one common data bus.
11
7
Verilog, Latches & Flip Flops: Verilog
& Simple "Memory" Circuit
Design a logic circuit using Verilog instead of Schematic Capture
in Xilinx. Understand/show the differences between latch and flipflop.
12
8
Counters: Latch, Flip-Flop, Up-Down
Counter
Design a 4-bit up-down counter and download the design to FPGA
9
Finite State Machines: Sequence
Detector
Design a state-machine sequence detector. Show state diagram,
state table and assignment table, K-maps, equations, logic circuit,
download design to FPGA.
14
Lab Quiz #2
Design a state-machine sequence detector. Show state diagram,
state table and assignment table, K-maps, equations, logic
circuit, download design to FPGA.
15
Final Project
Details given in lab
13
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