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IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 11, NO. 2, JUNE 2011
An Interactive Simulation Tool for Complex
Multilayer Dielectric Devices
Richard G. Southwick, III, Member, IEEE, Aaron Sup, Amit Jain, and
William B. Knowlton, Senior Member, IEEE
Abstract—Novel devices incorporating multiple layers of new
materials increase the complexity of device structures, particularly in field-effect transistors, capacitors, and nonvolatile memory
(NVM). The mounting complexity of these devices increases the
difficulty of generating energy band diagrams and performing
device parameter calculations whether these calculations are done
by hand, using spreadsheets, or via mathematical programs. Although finite-element Poisson–Schrodinger equation solvers are
available to perform the calculations, the cost and time spent
learning them can be a hindrance. A straightforward GUI interactive simulation tool is presented that quickly calculates and
displays energy bands, electric fields, potentials, and charge distributions for 1-D metal–multilayered-dielectrics–semiconductor
stacks. Fixed charge can be inserted into dielectric layers. The
freeware program calculates device parameters, (e.g., effective
oxide thickness, flat-band voltage (VFB ), threshold voltage (Vt ),
stack capacitance) and layer parameters (e.g., capacitance, potential, electric field, tunneling distance). Calculated data can be
exported. Using the simulation tool, trap-based flash NVM is
examined. Device performance characteristics such as the Vt and
VFB shifts of three different stacks are examined. Comparisons
between the program and a finite-element Poisson–Schrodinger
equation solver are performed to validate the program’s accuracy.
Index Terms—Energy band, high-κ dielectric, metal–oxide–
semiconductor (MOS) devices, simulation.
I. I NTRODUCTION
E
NERGY BAND diagrams have long been employed to
explain solid state principles and to understand device
behavior, including metal–oxide–semiconductor (MOS) structures. Energy band diagrams are essential for visualizing MOS
device operating regimes (i.e., inversion, depletion, and accumulation) and carrier transport mechanisms (e.g., hot carrier,
Manuscript received January 3, 2011; accepted February 2, 2011. Date
of publication March 17, 2011; date of current version June 15, 2011. This
work is supported in part by the Idaho SBoE-HERC and the Micron Ph.D.
Fellowship.
R. G. Southwick, III was with Boise State University, Boise, ID 83725
USA. He is now with the Semiconductor Electronics Division, National Institute of Standards and Technology, Gaithersburg, MD 20899 USA (e-mail:
Richard.Southwick@nist.gov).
A. Sup is with the Department of Physics, Boise State University, Boise ID
83725 USA (e-mail: AaronSup@u.boisestate.edu).
A. Jain is with the Department of Computer Science, Boise State University,
Boise ID 83725 USA (e-mail: amit@cs.boisestate.edu).
W. B. Knowlton is with the Departments of Electrical and Computer Engineering and Materials Science and Engineering, Boise State University, Boise,
ID 83725 USA (e-mail: bknowlton@boisestate.edu).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TDMR.2011.2129593
Fowler–Nordheim tunneling (FNT), direct tunneling (DT), etc.)
as well as complex device behavior such as anode hole injection
[1], [2], fast transient charge trapping [3], charge pumping [4],
photon stimulated current [5], and dipole formation in high
dielectric constant (κ) materials [6].
Many device parameters can also be extracted from accurately constructed energy band diagrams. The parameters
include the flat-band voltage (VFB ), threshold voltage (Vt ), and
electric field, which is useful in calculating FNT [7], [8], Poole–
Frenkel transport [9], [10], and Schottky emission [8], [11].
Unfortunately, despite the utility of energy band diagrams,
their accurate construction is time consuming and tedious. The
complexity of energy band diagrams in modern MOS devices
is further escalated by the recent introduction of multilayer
dielectrics. MOS multilayer dielectric devices include highκ oxides in MOS devices [12] and trap-based flash (TBF)
nonvolatile memory (NVM) devices [13], such as SONOS [14]
and TANOS [15], that incorporate trapped charge within the
multilayer dielectric stack. For these complex devices, creating
an accurate energy band diagram is quite challenging, particularly over a range of applied voltages.
Device structure parameter calculations can be performed by
hand, using spreadsheets, using mathematical programs (e.g.,
Matlab and Mathematica), or with Poisson–Schrodinger equation solvers (PSESs), which utilize finite-element approaches.
Parameter calculations performed by hand may be quick and
useful but typically employ simplifying assumptions such as
equating the surface potential of the semiconductor to twice
the body doping potential for inversion. Hand calculations are
rarely used to compute device parameters or generate energy
band diagrams of multilayer dielectric MOS devices due to their
complexity. Therefore, a quick visual method to understand
these devices is not available. While using spreadsheets or
mathematical programs for complex modeling is an improvement over hand calculations, programming and implementation
can be challenging and time consuming. Assuming that the
program accurately calculates device parameters for a MOS
structure, changing the existing calculations from a single
dielectric system to a more complex system, e.g., a threedielectric-layer system, requires additional nontrivial programming. Furthermore, spreadsheets or mathematical programs
require supplementary work to provide a specific customized
GUI for ease of use. Conversely, extremely powerful finiteelement PSESs are available to perform many device parameter
calculations and to graphically represent a variety of device
structures. However, the cost of software licenses and the effort
required to learn the program interface are substantial. Hence,
1530-4388/$26.00 © 2011 IEEE
SOUTHWICK et al.: SIMULATION TOOL FOR COMPLEX MULTILAYER DIELECTRIC DEVICES
these challenges leave many engineers and scientists without
the ability to easily and quickly calculate device parameters
or visualize the energy, electric field, or charge distributions of
multilayer dielectric device structures.
To address this dilemma, software was developed that swiftly
and readily visualizes energy band diagrams for dual-layer
high-κ dielectrics on semiconductors with the ability to calculate voltages, electric fields, and capacitances as a function of
applied voltages [16]. The approach is unique in that it does
not rely on purely numerical techniques, such as finite-element
PSESs, but rather an iterative approach based on the underlying
physics. The software is freely available to the public [17]. The
authors know of no other software with equivalent capabilities,
simplicity, speed, and cost (free).
Despite the success of providing engineers and scientists
with a platform to easily analyze the energy band structure
of dual layer dielectric MOS stacks, the energy band structure
of more complex designs could not be addressed using such
a quick method. This paper details a new approach to solving the energy band structure of MOS gate stacks composed
of an arbitrary number of dielectrics and metal films using
analytical equations (i.e., not finite-element equations). The
models support the arbitrary placement of floating metal layers
in the dielectric stack as well as trap charge. The incorporation
of multiple dielectric layers as well as trapped charge makes
the model well suited to analyze TBF NVM devices. Using
the proposed model, this paper illustrates various performance
tradeoffs of TBF NVM using various high-κ dielectrics.
237
where φboundary is the potential at the boundary of the dielectric of interest and xj is the location of the jth line charge.
Using the potential, the energy band is easily calculated by
applying the appropriate electron affinities and band gaps.
Equations (1) and (2) are applicable at any location inside
the dielectric and are not limited to a specified line charge. For
a metal, the electric field is assumed to be zero, and hence,
the potential does not change. Charge can be placed in the
metal, and although this will not change the electric field or
potential drop in the metal, its effects will be felt through charge
neutrality. A semiconductor can be placed at the bottom of the
stack, and the equations used for solving the charge, electric
field, and potential of the semiconductor are taken from [18].
Using [18], the potential drop in the semiconductor (surface
potential ψs ) for a given charge is given by
QC = ∓ 2qκs NA
· φt e−ψs /φt + ψs − φt + e−2φF /φt (φt eψs /φt − ψs − φt )
(3)
where Qc , q, NA , φt , and φF are the semiconductor charge
per unit area, electron charge, doping concentration, thermal
voltage, and semiconductor body doping potential, respectively.
To obtain the potential drop in the semiconductor as a function
of distance (x), the integral of the inverse of the electric field
yields the distance as follows [18]:
ψs
II. M ODEL
1
E(ψ̂)
dψ̂ = x − xsurface
(4)
ψ(x)
The simulation program implements a modular approach to
calculate the charge, electric field, potential, and energy of a
structure composed of metals, dielectrics, and a semiconductor.
In this approach, the 1-D Poisson’s equation is solved for each
material independently when given a starting charge and potential. For each dielectric, an arbitrary number of line charges can
be inserted within the material. Following Poisson’s equation,
the electric field (E) in the dielectric at a given line charge (j)
is given by
j
1
(1)
ρj
ρtotal +
Ej =
κ
0
where ρtotal is the sum of the charge in the structure up to
the interface of the dielectric of interest and ρj is the jth line
charge in the said dielectric. After the electric field is calculated, the potential (φ) can then be calculated at a given line
charge by
φj = φboundary +
j
1
E(ψ) = ±
−Ej−1 (xj − xj−1 )
(2)
where E(ψ) is the electric field of the semiconductor as a
function of potential and is calculated by (5) shown at the
bottom of the page [18].
Using (3)–(5), the potential, charge, and electric field in
the semiconductor can be calculated. The potential of the
entire stack is solved by choosing a starting gate charge and
determining if the resultant potential matches the desired input
voltage. A solution is obtained using this iterative approach.
The result of the analytical algorithm built into the program and
the assumptions described in Table I provides quick calculation
speeds.
The simulation program also supports a geometrically calculated tunneling distance. The tunneling distance, useful for
determining the FNT distance or DT distance for a specified
applied bias and the transition from DT to FNT as a function of
applied bias, is calculated using the resultant energy barriers.
The approach to determine the tunneling distance is only a
first-order approximation; however, it is of practical value. The
tunneling distance is calculated through a given dielectric layer
from an adjacent layer’s conduction band (CB) or valence band
√
2qκs NA
· φt e−ψ(x)/φt + ψ(x) − φt + e−2φF /φt φt eψ(x)/φt − ψ(x) − φt
κs
(5)
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IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 11, NO. 2, JUNE 2011
TABLE I
SIMULATION TOOL ASSUMPTIONS
(VB) into its own CB or VB or into another adjacent layer’s CB
or VB.
The simulation tool provides the user with the ability to
change any of the material parameters used in the model to
increase accuracy. Interfacial layers, common in high-κ dielectrics, can be simulated by adding additional layers, permitting further refinement to the simulation. An unlimited
amount of fixed sheet charge can be added to any dielectric to
simulate trapped fixed charge. The simulation tool also supports
temperature-dependent energy band gaps and intrinsic carrier
concentrations of semiconductors. An electric-field-dependent
dielectric constant is also supported for potential use in MOS
ferroelectric devices [19]. For further refinement of the model
itself, the source code for the program is available upon request
and is released under the GNU public license version 2.
With these capabilities, complex metal–insulator–
semiconductor devices whose configurations can include
m − Ij − X, M − Ii − M − Ij − X, and M − Ii − (M −
I)j − X, where m and I signify metal and insulator, i and j are
integer numbers, and X denotes a metal or a semiconductor,
can be readily examined and exported for further investigation.
III. A NALYZING N OVEL D EVICES AND DATA
Using the simulation tool, examples of TBF NVM dielectric
stacks were examined in a variety of ways. TBF NVM devices
incorporate three or more dielectrics into the gate stack such as
metal–SiO2 –Si3 N4 –SiO2 –Si (i.e., SONOS) and SONOS-like
devices [13], [14]. The basic operational principle in a typical
three-dielectric-layer TBF NVM is that, upon the application of
a bias, charge is injected through a thin dielectric tunnel layer
(TL) into a charge trapping layer (CTL) that incorporates the
smallest energy band gap of the three dielectrics. The smaller
energy band gap between two larger energy band gaps provides
a deep “well” to help confine the charge. The charge is then
trapped in discrete point defects in the CTL. The charge is
inhibited from escaping the CTL by both the defects and a
blocking dielectric layer (BL) that incorporates a larger energy
band gap than the CTL. Additional dielectric layers can be
integrated into the dielectric stack to augment the performance
of the TL, CTL, and/or BL. In the following paragraphs, the
results of employing the simulation tool to understand the
physics of operation for TBF NVM devices are presented.
The dielectric stacks examined are TiN–SiO2 –Si3 N4 –SiO2 –
pSi (stack 1), TiN–Al2 O3 –Ta2 O5 –HfO2 –pSi (stack 2), and
Fig. 1.
EOT, Vt , and Coxide for each stack for a 10-V applied bias.
TiN–La2 O3 –ZnO–ZrO2 –pSi (stack 3). Note that the dielectric
adjacent to the metal is the BL, the dielectric adjacent to the
Si is the TL, and the dielectric imbedded between the BL
and the TL is the CTL. Both the metal electrode (TiN) and
the p-Si doping (1 × 1018 cm−3 ) are held constant so that
the three dielectric layer stacks can be directly compared. The
thicknesses (tox ) of the TL, CTL, and BL are 2, 6, and 10
nm, respectively, which are similar to that of the TBF NVM
currently described in the literature [20]–[26]. The stacks were
chosen to provide variance in the material parameters, including
the band gap, κ, and electron affinity. The first dielectric stack
(stack 1) is a SONOS stack, and the second stack (stack 2)
incorporates higher κ layers than the SONOS stack, while the
third stack (stack 3) incorporates a CTL with a deeper well
(i.e., larger electron affinity or larger energy band offsets) and a
BL with a higher κ. Several of the material parameters and the
capacitances for each dielectric stack are shown in Fig. 1.
A. Dielectric Stack and Layer Parameters
Since a TBF NVM device is a charge storage device, it can be
thought of as an enhanced capacitor. Several metrics that can be
used to assess TBF NVM are effective oxide thickness (EOT),
Vt , and Cox . EOT and Cox are essentially inversely proportional
to one another. For capacitive devices, a large Cox and a small
EOT are desirable. To the first order, the lower the voltage used
to turn on the device, the lower the power required to turn
on the device, which is attractive for low-power applications.
Hence, a small Vt is appealing. These metrics are plotted for
each dielectric stack in Fig. 1. The plot shows that these metrics
are the least desirable for the SONOS stack (stack 1) and are the
most desirable for stack 3.
Fig. 1 shows that Cox for stack 3 is greater than that for
stack 2, yet the average of each stack’s κ’s is nearly identical.
To provide some insight into this observation, Fig. 2 may be
utilized. Fig. 2 shows layer parameters and the capacitance of
each layer. The layers are organized according to TL, CTL,
or BL. The smallest capacitance will dominate the total oxide
capacitance since the layers are in series. The smallest capacitance is dictated by both the layer with the lowest κ and that
with the largest thickness. The layers with the smallest κ in
SOUTHWICK et al.: SIMULATION TOOL FOR COMPLEX MULTILAYER DIELECTRIC DEVICES
Fig. 2. Material parameters and capacitance of the dielectric layers used in
the dielectric stacks arranged relative to BL, CTL, and TL.
Fig. 3. Energy band diagrams of three NVM stacks of various dielectrics
designated by line style and color at a 10-V applied bias. The metal electrode
and p-Si doping for each NVM stack are the same. The arrows designate the
electron (e− ) and hole (h+ ) tunneling currents. Respective thicknesses of the
TL, CTL, and BL are 2, 6, and 10 nm.
stacks 2 and 3 are Al2 O3 and ZnO, respectively. Since Al2 O3
is a BL and ZnO is a CTL, Al2 O3 is thicker than ZnO and
therefore provides the smallest capacitance.
B. Energy Band Diagrams, Electric Fields, and Potentials
One of the most informative ways to compare the three TBF
NVM stacks is via their energy band diagrams. The energy
band diagrams of the three TBF NVM devices at a 10-V bias
are superimposed in Fig. 3. The metal electrode and doping in
the p-Si are constant, so the BL, CTL, and TL of each stack
can be more easily compared. The superimposed energy band
diagrams reveal significant differences.
To facilitate the understanding of the device physics for
observed differences in the energy band diagrams (see Fig. 3) of
the TBF NVM stacks, several additional plots were generated.
The electric field and potential along the gate stacks were
determined and plotted (see Fig. 4) for several biases. Energy
band diagrams provide a means to visualize energy band gaps
and band offsets or differences in electron affinities of the three
TBF NVM stacks. Several desirable traits of the TBF NVM
are large energy band gaps for the BL, small energy band gaps
239
Fig. 4. Electric field and potential for the three TBF NVM dielectric stacks
are plotted as a function of distance along the stacks for a 10-V applied bias.
Regions for the TiN metal electrode, BL, CTL, TL, and p-Si are labeled.
for the CTL, and large electron affinity differences between
the BL–CTL and CTL–TL. Fig. 3 shows that each dielectric
stack provides these basic attributes. To offer a more in-depth
comparison of the three TBF NVM stacks, additional aspects
of the energy band diagrams can be examined such as band
bending and carrier tunneling distance.
Although the applied potential across each of the dielectric
stacks is the same (10 V), the band bending in the stacks
is distinctly different as seen in Fig. 3. Comparing the three
different TL dielectrics, SiO2 shows the greatest amount of
band bending. This effect is due to the fact that the slope of
the band bending is directly proportional to the electric field
according to Poisson’s equation. One would expect the CTL
and BL to also conform to the Poisson’s equation whereby
the layer with the lowest κ would exhibit the greatest amount
of band bending or highest electric field. However, this effect
is not always observed, demonstrating the complexity of the
device physics. For instance, although SiO2 has the lowest κ of
all the BL dielectrics (see Fig. 2), the Al2 O3 BL exhibits the
greatest amount of band bending. Fig. 4 confirms that Al2 O3
has the largest electric field and potential drop of the three BL
dielectrics. In the CTLs, ZnO shows the most significant band
bending (see Fig. 3); however, Si3 N4 has a lower κ. Fig. 4
reveals that the electric field of ZnO is three times greater than
that of the other two CTLs. Hence, it is evident that the other
dielectric layers in the stack influence the electric field and
potential drop across the third layer when under the constraint
of a constant applied bias. The simulation program provides
a means to deconvolve the physics governing these elaborate
multilayer dielectric device structures, revealing logical trends
with the data produced in Figs. 3 and 4.
Figs. 3 and 4 show that the presence of two dielectric layers
of the same material (SiO2 ) yields respective electric fields
that are nearly identical and independent of thickness. This
observation assumes that trapped charge is not present in any
of the dielectric layers. It may be initially unexpected, but the
concept that two dielectric layers of identical material systems
would have nearly corresponding electric fields since their κ’s
are equivalent is explicable. Another interesting aspect resulting
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IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 11, NO. 2, JUNE 2011
from dielectric interaction involves the presence of a lower
κ dielectric layer adjacent to two higher κ dielectric layers
as in the case of ZnO between La2 O3 and ZrO2 . The κ of
ZnO is larger than the κ of SiO2 (see Fig. 2), and at first
glance, one may expect the electric field and voltage drop to
be reduced due to its high κ. However, when placed between
La2 O3 and ZrO2 , ZnO displays the most band bending of any
of the dielectrics in Fig. 3. The κ’s of La2 O3 and ZrO2 are
considerably larger than that of ZnO (see Fig. 2). Figs. 3 and
4 reveal that the large difference in the κ’s dictates that the
majority of both the electric field and the potential drop will be
across the ZnO layer. Consequently, the large electric field will
drive any carriers present in the bands of the CTL toward the
BL which is undesirable because of the increased probability
of tunneling through the BL. While the relative difference in
the κ’s of the La2 O3 , ZnO, and ZrO2 dictates the electric field
and potential drop in the CTL, BL, and TL, the overall increase
in the absolute value of the κ’s increases the electric field and
potential drop in the Si for a given voltage bias.
C. Tunneling Distances
Because the program/erase modes of TBF NVM devices are
dependent on quantum mechanical (QM) tunneling, modeling
and understanding this phenomenon is of great importance. For
instance, the amount of tunneling through the TL at a given
write bias determines the amount of charge that can reach the
CTL. Additionally, the degree of tunneling through the BL at
a specific write bias determines how well the BL restricts the
charge from leaving the CTL, thereby allowing a measure of
the charge retention efficiency. Tunneling distance data coupled
with energy band diagrams and electric field and potential data
yield a thorough and comprehensive overview of the intricacies
of the device physics describing complex multilayer dielectric
systems.
The computed tunneling distance for electrons was performed for several scenarios for FNT: from the gate electrode to
either the CB or VB of the dielectric, from the semiconductor
CB to the CB of the dielectric, and from the semiconductor
Ef to the CB of the dielectric. The calculations for the DT of
electrons are similar to FNT. However, rather than FNT to the
CB or VB of the dielectric, DT is calculated with respect to the
adjacent dielectric or electrode layer and is simply the thickness
of the said layer. For holes, the FNT distance is taken from the
semiconductor VB and the semiconductor Fermi energy (Ef )
to the VB of the dielectric. The DT distance is analogous to the
FNT case; however, rather than FNT to the VB of the dielectric,
DT is calculated with respect to the adjacent dielectric or electrode layer. The tunneling distances have physical meaning only
for certain bias conditions or polarities. Consequently, judicious
care must be exercised when analyzing tunneling distances.
Using the energy band diagrams of the dielectric stack to aid the
interpretation of the tunneling distance is critical, and with this
information, calculations of tunneling distances can provide
unique insight to the physics of a dielectric structure at various
bias conditions.
The usefulness of tunneling distance data is demonstrated
by the further consideration of the three multilayer dielectric
Fig. 5. Electron tunneling distance as a function of erase voltage for the BLs
and write voltage for the TLs of the three dielectric stacks. The DT and FNT
regions for the BL and TLs are readily observed. Tunneling distance for the
TLs are shown as calculated from both the semiconductor (S/C) CB and Ef .
TBF NVM stacks highlighted in Fig. 3. The tunneling distances
calculated by the simulation tool as a function of applied bias
for these dielectric stacks are plotted in Fig. 5. The electron
tunneling distances for the BLs and TLs are shown for the erase
and the write modes, respectively. Other tunneling distances
are not shown here in order to minimize plot congestion. For
the write mode, the electron tunneling distance through the
TLs is shown in Fig. 5. The solid symbols represent tunneling
from the semiconductor CB, while the open symbols designate
tunneling from the semiconductor Ef . Comparing the transition
from DT to FNT, the transition occurs at a lower voltage
for tunneling from the semiconductor Ef than for tunneling
from the semiconductor CB. This effect may be explained by
noticing that the CB of the semiconductor at the TL interface
is at a lower energy than that of the semiconductor Ef at large
positive applied biases (e.g., see Fig. 3).
Fig. 5 can be used to assess several device performance
aspects of NVM operation. One aspect is the write bias required
to induce the transition from DT to FNT in the TLs. FNT is
the primary tunneling mode for programming an NVM device.
Since all the TLs of the three stacks are of the same thickness,
to the first order, the lower the voltage required for the FNT
transition to occur, the lower the power required to program the
device. Fig. 5 reveals that the transition from DT to FNT from
the semiconductor Ef occurs at a lower bias for ZrO2 , followed
by HfO2 and, then, SiO2 . While the electric field, and hence
the voltage drop, across the TL is highest in the SiO2 TL (e.g.,
see Fig. 3), the larger electron affinity of the ZrO2 compared
to HfO2 and SiO2 gives the ZrO2 TL an initial advantage,
enabling a lower voltage required to enter the FNT regime.
Another aspect to assess is the BL’s ability to impede charge
from entering the CTL during the erase mode. In this case,
a higher voltage is desired to induce the transition from DT
to FNT. Fig. 5 discloses that La2 O3 , followed by SiO2 and,
then, Al2 O3 , requires a larger bias to induce the DT-to-FNT
transition. The device physics providing this advantage is explained by the combination of the differences between La2 O3
and ZnO’s: 1) dielectric constants leading to a reduced electric
SOUTHWICK et al.: SIMULATION TOOL FOR COMPLEX MULTILAYER DIELECTRIC DEVICES
Fig. 6. Energy band diagram of TiN–SiO2 –Si3 N4 –SiO2 –pSi (see stack 1
in Fig. 1) without and with charge. An electron concentration of −1 ×
1013 e− /cm2 is used.
field, potential, and, thus, band bending in the La2 O3 and
2) electron affinities (i.e., CB offsets) providing a larger barrier
to tunneling. Further tuning of the transition voltage between
the DT and FNT of the BL is possible by engineering the gate
metal work function.
D. Capacitance, Sheet Charge, and Flat-Band Voltage
Fixed charge in the dielectrics of metal–insulator–
semiconductor devices is of particular interest because of the
adverse effects on device performance. Placing a sheet charge
concentration of −1 × 1013 e− /cm2 at the center of the 6-nmthick Si3 N4 trapping layer of stack 1 is shown in the energy
band diagram of Fig. 6. The differences exhibited in the energy
band diagrams of the structure with and without charge are
clearly evident. The sheet charge decreases the band bending
in the TL and increases the band bending of the BL. The TL
barrier for electrons in the Si is increased as negative charge
is trapped in the CTL, creating a self-limiting charge injection
process.
Examining the amount of charge trapped in the CTL is
determined experimentally by either measuring the Vt or VFB .
Changes in the amount of charge trapped in the CTL are
manifested as ΔVt or ΔVFB . The magnitude of ΔVt or
ΔVFB depends on the amount and location of the trapped
charge as well as the material parameters of the device. The
larger ΔVt or ΔVFB is, the easier it is to sense changes or
create multilevel NVM cells. Analyzing the response of the
three dielectric stacks due to the presence of trapped charge
was performed by inserting a charge concentration of −1 ×
1013 e− /cm2 or −1.6 × 10−6 C/cm2 at the center of the CTL.
The capacitance–voltage (C–V ) curves for the three dielectric
stacks with and without trapped charge are shown in Fig. 7.
Several observations may be noted concerning the C–V
curves shown in Fig. 7. First, as expected, the dielectric stack
with the smallest EOT (see Fig. 1) has the largest stack capacitance and ΔC. Second, shifts in ΔVFB are toward increasing
positive bias, indicating a presence of negative charge. Third,
the shapes of the curves do not change, indicating that the
charge concentration is constant and does not change with applied bias. Fourth, the minimum of the stack capacitance Cmin
241
Fig. 7. Stack capacitance is plotted as a function of gate voltage for the
three TBF NVM structures without and with electrons trapped in the center
of the CTL. The concentration of electrons are −1 × 1013 e− /cm2 or −1.6 ×
10−6 C/cm2 .
(in the depletion region) is related to the series capacitance of
the dielectric (Cox ) and semiconductor (CS ). Since the doping
concentration for the three dielectric stacks is the same, as Cox
increases, so does Cmin . Lastly and somewhat most revealing,
the magnitude of ΔVFB is stack dependent. The underlying
physics of the change in magnitude may be explained by recalling that ΔVFB is inversely proportional to the κ of the stack.
That is, the lower the average stack κ, the larger the ΔVFB .
This effect explains the large ΔVFB for the SiO2 –Si3 N4 –
SiO2 stack and the small ΔVFB for the La2 O3 –ZnO–ZrO2
stack. As discussed earlier, a large ΔVFB is attractive for
multilevel cell programming and easier to distinguish between
programmed and erased modes. However, there is a tradeoff;
the less sensitive an NVM stack is to changes in charge, the
less susceptible the device is to programming variation, and the
greater the number of charge states available as a function of
applied voltage.
E. Validation of the Model
The preceding examples and case studies using the simulation tool have demonstrated the flexibility, functionality,
and ease of use of the simulation tool. However, the question remains as to the accuracy of calculations performed by
the simulation tool. Because of the advanced capabilities of
finite-element PSES programs that far outweigh those of the
simulation program, the PSES program SILVACO [27] was
used to assess the accuracy of the simulation tool. Several data
calculated by the simulation tool are directly compared to the
data generated by SILVACO. The first data that are compared
are an energy band diagram of the TiN–La2 O3 –ZnO–ZrO2 –pSi
multilayer dielectric stack with a −10-V bias. The second comparison is of the electric field of each dielectric layer in the TiN–
La2 O3 –ZnO–ZrO2 –pSi stack as the voltage is swept from −10
to 10 V.
Fig. 8 shows an overlay of the same energy band diagram
of TiN–La2 O3 –ZnO–ZrO2 –pSi as calculated by the simulation
tool and SILVACO without and with QM corrections to the pSi. The energy band diagrams generated by both the simulation
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IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 11, NO. 2, JUNE 2011
Fig. 8. Energy band diagrams of TiN–La2 O3 –ZnO–ZrO2 –pSi calculated by
the simulation tool, SILVACO without QM corrections, and SILVACO with QM
corrections.
corrections, and the simulation tool methods for higher voltages
in the ZnO layer. At such a large bias in inversion which induces
a large carrier concentration, the observations of QM effects are
not surprising. Nevertheless, the electric fields in the La2 O3
and ZrO2 practically coincide for each calculation. Hence,
Fig. 9 demonstrates that the electric field of the dielectric
layers changes very little even with the quantum corrections.
For ultrathin single-layer dielectrics or multilayer dielectrics
with an EOT of ∼3 nm or less, quantum effects become
more significant. For these simulations, the voltage drops and
electric field in the dielectrics are an upper bound and are an
overestimation, while the voltage drop in the semiconductor is
underestimated, and the capacitance overestimated.
These calculations and comparisons demonstrate that the
simulation program provides results that are reasonable and
very similar to much more sophisticated calculations. The
time required to learn and then use the freeware program is
considerably less, thereby increasing the accessibility for those
that are not accustomed to involved simulations on complex
multilayer dielectric structures.
IV. S UMMARY
Fig. 9. Electric field of the layer is shown as a function of gate voltage for the
dielectric stack TiN–La2 O3 –ZnO–ZrO2 –pSi. The inset is a magnified view of
the electric field of each layer from 8 to 10 V. The electric field is calculated
using the simulation tool, SILVACO without QM corrections, and SILVACO
with QM corrections.
tool and SILVACO without QM corrections correlate very well.
The energy band diagram produced by SILVACO with QM
corrections differs somewhat in the p-Si and TL. The deviation
in the p-Si and TL is not so surprising since the simulation
tool does not incorporate QM corrections. What is revealing
is that the agreement is relatively close. Furthermore, it is
evident that QM corrections have little effect on the energy
bands of the BL and CTL. Additionally, excellent agreement
is observed comparing the energy band diagrams generated by
the simulation tool and SILVACO without QM corrections.
A comparison of the calculated electric field of each dielectric layer in the dielectric stack TiN–La2 O3 –ZnO–ZrO2 –pSi
is shown in Fig. 9 as the bias is stepped from −10 to 10 V.
The data are generated in three different ways: 1) using the
simulation tool; 2) using SILVACO without QM corrections;
and 3) using SILVACO with QM corrections. The data symbols
in Fig. 9 are spaced in such a manner as to aid in the comparison. In Fig. 9, the electric field in the La2 O3 and that in
the ZrO2 are nearly equivalent which is not surprising since
their κ’s are very similar. All three calculation methods yield
similar results. The inset shows some deviation between the
SILVACO QM correction method, the SILVACO without QM
Multilayer dielectric energy band diagrams and device parameter calculations can be performed by hand, using spreadsheets, using mathematical programs, or with finite-element
Poisson–Schrodinger equation solvers. Each of these approaches has limitations whether it is the financial expense
or the investment of time to perform the calculations, develop
programming code, or learn the program interface. To minimize
these constraints and build upon the success of the first simulation tool [16], [17], a freeware program was created, based
on a modular analytical algorithm solved using an iterative
approach for complex multilayer dielectric devices. The program includes the ability to easily and quickly visualize a wide
range of plots and diagrams and calculate a variety of device
parameters.
Charge trap-based NVM structures based on a three-layer
dielectric structure were analyzed using the simulation tool.
Understanding the role of material parameters (i.e., band gaps,
band offsets, dielectric constants, and thicknesses) on device
performance and characteristics was analyzed using three different gate dielectric stacks. In particular, the dielectric stacks
with trap charged were analyzed using device parameters,
including Vt , VFB , tunneling distances, and voltage shifts. The
easy-to-use interactive nature of the tool, its predictive capabilities, the speed of the calculations, and the free access [17] result
in a simulation tool that will be a benefit to many. The necessity
of such tools will increase as additional layers are introduced
into the NVM structure (e.g., a blocking layer composed of
three dielectrics).
ACKNOWLEDGMENT
The authors would like to thank Dr. A. Moll for the fruitful discussions and kind support and Dr. B. Yurke for his
contributions.
SOUTHWICK et al.: SIMULATION TOOL FOR COMPLEX MULTILAYER DIELECTRIC DEVICES
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Richard G. Southwick, III (S’04–M’11) was born
in Cedar City, UT, in 1981. He received the B.S.,
M.S., and Ph.D. degrees in electrical engineering
from Boise State University, Boise, ID, in 2004,
2008, and 2010, respectively.
He is currently performing research at the National
Institute of Standards and Technology, Gaithersburg,
MD, as a National Research Council Research Associate. His research interests include gate oxide
reliability studies, alternative gate oxide dielectrics,
and cryogenic measurements.
Dr. Southwick has served on the organizing committee for the IEEE International Integrated Reliability Workshop from 2009–2011.
Aaron Sup, photograph and biography not available at the time of publication.
Amit Jain, photograph and biography not available at the time of publication.
William B. Knowlton (M’00–SM’10) was born in
Sewart Air Force Base, TN, on June 15, 1960. He
received the B.S., M.S., and Ph.D. degrees in materials science and engineering from the University
of California at Berkeley, Berkeley, in 1992, 1995,
and 1998, respectively. His doctoral work included
the study of point defects and modeling diffusion
in silicon and the development, fabrication, characterization of dark matter particle detectors, X-ray
detectors, and far-infrared resonant detectors.
In 1997, he joined Hewlett Packard Labs where
he studied dislocations and structural properties of GaN material systems for
LEDs. He joined Insight Analytical Labs in 1998 where he consulted and performed microelectronic reliability studies. In 2000, he joined the faculty of the
Department of Electrical and Computer Engineering, Boise State University,
Boise, ID. He is a cofounder of the Department of Materials Science and
Engineering, where he is a Professor and Program Coordinator for Graduate
Studies and holds a joint appointment. He has published over 70 papers in peerreviewed journals and conferences. His research activities include biomolecular
electronic devices, MOS device reliability physics, material characterization,
and nanofabrication.
Prof. Knowlton is also a member of the Materials Research Society and
the American Physical Society. He has served on the organizing committees
for the IEEE International Integrated Reliability Workshop from 2002–2005
and 2008–2011 and for the 2009 IEEE International Semiconductor Device
Symposium and was a Guest Editor for the IEEE T RANSACTIONS ON D EVICE
AND M ATERIALS R ELIABILITY in 2006 and 2008. He has been honored with
several teaching and research awards, including the 2011, 2008, and 2004
Boise State University Top Ten Scholar/Alumni Association Honored Faculty
Member Awards, 2007 College of Engineering Professor of the Year Award,
2004 IEEE Student Chapter Electrical and Computer Engineering Professor
of the Year Award, the 2004 Boise State University Presidential Research and
Scholarship Award, and as a 2002 NSF New Century Scholar.