A Low Dispersion 2-GHz Comparator
By
William F. Johnston
Submitted to the Department of Electrical Engineering and Computer science
in Partial Fulfillment of the Requirements for the Degrees of
Bachelor of Science in Electrical Science and Engineering
and Master of Engineering in Electrical Engineering and Computer Science
at the Massachusetts Institute of Technology
xn
e
May 23, 2001
© Copyright 2001 William F. Johnston. All rights reserved.
The author hereby grants to M.I.T. permission to reproduce and
distribute publicly paper and electronic copies of this thesis
and to grant others the right to do so.
Author
Department of Elfftrical Engineering and Computer Science
May 23, 2001
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Accepted by
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LIBRARIES
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BARKER
A Low Dispersion 2-GHz Comparator
By
William F. Johnston
Submitted to the Department of Electrical Engineering and Computer Science
May 23, 2001
in Partial Fulfillment of the Requirements for the Degrees of
Bachelor of Science in Electrical Science and Engineering
and Master of Engineering in Electrical Engineering and Computer Science
Abstract
A low dispersion 2-GHz comparator is an essential part of the latest automated VLSI
tester by Teradyne Inc. With each new and faster CMOS logic VLSI microchips, faster
and more precise comparators are needed to verify that the static discipline is being met
on the many pins of the integrated circuit. As the error in the comparator is lowered, the
VLSI production yield is greatly increased because of greater certainty of the
measurements. The comparator described within is designed to test a variety of CMOS
logic levels at the expected logic levels and rise-times of the near future. The result is a
Si-Ge integrated comparator with l2psec of dispersion by detailed simulation awaiting
fabrication.
Index Terms-Complementary metal oxide semiconductor transistor technology
(CMOS technology), very large scale integration (VLSI), application specific
integrated circuit (ASIC), silicon germanium (Si-Ge), integrated circuits (IC),
automatic test equipment (ATE), personal computer (PC), digital signal processing
(DSP), direct current (DC), alternating current (AC), device under test (DUT), pin
electronics (PE), bipolar junction transistors (BJT), complementary metal oxide
semiconductor field effect transistor (MOSFET).
2
TABLE O F FIGURES: .......................................................................................................
TABLE OF TABLES:........................................................................................................
4
4
CH A PTER 1: OV ERV IEW .............................................................................................
5
5
1.1 THE A UTOMATIC TEST EQUIPM ENT INDUSTRY ........................................................
1.2 THE TESTING PROCESS ............................................................................................
C HA PTER 2: THE J2 SY STEM .....................................................................................
2.1 THE SYSTEM G OALS..................................................................................................
2.2 THE PROCESS.........................................................................................................
2.3 THE CHANNEL .........................................................................................................
C HA PTER
.................................................
5
8
8
8
9
12
3.1 M EETING THE SPECIFICATIONS ...............................................................................
12
3.2 THE A MD 1685.........................................................................................................
14
3.3 THE LM 161..............................................................................................................
15
3.4 THE A D 96685 .......................................................................................................
3.5 LAST REQUIREM ENTS ............................................................................................
15
16
CHAPTER 4: COMPARATOR DESIGN ....................................................................
17
4.1 COM PARATOR SYSTEM ..........................................................................................
17
4.2 TRANSISTOR SELF-H EATING...................................................................................
4.3 THE V OLTAGE BUFFER AND A TTENUATOR ............................................................
4.4 D IFFERENTIAL PAIR STAGE.....................................................................................29
4.5 THE LATCH STAGE....................................................................................................
4.6 THE SLAVE LATCH................................................................................................
4.7 D ISABLED M ODE ...................................................................................................
18
24
CHAPTER 5: SIMULATION AND LAYOUT ............................................................
5.1 SIMULATION ...........................................................................................................
33
35
37
38
38
5.2 LAYOUT....................................................................................................................38
A . BIBLIO GRA PH Y ...................................................................................................
40
3
Table Of Figures:
9
Figure 1: T-Coil Input .....................................................................................................
10
.................................................................................
Setup
Comparator
2:
Basic
Figure
17
Figure 3: Comparator System Diagram ............................................................................
Figure 4: IBM Si-Ge transistor cross-section (IBM Microelectronics Division)......19
20
Figure 5: Thermal circuit model of transistor self-heating. ...........................................
Figure 6: Thermal Self-Heating Magnitude and Time Constant....................................21
25
Figure 8: Buffer and Attenuator Stage ..........................................................................
26
Figure 9: Level Shifter Circuit .....................................................................................
30
Figure 10: Self-Heating Compensation........................................................................
31
Figure 11: Differential Pair Switching Example..........................................................
32
Figure 12: W ave Form Simulation....................................................................................
33
Figure 13: Differential Stage........................................................................................
34
Figure 14: Latch Stage ...................................................................................................
37
Figure 15: Slave-Latch.................................................................................................
39
Figure 16: J2 Comparator Layout .................................................................................
Table of Tables:
Table 1: Comparators of the Past and Present...............................................................
Table 2: Basic Specifications for Comparator ...............................................................
12
16
4
Chapter 1: Overview
1.1 The Automatic Test Equipment Industry
During recent years the production of VLSI circuits has increased, while device
speed and density have risen as well. Around 1980, the latest CMOS technology
produced logic ICs running at a speed of 6MHz; nowadays, however, 1GHz CMOS ICs
are not uncommon and chip speeds are ever increasing. The ATE industry creates VLSI
testing machines used to perform high volume tests that are able to verify electrical
quality and functionality of the VLSI ICs.
Currently, the speed of available VLSI ATE is not as fast as the CMOS
technology available. This means that the industry has not been able to test the ICs as
scrupulously as it would like because the testers are too slow. Lower speed functionality
tests are available; however, high-speed test VLSI ATE is in high demand to increase the
development and output production rate of multiple pinned high speed VLSI ICs (such as
PC processors and DSP ICs for the Internet and cellular phones).
Teradyne, a company that designs and manufactures ATE, is developing a VLSI
tester called the J2, which they hope will be able to meet this demand for higher speed
testers.
1.2 The Testing Process
The two major types of testing of VLSI ICs are DC and AC testing. The DC
testing verifies characteristics such as the leakage current of the DUT. The AC testing
verifies the functionality and static discipline of the digitally natured DUT. Even though
5
there are many varieties and functions of DUTs, each is an electrical device that has pins
that receive electrical voltage signals, pins that produce electrical voltage signals, or pins
that both create and receive electrical voltage signals. More specifically, Teradyne's
VLSI tester must be able to create input voltage signals to send to pins on the DUT while
monitoring the output signals sent from these pins. This will allow the manufacturer to
determine if the DUT is performing as desired.
Because the type of DUT the J2 test system is made to test is digital in nature, the
testing problem is simplified. The DUT with respect to functionally, static discipline, and
the speed desired, must output the correct voltage signal given a design and input voltage
signals. Therefore there must be an electrical driver and sensor on Teradyne's tester for
each of the input pins of the DUT. The current driver must be able to create the needed
signals at a speed and voltage for verification of performance based on the manufacture
of the DUT's specification. However, the comparator, not the driver, is the focus of this
thesis.
The sensors must be able to record output voltages from the DUT to determine if
the voltage is correct while meeting the static discipline. Because the DUT is digital in
nature, the tester must verify if the output signals are "low" or "high" at the end of each
period of the clock. The static discipline system defines how to verify these
characteristics. Static discipline states that during each cycle of the clock, there exists a
point in each clock cycle when the voltage on the pin must be below a certain value to be
interpreted as "low." In contrast, static discipline also states that at this same moment
during the clock cycles, the voltage signal on the pin should be above a certain value to
be interpreted as "high." If the signal fails to be "high" or "low" or is incorrectly "high"
6
or "low" given the proper input, then the device is said to have made an error.
If the voltage signal is appropriately "high" or "low" at the proper time during the
clock cycle, the DUT is operating correctly. Comparators are designed to determine
whether a voltage is above or below another voltage. Furthermore, by using a latch
comparator, the voltage can be determined at a certain time. Because comparators create
extra load on the pin, there is a need to use as few comparators as possible. However,
one comparator will be needed to determine "high" and one to determine "low" at the end
of each clock cycle. Accordingly, the system is designed with the notion that one
comparator can be cycled at least as fast as the DUT. Furthermore, because there are
many pins on each DUT, these comparator circuits must be repeated for each pin of the
DUT on what is called a channel. The comparators will be included in the pin electronics
(PE) IC of the system and will reside on channel cards, which can be added or removed
to meet the number of pins of the DUT.
The VLSI tester is comprised of many parts. The pin electronics (PE) are
controlled by the control system logic of the remainder of the tester, which is connected
to a computer controlled by the customer. The controlling logic signals and timing logic
signals that the control system sends to the PE are sufficient for sending signals to the
DUT and controlling the retrieval of output signal from the DUT. Furthermore, the
retrieval of logic states from the PE is sufficient to verify performance of the DUT. For
example, the controlling signals are able to latch the comparators and retrieve the output
states when needed.
7
Chapter 2: The J2 System
2.1 The System Goals
The Teradyne J2 system will be a system capable of testing VLSI circuits at
speeds up to 2 Giga-bits per second per pin on up to 1200 independent pins. This
objective means that there must be a concentration of high speed testing devices
synchronized with a test fixture that can be placed reasonably close to the device being
tested. This goal poses many challenges: how to place many high speed components
close to the DUT, how to route all the high speed signal with minimal noise, and how to
cool such a high powered system. In order to over come these challenges, the J2 system
will have a concentration of Si-Ge ASICs mounted close to the DUT with an extensive
cooling system.
2.2 The Process
The IBM Si-Ge process that Teradyne is using is very good at the task of creating
a high tester because it provides the necessary high-speed BJT transistors that few
processes can provide with the needed integration capabilities. Furthermore, it also
possesses CMOS technology on the same chip for the processing of the vast amounts of
data that will be obtained. The process yields almost all active devices and passive
devices at nominal performance; however, for the high speed design needed by Teradyne,
only the npn BJT's, and p-channel MOSFETS are useful active components. There is
good resistor and capacitor matching with low thermal time constants as well.
8
2.3 The Channel
The channel is the node of conduction that will be the connection between the DUT and
the testing circuitry. The chore of getting the signals to and from the DUT turns out to be
quite a challenge. The DUT is connected directly to a 50Q coaxial cable with good high
frequency performance. This cable runs a very short distance to the input of the module
that contains the Si-Ge ASIC on which the testing circuitry will be locaied. A very short
wire is run from the coaxial cable to this ASIC where the signal is terminated to 500 to
avoid reflections. There is also a T-coil circuit on the input of the circuitry to cancel out
the parasitic capacitance that exists on our testing circuitry inputs. The T-Coil (Figure 1)
C
50Transmission Line
50Q
Off Chip
On Chip
..
H
L
L
-C.
Figure 1: T-Coil Input
9
is a method of keeping the parasitic capacitance (Cparasitic) of about 2pF from loading the
transmission line. By adding the T-Coil of Figure 1, the effect of all the measuring
devices' (like the comparator, leakage current detector, current driver, etc.) lumped
capacitance have reduced reflective effects on the transmission line. Furthermore, the
bandwidth to the measuring devices is increased by about a factor of 1.6 if matched
properly. This increase is important because without the T-Coil, the bandwidth is about:
Bandwidth =
1
2 nRC
1
-
(2.1)
= 3.2GHz
2it(25Q)(2pF)
The resistance is that of the 50Q transmission line in parallel with 50Q resistor (Figure
1). This equates to about a 1 Opsec signal rise time, which is more than the needed
100psec specification. By adding the T-Coil, the rise time is reduced to around 70psec.
After the voltage signal goes through the T-Coil, it reaches the comparator input
Ground Vcc=
5.3v
Vee=
-6.2v
Vout +
Vout Rref=1-l
1VG
10kn
Figure 2: Basic Comparator Setup
10
v[ (Figure 1). This input is where the logic level of the DUT will be verified to meet the
static discipline. The comparator will receive this input signal (vm4) and a reference
signal
(vREF)
and make comparisons at the rising edge of the latch signal
(vLATCH).
There
is a disabled mode where the comparator will be shut off to save power and also to
measure the leakage current of DUT which calls for the comparator input current to be on
the order of 1 OnA. The output of the comparator will be fed into high-speed logic to
verify that the signals are as expected.
I1
Chapter 3: Old and New Comparators
3.1 Meeting the Specifications
The edge comparator that Teradyne desires to use in the J2 test system is unique and
highly specialized. For comparison, Table 1 lists of some of the specifications along with
some of the characteristics of older comparators.
LM161/LM361
(National Semiconductor Inc)
AD96685
(Analog
Devices)
1700
3nsec
3000
3nsec
~15
50psec
+-3v
+-5v
+-5v
+-5v
1000mW
5mV
~100psec
lOnA
300mW
2mV
~3.5nsec
N/A
600mW
1mV
~1nsec
N/A
118mW
2mV
~200psec
N/A
400psec
-20kQ
5nsec
20kQ
3nsec
20kQ
1.5nsec
200kQ
Specification Name
Specification
Value for the
J2
Av (gain)
Dispersion Over
Range of Input
N/A
15psec
AMD1685
(Advanced
Micro
Device Inc)
Signals
Differential Input
Range
Power
Offset Constant
Input Rise-time
Input Leakage During
Disabled Mode
Setup and Hold Time
Input Resistance
Table 1: Comparators of the Past and Present
As shown in Table 1, the output of the J2 comparator will always be latched. The gain is
not important as long as other specifications are met. This feature is very useful in
designing the comparator. Of the specifications listed, the most difficult to meet are the
input range, offset constant, and dispersion.
The input range is difficult because of the transistor limitations. Comparators
usually use a differential emitter coupled pair transistor configuration as their main
12
switching element. With the choice of the high speed Si-Ge fabrication process comes
the problem of reverse breakdown. This characteristic is because shorter base width
often improves speed although it makes the transistor more vulnerable to damage. The
fast transistors mean that the reverse breakdown voltage is much smaller than normal
transistors. Furthermore, the fabrication process does not have fast Schottky diodes,
which could solve the problem without severely degrading performance. Comparators
made with thick base transistors or with fast Schottky diodes to clamp the voltage have
been able to obtain a large input range. However, most high performance comparators
have limited ranges. The extremely small reverse breakdown associated with the IBM
Si-Ge process means that the need to increase this range limitation is critical.
Keeping the input offset constant is another problem for comparators. Because
the input (vN) will be a single input voltage, the negative input (vREF) will be a DC
voltage. The J2 system will be able to calibrate and subtract off a polynomial matched
set of offsets that result from resistor mismatches, nonlinear scaling and so forth.
However, mismatches due to thermal change or other such time varying factors cannot be
compensated for in this fashion. In slower comparators, auto zeroing or other methods
can be used to reduce some of the offset; however, this method creates timing limitations
in their performance, which is not acceptable for the J2 comparator. Even high-speed
sampling oscilloscopes benefit from the repetition of the signals that they measure, but
the J2 system does not have this luxury because it must function continuously for many
seconds in a row with non-repeating signals.
The last challenge is to reduce the dispersion. More specifically, if the offset is
brought down to within a small satisfactory range in terms of thermal offsets or time
13
dependent offsets and so forth, the comparator must have a consistent output delay over
various input steps rise times (0.5v/nsec to 30v/nsec) and overdrives (100mV to 1.5v).
Over a set of various input signals with different overdrives or rise times, how accurately
the comparator maintains its delay is called the dispersion. In the case of the J2, because
there will be only a latched output, how much the latching moment varies in order to
catch the transition in question is the dispersion. This characteristic is very important to
Teradyne, because the more accurately a step can be measured, the more precisely the
static discipline of digital circuits can be verified. With the more precise measurement of
the static discipline, Teradyne's customers increase the yield of their VLSI parts since
measurement error reduces the known level of performance. Though this has not been
the focus of some of the comparators of the past, the J2 specification for dispersion is
15psec, down sharply from around the 50psec currently available.
3.2 The AMD1685
One of the previous comparators that was studied in order to come up with the J2
comparator design is the AMD1685 by Advanced Micro Devices, Inc.. The AMD
comparator is one of the benchmark comparators of the industry. Although it was created
around 25 years ago, the comparator still possesses one of the best performances to date
and only moderate improvements have been made in performance since its initial
creation. The AMD 1685 possessed a gain of about 1700 and was made with high speed
npn transistors. It possessed a latch and provided high speed ECL output. The
bandwidth of the device is still in the 100MHz range, which is a result of its multiple
stage topology. The typical delay is around 4nsec, though it could get to 6nsec with a
small 5mV overdrive. With a gain of 1700, 5mV overdrive shows up clearly at the ECL
14
output.
However, this topology does not meet the J2 specifications. The AMD 1685 is
built on a 2GHz process, and has a bandwidth of around 100MHz. The J2 comparator
uses a 40GHz process in order to handle rise times on the order of 100psec (3.5GHz).
The J2 dispersion value of less than 15psec from its own internal latch is also a
specification that the AMD1685 does not meet. However, the J2 comparator will only be
used with a latch. Therefore much of the gain which the AMD part had to achieve ECL
level outputs can be reduced to a gain sufficient to be latched.
3.3 The LM161
The LM 161 by National Semiconductors was created about the same time as the
AM1685. This comparator is only slightly better than the AMD1685 (for the J2
specifications) because it has two internal alternating latches that provide a faster setup
and hold time for the latch. However, the part requires more power for the added
performance.
3.4 The AD96685
The recent AD96685 comparator is closest to meeting Teradyne's J2
specifications. Though the dispersion is lower than most comparators, the setup and hold
time does not meet Teradyne's needs and it is still far from the J2 specifications. The
power of this comparator is a very inviting feature for the J2 system, which will have
thousands of comparators, but without meeting the other specifications, the comparator
will not suffice.
15
3.5 Last Requirements
A few last requirements are listed in Table 2. Of these last specifications, the
power supplies are the most difficult to deal with because of the 0.75nH inductance in
series with the supplies. Even with the flip chip technology, there is a small amount of
wire between the closest large off-chip power supply capacitors and the circuits using
current. When building an edge comparator running off these supplies, even with most
switching done with differential pairs and large on-chip capacitors built-in to help, there
is significant variation in power supply voltage. Often the rails move greater than 25mV
due to rapidly rising input signals. Luckily, the comparisons on such rapidly moving
signals are usually offset only slightly in time because of the rapid slew rate of the
signals.
vIN (main input signal)
vREF (voltage reference
signal)
vLATCH
(disable signal
for comparator for low
input leakage and 25%
power)
Power Supplies
VINPUTOFF
3v 100psec maximum rise/fall-time, -.5v to
3.3v maximum range, 50K output
impedance.
DC voltage, -.5v to 3.3v maximum range,
1kQ output impedance.
Differential signal, -3.5v and -3.7 logic
levels, approx. 100psec rise/fall-time,
Latch on rising edge, 400psec minimum
between latch signals, and about 25Q
resistance.
Differential signal, -3.5v and -3.7 logic
levels, approx. 100psec rise/fall-time, and
about 25Q resistance.
5.3v, Ov, -6.2v. +- IOOmV with .75nH in
series
4v Common mode signal with 200mV
Output
differential signal and less than about 25Q
resistance.
Operating Temperature
60-80 0 C
Table 2: Basic Specifications for Comparator
16
Chapter 4: Comparator Design
4.1 Comparator System
Channel
Voltage
Signal
Voltage
Buffer
Attenuation
Thermal
Compensation
Differential Pair
Stage with feed forward
compensation and
gain
Latch
Slave
Latch
Output
Voltage
Signal
Figure 3: Comparator System Diagram
The comparator block diagram (Figure 3) is the open loop design method used to
compensate for the characteristics that hinder the transistors' performance and, therefore,
the performance of the comparator. The first stage is a voltage buffer. At this stage, the
input resistance of the comparator should be on the order of 20kQ or more. Furthermore,
the reference signal (or the negative terminal of the comparator) is expected to have a
high resistance, so it is important for this symmetric comparator to have high input
resistance for the reference signal. The attenuation stage is a solution to the problem of
excessive reverse breakdown voltage. Like regular transistors, if the Si-Ge transistors
have a reverse voltage of greater than a certain amount, then they will fail. While a
typical silicon transistors reverse breakdown is around 5v base emitter voltage, the Si-Ge
transistors that are used in this comparator design must not be reverse biased more than
2v. Again, good high-speed Schottky diodes could alleviate this problem by clamping
17
the input; however, they are not available with the Si-Ge fabrication process. Therefore
the input signal is attenuated, which unfortunately makes it more sensitive to thermal
offset effects. The thermal compensation stage compensates for the self-heating thermal
mismatch that occurs in the differential pair. Because the comparator will be symmetric,
the overall temperature of the comparator is not really important (over a limited range);
however the variation in temperatures across the microchip will be. The differential pair
stage is designed with extra feed-forward in order to switch more accurately at high
speeds. The last two stages are the latch and slave latch, which are used to catch the state
of the comparator output at the times needed.
One aspect of the comparator not shown Figure 3 is the symmetry of comparator.
Although most comparators have a large degree of symmetry, and the importance of this
technique should not go unnoticed. Also not shown in Figure 3 is the vLATCH and
vINPUTOFF.
Both of these signals are used throughout the comparator, sometimes level
shifted and buffered; however, both are rather unimportant to the design of the
comparator.
4.2 Transistor Self-Heating
The fabrication process is the IBM Silicon-Germanium 5 HP process. Of all the
characteristics examined of the transistors, there are three that are particularly unusual
which require careful examination.
The first trait is the unity gain frequency of 40 GHz. The comparator must run at
least a 2 GHz latching speed, must take vN rise times at least 100psec at 3v, and must
maintain a low dispersion. Therefore the 40GHz unity gain frequency becomes a critical
trait for these transistors. The second important characteristic is the reverse breakdown
18
limitation that is taken into consideration during the design. The most unusual
characteristics, however, are the thermal tendencies of the Si-Ge transistors.
For an offset change of less than 5mV over all signals, the controlling of the
thermal effects on the transistors is critical. A 30*C difference between the input
differential pair can easily cause a 25mV offset that will vary with temperature as
apparent in equation 4.1.
Figure 4: IBM Si-Ge transistor cross-section (IBM Microelectronics Division)
19
aVBE
aT
VBE - VBG
i.
~
T
=
mV
.9 -1.2
= -. 874
343
C
(4.1)
As shown in Figure 4, each transistor is separated from other circuit components
with a deep silicon oxide trench that isolates it both electrically and thermally. The long
parallel lines in Figure 4 are the walls of the trench that consist of a silicon oxide on polysilicon. Electrical isolation is critical and usually assumed for most transistors while
such strong thermal isolation is a little unusual. This structure yields a self-heating
transistor with a moderate thermal resistance to the silicon substrate. Thermal effects are
typically modeled similar to that of a variable current source, capacitor, resistor, and a
constant voltage source (Figure 5). In the thermal model, this components would be a
power dissipating source (a transistor in our case), a specific heat container (the transistor
volume times its specific heat), thermal conductivity (the conduction between the
transistor and the substrate), and a controller temperature area (the substrate). This
circuit yields a first order system with the input being the power dissipation of the
transistor:
temperature
+ 0
s
Cth
Rth
Figure 5: Thermal circuit model of
transistor self-heating.
20
Power =Ch d(temperaturet,,,ransst)
dth
temperaturesisto,-temperaturesubstmte
dt
(4.2)
Rth
Though this is the model that is used during the design, some interesting
characteristics are found upon closer examination. The smallest transistors have the
highest thermal resistance. This fact means that the smallest-sized transistors have the
worst self-heating problems both in terms of overall temperature changes due to selfheating and the longest thermal time constant. Because the smallest-sized transistors are
the fastest and often used at critical fast nodes in our circuits (including the main
differential pair), careful examination was done on these transistors to discover how to
handle the effects of this problem.
As Figure 6 shows, the thermal characteristics of the transistor is modeled well
with a first order system; however, there is a very long tail on the Figure 6 graph. This
60
50
0%- 40
--
4mW Smallest Si-Ge
Transistor
-U- Expontial
Approximation
~30
E 20
10
0
0
2000
4000
6000
Time (nsec)
Figure 6: Thermal Self-Heating Magnitude and Time Constant
21
implies that a better model might be a lossy transmission line model. The long tail
indicates that a better model might be a multiple capacitors to ground between resistors in
series. This model is likely because the silicon path between the transistor and the
substrate has its own specific heat intertwined with its thermal resistance. However, the
first order model represents the system to a degree of accuracy sufficient for the J2
comparator design.
For the smallest, fastest, and most used transistor on our fabrication process
(length of 2.5gm), the Rtb is around 4.8 0 C/mW which represents about 4mV/mW change
in VBE given equation 4.1. With approximately a 1mW power used in transistors to
operate at full speed (with vCB=Ov), the offset would show up very visibly over a slow
rise time signal, like 0.5v/nsec (2psec/mV), confirming that self-heating would be a
problem.
Modeling the self-heating of the transistors and testing our model produced and
confirmed several of its useful traits. For one, because there is a direct dependency of
temperature upon power, the comparator could be designed using various methods to try
and maintain constant power to avoid self-heating problems. Another useful trait is that
the time constant is on the order of IOOnsec. This meant that it was a slow enough time
constant to compensate for electrically while not so fast as to be negligible given our
signal speeds (although the time constant of 1 OOnsec explains how low frequency
comparators manage to avoid many self-heating problems). Finally, the magnitude of the
vBE
change is on the order of 4mV/mW, which means that the amount of deviation of vBE
is just a little more than specification in one moderately powered transistor.
Of the typical modules used in the npn process, some are immune to the offset
22
problems while others are very vulnerable. There are three main circuits that are used in
the Si-Ge process to design the signal path of the comparator: the emitter-follower, the
common-base, and the differential pair. Under the correct configuration, emitter
followers are not susceptible to the self-heating problem. In an emitter follower circuit,
collector current can be maintained at a constant, and the collector emitter voltage can be
kept almost constant as well, so as to produce constant power dissipation. Therefore,
there is no self-heating relative to the complementary side based on input levels. The
common-base circuits have about a 3% change in
f
which means that the collector
current is relative to a change in temperature of .5% as shown in equations 4.3 and 4.4.
(70 0 C=343K)
#(80 0 C = 353K)
-e
# (70C)
_ #(80*C) C) +
#(70 C) + 1 #(80
)=1.03=103%
(4.3)
(4%4)
1
This mismatch might be a significant amount of offset depending on the amount
of resistance that is being driven. However, a lot of this mismatch is avoided by using
larger transistors that have much lower thermal resistance while still maintaining their
speed.
Because the differential pair switches current completely, there is going to be a
change of power and therefore an unavoidable offset. Of the modules used in the design
of the comparator, the differential pair was one of the most important, and it suffered
from the problems of self-heating the most. The differential pair is unique in that it has
one of the only transistors in the signal path that actually turns off. This means that one
transistor will be receiving all the current while the other will be receiving none while
switched. Therefore there is a great imbalance in the power of these two comparing
23
transistors, creating the potential for vj pattern dependent voltage offsets. At worst an
8mV offset could come on a differential pair running at constant VCB of Ov and switching
current of ImA.
4.3 The Voltage Buffer and Attenuator
The voltage buffer is the first stage of the comparator. It must provide a high
input resistance, drive the attenuator stage, and maintain a high degree of accuracy
compared to its complementary side for all signals. The second stage of the comparator
is the attenuator. It was implemented with a simple resistive voltage divider between the
input and the reference. As mentioned before, self-heating could be as large as 4mV/mW
variable offset on the smaller transistors and could sum with each stage. Therefore, as the
stages of the signal path increase, the importance of keeping the self-heating offset to a
minimum becomes more important. The input offset due to the self-heating effect of 6
transistors at 1mW of power in the emitter follower configuration in the signal path could
be as large as 25mV input offset. The emitter followers in the signal path have their
power maintained. As Figure 7 shows, only two transistors (Q2 and Q12) are in the signal
path; however, many more emitter followers are to come in the signal path. Many devices
are used to maintain the power through these transistors showing that fixing this problem
does have its costs. The vcB of both input transistors are maintained with a level shifter.
Without pnp transistors available, the level shifters of Figure 7 (and also shown in Figure
8) create a constant vcB of a little over a volt. The reason for the large vcB was that with
the fast slewing rising edge signals, the level shifter could not maintain the collector to
base voltage consistently.
24
5.3v
300003
30000
0
Q12
F
51m
5pm
Q2
5pm
5pm
OP
4
10[
m30f
-6 .2
5 m
25000
000
U
330
<
-6.2T
F
-,S
I ] ]
'AA-I
AIR
Differential
Stage
VN+
Q7
15000
010
10pm
VIN 2 -
20
10
Q 17
m
19
10pm
Q9
10pm
15000
-6 .62
2v
I
EI
E
Figure 7: Buffer and Attenuator Stage
(All transistors 2.5gm unless notes otherwise)
E
The level shifter (Figure 8) is made by creating a differential pair with emitter
degeneration (Q4 and Q5). Then the collector current of Q3 runs through a resistor to
produce the total gain of 1.15 (Equation 4.1). The purpose of a gain of more than one is
(f)Rc
vou-
+(P3+1)RE
vIN
(4.1)
=1.15
RR
to account for the parasitic resistance that reduces the gain. As shown in Equation 4.6,
the rise time of a signal going throughout the level shift would be on the order of 60psec.
The capacitor of 30fF increases the level shifters transient response. With this feedforward capacitor, the level shifter's capacitive nodes will be charged up more rapidly
30
5.3v
Vout
5pm
Q3
Spm
55M
5pm
Q5
Q4
V in
5pm
2
o
5
m
30f
Figure 8: Level Shifter Circuit
26
than if it were not there. This occurs because the feed-forward capacitor allows the large
2500Q resistor to be shorted at high frequencies. The resulting rise time is closer to the
order of 25psec which makes input rise times of 100psec less threatening to the level
shifter which might saturate Q2 otherwise. However the level shifter is not very precise
and has significant noise on it, which is the reason for the extra vBECn = 25fF@.75mA
(4.2)
C9 =3fF
(4.3)
CgLayotParacitics) =
1 = IC
_
rm
tr = 2.2
T = 2.2(3(
VT
(4.4)
5 fF
.75mA
.03V
mA
(4.5)
V
' )+(C9+Cp(LayoutPacitics))3000Q) = 60psec
(46
The level shifter maintains a constant vcB on transistors Q2 and Q12. Therefore,
in order to maintain a constant power in the emitter follower transistor, a constant current
needs to be applied. Keeping the current constant through the emitter followers serves to
make them faster. This fact comes about because there is no change in current, making
the circuit more accurate at some of the medium speed rise times. In Figure 7, Q6, Q7,
Q8, Q16, Q17, and Q18 only buffer the input signal while the Q9 and Q19 is another
emitter degenerative differential pair outputting the same current that is lost by Q2 and
Q12 to the attenuation resistor of 15000. The current is buffered by Q10 and Q20 and
fed back into the emitters of Q2 and Q12 to balance the current. The reason for using Q6,
Q7, Q8, Q 16, Q17, and Q18 in the emitter follower configuration rather than as diodes, is
to allow for the disabled mode. During the disabled mode, all current sources in Figure 7
27
will be turned off except for the currents going into the emitter of Q9 and Q19. The
currents cannot easily be turned off due to their low voltage levels. Therefore the base
current will be attenuated from these transistors so that by the time the current reaches the
input transistors Q2 and Q12, it is negligible.
The last part of the circuit in Figure 7 is the attenuator stage, which is constructed
out of a differential voltage divider. As shown in equation 4.7, the vid signal is attenuated
by 0.6. This attenuation means that the largest expected input signals of 3v would be
attenuated down to 1.8v, which is well within the range of a differential pair on this
process. With a vBE drop taken from the differential voltage, the 1.8v will only result in a
lv reverse voltage being applied to the off transistor of a differential pair.
1500Q
out
id 15000+2(300Q)
(4.7)
id
Also worth noting in the attenuator stage is that a lot of effort is put into turning
off currents and changing voltage biases when the input stage is in the disabled mode.
Although it will be mentioned briefly later, the purpose is to avoid excessive vcB which
will in turn avoid breakdown. Many of the transistors in the current sources of Figure 7
have unseen current source transistors that are biased very precisely to avoid more than
about 4v VCB during normal operation. During the disabled mode, a lot of this biasing has
to be changed requiring that the biasing be rather complicated.
The time offset to different slew rates is very important to the comparator because
the change in this offset determines the dispersion. The differential pair stage connected
to this node puts a lot of capacitive loading on the vm2+ and vIN2- nodes (about 100ff).
With about 215Q (from the half circuit model) in series with this capacitance (Figure 7)
maintaining the timing accuracy seems rather unlikely. However, the accuracy needed
28
for a small dispersion is only a small offset in time (not voltage). If the vIN2+ node is
approximated by an RC circuit, then the error series is:
R
dvin(t)
et)= -RC- dt
2
+
dv i
(RC)
3
dt 2
d3 v (t)
dt
(4.8)
Using this error series in conjunction with the slew rate the time delay can be found:
dvi_(t)
d2V (t)
t-
The
ve
dvi(t)
dt
td
= -RC+ (RC) 2
dt2
dvi(t)
dt
-(RC)3
(4.9)
dt3
dvi()
dt
turns out to vary only about 1 Opsec for the worst-case expected input rise
times though there is a constant delay of about 2 1psec. Therefore, despite the long time
constant associated with the attenuating node, the dispersion is not effected very much.
4.4 Differential Pair Stage
The differential pair stage is important because it must maintain the high speed of
the signal while not causing more self-heating problems. The output of the differential
pair is a current signal that is differential in nature (iN+ and iIN-). This signal makes the
later stages of the comparator much easier to design because they will not have to deal
with common mode signal. Furthermore, the later stages will have a much more limited
range and a signal amplified from the input differential level.
There are several obstacles to deal with in the differential stage. The first is the selfheating effects of the differential pair. If the differential pair has a Ov vcB and the switch
current is 1 mA, there will be a change of power of 2mW between the transistors of the
differential pair. From equation 4.1 and the data in Figure 5, the change in vBE is going to
be on the order of 8mV. Because this stage is after the attenuation stage in the circuit, the
29
1-~ -7-
- -
-~
---
-
-.
-
5.3V
30000
Q30
0pm
5P "!
034
023
5p.
033
54M
31
5pm M
V.
022
21
PM
15FE
000
6p
5P1
5005.
.6pF
025
Q24
020
1000n0
029
I---AAA,
4.2
462
2Q7
-6.2
q-3V
-3V.
Figure 9: Self-Heating Compensation
Vid
is going to be reduced by a factor of 0.6 at this point. Therefore the total input offset
that would be added would be about 13mV without compensation. In order to
compensate for the change in power, emitter followers are placed in series with the
differential pair with the opposite change in power (Figure 9). They are the same size so
that they have the same thermal time constants, and because the collectors of the emitter
followers can have any voltage, the voltage is varied at their collectors to create the
power change of the differential pair. In order to create this change in voltage, a dummy
differential pair (Q26 and Q27) is set up so that the collector currents switch at
approximately the same rate as the comparator. The collector currents are buffered
through a low pass filter because the differential pair would switch very quickly even on
slow rise times injecting a lot of current from
VLEVEL+
and vLEVEL- through C, into the
vin2+ and vin2- nodes. This might not be a problem for fast rise time signals; however,
30
with slower rise time signals the amount of current injected would be enough to throw
30mV of signal into the node for a short period of time. The end result is a change in VCB
and therefore power of the emitter followers in the signal path in order to compensate for
the power change in the main differential pair.
A comparator's purpose is to differentiate between voltages. Therefore it is
forced to operate around the switch points of non-linear elements like transistors or
diodes. The differential pairs of operational amplifiers reside with their inputs close
together most of the time. However, with comparators, there is no feedback keeping the
inputs within close proximity, and therefore the differential pair produces a rather
unusual switch behavior.
In order to understand the switching of the differential pair to a rising signal, it is
helpful to see what a fast rising edge applied to one side of the differential pair looks like.
Vcc
Q100
Q101
Q0
Q201
<Q202
1202
(A)
(B)
Figure 10: Differential Pair Switching Example
The C, capacitor value varies from around 20fF when switched off to 27fF at
ImA (more when parasitic capacitance is included). In contrast C,. is a negligible 3fF. As
shown in Figure 1 OA, as a step is applied with 10% overdrive, the charging of C, draws
current away from the differential pair making the differential current at the output nearly
zero because most of the current is going from the emitter to the base. The resulting
31
output current waveform is shown in white in Figure 11 for a fast signal. This waveform
shows how neither transistor has a substantial amount of current running through it, even
though in the end, it switches accurately.
Figure 11: Wave Form Simulation
In order to make the transition more clear, a cross-Darlington circuit was designed
(Figure lOB and implemented in Figure 12). The theory is that emitter followers in
front of each input to a differential pair with a current source biasing should only have a
change of current equal to the base current change of the differential pair. Very little of
this current will be biasing current, and the rest will be that current which escapes from
the differential pair through Cg. This change of current will go through the emitter
follower and is fed back around to the collector of the opposite stage. In effect, these
32
--
~.
-
III.
-~ -
-
----
--
--
- -
-
---
- -.-- -
- ------
-
-~
-
Latch Stage
7
057
CofBuffer
V.-
052
Buffer
Attenuator
Stage
0563
.2
B52Atenuator
IL,2
064
)~ICAI
-6.2y
Stage
I.iM
1
Figure 12: Differential Stage
emitter followers act also as common base circuits. They do not turn on and off like the
differential pair, so they operate at a high speed. The resulting output current waveform
from a cross-Darlington is shown in gray in Figure 11. Depending on the rise time, there
is a fair amount of common mode noise associated with the output signal which is
expected from the current resulting from charging nodes on a rise edge, and discharging
nodes on a falling edge. Although the differential signal still has significant delay and a
little added power, the results of using this cross-Darlington configuration is a much
sharper waveform.
4.5 The Latch Stage
The next stage is the latch stage. All the complexity of previous stages leaves this
stage moderately simple. The current input from the previous stages are setup to be
switched on and off. A dummy current switches on to maintain the same voltage levels
while the
33
5.3v
Q772
0u751
Q84
085
ow3
Q52
081
OW0
07a
079
7
7
Differential Stage
Figure 13: Latch Stage
circuit is latched. The resistors are set to 5000 to provide a differential gain of about 8.3.
The gain is good because it was enough to reduce the self-heating offset effects.
However, it is not large enough to slow down the switching differential latch stage or to
create such a large differential voltage level on the latch differential pair that the
waveform of Figure 11 (white) shows up.
Q72 and Q73 are in the emitter follower configuration to buffer the comparator
signal to the actual latch differential pair. The latch differential pair is built out of large
1 Ogm transistors. In simulation testing, it was found that the large latching transistors
cause Q72 and Q73 to ring too much due to the large capacitance of Q74 and Q75;
however, this problem was avoided by decreasing the current through Q72 and Q73 to
.5mA. The lower current was enough to provide high speed, yet low enough to reduce
the ringing significantly. The resistor in-between Q72 and Q73 is for self-heating issues.
The resistor makes the power through these emitter followers constant. Large sized
34
differential latching transistors were used because of their low thermal resistance making
self-heating less of a problem. Because the differential voltage level at this stage is
moderately low, the differential pair latches very accurately despite its size. When the
current is switched on through the differential-pair of the latching circuit, there is positive
feedback. The output current of the latching transistors is fed back to the 500Q resistors,
and the circuit becomes latched. When there is no current through the differential pair,
the circuit is transparent and the output is the continuous output of the comparator. A
small current (2gA) is maintained through the latching circuit throughout the operation.
This current keeps at least one of the transistors on so that the turn-on time of the
differential pair does not limit the time between latching.
One of the difficulties of the switching circuitry in this stage is in getting the
current to consistently switch into the latch stage. If the switching has its own selfheating timing problems, then all the work done to maintain good dispersion throughout
the circuit will be for naught. Based on the fact that there will be a 1 00psec rise time, the
VLATCH
signal is buffered and the level is shifted between emitter followers and
differential pairs to cancel out any self-heating problem for vLATCH2-
4.6 The Slave Latch
The slave latch is shown in Figure 14. The slave latch has a transparent state and
a latched state. However, the slave latch is transparent when the latch is active (VLATCH is
high), and it latches when the latch is transparent
(vLATCH
iS low). The end result of the
output is, therefore, the latched signal at the instant of the last rising edge. This design is
done so that the comparator output go into a 2GHz logic. It is critical that the slave latch
is be timed precisely as to not miss the state of the latch and to provide a clear signal.
35
The voltage buffers and level shifters that take
VLATCH to VLATCH2 for
the latch and slave
latch stages do maintain the timing. The output of this stage is simply buffered by some
emitter followers.
36
5.3V
f
Om
Om
CO
QI"
097
Cm
L-g
0692
C1195
nQ93CO4
Sta.
\6.-
+
+
C"
Q89
Figure 14: Slave-Latch
4.7 Disabled Mode
During the disabled mode of operation, much of the biasing circuitry changes to
lower the power and to eliminate much of the input current. The disabling is produced by
turning off and reducing current source currents as well as changing voltages
accordingly to avoid excessive vCB (over about 4v). Although there is quite a bit of
circuitry used to do this, it is more of an exercise in biasing than anything else. Although
simulations of the input leakage during the disabled mode are approximately InA or less
of current over all ranges, testing of previous designs show a lack of accuracy of the
software simulation models in comparison to real world measurements in dealing with
these characteristics.
37
Chapter 5: Simulation and Layout
5.1 Simulation
The final part of the design of the comparator was to simulate and layout the
circuit. Using Cadence Composer, Cadence Spectre, and HSpice software, and device
models with a known level of accuracy, the circuit was designed and debugged. The
circuit topology as described was used after reviewing previous designs, noting the
problems found in those designs, and reviewing several possible topologies. Self-heating
and poor differential switching are common problems in all high-speed comparators.
Simulations support a low dispersion of l2psec over a wide range of signals and a
varying offset of less than 5mV. The simulations also have helped to alleviated fears
about the amount of supply voltage noise in the comparator. The power came out to be
around 0.9 watts. Although this is more power than previous versions of comparators
designed at Teradyne, the tradeoff is performance.
5.2 Layout
The layout of the comparator is nearly complete in preparation of fabricating the
comparator onto a test chip. The comparator layout is geometrically complicated (Figure
15), though it is simply an attempt to keep the capacitance of all high-speed, highimpedance signal path wires at a minimum. Differential pairs are located close together
to avoid possible die temperature variations, and the circuit is setup up as symmetrically
as possible to avoid possible parasitic surprises. The fabrication will be on a 5-layer
38
aluminum metal process with maximum size capacitors at 1.7pF and resistors at 8k4.
As
seen in Figure 15, the layout also requires large wire widths and capacitors for the
incoming power supplies (left side of layout). Some large capacitors and resistors are
also used in this design taking up lots of die area. Again, the tradeoff is performance.
Figure 15: J2 Comparator Layout
39
A. BIBLIOGRAPHY
[1]
Paul R. Gray and Robert G. Meyer, Analysis andDesign ofAnalog Integrated
Circuit-
[2]
3 rd
ed. New York, NY: John Wiley & Sons, Inc., 1977.
James K. Roberge, OperationalAmplifiers: Theory and Practice. New York,
NY: John Wiley & Sons, Inc., 1975.
[3]
David Johns and Ken Martin, Analog IntegratedCircuitDesign. New York, NY:
John Wiley & Sons, Inc., 1997.
[4]
Kenneth S. Kundert, The Designer's Guide to Spice & Spectre. Boston, MA:
Kluwer Academic Publishers, 1995.
[5]
MAX9685: Ultra Fast ECL Output Comparator with Latch Enable. 1999.
Descriptionof one of the faster Comparators.
[6]
Barrie Gilbert, Design PracticesforIC Manufacture. Beaverton, OR: Analog
Devices Inc., 1996
[7]
Alan B. Grebene, Bipolar and MOS Analog Integrated Circuit Design. New York,
NY: John Wiley & Sons, Inc., 1984.
[8]
Jim Giles and Alan Seales, "A New High-Speed Comparator the Am685," in
Advanced Micro Devices Applications Guide. Sunnyvale, CA: Advanced Micro
Devices Inc., 1973.
[9]
Paul M. Solomon, "A Comparison of Semiconductor Devices for High-Speed
Logic," in Proceedingsof the IEEE, vol. 70, NO. 5, May 1982, pp. 1916-1925.
[10]
Behzad Razavi and Bruce Wooley, "Design Techniques for High-Speed, HighResolution Comparator," IEEE J.Solid-State Circuits,vol. 27, NO. 12, December
40
1992.
[11]
Mark Barber, "Subnanosecond Timing Measurements on MOS Devices using
Modem VLSI Test Systems" Proceedingsof the ITC. Murray Hill, NJ: 1978?
[12]
Frank Goodenough, "Linear Ics Attain 8-GHz NPNs, 4-GHz PNPs"
ElectronicDesign. December 19, 1991. pp. 35-45.
41