June 01, 2009
Lev Uvarov
Address Counter Register Group update
CNT_ETA – Eta Address Counter
This read/write register carries current value of the Address Counter for an array of Eta and Phi
Track Constraints. The default register value on power-up is zero. The counter auto-increments
on every access to the DAT_ETA register. The counter can be reset with the ACT_ACR
command.
Table 1: CNT_ETA Data Format for SP_FPGA
D15
X
0
D14
X
0
D13
X
0
D12
X
0
D11
D10
X
X
0
0
Not Used
D9
X
0
D8
X
0
D7
X
0
D6
X
0
D5
ETA5
ETA5
D4
D3
D2
D1
ETA4 ETA3 ETA2 ETA1
ETA4 ETA3 ETA2 ETA1
ETA Address Counter
D0
ETA0
ETA0
TRN
WR
RD
Here:
− X – Don’t care bit;
− ETA [5:0] = 0…40 – Address Counter.
Data Register Group update
DAT_ETA – Eta and PHI Track Constraints
This read/write register provides access to the register file content, which keeps a set of angle
constraints for collision and halo muons. The SP core logic uses these constraint, when it builds
tracks from the input stubs. The total number of constraints in the register file is 41. As a rule, all
constraints should be loaded or read out as an array of values, after resetting the register file
address counter with ACT_ACR/MA/SP/W/0x0008. Alternatively, when only single constraint
should be updated, the user may first download a constraint number in the address counter with
CNT_ETA/MA/SP/W/D=constraint_number, and then load a constraint value with
DAT_ETA/MA/SP/W/D=constraint_value.
Constraint numbers, ranges and default values are listed in Table 2.
Table 2: DAT_ETA Data Format for SP_FPGA (SP Core Version 2)
0
1
Minimum eta difference for track cancellation logic
Minimum eta difference for halo track cancellation logic
Value
Range
0-31
0-31
2
3
4
5
6
7
8
9
Minimum eta for ME1-ME2 collision tracks
Minimum eta for ME1-ME3 collision tracks
Minimum eta for ME2-ME3 collision tracks
Minimum eta for ME2-ME4 collision tracks
Minimum eta for ME3-ME4 collision tracks
Minimum eta for ME1-ME2 collision tracks in overlap region
Minimum eta for ME2-MB1 collision tracks
Minimum eta for ME1-ME4 collision tracks
0-127
0-127
0-127
0-127
0-127
0-127
0-127
0-127
#
Constraint Name
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Default
Value
8
8
22
22
14
14
14
14
10
22
June 01, 2009
Lev Uvarov
10
11
12
13
Minimum eta difference for ME1-ME2 (except ME1/1) halo tracks
Minimum eta difference for ME1-ME3 (except ME1/1) halo tracks
Minimum eta difference for ME1/1-ME2 halo tracks
Minimum eta difference for ME1/1-ME3 halo tracks
0-127
0-127
0-127
0-127
8
19
19
30
14
15
16
17
18
19
20
21
Maximum eta for ME1-ME2 collision tracks
Maximum eta for ME1-ME3 collision tracks
Maximum eta for ME2-ME3 collision tracks
Maximum eta for ME2-ME4 collision tracks
Maximum eta for ME3-ME4 collision tracks
Maximum eta for ME1-ME2 collision tracks in overlap region
Maximum eta for ME2-MB1 collision tracks
Maximum eta for ME1-ME4 collision tracks
0-127
0-127
0-127
0-127
0-127
0-127
0-127
0-127
127
127
127
127
127
24
24
127
22
23
24
25
Maximum eta difference for ME1-ME2 (except ME1/1) halo tracks
Maximum eta difference for ME1-ME3 (except ME1/1) halo tracks
Maximum eta difference for ME1/1-ME2 halo tracks
Maximum eta difference for ME1/1-ME3 halo tracks
0-127
0-127
0-127
0-127
14
25
25
36
26
27
28
29
30
31
32
Eta window for ME1-ME2 collision tracks
Eta window for ME1-ME3 collision tracks
Eta window for ME2-ME3 collision tracks
Eta window for ME2-ME4 collision tracks
Eta window for ME3-ME4 collision tracks
Eta window for ME1-ME2 collision tracks in overlap region
Eta window for ME1-ME4 collision tracks
0-255
0-255
0-255
0-255
0-255
0-255
0-255
4
4
4
4
4
4
4
33
34
35
36
Maximum phi difference for ME1-ME2 (except ME1/1) halo tracks
Maximum phi difference for ME1-ME3 (except ME1/1) halo tracks
Maximum phi difference for ME1/1-ME2 halo tracks
Maximum phi difference for ME1/1-ME3 halo tracks
0-1023
0-1023
0-1023
0-1023
64
64
64
64
37
38
Minimum phi difference for track cancellation logic
Minimum phi difference for halo track cancellation logic
0-4095
0-4095
128
128
39
40
Parameter for the correction of misaligned 1-2-3-4 straight tracks
Parameter for the correction of misaligned 1-2-3-4 curved tracks
0-4095
0-4095
60
200
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June 01, 2009
Lev Uvarov
CSR_SCC – SP Core Configuration
This read/write register keeps the SP core configuration options. The register is protected
against accidental accesses: in order to get VME access to this register the SP should be set to the
VME fast control mode.
Please note that the register format changes for every core version. Version bits are read-only
bits. Some fields have a limited set of valid values. Using not listed values may result in an
unpredicted core behavior.
Table 3: CSR_SCC Data Format for SP_FPGA (SP Core Version 0)
D15
X
0
D14
D13
X
X
0
0
Not Used
D12
X
0
D11
D10
X
X
0
0
Core Version
D9
X
0
D8
DTE
DTE
D7
D6
X
X
0
0
Mode Control
D5
D4
Q4EN Q3EN
Q4EN Q3EN
D3
D2
D1
D0
X
X
X
BXE
0
0
0
BXE
Bunch Crossing Analyzer
TRN
WR
RD
Here:
−
−
−
−
−
X – Don’t care bit for writes and zero for reads;
BXE = 0 (default) / 1 – disable (default) / enable Bunch Crossing Analyzer;
DTE = 0 (default) / 1 – disable (default) / enable Drift Tube data inputs to SP Core;
Q3EN = 0 (default) / 1 – disable (default) / enable processing stubs with Quality = 3;
Q4EN = 0 (default) / 1 – disable (default) / enable processing stubs with Quality = 4.
Table 4: CSR_SCC Data Format for SP_FPGA (SP Core Versions 1) +5 bx release
D15
X
0
D14
D13
X
X
0
0
Not Used
D12
X
0
D11
D10
X
X
1
0
Core Version
D9
D8
PRE1 PRE0
PRE1 PRE0
Pre-Trigger
D7
DTE
DTE
D6
D5
D4
X
Q4EN Q3EN
0
Q4EN Q3EN
Mode Control
D3
D2
D1
D0
X
X
BXA1 BXA0
0
0
BXA1 BXA0
Bunch Crossing Analyzer
TRN
WR
RD
Here:
−
−
−
−
−
−
X – Don’t care bit for writes and zero for reads;
PRE [1:0] = 1, 2 (default), 3 – Pre-Trigger control;
DTE = 0 (default) / 1 – disable (default) / enable Drift Tube data inputs to SP Core;
Q3EN = 0 (default) / 1 – disable (default) / enable processing stubs with Quality = 3;
Q4EN = 0 (default) / 1 – disable (default) / enable processing stubs with Quality = 4;
BXA [1:0] = 0, 1, 2 (default) – Bunch Crossing Analyzer history control.
Table 5: CSR_SCC Data Format for SP_FPGA (SP Core Versions 1) +4 bx release, Sep 10, 2008 and later
D15
D14
X
X
0
0
Not Used
D13
D12
HDL1 HDL0
HDL1 HDL0
Halo Delay
D11
D10
X
X
1
0
Core Version
D9
D8
PRE1 PRE0
PRE1 PRE0
Pre-Trigger
D7
DTE
DTE
D6
D5
D4
X
Q2EN Q1EN
0
Q2EN Q1EN
Mode Control
D3
D2
D1
D0
X
X
BXA1 BXA0
0
0
BXA1 BXA0
Bunch Crossing Analyzer
TRN
WR
RD
Here:
− X – Don’t care bit for writes and zero for reads;
− HDL [1:0] = 0 (default), 1, 2, 3 – Halo Trigger Delay = additional latency of 0, 0, 1, 2
for Halo Triggers; applies to output 3 only.
− PRE [1:0] = 1, 2 (default), 3 – Pre-Trigger control;
− DTE = 0 (default) / 1 – disable (default) / enable Drift Tube data inputs to SP Core;
− Q1EN = 0 (default) / 1 – disable (default) / enable processing stubs with Quality = 1;
− Q2EN = 0 (default) / 1 – disable (default) / enable processing stubs with Quality = 2;
− BXA [1:0] = 0, 1, 2 (default) – Bunch Crossing Analyzer history control.
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June 01, 2009
Lev Uvarov
Table 6: CSR_SCC Data Format for SP_FPGA (SP Core Versions 2), Jun 01, 2009 and later
D15
X
0
D14
D13
X
X
0
0
Not Used
D12
X
0
D11
D10
X
X
0
1
Core Version
D9
D8
PRE1 PRE0
PRE1 PRE0
Pre-Trigger
D7
DTE
DTE
D6
D5
D4
WPHI HDL1 HDL0
WPHI HDL1 HDL0
Mode Control
D3
D2
D1
D0
X
X
BXA1 BXA0
0
0
BXA1 BXA0
Bunch Crossing Analyzer
TRN
WR
RD
Here:
−
−
−
−
−
X – Don’t care bit for writes and zero for reads;
PRE [1:0] = 1, 2 (default), 3 – Pre-Trigger control;
DTE = 0 (default) / 1 – disable (default) / enable Drift Tube data inputs to SP Core;
WPHI = 0 (default) / 1 – enable Wider Phi extrapolation
HDL [1:0] = 0 (default), 1, 2, 3 – Halo Trigger Delay = additional latency of 0, 0, 1, 2
for Halo Triggers; applies to output 3 only.
− BXA [1:0] = 0, 1, 2 (default) – Bunch Crossing Analyzer history control.
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