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[4] N. D. Jankovic, “Pre-turn-on source bipolar injection in graded
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[5] A. Amerasekera, S. Ramaswamy, M.-C. Chang, and C. Duvvury, “Modeling MOS snapback and parasitic bipolar action for circuit-level ESD
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[7] A. Amerasekera, S. Ramaswary, M. Chang, and C. Duvvury, “Modeling MOS snapback and parasitic bipolar action for circuit-level ESD
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[8] S. L. Lim, X. Y. Zhang, Z. Yu, S. Beebe, and R. W. Dutton, “A computationally stable quasiempirical compact model for the simulation of
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breakdown model for short-channel MOSFET’s,” IEEE Trans. Electron.
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[21] Smart SPICE C-Interpreter User’s Manual, 2000.
Test Vector Generation for Charge Sharing Failures in
Dynamic Logic
Keerthi Heragu, Manish Sharma, Rahul Kundu, and R. D. Blanton
Abstract—Dynamic logic is increasingly becoming a logic type of choice
for designs requiring high speed and low area. Charge sharing is one of
many problems that may cause failure in dynamic logic circuits due to their
low noise immunity. The authors address the charge-sharing noise issue.
Specifically, they develop an accurate but tractable model for analyzing
charge sharing that avoids costly Hspice simulations. The model is used
to generate test vectors using a generalized ATPG tool. The charge-sharing
model and the corresponding tests are validated using Hspice simulations
on industrial circuits and it is also demonstrated that test vectors that establish high amounts of charge sharing could be generated for most domino
gates.
Index Terms—ATPG, charge sharing, dynamic logic.
I. INTRODUCTION
Dynamic logic design is increasingly being used for high-speed circuit design. Without loss of generality, we restrict our discussion to
domino logic circuits while using the terms “domino” and “dynamic”
interchangeably. A CMOS dynamic logic gate is different from a static
logic gate in that it either does not have the P-pull up network or it
does not have the N-pull down network. Such circuit implementations
are known as N-Dynamic and P-Dynamic logic circuits, respectively.
An example of an N-Dynamic logic implementation of a gate with
a boolean function Z = f[(D + C )E + B ]G + AgF is shown in
Fig. 1. The operation of a dynamic circuit can be illustrated using this
example. When CLK is low, the precharge transistor is ON and the
foot-switch transistor is OFF, therefore the output node 1 is charged
to a high voltage (this is known as the precharge phase). We will refer
to node 1 as the “output” node although the actual output of the gate
is Z. When the clock goes high, the precharge transistor turns OFF and
the foot-switch transistor turns ON and depending on the values of the
inputs A-G, the output node 1 is either pulled to zero (if there is a path
to ground from node 1) or it remains floating at a high voltage because
of the charge stored at the node (this is known as the evaluate phase).
Notice that the foot-switch can be avoided if it is ensured by design that
no path to ground is ON during the precharge phase.
The absence of a P-pull up network or an N-pull down network
reduces the capacitance on the output node, thereby improving speed
and reducing area. However, dynamic circuits suffer from various
drawbacks, prominent among them being charge sharing. In order
to understand how charge sharing can cause a dynamic circuit to
function erroneously, consider the circuit in Fig. 1. Assume that
during the precharge phase all the inputs are zero so that only the
output node 1 is precharged. Now, if during the evaluate phase the
inputs take on the following values: B = C = E = G = 1 and
A = D = F = 0, then the charge on node 1 gets shared among
nodes 1–4. Since there is no pull-up network, this sharing of charge
will cause the voltage on node 1 to drop and if it drops below
the switching point of the inverter, the output Z will erroneously
transition to a logic 1 (whereas it should remain at logic 0).
Manuscript received July 5, 2001; revised March 14, 2002 and May 22, 2002.
This paper was recommended by Associate Editor S. Reddy.
K. Heragu is with Texas Instruments Inc., Dallas, TX USA (e-mail:
heragu@ti.com).
M. Sharma is with the University of Illinois, Urbana, IL USA (e-mail:
msharma@crhc.uiuc.edu).
R. Kundu and R. D. Blanton are with Carnegie Mellon University, Pittsburgh,
PA 15213 USA (e-mail: {rkundu; blanton}@ece.cmu.edu).
Digital Object Identifier 10.1109/TCAD.2002.804377
0278-0070/02$17.00 © 2002 IEEE
© 2002 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media,
including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution
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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 21, NO. 12, DECEMBER 2002
Fig. 1. An N-dynamic logic circuit implementing the boolean function
[( + ) + ] +
.
Fig. 3.
Weak p-feedback used to alleviate charge sharing.
Fig. 4.
Transistor model for an NMOS transistor.
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=
Fig. 2. Block diagram of a dual-rail logic circuit.
A considerable amount of work has been done on modeling
other kinds of faults in dynamic circuits. For example, [1] considers
transistor stuck-on and stuck-off failures, [2] and [3] analyze IDDQ
failures, [4] considers the test of resistive-bridge defects, [5] and
[6] consider path-delay tests, and [7] considers crosstalk switch
failures in domino logic. However, little consideration has been
given to fault modeling charge sharing for manufacturing test. The
charge sharing problem was first considered by Shubat et al. [8].
Using a quantitative analysis of charge sharing, an expression was
developed to predict the voltage drop due to charge sharing. Some
circuit techniques were also proposed to alleviate charge sharing.
Chi et al. [9] presented a test generation technique to detect charge
sharing failures in a dynamic gate. The basis for this work was
the notion of CS-vulnerability of a dynamic gate. CS-vulnerability
is the ratio of the total source and drain junction capacitances of
the on-transistors in the evaluation chain, to the input capacitance
of the inverter of the dynamic gate. The work of [9], however,
did not take into account the effect of the gate capacitances of the
on-transistors in the evaluate chain. Nor did the authors explain how
source and drain capacitances are derived given that the capacitances
are voltage dependent. In certain circuits, depending on the circuit
parameters, such an imcomplete analysis may incorrectly ignore
probable charge-sharing related faults. In a similar work, domino
circuits are synthesized to minimize charge sharing [10].
Techniques used to overcome the charge-sharing problem include
the use of dual-rail logic, middle precharge transistors, and p-feedback
(or n-feedback) transistors. In dual-rail logic, a complementary logic
gate is implemented for every gate in the circuit (thus for every gate
output in the circuit, an output with the complementary logic value is
also present, hence the name “dual rail”). These complementary nodes
are then cross coupled as shown in Fig. 2. Whenever the output node
Y is at logic 1, it is pulled up through the cross-coupling transistor
T2 and when Y is at logic 0, the complementary output is pulled up
through transistor T1. The effect of charge sharing can also be reduced
by having additional precharge transistors that charge up internal nodes
(in addition to the output node) during the precharge phase. In addition,
weak pull up p-feedback transistors, also called “keepers,” can be used
as shown in Fig. 3. When the output node 1 is floating at logic 1, it is
pulled up by the feedback transistor T1.
The presence of these extra transistors that do not directly determine
the logic behavior of the circuit raises concerns about their testing.
Clearly, test generation based on a purely logical fault model cannot be
used here. In this paper, we propose the use of charge-sharing phenomenon to generate tests for stuck-open faults on these transistors
and any other fabrication variaton or defect that may exacerbate
charge sharing beyond what was expected in the design process.
In particular, if we invoke the worst case charge sharing in a dynamic
circuit, then the output may erroneously be forced to a wrong value
in the presence of a stuck-open fault at one of the feedback or middle
precharge transistors or due to some other fabrication irregularity. The
resulting fault effect can then be propagated through the circuit to a
primary output, where it can be observed. In order to accomplish the
above, we have to fully understand the phenomena of charge sharing.
The next section describes this in greater detail.
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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 21, NO. 12, DECEMBER 2002
Fig. 6. RC-network model simplication for operation in the steady state when
the network is undriven.
2) The capacitances associated with a transistor are almost constant
when the transistor is operating in the linear region and the cutoff
region.
3) The transistor network reaches a steady state before the end of
evaluate phase and in steady state each transistor is operating in
the linear region. This is valid when the gate voltage is sufficiently higher that the source voltage.
If the network is undriven, then no current flows through the network
in steady state. All circuit nodes can therfore be collapsed into a single
node and the network reduces to a simple capacitive circuit as shown
in Fig. 6, where the capacitance values are defined as follows:
CV dd =
(all capacitor
values connected
between an internal node
CGnd =
and power supply V dd)
(all capacitor
(1)
values connected
between an internal node
Fig. 5. RC-network model for the circuit in Fig. 1 , where all capacitances in
parallel have been combined into a single capacitor.
II. CHARGE SHARING IN DYNAMIC CIRCUITS
Hereafter, we will use the term leaf cell when referring to a dynamic
logic gate. We have seen that charge sharing among various circuit
nodes can cause the output to take a wrong logic value. In analyzing the
effects of charge sharing in dynamic circuits, we can model the MOS
transistor as a resistance between its source and drain terminals and
capacitances between various terminals as shown in Fig. 4. In general,
the value of capacitances and the resistance are a nonlinear function of
the voltages at the terminals of the transistor. Using this model of the
transistor, we can represent a leaf cell as an RC-network. Thus, for example, the circuit in Fig. 1 can be modeled as shown in Fig. 5. Now if
the input vector is such that no path to ground is ON during the evaluate phase, the RC-network is said to be “undriven” and charge sharing
can cause a drop in the voltage at the output node. In such a case, the
voltage at the output node at any given time, specifically at the end
of a the evaluate phase, can be evaluated by solving the RC-network,
provided that the initial voltages at all the nodes are known. Since the
values of resistors and capacitors in the network are nonlinearly related to voltages in the network, solving the network is not trivial and
an accurate value for the final voltage at the output node can only be
determined by actual SPICE simulations. However, in the context of
test generation based on charge sharing, as will be shown in the next
section, we are only concerned with a reasonably accurate method for
ranking different input vectors pairs according to the degree to which
they invoke charge sharing. Thus, the transistor model can be simplified based on the following assumptions.
1) The resistance RDS for a transistor in cutoff is infinite, and as
a result, a negligible amount of charge leaks from the network
when the network is undriven.
and Ground)
(2)
Therefore the capacitor values in the collapsed C-network can be
determined from the circuit structure and the input vector. For example,
if the input vector B = C = E = G = 1 and A = D = F = 0 is
applied to the circuit in Fig. 1, then CV dd = C2 + C3 + C6 + C7 +
C8 + C9 + C10 + C11 + C16 + C17 and CGnd = C4 + C5 + C12 +
C13 + C14 + C15 + C18 + C21 + C24 . Once the collapsed C-network is
determined, the final voltage on the output node can be easily computed
using the equation given as follows:
Vout = V Cdd C+V ddC + Qi
V dd
Gnd
1
(3)
where Qi is the total initial charge stored in the capacitors. From (3)
it is clear that for an input vector pair to invoke the worst case charge
sharing effects, the first vector should drain as many nodes as possible
to minimize Qi and the second vector should minimize the ratio of
CV dd to the total capacitance connected to the output node.
III. CHARGE-SHARING TEST GENERATION
As already described, the phenomena of charge sharing can be
used to generate vector pairs to test for stuck-open faults on the
transistors that are added to a dynamic circuit to alleviate the effects
of charge sharing or any other fabrication irregularity that adversely
affects charge sharing. Thus, if a vector pair that evokes the worst case
charge sharing in a leaf cell is used to exercise the circuit, it can catch
stuck-open faults on protection devices such as feedback transistors,
middle-precharge transistors, or cross-coupling transistors by forcing
the output to assume a wrong value. Tests generated using a logical
fault model may not be able to detect these defects.
Test generation based on charge sharing is a two-step process. In the
first step, for each type of leaf cell in a given circuit, the k -worst vector
pairs, in terms of the degree to which they invoke charge sharing in the
leaf cell, are determined assuming that all the inputs to the leaf cell are
fully controllable and all the outputs are fully observable. These vectors
may not cover faults on all middle precharge transistors as illustrated
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 21, NO. 12, DECEMBER 2002
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Fig. 8. Algorithm for generating an ordered list of second vectors.
Fig. 7. Leaf cell with untested fault on a middle precharge transistor.
by the circuit of Fig. 7. Assume that the vector pair A = 10, B =
10, C = 10, D = 11, E = 11, F = 11 and G = 10 invokes
the worst case charge sharing. Clearly, this vector pair cannot detect a
stuck-open fault on the middle precharge transistor T1 because A = 0
in the second vector prevents node ai from being involved in charge
sharing. Therefore, additional vector pairs are added to the above set
of k -worst vector pairs to ensure that faults on all the middle precharge
transistors are covered. This is accomplished by assuming that only
a single fault is present and then explicitly “faulting” each uncovered
middle precharge transistor (i.e., removing it from the circuit) and again
generating k -worst vector pairs for the modified circuit.
In the second step, these vectors are justified at the inputs of a leaf
cell wherever it occurs in the circuit and the output of the leaf is sensitized so that it can be observed at a primary output of the circuit. The
worst k -vector pairs for a leaf are then tried in a sequential manner for
each instantiation of the leaf cell in the circuit. The worst vector pair is
tried first and if that cannot be justified and observed then the “second
worst” vector is tried for justification and so on until the set of test
vector pairs is exhausted. The process is then repeated for test vector
pairs required for covering faults on middle precharge transistors. The
parameter k denotes the number of test vector pairs to be tried and can
be chosen by the user; it represents the tradeoff between test generation
time and fault coverage. If the value of k is large, there is more chance
of finding a vector pair that can be justified in the circuit. The next two
sections describe how both of these steps are implemented in detail.
IV. WORST CASE CHARGE SHARING
A vector pair invokes charge sharing in a leaf cell if the second vector
does not turn ON any path between the output node and ground during
the evaluate phase. The final voltage on the output node after charge
sharing can be estimated by (3), as described in Section II. The final
voltage estimate gives a measure of the degree to which charge sharing
is invoked by the vector pair. Therefore, the problem of determining
k -worst charge sharing vectors can be stated as the problem of finding
k -vector pairs that have the k -minimum final voltage estimates. Note
that the final voltage estimate given by (3) depends on both vectors in
the vector pair. The first vector determines the initial charge Qi on all
the nodes in the network and the second vector determines the various
capacitance values. Therefore, in a way, the problem is a two-dimensional optimization process. However, we use a two-step process to decouple the problem into two smaller problems. First, the second vector
is determined separately, and next the first vector is determined based
on each second vector as described below.
A. Step 1: Second Vector Ordering
In the first step it is assumed that at the beginning of the second
precharge phase of the test cycle all nodes in the circuit have zero
charge (i.e., the first vector has drained all the nodes in the circuit).
With this assumption, the final voltage can now be estimated solely
based on the second vector. An exhaustive list of all possible second
vectors is ranked in decreasing order of final voltage estimates.
Fig. 8 gives an outline of the overall algorithm. The routines Estimate_Ground_Capacitance and Estimate_VDD_Capacitance essentially evaluate (4) and (5), respectively, for a given input vector
Gnd =
C
i2ND
t2ON TX
+
V dd =
C
i2ND
d LINEAR
C
t2OFF TX
t2ON TX
g OFF
(4)
C
g LINEAR
C
:
(5)
The equation terms are defined as follows:
all nodes connected to the output node when vector
V
V2 is applied;
T Xi
all transistors connected to node i;
ON T Xi
all transistors connected to node i whose input is
high;
OFF T Xi
all transistors connected to node i whose input is
low;
Cd LINEAR
drain capacitance of transistor t in the linear region;
Cg LINEAR
gate capacitance of transistor t in the linear region;
Cg OFF
gate capacitance of transistor t in cutoff.
Equations (4) and (5) have been directly derived from the definitions
of CV dd and CGnd given in (1) and (2) of Section II.
During the precharge phase, some amount of charge Qis is stored
on the output node and the middle precharge nodes in the circuit. Assuming that all the inputs are zero during the precharge phase (which
is usually the case due to design of dynamic circuits), Qis can be determined as follows:
ND
is =
Q
i2MP
i
V
t2TX
g
d
(C OFF + C OFF )
(6)
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Fig. 9.
Cd
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 21, NO. 12, DECEMBER 2002
Example circuit to demonstrate Step 2.
drain capacitance of transistor t in cutoff;
all precharge nodes (including the output node) connected
to the output node when vector V2 is applied;
All other terms are as defined before.
For example, for the circuit in Fig. 1 there are no middle precharge
nodes. So, for calculating Qis , the only node that we need to consider
is the output node 1. For node 1, the capacitors C2 , C4 , C6 , C8 , C13
belong to i2MP
t2T X Cg OFF and the capacitors C3 , C14 belong to i2MP
t2T X Cd OFF , Vi for node 1 is Vdd as this node
was charged to Vdd during the precharge phase.
Note that capacitance values for the cutoff region are used because
all the inputs are assumed to be zero in the precharge phase. The final
voltage Vi on a middle precharge node is a function of the size of the
precharging transistor and the sizes of the other transistors connected
to it. We use an empirical characterization of this relationship to fix Vi
for some middle precharge node i. In the algorithm of Fig. 8, routine
Estimate_Initial_Charge() calculates Qis .
Thus, at the end of the first step we have an ordered list of second
vectors in terms of the degree of charge sharing they invoke, assuming
that the first vector drains all the internal nodes. In the second step,
first vectors are determined thus completing the process of generating
k -worst vector pairs.
OFF
Fig. 10.
Example domino circuit.
M PV
B. Step 2: Determining First Vectors
The goal here is to find a first vector V1 corresponding to a second
vector V2 (from among the list of second vectors generated in the first
step) that drains all the internal nodes n 2 N DV . This is done as
follows: First a boolean SOP expression Pi is determined for each internal node i in the circuit. The expression Pi is a function of the input
literals to the leaf cell and is one where the input vector is such that
node i is connected to ground and is zero otherwise. This boolean expression is determined by exhaustively traversing each path from the
node i to ground. A first vector V1 that connects all the nodes in the
set n 2 N DV can therefore be found by taking the logical AND of all
the expressions Pn . If the logical AND is not identically equal to zero
then we have found the required vector V1 which is the input vector
corresponding to any product term in the SOP expression. An example
is shown in Fig. 9. Let us assume that we want to discharge the nodes
i1 and i3. The expression for discharging i1 is B:C (as determined by a
traversal from node i1 to ground) and the expression for discharging i3
is (E :F + A:B ). So, the combined expression for discharging both i1
and i3 is B:C:(E :F + A:B ) = B:C:E :F which implies that B = 1,
C = 1, E = 1, F = 1 is a valid vector for discharging i1 and i3.
If, however, the logical AND is identically equal to zero then no such
vector exists. This essentially means that all nodes in N DV cannot be
drained simultaneously. An example is shown in Fig. 9 where, if we
want to discharge both the nodes i1 and i5, the combined expression
for that is B:C:B = 0. This implies that the nodes i1 and i5 cannot
be drained simultaneously. Therefore, only a subset of these nodes can
possibly be drained by some first vector. In order to find such a subset
with the overall result that the vector pair produces the maximum possible charge sharing effects, we can use the final voltage equation in
the algorithm of Fig. 8. The only term that gets affected if all the internal nodes cannot be drained by the first vector is Qis , since the initial charge in the network is greater. The value of this additional initial
charge for a subset SN DV can be
SND
Qia
=
i2
= SND
(V dd 0 VT )
t2T X
(Cg
OFF
+ Cd
OFF
)
(7)
where VT equals threshold voltage and the other terms are as defined
before.
Therefore, the final voltage for each possible subset SN DV of
N DV can be estimated as
nal voltage =
V dd
1
CV
dd
+
CV dd
Qis
SND
+ Qia
+ CGnd
:
(8)
In this manner, the subsets are ordered by their final voltage estimates. Each subset yields a first vector that is obtained by taking
the AND of the boolean expression Pi for all the nodes in it as explained above. The vector pairs thus obtained are inserted into the list
of second vectors at appropriate positions according to their voltage
estimates. The entire process is repeated for successive second vectors
until k -worst vector pairs are obtained.
It is to be noted that the selection of the first vector only ensures that
for each intermediate node, there is an on path that connects the intermediate node to ground, so that the intermediate node is discharged
during the evaluate phase of the first vector. However, it may happen
that in the first vector, there is also an on path that connects the intermediate node to the dynamic node. This will not have any effect during
the evaluate phase, but after the evaluate phase of the first vector, if the
path connecting the intermediate node to ground turns off before the
path connnnecting the intermediate node to the dynamic node, the intermediate node may be charged somewhat during the precharge phase.
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 21, NO. 12, DECEMBER 2002
1507
However, the resulting error is typically negligible since the charging
process described above occurs for a very short duration through a series combination of a partially on pmos (main precharge transistor that
is turning on) and a partially on nmos (that is turning off). Hence, the
charging current will be negligible.
C. Step 3: Second Vector Redundancy
Since the second vectors in the k -worst vector pairs are determined
by exhaustive enumeration in Step 1, some bits in a second vector
V2 may be redundant. As an example consider the circuit in Fig. 1.
The vectors A = F = B = G = 0, C = D = E = 1 and
A = B = G = 0, C = D = E = F = 1 are equivalent as far
as charge sharing is concerned. Thus the input F is redundant. In order
to avoid over specifying the each vector we have to identify such inputs
and assign a don’t care value to them. This is done using the following
fact: for a second vector V2 , all inputs that are connected to transistors whose terminals are connected to nodes that are not in N DV are
redundant. Based on this observation all redundant bits in each of the
second vectors in the k -worst vector pairs are identified and assigned
the don’t care value.
Fig. 11.
Workaround circuit for Fig. 10 .
V. ATPG USING FAULT TUPLES
After the second step, we have an ordered set of gate input signal
assignments ranked according to the amount of charge sharing they
create. Now we want to justify each of these signal assignments in order
and propagate the resulting error. To generate tests according to the
order of most charge sharing to least charge sharing, we use a fault tuple
based test generator [11]. A fault tuple is a three-tuple represented as
hl; v; ti, where l is a signal line, v is a value, and t is a clock cycle
constraint. The value set for each of the elements is given as follows:
lines
01
+
l 2f
v 2f ;
t 2fi; i
g
; D; Dg
N; i >; i ;
...
g:
If v 2 f0; 1g, then the signal l must be controlled to v within the
clock cycle range described by t. If v 2 fD; Dg, then the signal line
must be activated and the resulting error discrepancy (D or D ) must be
propagated to an observable point.
Utility of fault tuples for the charge-sharing test generation problem
stems from their ability to be combined. For example, assume that a
charge sharing test for the circuit of Fig. 7 requires A = D = 1 to be
true in the first vector and D = 1 and G = 0 to be true in the second
vector. The conjunction of fault tuples
P
=
h
A; 1; iihD; 1; iihD; 1; i + 1ihG; 0; i + 1ihY; D; i + 1i 1 1 1
captures the partial testability requirements. The product P is considered to be deteced only if A and D are set to one in some clock cycle i,
G and 0 are set to zero in the very next clock cycle i +1, and the error resulting at Y is propagated to an observable point. Other products, each
of which represent a vector pair that causes charge sharing, can be combined disjunctively (i.e., “ORed” together) to represent a charge sharing
fault F = P1 + P2 . . . Pn . Our fault tuple test generator attempts to
generate tests for a fault F by considering each product in the order as
it appears in F . If it succeeds in generating a test for a given product, it
reports the test and disregards any remaining products. If not, it tries to
satisfy the next product. Thus, if the product corresponding to the worst
case charge sharing appears first in F , the product for the next worst
case of charge sharing appears next in F and so on, the test generator
will automatically find a vector that generates the worst case charge
sharing. If, however, separate faults are considered for each product
(i.e., F1 = P1 ; F2 = P2 . . . Fn = Pn ) then tests can be generated for
every possible case of charge sharing (if one exists).
Fig. 12. SPICE simulation results for ordered vector pairs for: (a) Ckt. C and
(b) Wallace-tree multiplier.
VI. INTERFACE TO A TRANSITION TEST TOOL
The following section describes a procedure to generate a vector that
exhibits the worst case charge sharing in a leaf cell by directly modifying the circuit so that any off-the-shelf automatic stuck-at/transition
fault test pattern generator (such as Mentor Fastscan) can be used to
generate vectors for charge sharing. The idea is illustrated in Fig. 11
using the example circuit of Fig. 10.
Fig. 11 shows additional logic, consisting of three AND gates
(G1,G2,G3) and an OR gate (G4) that is added to the existing leaf cell
and satisfies the following constraints.
• All inputs to nMOS transistors that make up the leaf cell under
consideration feed directly into AND gate G1.
• Inputs of nMOS transistors, whose sources are connected
to ground, are inverted and fed into AND gate G2. Inputs of
remaining nMOS transistors feed directly into AND gate G2.
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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 21, NO. 12, DECEMBER 2002
TABLE I
FAULT COVERAGE RESULTS FOR CHARGE SHARING
This model is input to an automatic test pattern generator (ATPG)
and the falling transition fault on m, the output of gate G1, is targeted
for test generation. Generation of a test for guarantees the following.
• A logic 1 on m on the first vector. This in turn implies that all the
inputs to the AND gate G1 (and hence the leaf cell under consideration) should be 1. This leads to the discharging of all internediate
nodes (refer to Section IV).
• A logic 1 on n, the output of gate G2, on the second vector to
ensure observability.
• Stuck-at-1 fault on m is observed at a primary output of the circuit
on the second vector. This in turn implies that the stuck-at-0 fault
on o is observed on the second vector.
The above sequence automatically evokes the worst charge sharing
behavior and if charge-sharing changes the node voltage at o to 0 on
the second vector, its effect is observed at a primary output. One of the
key features of this technique is that the addition of this logic does not
interfere with the functionality of the leaf cell. Hence, the extra logic
can be added simultaneously to all leaf cells and test pattern generation
can be done without modifying the circuit multiple times.
VII. EXPERIMENTAL RESULTS
We have applied the techniques described above to industrial circuits
and a Wallace tree multiplier circuit [12]. The validity of the charge
sharing model (i.e., the k -worst vector pair ordering) was analyzed by
obtaining voltages from actual SPICE simulations. Fig. 12(a) and (b)
shows the results for leaf cells in two circuits. The X axis represents
the order of vector pairs determined by estimating the output voltages
using our charge-sharing model described in previous sections. The Y
axis represents the actual output voltage for the corresponding vector
pair as predicted by SPICE. It can be easily seen that the actual voltages
follow the estimated order fairly accurately. It was observed that the
time required for ranking the vectors (gate input signal assignments)
as mentioned in Section IV-C required 0.03 s of CPU time using our
analytical method, whereas a similar ranking procedure using Hspice
simulations required 100X more time (3 s).
Another set of experiments was performed by modeling each
charge-sharing vector pair for every leaf cell as a product of fault
tuples. The resulting products for a leaf cell are then disjunctively
combined into a charge-sharing fault for that leaf cell. The testability
of each fault was determined. Table I summarizes the results. The
first column is the name of the circuit or subcircuit. The second
column gives the corresponding total number of faults and the
following columns give the number of faults that remain untestable
after each successive product’s testability is considered. As indicated
in Table I, fairly high amounts of fault coverage is achieved without
considering many products for each leaf cell. For example, out of
the 390 possible faults in Ckt. A, 357 can be tested so that the
maximum charge sharing is exhibited and for the multiplier, the
highest level of charge sharing is achievable.
VIII. CONCLUSION
In this paper, we have studied the problem of testing for defects in
feedback, precharge, and cross-coupling transistors used to alleviate
the effects of charge sharing in dynamic logic circuits. We have introduced a novel concept of testing for such defects by applying vector
pairs which invoke the worst case charge sharing in leaf cells. Abstract
transistor models for fast ordering of vector pairs (by the degree by
which they invoke charge sharing) have been given. Results show that
such models give a fairly accurate ordering of vector pairs. We have
also used products of fault tuples for charge sharing based test generation. Fault tuples easily allow ordering of vector combinations according to the amount of charge sharing each produces. Therefore, any
generated test maximizes the amount of charge sharing. All the above
techniques have been implemented and integrated to form a charge
sharing test vector generation tool. The tool takes in as the input the
circuit netlist and the transistor-level SPICE description of each of the
leaf cells comprising it. The transistor-level description is used to generate the vector pairs that invoke the worst case charge sharing in each
of the leaf cells. The tool has been tested on a number of functional
modules contained in industrial circuits. Results show that fairly high
fault coverages can be achieved.
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