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CMS Week, February 2000
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Darin Acosta
Channel Link Backplane Tests
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CMS Week, February 2000
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Prototype VME Backplane
CMS Week, February 2000
3
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CSC Track-Finder Backplane
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Status of Prototype TF Backplane
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Status of Prototype Track-Finder
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CMS Week, February 2000
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UCLA meeting (current version)
Extrapolation
Units
Track
Assembler Units
Two BX
analyzer
Pt-assignment
Unit
LVDS Channel
Links
LVDS Channel
Links
Board Layout of the Sector Processor.
Sector Processor FPGA type
Design status
Started
1. Two Bunch Crossing Analyzer (endcap)
2. Two Bunch Crossing Analyzer + FIFO as delay
(barrel)
3. Extrapolation Unit + Global FIFO
(MB1 – ME2, MB2 – ME2)
4. Extrapolation Unit + Global FIFO
(ME1 – ME2) or (ME1 – ME3)
5. Extrapolation Unit + Global FIFO
(ME2 – ME3, ME2 – ME4, ME3 – ME4)
6. Final Selection Unit
7. Pt – assignment 1
8. Pt – assignment 2
9. Pt – assignment 1 (lowest priority)
10. Pt – assignment 2 (medium priority)
11. Pt – assignment 3 (highest priority)
12. Output data storage
13. VME Interface
14. Clock Distribution and control signals
Underway
√
Finished
√
√
√
√
√
Removed from design
FPGA design current status
√
√
√
√
√
√
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Sector Processor FPGAs
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CMS Week, February 2000
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Darin Acosta
TDI
CHAIN 0
TDO
A12-A14
TDI
TDO
TMS
FPGA
TCK
TDI
TMS
TDO
CHAIN 1
TDO
TMS
TDI
TDI
SCK
TCK
TCK
20 MHz
CNTR
TMS1
FPGA
DATA
CNTR
TMS0
TCK
D00-D07
TDO
FPGA
CE
PSC100F CONTROLLER
ADDR
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D00-D15
TDI
TMS
TCK
A12- A23
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BIT3 CONTROLLER
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FPGA
TCK
CNTR
TDO
TMS
D00-D15
VME INTERFACE
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Sector Processor FPGAs:
18 M Bit Configuration Sequence
Parallel/ Serial Converter by Bit 3 and PSC100F Controllers
CON10X
PD1-8
TDO
PRG
OE 24
DONE
INIT
CS 23
CLK
OE23
CS22
RST
RST
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SYSFAIL
DTACK
RAM
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RAM
21
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ACK
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SCK
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SWITCHES
RAM
23
SYSFAIL
R/W
STB
J1 CONNECTOR
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DS1
RST
CE
A12-A14
D00-D07
TDO
TCK
TMS0
TMS1
TDI
OE4
CS 3
OE3
CS 2
OE2
CS 1
OE1
RAM
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RAM
3
RAM
2
RAM
1
RW
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Up to 24 RAMs
4MW Each
VME BUS
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DS0
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AS
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TDI
TCK
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TMS1
Sector Processor:
30 M Word Look-Up Map
18 M Bit FPGA Configuration Sequence
TDO
Two FPGA
Chains
TCK
CS 24
XC18V256 PROM
TDI
TMS
Module Units
VME and VME/JTAG Interface
Sector Processor Latency
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CMS Week, February 2000
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Darin Acosta
Plan for Sector Processor
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CMS Week, February 2000
9
Darin Acosta
Ghost-Busting in the TF
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Ghost Hits
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η1
Try all
combinations in
Track-Finder by
swapping η values
CMS Week, February 2000
η2
11
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Ghost-Busting Simulation
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CMS Week, February 2000
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Darin Acosta
Track Finding Eff vs Pt Threshold cut
Efficiency
Two LCTs in one ME1/2 chamber (Pt = 25 GeV/c)
1.2
1
0.8
0.6
0.4
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Mix (No Fix)
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1
10
2
10
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• The “Mix” sample after treated by Ghostbusting gives
a slightly higher track finding efficiency. This is because the TF tends to select from the extrapolation
combinations the one that gives a higher Pt measurement.
σ( 1/Ptrec - 1/Ptgen )/( 1/Ptgen )
CSC Track-Finder PT Resolution
0.7
Pt = 5 GeV (2 Stn)
(ME1-ME2)
0.6
0.5
ME1/3
MB1
Pt = 5 GeV (3 Stn)
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ME1/1
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2
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S.M.Wang
CMS Week, February 2000
13
2.4
ηrec
Darin Acosta
L1 CSC Trigger Efficiency
2-Station Tracks
3-Station Tracks
Single µ Trk Finding Eff (3-Station Pt Assignment)
3 CSC Stns (no ME4)
Efficiency
Efficiency
Single µ Trk Finding Eff (2-Station Pt Assignment)
1.2
4 CSC Stns
1
1.2
3 CSC Stns (no ME4)
1
Pt=100 GeV/c
Pt=100 GeV/c
0.8
LCT at
95% Eff
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0.8
1
1.2
4 CSC Stns
1.4
1.6
1.8
2
2.2
0
0.8
2.4
LCT at
95% Eff
1
1.2
1.4
CMS Week, February 2000
ME1 required in both cases
14
1.8
2
2.2
2.4
ηgen
ηgen
S.M.Wang
1.6
Darin Acosta
L1 CSC Single µ Rate
Rate dN/dηdt (kHz)
Single µ Rate (Min Bias sample 14 collisions in 1 BX)
10
4
ME4/1 and ME4/2
3-Stn Pt
10 3
ME4/1 only
2/3-Stn Pt for η < 1.8
3-Stn Pt for η > 1.8
No ME4
2-Stn Pt
10 2
Target Rates
10
L=1033 cm-2s-1
1
L=1034 cm-2s-1
10
10
-1
-2
1.2 < |η| < 2.4
34
-2 -1
L = 10 cm s
10
-3
1
10
10
Ptmin (GeV)
S.M.Wang
CMS Week, February 2000
2
15
Darin Acosta
Conclusion of ME4 Trigger Studies
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CMS Week, February 2000
16
Darin Acosta
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