7KH&6&7UDFN)LQGHU +DUGZDUH6WDWXV *KRVWEXVWLQJ LQ0( $UJXPHQWVIRU0( '$FRVWD$0DGRUVN\60:DQJ 8QLYHUVLW\RI)ORULGD $$WDPDQFKXN9*RORYWVRY%5D]P\VORYLFK 313, CMS Week, February 2000 1 Darin Acosta Channel Link Backplane Tests 3URWRW\SH90( EDFNSODQHWHVWHGZLWK&KDQQHO/LQN OD\HUV PLO SLWFK LPSHGDQFH PHDVXUHG WR EH Ω ➨ /RQJHVW WUDFHV H[WHQG 90( VORWV ➨ =3DFN FRQQHFWRUV ZLWK URZV PP SLWFK ➨ 7UDQVPLWWHU DQG 5HFHLYHU ERDUGV KDYH LQSXWRXWSXW ),)2V LPSOHPHQWHG LQ )3*$ ➨ 1R(UURUVIRXQGRSHUDWLQJ&KDQQHO/LQNDW0+] )L[HG DQG UDQGRP SDWWHUQV WHVWHG ➨ ),)2V VHQGUHFHLYH GDWD DW IXOO VSHHG ➨ 0D[LPXP FORFN DFKLHYHG LV 0+] ZLWKRXW HUURUV 0+] EDFNSODQH IUHTXHQF\ ➨ 6WDWHG PD[LPXP VKRXOG EH 0+] ➨ CMS Week, February 2000 2 Darin Acosta Prototype VME Backplane CMS Week, February 2000 3 Darin Acosta CSC Track-Finder Backplane 7KH&6&7UDFN )LQGHUFUDWHFRQWDLQV 6HFWRU 3URFHVVRUV GRXEOHZLGWKPRGXOHV ➨ 6HFWRU 5HFHLYHUV ➨ &ORFN DQG &RQWURO %RDUG ➨ (DFK6HFWRU3URFHVVRUUHFHLYHVaVLJQDOVYLD &KDQQHO/LQN %DFNRIFUDWHDOVRKDVWUDQVLWLRQERDUGVWR'7 7ULJJHUV\VWHP ➨ 5HTXLUHV PDOH FRQQHFWRUV WR SXQFK WKURXJK WR EDFN RI FUDWH CMS Week, February 2000 4 Darin Acosta Status of Prototype TF Backplane 3URWRW\SHEDFNSODQHGHVLJQHGIRURQHVHFWRU KDOIRIFUDWH 6WDQGDUG890([XSSHUFRQQHFWRU ➨ $' 90( FRQWURO DQG 9 SRZHU &XVWRP8&KDQQHO/LQN EDFNSODQH 5RXWLQJEDVLFDOO\FRPSOHWH 3URGXFWLRQWREHJLQLQDPRQWKRUWZR ➨ :KHQ 65 DQG 63 SURWRW\SHV DUH UHDG\ WR JR WR SURGXFWLRQ &UDWHWHVWVWREHJLQ-XQH CMS Week, February 2000 5 Darin Acosta Status of Prototype Track-Finder 6HFWRU 3URFHVVRU 6HFWRU 5HFHLYHU LQWHUIDFH GHILQHG ➨ ,QFOXGHV H[WUD ELWV WR KDQGOH JKRVWEXVWLQJ ➨ %DFNSODQH URXWLQJ QHDUO\ FRPSOHWH '7 7ULJJHU LQWHUIDFH VWLOO WR EH IXOO\ GHILQHG ➨ ,QLWLDO GLVFXVVLRQV WR WDNH SODFH WKLV ZHHN ➨ )UHH]H GHVLJQ IRU FXUUHQW SURWRW\SH WKRXJK )3*$ VFKHPDWLFV DUH QHDUO\ ILQLVKHG IRU WULJJHU ORJLF %RDUG URXWLQJ XQGHUZD\ ➨ OD\HUV LQFOXGLQJ SRZHU SODQHV 90(-7$* LQWHUIDFH XQGHUZD\ ➨ ;LOLQ[ 6SDUWDQ 90( ,QWHUIDFH ➨ 1DWLRQDO 6&$136&) 3DUDOOHO WR 6HULDO LQWHUIDFH IRU -7$* CMS Week, February 2000 6 Darin Acosta UCLA meeting (current version) Extrapolation Units Track Assembler Units Two BX analyzer Pt-assignment Unit LVDS Channel Links LVDS Channel Links Board Layout of the Sector Processor. Sector Processor FPGA type Design status Started 1. Two Bunch Crossing Analyzer (endcap) 2. Two Bunch Crossing Analyzer + FIFO as delay (barrel) 3. Extrapolation Unit + Global FIFO (MB1 – ME2, MB2 – ME2) 4. Extrapolation Unit + Global FIFO (ME1 – ME2) or (ME1 – ME3) 5. Extrapolation Unit + Global FIFO (ME2 – ME3, ME2 – ME4, ME3 – ME4) 6. Final Selection Unit 7. Pt – assignment 1 8. Pt – assignment 2 9. Pt – assignment 1 (lowest priority) 10. Pt – assignment 2 (medium priority) 11. Pt – assignment 3 (highest priority) 12. Output data storage 13. VME Interface 14. Clock Distribution and control signals Underway √ Finished √ √ √ √ √ Removed from design FPGA design current status √ √ √ √ √ √ √ √ Sector Processor FPGAs 'HVLJQLQFRUSRUDWHV ;LOLQ[9LUWH[)3*$V %XQFK&URVVLQJ$QDO\]HU ;&9%*& VSHHG JUDGH ➨ 1XPEHU RI VOLFHV RXW RI ➨ 1XPEHU RI ,2% RXW RI 0+] ➨ 0D[LPXP IUHTXHQF\ ➨ &RVW ➨ ([WUDSRODWLRQ8QLW*OREDO),)2 ;&9%*& VSHHG JUDGH ➨ 1XPEHU RI VOLFHV RXW RI ➨ 1XPEHU RI ,2% RXW RI 0+] ➨ 0D[LPXP IUHTXHQF\ ➨ &RVW ➨ CMS Week, February 2000 7 Darin Acosta TDI CHAIN 0 TDO A12-A14 TDI TDO TMS FPGA TCK TDI TMS TDO CHAIN 1 TDO TMS TDI TDI SCK TCK TCK 20 MHz CNTR TMS1 FPGA DATA CNTR TMS0 TCK D00-D07 TDO FPGA CE PSC100F CONTROLLER ADDR A15-A23 D00-D15 TDI TMS TCK A12- A23 COMPARATOR D16/ A24 VME BUS BIT3 CONTROLLER A01-A23 FPGA TCK CNTR TDO TMS D00-D15 VME INTERFACE A01-A23 Sector Processor FPGAs: 18 M Bit Configuration Sequence Parallel/ Serial Converter by Bit 3 and PSC100F Controllers CON10X PD1-8 TDO PRG OE 24 DONE INIT CS 23 CLK OE23 CS22 RST RST IACK SYSFAIL DTACK RAM 22 RAM 21 IACK ACK CS 4 RDY 20 MHz SCK A15-A23 8-BIT COMPARATOR SWITCHES RAM 23 SYSFAIL R/W STB J1 CONNECTOR OE21 DS1 RST CE A12-A14 D00-D07 TDO TCK TMS0 TMS1 TDI OE4 CS 3 OE3 CS 2 OE2 CS 1 OE1 RAM 4 RAM 3 RAM 2 RAM 1 RW A01-A22 Up to 24 RAMs 4MW Each VME BUS DRIVER A00-A23 CS21 DS0 XILINX XCS30XL SPARTAN DS1 AS NATIONAL SCANPSC100F CONTROLLER DS0 VME BUS DRIVER AS WRITE BUS DRIVER WRITE OE22 RAM 24 D00-D15 VNE BUS TRANSCEIVER D00 -D15 TDI TCK TMS0 TMS1 Sector Processor: 30 M Word Look-Up Map 18 M Bit FPGA Configuration Sequence TDO Two FPGA Chains TCK CS 24 XC18V256 PROM TDI TMS Module Units VME and VME/JTAG Interface Sector Processor Latency /DWHQF\RISUHVHQWSURWRW\SHZLOOEH ➨ E[ ,IZHGURSWKHPXOWLSOHE[LQSXWIRU &6&V GURS&KDQQHO/LQNVHULDOL]DWLRQDQGJHWPRGHVW )3*$LPSURYHPHQW ➨ E[ LV SRVVLEOH ,IZHJHWGUDPDWLF)3*$LPSURYHPHQWWKHQE[ PD\EHSRVVLEOHZLWKDOOFDSDELOLW\ CMS Week, February 2000 8 Darin Acosta Plan for Sector Processor &UDWHWHVWVZLWK6565&&%DQG70%03& VFKHGXOHGWREHJLQ-XQH 63GHVLJQLVSURFHHGLQJZHOODQGZHVKRXOGEHDEOH WRPDNHGDWH 6WLOODORWRIZRUNWRGRDQGVRIWZDUHWRZULWH« CMS Week, February 2000 9 Darin Acosta Ghost-Busting in the TF $OJRULWKP GHYHORSHG WR KDQGOH JKRVWV KLWV LQ WKH &6& FKDPEHUV E\ WKH 7UDFN)LQGHU ➨ $SSOLHV WR 0( FKDPEHUV RQO\ EXW WKH\ DUH PRVW OLNHO\ WR KDYH SXQFKWKURXJK KLWV ➨ $OO SRVVLEOH η ϕ FRPELQDWLRQV WULHG 5HTXLUHV ➨ H[WUD ELWV SHU PXRQV IURP WKH &6& 6HFWRU 5HFHLYHU ➨ $GGLWLRQDO ORJLF DQG LQWHUFRQQHFWLRQV LQ WKH 6HFWRU 3URFHVVRU ([WUDSRODWLRQ 8QLWV /RRNV TXLWH IHDVLEOH 0HWKRG ZRUNV RQO\ ZKHQ ERWK /&7V VXUYLYH 3RUW &DUG ➨ ≤ VWXEV VHFWRU VWDWLRQ 6LPXODWLRQ VKRZV WKDW LW ZRUNV CMS Week, February 2000 10 Darin Acosta Ghost Hits ϕ1 ϕ2 η1 Try all combinations in Track-Finder by swapping η values CMS Week, February 2000 η2 11 Darin Acosta Ghost-Busting Simulation &RQWULYHGSXQFKWKURXJKVLPXODWLRQ *HQHUDWH VLQJOH PXRQV ZLWK 37 *H9 WKDW HQWHU 0( ➨ $GG RQH H[WUD /&7 LQ VDPH 0( FKDPEHU UDQGRPO\ GLVWULEXWHG EXW OHDYH RWKHU VWDWLRQV DORQH ➨ $VVXPH SUREDELOLW\ RI JHWWLQJ ηϕ DVVRFLDWLRQ FRUUHFW ➨ $SSO\JKRVWEXVWLQJDOJRULWKPDQGPHDVXUH HIILFLHQF\ ➨ 'RQH ZLWK VWDQGDORQH & 7UDFN)LQGHU VLPXODWLRQ 6WLOOQHHGWRVWXG\LPSDFWRQ/UDWH CMS Week, February 2000 12 Darin Acosta Track Finding Eff vs Pt Threshold cut Efficiency Two LCTs in one ME1/2 chamber (Pt = 25 GeV/c) 1.2 1 0.8 0.6 0.4 No Mix Mix (No Fix) 0.2 Mix (Fix) 0 -1 10 1 10 2 10 Ptcut (GeV/c) • The “Mix” sample after treated by Ghostbusting gives a slightly higher track finding efficiency. This is because the TF tends to select from the extrapolation combinations the one that gives a higher Pt measurement. σ( 1/Ptrec - 1/Ptgen )/( 1/Ptgen ) CSC Track-Finder PT Resolution 0.7 Pt = 5 GeV (2 Stn) (ME1-ME2) 0.6 0.5 ME1/3 MB1 Pt = 5 GeV (3 Stn) (ME1-ME2-ME3) ME1/2 ME1/1 0.4 7KH3 7 UHVROXWLRQ LPSURYHVIURP DERXWWR XVLQJ&6& VWDWLRQVUDWKHU WKDQ 0XVWKDYH0(LQ ERWKFDVHV 0.3 0.2 &DSDELOLW\DGGHGWR KDUGZDUH 0.1 0 0.8 1 1.2 1.4 1.6 1.8 2 2.2 S.M.Wang CMS Week, February 2000 13 2.4 ηrec Darin Acosta L1 CSC Trigger Efficiency 2-Station Tracks 3-Station Tracks Single µ Trk Finding Eff (3-Station Pt Assignment) 3 CSC Stns (no ME4) Efficiency Efficiency Single µ Trk Finding Eff (2-Station Pt Assignment) 1.2 4 CSC Stns 1 1.2 3 CSC Stns (no ME4) 1 Pt=100 GeV/c Pt=100 GeV/c 0.8 LCT at 95% Eff 0.8 0.6 0.6 0.4 0.4 0.2 0.2 0 0.8 1 1.2 4 CSC Stns 1.4 1.6 1.8 2 2.2 0 0.8 2.4 LCT at 95% Eff 1 1.2 1.4 CMS Week, February 2000 ME1 required in both cases 14 1.8 2 2.2 2.4 ηgen ηgen S.M.Wang 1.6 Darin Acosta L1 CSC Single µ Rate Rate dN/dηdt (kHz) Single µ Rate (Min Bias sample 14 collisions in 1 BX) 10 4 ME4/1 and ME4/2 3-Stn Pt 10 3 ME4/1 only 2/3-Stn Pt for η < 1.8 3-Stn Pt for η > 1.8 No ME4 2-Stn Pt 10 2 Target Rates 10 L=1033 cm-2s-1 1 L=1034 cm-2s-1 10 10 -1 -2 1.2 < |η| < 2.4 34 -2 -1 L = 10 cm s 10 -3 1 10 10 Ptmin (GeV) S.M.Wang CMS Week, February 2000 2 15 Darin Acosta Conclusion of ME4 Trigger Studies 5HTXLUH6WDWLRQ3 7 PHDVXUHPHQWDWKLJK η RUDW KLJKOXPLQRVLW\IRUDFFHSWDEOH/UDWH 1RUHGXQGDQF\ZLWKRXW0( ➨ &DXVHV SRRU HIILFLHQF\ $WORZOXPLQRVLW\UHTXLUH0(WRWULJJHU η! ➨ 3\WKLD VWXG\ VKRZV WKDW RI WKH DFFHSWDQFH IRU E→µ JRHV LQWR η $WKLJKOXPLQRVLW\UHTXLUH0(DQG0( CMS Week, February 2000 16 Darin Acosta