mm
40
60
80
100
120
7. Combinational Circuits
40
J. A. Abraham
60
Department
of Electrical and Computer Engineering
The University of Texas at Austin
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ECE Department, University of Texas at Austin
VLSI Design
Fall 2015
September 21, 2015
Lecture 7. Combinational Circuits
J. A. Abraham, September 21, 2015
1 / 20
Review: Decoder Example, Number of Stages
16 word, (32 bit) register file
Each
mmbit presents
40 load of 3 unit-sized
60
transistors
80
100
120
True and complementary address inputs
A[3:0]
40 input may drive 10 unit-sized
Each
transistors
Find: number of stages, sizes of gates, speed
Decoder effort is mainly electrical and branching
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Electrical Effort: H = (32*3)/10 = 9.6
Branching Effort: B = 8
If we neglect logical effort (assume G = 1)
Path Effort: F = GBH = 76.8
80
Number of Stages: N = log4 F = 3.1
Try a 3-stage design
ECE Department, University of Texas at Austin
Lecture 7. Combinational Circuits
J. A. Abraham, September 21, 2015
1 / 20
Decoder Review: Gate Sizes and Delay
Logical Effort: G = 1 * 6/3 * 1 = 2
mm
Path Effort: 40
F = GBH =60
154
80
100
120
1
3
Stage Effort: fˆ = F = 5.36
Path Delay: D = 3fˆ + 1 + 4 + 1 = 22.1
Gate sizes: z = 96*1/5.36 = 18
40
Gate sizes: y = 18*2/5.36 = 6.7
60
80
ECE Department, University of Texas at Austin
Lecture 7. Combinational Circuits
J. A. Abraham, September 21, 2015
2 / 20
Decoder Review: Comparison
mm
40
60
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100
120
Compare many alternatives with a spreadsheet
Design
NAND4-INV
40
NAND2-NOR2
INV-NAND4-INV
NAND4-INV-INV-INV
NAND2-NOR2-INV-INV
60
NAND2-INV-NAND2-INV
INV-NAND2-INV-NAND2-INV
NAND2-INV-NAND2-INV-INV-INV
N
2
2
3
4
4
4
5
6
G
2
20/9
2
2
20/9
16/9
16/9
16/9
P
5
4
6
7
6
6
7
8
D
29.8
30.1
22.1
21.1
20.5
19.7
20.4
21.6
80
ECE Department, University of Texas at Austin
Lecture 7. Combinational Circuits
J. A. Abraham, September 21, 2015
3 / 20
Review: Logical Effort Example
Find the logical efforts for the inputs, a, b, and c in the circuit
mm
40
60
80
100
below.
Output
Rising
120
Falling
a
40
b
c
60
80 a way to reduce the parasitic delay of this circuit by
Suggest
modifying the structure (but keeping the same function).
ECE Department, University of Texas at Austin
Lecture 7. Combinational Circuits
J. A. Abraham, September 21, 2015
4 / 20
Example, Cont’d
Find the logical efforts for the inputs, a, b, and c in the circuit
below.
mm
40
60
80
100
Output
40
Rising
Falling
a
55/18
22/15
b
55/18
22/15
c
35/18
7/9
120
60
To reduce
the parasitic delay of this circuit, swap the parallel
80
combination of pMOS transistors with inputs a, b with the pMOS
transistor with input c
ECE Department, University of Texas at Austin
Lecture 7. Combinational Circuits
J. A. Abraham, September 21, 2015
5 / 20
Example: Sizing Paths
Size the path G1-G2-G3-G4 in the circuit below using logical effort
Find the minimum delay and give the sizes of the P and N
mm
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60
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120
transistors to achieve this delay
Assume that the off-path capacitance is the same as the on-path
capacitance for each branch
Input capacitance of Inverter G1 = 3 units.
Load 40
capacitance driven by Gate G4 = 52 units.
60
80
ECE Department, University of Texas at Austin
Lecture 7. Combinational Circuits
J. A. Abraham, September 21, 2015
6 / 20
Sizing Paths, Cont’d
Size the path G1-G2-G3-G4 in the circuit
Inputmm
capacitance40
of Inverter G1
60 = 3 units.80
100
Load capacitance driven by Gate G4 = 52 units.
Delay = 4.8 FO4 units
120
Sizes of transistors:
40
60
Gate
P
N
Gate G4
8
8
Gate G3
5
5
Gate G2
3
3
Gate G1
2
1
80
Delay of the path from A through gates G5 and G4 (assuming the
input from G2=1 and D=0): 2.08 FO4 units
ECE Department, University of Texas at Austin
Lecture 7. Combinational Circuits
J. A. Abraham, September 21, 2015
7 / 20
Example of “Bubble Pushing”
mm
40
60
80
100
120
Implement the circuit described by the code below
module mux(input s, d0, d1,
output y);
assign
y
=
s ? d1 : d0;
40
endmodule
The60specifications are
easily met with a design
using AND, OR and
NOT gates
80
ECE Department, University of Texas at Austin
Lecture 7. Combinational Circuits
J. A. Abraham, September 21, 2015
8 / 20
Convert to Design using NAND/NOR/NOT Gates
Bubble
mmPushing 40
60
Start with network of AND/OR gates
Convert to NAND/NOR + inverters
Push bubbles around to simplify logic
Use DeMorgan’s
Law
40
80
100
120
60
80
ECE Department, University of Texas at Austin
Lecture 7. Combinational Circuits
J. A. Abraham, September 21, 2015
9 / 20
Example, Continued
Now,mm
design the circuit
with one
40
60 compound
80gate and one
100 inverter. 120
Assume that S̄ is available
40
60
80
ECE Department, University of Texas at Austin
Lecture 7. Combinational Circuits
J. A. Abraham, September 21, 2015
10 / 20
Compound Gates
mm
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60
80
100
120
40
60
80
ECE Department, University of Texas at Austin
Lecture 7. Combinational Circuits
J. A. Abraham, September 21, 2015
11 / 20
Another Example
A multiplexer has a maximum input capacitance of 16 units on
eachmm
input. It must
40 drive a load
60 of 160 units
80
100
Estimate the delay of the NAND and compound gate designs
NAND Solution
120
Compound Solution
40
H = 160/16 = 10
B = 160
N =2
P =2+2=4
G = (4/3) · (4/3) = 16/9
F = GBH
= 160/9
80
√
fˆ = N F = 4.2
D = N fˆ + P = 12.4τ
ECE Department, University of Texas at Austin
H = 160/16 = 10
B=1
N =2
P =4+1=5
G = (6/3) · (1) = 2
F = GBH
= 20
√
fˆ = N F = 4.5
D = N fˆ + P = 14τ
Lecture 7. Combinational Circuits
J. A. Abraham, September 21, 2015
12 / 20
Example, Cont’d
Annotate
with
sizes which120
mm the designs
40 for the multiplexer
60
80 transistor100
achieve the minimum delay
40
60
80
ECE Department, University of Texas at Austin
Lecture 7. Combinational Circuits
J. A. Abraham, September 21, 2015
13 / 20
Order of Inputs to a Transistor Stack
Delay of CMOS gate is affected
mmorder
40
60
by input
Parasitic delay model used in
logical effort calculations is
too simple
40
Example,
calculate parasitic
delay for Y falling
80
100
120
If A arrives latest: 2τ
If B arrives latest: 2.33τ
60
Choosing inner and outer inputs
Outer input is closest to rail (power or ground): B
Inner input is closest to output: A
If80input arrival time is known
Connect latest arriving input to inner terminal
ECE Department, University of Texas at Austin
Lecture 7. Combinational Circuits
J. A. Abraham, September 21, 2015
14 / 20
Asymmetric Gates
Asymmetric gates favor one input over another
mm
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60
80
100
120
Example, suppose input A of a
NAND gate is most critical
Use smaller transistor on A
40
(less capacitance)
Boost size of noncritical input
So total resistance is same
60
Calculate logical effort
gA = 10/9
gB = 2
gtotal = gA + gB = 28/9
80
Symmetric gate approaches g = 1 on critical input
However, total logical effort goes up
ECE Department, University of Texas at Austin
Lecture 7. Combinational Circuits
J. A. Abraham, September 21, 2015
15 / 20
Symmetric Gates
mm
40
60
Inputs can be made perfectly symmetric
80
100
120
40
60
Make both A and B behave like inner/outer inputs, and keep the
P:N ratio 2:1
80
ECE Department, University of Texas at Austin
Lecture 7. Combinational Circuits
J. A. Abraham, September 21, 2015
16 / 20
Skewed Gates Favor One Edge Over Another
Example, suppose
rising output of
inverter
mm is most critical
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60
80
100
120
Downsize
noncritical nMOS
transistor
Calculate
logical effort by comparing to unskewed inverter
40
with same effective resistance on that edge
gu = 2.5/3 = 5/6;
gd = 2.5/1.5 = 5/3
Definition: Logical effort of a skewed gate for a particular
transition is the ratio of the input capacitance of that gate to
60
the
input capacitance of an unskewed inverter delivering the
same output current for the same transition
Skewed gates reduce size of noncritical transistors
80
HI-skew gates favor rising output (small nMOS)
LO-skew gates favor falling output (small pMOS)
Logical effort is smaller for favored direction, but larger for the
other direction
ECE Department, University of Texas at Austin
Lecture 7. Combinational Circuits
J. A. Abraham, September 21, 2015
17 / 20
Catalog of Skewed Gates
mm
40
60
80
100
120
40
60
80
ECE Department, University of Texas at Austin
Lecture 7. Combinational Circuits
J. A. Abraham, September 21, 2015
18 / 20
Asymmetric Skew
mm asymmetric
40 and skewed
60 gates
80
100
Combine
Downsize noncritical transistor on unimportant input
120
Reduces parasitic delay for critical input
40
60
80
ECE Department, University of Texas at Austin
Lecture 7. Combinational Circuits
J. A. Abraham, September 21, 2015
19 / 20
Best P/N Ratio
We have selected P/N ratio for unit rise and fall
mm
60
80
resistance
(µ =402-3 for an inverter).
100
120
Alternative: choose ratio for least average delay
Example: inverter
40
Delay driving identical inverter
tpdf = (P + 1)
tpdr = (P + 1)(µ/P )
tpd = (P + 1)(1 + µ/P )/2 = (P + 1 + µ + µ/P )/2
√
Differentiating tpd w.r.t. P, we get, least delay for P = µ
In general, best P/N ratio is sqrt of that giving equal delay
60
Only improves average delay slightly for inverters
But significantly decreases area and power
80
ECE Department, University of Texas at Austin
Lecture 7. Combinational Circuits
J. A. Abraham, September 21, 2015
20 / 20