ch09

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Digital Design
Chapter 9:
Hardware Description Languages
Slides to accompany the textbook Digital Design, First Edition,
by Frank Vahid, John Wiley and Sons Publishers, 2007.
http://www.ddvahid.com
Copyright © 2007 Frank Vahid
Instructors of courses requiring Vahid's Digital Design textbook (published by John Wiley and Sons) have permission to modify and use these slides for customary course-related activities,
subject to keeping
this copyright
notice in place and unmodified. These slides may be posted as unanimated pdf versions on publicly-accessible course websites.. PowerPoint source (or pdf
Digital
Design
with animations) may not be posted to publicly-accessible websites, but may be posted for students on internal protected sites or distributed directly to students by other electronic means.
Copyright © 2006
1
Instructors may make printouts of the slides available to students for a reasonable photocopying charge, without incurring royalties. Any other use requires explicit permission. Instructors
Franksource
Vahidor obtain special use permissions from Wiley – see http://www.ddvahid.com for information.
may obtain PowerPoint
9.1
Introduction
DoorOpener
• A drawing of a circuit, or
schematic, contains
graphical information about
a design
c
– Inverter is above the OR gate,
AND gate is to the right, etc.
• Such graphical information
may not be useful for large
designs
• Can use textual language
instead
Digital Design
Copyright © 2006
Frank Vahid
f
h
p
si
a
tap
a
rtn
o
co
t
g
2
Note: Slides with animation are denoted with a small red "a" near the animated items
Textual Language – English
• Can describe circuit using English text rather than using a drawing
– Of course, English isn't a good language for a computer to read
– Need a more precise, computer-oriented language
(a)
(b)
DoorOpener
Inv_1
c
h
f
n1
p
n2
OR2_1
AND2_1
Digital Design
Copyright © 2006
Frank Vahid
We'll now describe a circuit whose name isDoorOpener.
The external inputs are c, h and p, which are bits.
The external output isf, which is a bit.
We assume you know the behavior of these components:
An inverter, which has a bit input x, and bit output F.
A 2-input ORgate, which has inputs x and y, and bit output F.
A 2-input AND gate, which has bit inputs x and y, and bit output F.
The circuit has internal wires n1 and n2, both bits.
The DoorOpener circuit internally consists of:
An inverter named Inv_1, whose input x connectsto
external input c, and whose output connectsto n1.
A 2-input ORgate named OR2_1, whose inputsconnect to external
inputs h and p, and whose output connectsto n2.
A 2-input AND gate named AND2_1, whose inputsconnect to n1
and n2, and whose output connectsto external output f.
That's all.
3
Computer-Readable Textual Language for
Describing Hardware Circuits: HDLs
• Hardware description language (HDL)
– Intended to describe circuits textually, for a computer to read
– Evolved starting in the 1970s and 1980s
• Popular languages today include:
– VHDL –Defined in 1980s by U.S. military; Ada-like language
– Verilog –Defined in 1980s by a company; C-like language
– SystemC –Defined in 2000s by several companies; consists of
libraries in C++
Digital Design
Copyright © 2006
Frank Vahid
4
Combinational Logic Description using Hardware
Description Languages
• Structure
9.2
DoorOpener
– Another word for "circuit"
– An interconnection of
components
– Key use of HDLs is to describe
structure
c
f
h
p
a
tap
a
si
Note: The term "instantiate" will be used to indicate adding
rtn a new
o
co
copy of a component to a circuit
t
The OR component
Three instances of the OR component
g
OR_2
OR_1
OR_3
Digital Design
Copyright © 2006
Frank Vahid
5
Describing Structure in VHDL
•
Entity – Defines new
item's name & ports
(inputs/outputs)
– std_logic means bit
type, defined in ieee
library
•
Architecture –
Describes internals,
which we named "Circuit"
–
–
Declares 3 previouslydefined components
Declares internal
signals
•
–
Note "--" comment
Instantiates and
connects those
components
Digital Design
Copyright © 2006
Frank Vahid
DoorOpener
Inv_1
c
h
f
n1
p
n2
AND2_1
OR2_1
(a)
We'll now describe a circuit whose name is DoorOpener.
The external inputs are c, h and p, which are bits.
The external output is f, which is a bit.
We assume you know the behavior of these components:
An inverter, which has a bit input x, and bit output F.
A 2-input OR gate, which has inputs x and y,
and bit output F.
A 2-input AND gate, which has bit inputs x and y,
and bit output F.
The circuit has internal wires n1 and n2, both bits.
The DoorOpener circuit internally consists of:
An inverter named Inv_1, whose input x connects to
external input c, and whose output connects to n1.
A 2-input OR gate named OR2_1, whose inputs
connect to external inputs h and p, and whose output
connects to n2.
A 2-input AND gate named AND2_1, whose inputs
connect to n1 and n2, and whose output connects to
external output f.
That's all.
(b)
l i br a r y i e e e ;
us e i e e e . s t d _ l o g i c _ 1 1 6 4 . a l l ;
e n t i t y Do o r Op e n e r i s
por t ( c , h , p : i n s t d _ l o g i c ;
f : out s t d _ l o g i c
);
e n d Do o r Op e n e r ;
a r c h i t e c t u r e Ci r c u i t o f Do o r Op e n e r i s
c o mp o n e n t I n v
por t ( x : i n s t d _ l o g i c ;
F: out s t d _ l o g i c ) ;
e n d c o mp o n e n t ;
c o mp o n e n t OR2
por t ( x , y : i n s t d _ l o g i c ;
F: out s t d _ l o g i c ) ;
e n d c o mp o n e n t ;
c o mp o n e n t AND2
por t ( x , y : i n s t d _ l o g i c ;
F: out s t d _ l o g i c ) ;
e n d c o mp o n e n t ;
s i g n a l n 1 , n 2 : s t d _ l o g i c ; - - i n t e r n a l wi r e s
be gi n
I n v _ 1 : I n v p o r t ma p ( x = > c , F = > n 1 ) ;
OR2 _ 1 : OR2 p o r t ma p ( x = > h , y = > p , F = > n 2 ) ;
AND2 _ 1 : AND2 p o r t ma p ( x = > n 1 , y = > n 2 , F = > f ) ;
e n d Ci r c u i t ;
(c)
6
Describing Structure in Verilog
• Modules defined for
Inv, OR2, and AND2
(details omitted)
– Note "//" comment
• Module defined for
DoorOpener
– Lists inputs and
outputs
– Declares internal
wires
– Instantiates and
connects three
components
Digital Design
Copyright © 2006
Frank Vahid
DoorOpener
Inv_1
c
h
f
n1
p
n2
AND2_1
OR2_1
(a)
We'll now describe a circuit whose name is DoorOpener.
The external inputs are c, h and p, which are bits.
The external output is f, which is a bit.
We assume you know the behavior of these components:
An inverter, which has a bit input x, and bit output F.
A 2-input OR gate, which has inputs x and y,
and bit output F.
A 2-input AND gate, which has bit inputs x and y,
and bit output F.
The circuit has internal wires n1 and n2, both bits.
The DoorOpener circuit internally consists of:
An inverter named Inv_1, whose input x connects to
external input c, and whose output connects to n1.
A 2-input OR gate named OR2_1, whose inputs
connect to external inputs h and p, and whose output
connects to n2.
A 2-input AND gate named AND2_1, whose inputs
connect to n1 and n2, and whose output connects to
external output f.
That's all.
(b)
mo d u l e I n v ( x ,
i nput x ;
out put F;
/ / det ai l s
e n d mo d u l e
mo d u l e OR2 ( x ,
i nput x , y ;
out put F;
/ / det ai l s
e n d mo d u l e
mo d u l e AND2 ( x ,
i nput x , y ;
out put F;
/ / det ai l s
e n d mo d u l e
F) ;
not
y,
not
y,
not
s h o wn
F) ;
s h o wn
F) ;
s h o wn
mo d u l e Do o r Op e n e r ( c , h , p ,
i nput c , h , p ;
out put f ;
wi r e n 1 , n 2 ;
I nv I nv_1( c, n1) ;
OR2 OR2 _ 1 ( h , p , n 2 ) ;
AND2 AND2 _ 1 ( n 1 , n 2 , f ) ;
e n d mo d u l e
f ) ;
(c)
7
Describing Structure in SystemC
• Module defined
– Declares inputs
and outputs
– Declares internal
wires
• Note "//"
comment
– Declares three
previously-defined
components
– Constructor
function "CTOR"
• Instantiates
components
• Connects
components
Digital Design
Copyright © 2006
Frank Vahid
DoorOpener
Inv_1
c
h
f
n1
p
n2
AND2_1
OR2_1
#i
#i
#i
#i
nc l
nc l
nc l
nc l
ude
ude
ude
ude
"
"
"
"
s y s t e mc . h "
i nv. h"
or 2. h"
and2. h"
(a)
We'll now describe a circuit whose name is DoorOpener.
The external inputs are c, h and p, which are bits.
The external output is f, which is a bit.
We assume you know the behavior of these components:
An inverter, which has a bit input x, and bit output F.
A 2-input OR gate, which has inputs x and y,
and bit output F.
A 2-input AND gate, which has bit inputs x and y,
and bit output F.
The circuit has internal wires n1 and n2, both bits.
The DoorOpener circuit internally consists of:
An inverter named Inv_1, whose input x connects to
external input c, and whose output connects to n1.
A 2-input OR gate named OR2_1, whose inputs
connect to external inputs h and p, and whose output
connects to n2.
A 2-input AND gate named AND2_1, whose inputs
connect to n1 and n2, and whose output connects to
external output f.
That's all.
(b)
SC_ MODUL E ( Do o r Op e n e r )
{
s c _ i n<s c _ l ogi c > c , h , p ;
s c _ out <s c _ l ogi c > f ;
/ / i n t e r n a l wi r e s
s c _ s i gna l <s c _ l ogi c > n 1 , n 2 ;
/ / c o mp o n e n t d e c l a r a t i o n s
I nv I nv1;
OR2 OR2 _ 1 ;
AND AND2 _ 1 ;
/ / c o mp o n e n t i n s t a n t i a t i o n s
SC_ CT OR( Do o r Op e n e r ) : I n v _ 1 ( " I n v _ 1 " ) ,
OR2 _ 1 ( " OR2 _ 1 " ) , AND2 _ 1 ( " AND2 _ 1 " )
{
I nv_1. x( c) ;
I n v _ 1 . F( n 1 ) ;
OR2 _ 1 . x ( h ) ;
OR2 _ 1 . y ( p ) ;
OR2 _ 1 . F ( n 2 ) ;
AND2 _ 1 . x ( n 1 ) ;
AND2 _ 1 . y ( n 2 ) ;
AND2 _ 1 . F ( f ) ;
}
} ;
(c)
8
Combinational Behavior
• Combinational behavior
– Description of desired behavior of combinational circuit without
creating circuit itself
– e.g., F = c' * (h + p) can be described as equation rather than circuit
– HDLs support description of combinational behavior
Digital Design
Copyright © 2006
Frank Vahid
9
Describing Combinational Behavior in VHDL
• Describing an OR gate's
behavior
– Entity defines input/output ports
– Architecture
• Process – Describes behavior
– Process "sensitive" to x and y
» Means behavior only
executes when x
changes or y changes
– Behavior assigns a new value
to output port F, computed
using built-in operator "or"
Digital Design
Copyright © 2006
Frank Vahid
library ieee;
use ieee.std_logic_1164.all;
entity OR2 is
port (x, y: in std_logic;
F: out std_logic
);
end OR2;
architecture behavior of OR2 is
begin
process (x, y)
begin
F <= x or y;
end process;
end behavior;
10
Describing Combinational Behavior in VHDL
• Describing a custom
function's behavior
– Desired function: f = c'*(h+p)
– Entity defines input/output ports
(not shown)
– Architecture
• Process
– Sensitive to c, h, and p
– Assigns a new value to output
port f, computed using built-in
operators "not", "and", and "or"
Digital Design
Copyright © 2006
Frank Vahid
architecture beh of DoorOpener is
begin
process(c, h, p)
begin
f <= not(c) and (h or p);
end process;
end beh;
11
Describing Combinational Behavior in Verilog
• Describing an OR gate's
behavior
– Module declares input/output
ports
• Also indicates that F is "reg"
• Means F stores value
– By default, ports are wires,
having no storage
– "always" procedure executes
statement block when change
occurs on x or on y
module OR2(x,y,F);
input x, y;
output F;
reg F;
always @(x or y)
begin
F <= x | y;
end
endmodule
• "Sensitive" to x and y
• Assigns value to F, computed
using built-in OR operator "|"
Digital Design
Copyright © 2006
Frank Vahid
12
Describing Combinational Behavior in Verilog
• Describing a custom
function's behavior
– Desired function: f = c'*(h+p)
– Module defines input/output
ports
• Output f defined as "reg"
– "always" procedure sensitive to
inputs
module DoorOpener(c,h,p,f);
input c, h, p;
output f;
reg f;
always @(c or h or p)
begin
f <= (~c) & (h | p);
end
endmodule
• Assigns value to f, computed
using built-in operators for NOT
(~), AND (&), and OR (|)
Digital Design
Copyright © 2006
Frank Vahid
13
Describing Combinational Behavior in SystemC
• Describing an OR gate's
behavior
– Module declares input/output
ports
– Constructor (CTOR)
• Indicates module described by a
method (procedure) "comblogic"
• Sensitive to x and y
– Method "comblogic" assigns F a
new value using built-in OR
operator "|"
• Reading input port done using
.read() function defined for input
port type; likewise, writing done
using .write() function
Digital Design
Copyright © 2006
Frank Vahid
#include "systemc.h"
SC_MODULE(OR2)
{
sc_in<sc_logic> x, y;
sc_out<sc_logic> F;
SC_CTOR(OR2)
{
SC_METHOD(comblogic);
sensitive << x << y;
}
void comblogic()
{
F.write(x.read() | y.read());
}
};
14
Describing Combinational Behavior in SystemC
• Describing a custom function's
behavior
– Desired function: f = c'*(h+p)
– Module defines input/output ports
– Constructor
# i nc l ude
SC_ MODUL E ( Do o r Op e n e r )
{
s c _ i n<s c _ l ogi c > c , h ,
s c _ out <s c _ l ogi c > f ;
– "comblogic" method
Digital Design
Copyright © 2006
Frank Vahid
p;
SC_ CT OR( Do o r Op e n e r )
{
SC_ MET HOD ( c o mb l o g i c ) ;
s e ns i t i v e << c << h << p ;
}
• Indicates module described by a
method (procedure) "comblogic"
• Sensitive to c, h, and p
• Assigns value to f, computed
using built-in operators for NOT
(~), AND (&), and OR (|)
" s y s t e mc . h "
v o i d c o mb l o g i c ( )
{
f . wr i t e ( ( ~ c . r e a d ( ) ) & ( h . r e a d ( )
p. r ead( ) ) ) ;
}
} ;
15
|
Testbenches
• Testbench
– Assigns values to a system's inputs, check that system outputs
correct values
– A key use of HDLs is to simulate system to ensure design is correct
Testbench
Set input
values,
check
output
values
Digital Design
Copyright © 2006
Frank Vahid
SystemToTest
16
Testbench in VHDL
• Entity
l i br a r y i e e e ;
us e i e e e . s t d _ l o g i c _ 1 1 6 4 . a l l ;
– No inputs or outputs
e nt i t y Te s t b e n c h
e nd Te s t b e n c h ;
• Architecture
– Declares component to test,
declares signals
– Instantiates component, connects
to signals
– Process writes input signals,
checks output signal
a r c hi t e c t ur e b e h a v i o r of Te s t b e n c h i s
c o mp o n e n t Do o r Op e n e r
por t ( c , h , p : i n s t d _ l o g i c ;
f : out s t d _ l o g i c
) ;
e n d c o mp o n e n t ;
s i gna l c , h , p , f : s t d _ l o g i c ;
be gi n
Do o r Op e n e r 1 : Do o r Op e n e r p o r t ma p ( c , h , p , f ) ;
pr oc e s s
be gi n
- - case 0
c <= ' 0' ; h <= ' 0' ; p <= ' 0' ;
wa i t f o r 1 n s ;
a s s e r t ( f = ' 0 ' ) r e p o r t " Ca s e 0 f a i l e d " ;
• Waits a small amount of time
after writing input signals
• Checks for correct output value
using "assert" statement
DoorOpener1
Testbench
process
Digital Design
Copyright © 2006
Frank Vahid
Set input
values,
check
output
values
SystemToTest
i s
- - case 1
c <= ' 0' ; h <= ' 0' ; p <= ' 1' ;
wa i t f o r 1 n s ;
a s s e r t ( f = ' 1 ' ) r e p o r t " Ca s e 1 f a i l e d " ;
- - ( c a s e s 2 - 6 o mi t t e d f r o m f i g u r e )
- - case 7
c <= ' 1' ; h <= ' 1' ; p <= ' 1' ;
wa i t f o r 1 n s ;
a s s e r t ( f = ' 0 ' ) r e p o r t " Ca s e 7 f a i l e d " ;
wa i t ; - - p r o c e s s
e nd pr oc e s s ;
e nd b e h a v i o r ;
does
not
wa k e u p a g a i n
17
Testbench in Verilog
• Module
– Three register signals for
inputs (values must be written and
mo d u l e T e s t b e n c h ;
r eg c, h, p;
wi r e f ;
stored)
– One wire signal for output
Do o r Op e n e r
Do o r Op e n e r 1 ( c ,
h,
p,
f ) ;
(value is only read, need not be stored)
– Instantiates component,
connects to signals
– "initial" procedure executed
only once at beginning
• Sets input values
• Displays output value
i ni t i a l
be gi n
/ / case 0
c <= 0; h <= 0; p <= 0;
# 1 $ d i s p l a y ( " f = %b " , f ) ;
/ / case 1
c <= 0; h <= 0; p <= 1;
# 1 $ d i s p l a y ( " f = %b " , f ) ;
/ / ( c a s e s 2 - 6 o mi t t e d f r o m f i g u r e )
/ / case 7
c <= 1; h <= 1; p <= 1;
# 1 $ d i s p l a y ( " f = %b " , f ) ;
e nd
e n d mo d u l e
DoorOpener1
Testbench
"initial" procedure
Digital Design
Copyright © 2006
Frank Vahid
Set input
values,
check
output
values
SystemToTest
18
Testbench in SystemC
# i nc l ude
• Module
– Testbench is its own module
– Three outputs, one for each input
of system to test
– One input, for the one output of
the system to test
– Constructor defined as THREAD
SC_ MODUL E ( T e s t b e n c h )
{
s c _ out <s c _ l ogi c > c _ t ,
s c _ i n<s c _ l ogi c > f _ t ;
p_t ;
v oi d t e s t b e n c h _ p r o c ( )
{
/ / case 0
c _ t . wr i t e ( SC_ L OGI C_ 0 ) ;
h _ t . wr i t e ( SC_ L OGI C_ 0 ) ;
p _ t . wr i t e ( SC_ L OGI C_ 0 ) ;
wa i t ( 1 , SC_ NS) ;
a s s e r t ( f _ t . r e a d ( ) = = SC_ L OGI C_ 0 ) ;
– testbench procedure writes
outputs, waits for small amount of
time, checks for correct output
/ / case
c _ t . wr i t
h _ t . wr i t
p _ t . wr i t
wa i t ( 1 ,
asser t (
• assert function prints error if
condition is not true
DoorOpener1
1
e ( SC_ L OGI
e ( SC_ L OGI
e ( SC_ L OGI
SC_ NS) ;
f _t . r ead(
C_ 0 ) ;
C_ 0 ) ;
C_ 1 ) ;
)
= = SC_ L OGI C_ 1 ) ;
/ / ( c a s e s 2 - 6 o mi t t e d f r o m f i g u r e )
/ / case 7
c _ t . wr i t e ( SC_ L OGI C_ 1 ) ;
h _ t . wr i t e ( SC_ L OGI C_ 1 ) ;
p _ t . wr i t e ( SC_ L OGI C_ 1 ) ;
wa i t ( 1 , SC_ NS) ;
a s s e r t ( f _ t . r e a d ( ) = = SC_ L OGI C_ 0 ) ;
Testbench
Digital Design
Copyright © 2006
Frank Vahid
h_t ,
SC_ CT OR( T e s t b e n c h )
{
SC_ T HREAD( t e s t b e n c h _ p r o c ) ;
}
• Like MODULE, but allows use of
"wait" to control timing
Set input
values,
check
output
values
" s y s t e mc . h "
SystemToTest
s c _ s t op( ) ;
}
} ;
19
Sequential Logic Description using Hardware
Description Languages
9.3
• Will consider description of three sequential components
– Registers
– Oscillators
– Controllers
si
a
tap
a
rtn
o
co
t
g
Digital Design
Copyright © 2006
Frank Vahid
20
Describing a 4-bit Register in VHDL
• Entity
– 4 data inputs, 4 data outputs, and a
clock input
– Use std_logic_vector for 4-bit data
• I: in std_logic_vector(3 downto 0)
• I <= "1000" would assign I(3)=1,
I(2)=0, I(1)=0, I(0)=0
• Architecture
– Process sensitive to clock input
• First statement detects if change on
clock was a rising edge
• If clock change was rising edge,
sets output Q to input I
• Ports are signals, and signals store
values – thus, output retains new
value until set to another value
Digital Design
Copyright © 2006
Frank Vahid
l i br a r y i e e e ;
us e i e e e . s t d _ l o g i c _ 1 1 6 4 . a l l ;
e n t i t y Re g 4 i s
p o r t ( I : i n s t d _ l o g i c _ v e c t o r ( 3 d o wn t o 0 ) ;
Q: o u t s t d _ l o g i c _ v e c t o r ( 3 d o wn t o 0 ) ;
cl k: i n st d_l ogi c
) ;
e n d Re g 4 ;
a r c h i t e c t u r e b e h a v i o r o f Re g 4 i s
be gi n
pr oc e s s ( c l k )
be gi n
i f ( c l k =' 1 ' a nd c l k ' e v e nt )
Q <= I ;
e nd i f ;
e nd pr oc e s s ;
e nd b e h a v i o r ;
t he n
21
Describing a 4-bit Register in Verilog
• Module
– 4 data inputs, 4 data outputs,
and a clock input
– Define data inputs/outputs as
vectors
• input [3:0] I
• I<=4'b1000 assigns I[3]=1,
I[2]=0, I[1]=0, I[0]=0
• Output defined as register to
store value
mo d u l e Re g 4 ( I , Q,
i nput [ 3 : 0 ] I ;
i nput c l k ;
o u t p u t [ 3 : 0 ] Q;
r e g [ 3 : 0 ] Q;
a l wa y s @( p o s e d g e
be gi n
Q <= I ;
e nd
e n d mo d u l e
cl k) ;
cl k)
– "always" procedure sensitive to
positive (rising) edge of clock
• Sets output Q to input I
Digital Design
Copyright © 2006
Frank Vahid
22
Describing a 4-bit Register in SystemC
• Module
– 4 data inputs, 4 data outputs,
and a clock input
– Define data inputs/outputs as
vectors
• sc_in<sc_lv<4> > I;
• I<=“1000" assigns I[3]=1, I[2]=0,
I[1]=0, I[0]=0
# i nc l ude
SC_ MODUL E ( Re g 4 )
{
sc _i n<sc _l v <4> > I ;
s c _ o u t < s c _ l v < 4 > > Q;
s c _ i n<s c _ l ogi c > c l k ;
SC_ CT OR( Re g 4 )
{
SC_ MET HOD( s e q _ l o g i c ) ;
s e ns i t i v e _ pos << c l k ;
}
– Constructor calls seq_logic
method, sensitive to positive
(rising) edge of clock
• seq_logic writes output Q with
input I
• Output port is signal, and signal
has storage, thus output retains
value
Digital Design
Copyright © 2006
Frank Vahid
" s y s t e mc . h "
v oi d s e q _ l o g i c ( )
{
Q. wr i t e ( I . r e a d ( ) ) ;
}
} ;
23
Describing an Oscillator in VHDL
• Entity
– Defines clock output
• Architecture
– Process
• Has no sensitivity list, so
executes non-stop as infinite loop
• Sets clock to 0, waits 10 ns, sets
clock to 1, waits 10 ns, repeats
Digital Design
Copyright © 2006
Frank Vahid
l i br a r y i e e e ;
us e i e e e . s t d _ l o g i c _ 1 1 6 4 . a l l ;
e n t i t y Os c i s
por t ( c l k : out
e n d Os c ;
st d_l ogi c
a r c hi t e c t ur e b e h a v i o r
be gi n
pr oc e s s
be gi n
c l k <= ' 0' ;
wa i t f o r 1 0 n s ;
c l k <= ' 1' ;
wa i t f o r 1 0 n s ;
e nd pr oc e s s ;
e nd b e h a v i o r ;
of
Os c
) ;
i s
24
Describing an Oscillator in Verilog
• Module
– Has one output, clk
• Declare as "reg" to hold value
– "always" procedure
• Has no sensitivity list, so
executes non-stop as infinite
loop
• Sets clock to 0, waits for 10 ns,
sets clock to 1, waits for 10 ns,
repeats
Digital Design
Copyright © 2006
Frank Vahid
module Osc(clk);
output clk;
reg clk;
always
begin
clk <= 0;
#10;
clk <= 1;
#10;
end
endmodule
25
Describing an Oscillator in SystemC
• Module
– Has one output, clk
– Constructor creates single
thread
# i nc l ude
" s y s t e mc . h "
SC_ MODUL E ( Os c )
{
s c _ out <s c _ l ogi c > c l k ;
SC_ CT OR( Os c )
{
SC_ T HREAD( s e q _ l o g i c ) ;
}
• Thread consists of infinite loop
– while (true) {
• Sets clock to 0, waits 10 ns,
sets clock to 1, waits 10 ns,
repeats
v oi d s e q _ l o g i c ( )
{
wh i l e ( t r u e ) {
c l k . wr i t e ( SC_ L OGI C_ 0 ) ;
wa i t ( 1 0 , SC_ NS) ;
c l k . wr i t e ( SC_ L OGI C_ 1 ) ;
wa i t ( 1 0 , SC_ NS) ;
}
}
} ;
Digital Design
Copyright © 2006
Frank Vahid
26
Off
FSM
inputs
Inputs: b; Outputs: x
x=0
b’
Combinational n1
logic
n0
s1 s0
b
•
x=1
x=1
x=1
On1
On2
On3
x
b
clk
FSM
outputs
Describing a Controller in
VHDL
FSM behavior captured using architecture
with 2 processes
– First process models state register
• Asynchronous reset sets state to "S_Off"
• Rising clock edge sets currentstate to
nextstate
– Second process models combinational logic
– Note declaration of new type, statetype
Digital Design
Copyright © 2006
Frank Vahid
e n t i t y L a s e r T i me r i s
por t ( b : i n s t d _ l o g i c ;
x : out s t d _ l o g i c ;
cl k, r st : i n st d l ogi c
) ;
e n d L a s e r T i me r ;
outputs
FSM
State register
• Sensitive to currentstate and FSM inputs
• Sets FSM outputs based on currentstate
• Sets nextstate based on currentstate and
present FSM input values
l i br a r y i e e e ;
us e i e e e . s t d _ l o g i c _ 1 1 6 4 . a l l
a r c h i t e c t u r e b e h a v i o r o f L a s e r T i me r i s
t y pe s t a t e t y p e i s
( S_ Of f , S_ On 1 , S_ On 2 , S_ On 3 ) ;
s i gna l c u r r e n t s t a t e , n e x t s t a t e :
st at et ype;
be gi n
s t a t e r e g : pr oc e s s ( c l k , r s t )
be gi n
i f ( r s t =' 1 ' ) t he n - - i n t i a l s t a t e
c u r r e n t s t a t e < = S_ Of f ;
e l s i f ( c l k =' 1 ' a nd c l k ' e v e nt ) t he n
c ur r ent s t at e <= nex t s t at e;
e nd i f ;
e nd pr oc e s s ;
c o mb l o g i c :
be gi n
case cur
wh e n
x
i f
pr oc e s s
( cur r ent st at e,
r ent st at e
S_ Of f = >
<= ' 0' ; - ( b=' 0' ) t
next st at e
el se
next st at e
e nd i f ;
wh e n S_ On 1 = >
x <= ' 1' ; - nex t s t at e <=
wh e n S_ On 2 = >
x <= ' 1' ; - nex t s t at e <=
wh e n S_ On 3 = >
x <= ' 1' ; - nex t s t at e <=
e nd c a s e ;
e nd pr oc e s s ;
e nd b e h a v i o r ;
b)
i s
l aser of f
he n
< = S_ Of f ;
< = S_ On 1 ;
l aser on
S_ On 2 ;
l aser st i l l
S_ On 3 ;
on
l aser st i l l
S_ Of f ;
on
27
Off
FSM
inputs
Inputs: b; Outputs: x
x=0
b’
Combinational n1
logic
n0
s1 s0
b
•
x=1
x=1
x=1
On1
On2
On3
x
b
clk
FSM
outputs
Describing a Controller in
Verilog
p a r a me t e r
outputs
FSM
State register
FSM behavior captured using 2 "always"
procedures
– First procedure models state register
• Asynchronous reset sets state to "S_Off"
• Rising clock edge sets currentstate to
nextstate
– Second process models combinational logic
• Sensitive to currentstate and FSM inputs
• Sets FSM outputs based on currentstate
• Sets nextstate based on currentstate and
present FSM input values
– Note state register size must be explicit – 2
bits, reg [1:0] currentstate
Digital Design
Copyright © 2006
Frank Vahid
mo d u l e L a s e r T i me r ( b , x ,
i nput b , c l k , r s t ;
out put x ;
r eg x;
S_ Of f = 2 '
S_ On 1 = 2 '
S_ On 2 = 2 '
S_ On 3 = 2 '
cl k,
r st ) ;
b00,
b01,
b10,
b11;
r eg [ 1: 0] cur r ent st at e;
r eg [ 1: 0] next st at e;
/ / st at e r egi st er pr ocedur e
a l wa y s @( p o s e d g e r s t o r p o s e d g e c l k )
be gi n
i f ( r s t ==1) / / i ni t i al s t at e
c u r r e n t s t a t e < = S_ Of f ;
el se
c ur r ent s t at e <= nex t s t at e;
e nd
/ / c o mb i n a t i o n a l l o g i c p r o c e d u r e
a l wa y s @( c u r r e n t s t a t e o r b )
be gi n
case ( cur r ent st at e)
S_ Of f : b e g i n
x <= 0; / / l as er of f
i f ( b==0)
n e x t s t a t e < = S_ Of f ;
el se
n e x t s t a t e < = S_ On 1 ;
e nd
S_ On 1 : b e g i n
x <= 1; / / l as er on
n e x t s t a t e < = S_ On 2 ;
e nd
S_ On 2 : b e g i n
x <= 1; / / l as er s t i l l on
n e x t s t a t e < = S_ On 3 ;
e nd
S_ On 3 : b e g i n
x <= 1; / / l as er s t i l l on
n e x t s t a t e < = S_ Of f ;
e nd
e ndc a s e
e nd
e n d mo d u l e
28
Off
FSM
inputs
Inputs: b; Outputs: x
x=0
b’
b
Combinational n1
logic
n0
s1 s0
b
•
x=1
x=1
x=1
On1
On2
On3
x
clk
FSM
outputs
Describing a Controller in
SystemC
# i nc l ude
e num s t a t e t y p e {
S_ Of f ,
S_ On 1 ,
S_ On 2 ,
SC_ MODUL E ( L a s e r T i me r )
{
s c _ i n<s c _ l ogi c > b , c l k , r s t ;
s c _ out <s c _ l ogi c > x ;
s c _ s i gna l <s t a t e t y p e > c u r r e n t s t a t e ,
S_ On 3 } ;
next st at e;
outputs
FSM
SC_ CT OR( L a s e r T i me r ) {
SC_ MET HOD ( s t a t e r e g ) ;
s e ns i t i v e _ pos << r s t << c l k ;
SC_ MET HOD ( c o mb l o g i c ) ;
s e ns i t i v e << c u r r e n t s t a t e << b ;
}
State register
v oi d s t a t e r e g ( ) {
i f ( r s t . r e a d ( ) = = SC_ L OGI C_ 1 )
c u r r e n t s t a t e = S_ Of f ; / / i n i t i a l
el se
cur r ent st at e = next st at e;
}
v o i d c o mb l o g i c ( ) {
s wi t c h ( c u r r e n t s t a t e ) {
c a s e S_ Of f :
x . wr i t e ( SC_ L OGI C_ 0 ) ; / / l a s e r
i f ( b . r e a d ( ) = = SC_ L OGI C_ 0 )
n e x t s t a t e = S_ Of f ;
el se
n e x t s t a t e = S_ On 1 ;
br e a k ;
c a s e S_ On 1 :
x . wr i t e ( SC_ L OGI C_ 1 ) ; / / l a s e r
n e x t s t a t e = S_ On 2 ;
br e a k ;
c a s e S_ On 2 :
x . wr i t e ( SC_ L OGI C_ 1 ) ; / / l a s e r
n e x t s t a t e = S_ On 3 ;
br e a k ;
c a s e S_ On 3 :
x . wr i t e ( SC_ L OGI C_ 1 ) ; / / l a s e r
n e x t s t a t e = S_ Of f ;
br e a k ;
}
}
FSM behavior captured using 2 methods
– First method models state register
• Asynchronous reset sets state to "S_Off"
• Rising clock edge sets currentstate to
nextstate
– Second process models combinational logic
• Sensitive to currentstate and FSM inputs
• Sets FSM outputs based on currentstate
• Sets nextstate based on currentstate and
present FSM input values
– Note use of new type, statetype
Digital Design
Copyright © 2006
Frank Vahid
" s y s t e mc . h "
} ;
st at e
of f
on
st i l l
on
st i l l
on
29
Datapath Component Description using
Hardware Description Languages
9.4
• Will consider description of three datapath components
– Full-adders
– Carry-ripple adders
– Up-counter
si
a
tap
a
rtn
o
co
t
g
Digital Design
Copyright © 2006
Frank Vahid
30
Describing a Full-Adder in VHDL
a b
• Entity
– Declares
inputs/outputs
• Architecture
– Described
behaviorally (could have
been described structurally)
– Process sensitive to
inputs
– Computes
expressions, sets
outputs
Digital Design
Copyright © 2006
Frank Vahid
ci
s = a xor b xor ci
co = bc + ac + ab
Full
adder
co
s
l i br a r y i e e e ;
us e i e e e . s t d _ l o g i c _ 1 1 6 4 . a l l ;
e n t i t y F u l l Ad d e r i s
por t ( a , b , c i : i n s t d _ l o g i c ;
s , c o : out s t d _ l o g i c
) ;
e n d F u l l Ad d e r ;
a r c h i t e c t u r e b e h a v i o r o f F u l l Ad d e r i s
be gi n
pr oc e s s ( a , b , c i )
be gi n
s <= a x or b x or c i ;
c o <= ( b a nd c i ) or ( a a nd c i ) or
e nd pr oc e s s ;
e nd b e h a v i o r ;
( a a nd b ) ;
31
Describing a Full-Adder in Verilog
a b
ci
• Module
– Declares inputs/outputs
– Described behaviorally (could
s = a xor b xor ci
co = bc + ac + ab
Full
adder
have been described structurally)
– "always" procedure
• Sensitive to inputs
– Computes expressions, sets
outputs
mo d u l e F u l l Ad d e r ( a ,
i nput a , b , c i ;
out put s , c o ;
r eg s, co;
b,
ci ,
s,
a l wa y s @( a o r b o r c i )
be gi n
s <= a ^ b ^ c i ;
c o <= ( b & c i ) | ( a & c i )
e nd
e n d mo d u l e
Digital Design
Copyright © 2006
Frank Vahid
s
co
co) ;
|
( a & b) ;
32
Describing a Full-Adder in SystemC
a b
ci
• Module
– Declares
inputs/outputs
– Described
behaviorally (could have
been described structurally)
– comblogic method
• Computes
expressions, sets
outputs
Digital Design
Copyright © 2006
Frank Vahid
s = a xor b xor ci
co = bc + ac + ab
Full
adder
co
s
#include "systemc.h"
SC_MODULE(FullAdder)
{
sc_in<sc_logic> a, b, ci;
sc_out<sc_logic> s, co;
SC_CTOR(FullAdder)
{
SC_METHOD(comblogic);
sensitive << a << b << ci;
}
void comblogic()
{
s.write(a.read() ^
co.write((b.read()
(a.read()
(a.read()
}
};
b.read() ^ ci.read());
& ci.read()) |
& ci.read()) |
& b.read()));
33
Describing a Carry-Ripple Adder in VHDL
• Entity
– Declares inputs/outputs
– Uses std_logic_vector for
4-bit inputs/outputs
• Architecture
– Described structurally by
composing four fulladders (could have been
described behaviorally instead)
– Declares full-adder
component, instantiates
four full-adders, connects
• Note use of three internal
signals for connecting
carry-out of one stage to
carry-in of next stage
Digital Design
Copyright © 2006
Frank Vahid
a3 b3
a2 b2
a1 b1
a0 b0 ci
a b ci
a b ci
a b ci
a b ci
FA
FA
FA
FA
co
s
co
s3
co
co3
l i br a r y i e e e ;
us e i e e e . s t d _ l o g i c _ 1 1 6 4 . a l l ;
e n t i t y Ca r r y Ri
por t ( a :
b:
ci :
s:
co:
) ;
e n d Ca r r y Ri p p l
a r c hi t e c t ur e
c o mp o n e n t
por t (
ppl
i n
i n
i n
out
out
s
s2
co
co2
s
s1
co
co1
e Ad d e r 4 i s
s t d _ l o g i c _ v e c t o r ( 3 d o wn t o 0 ) ;
s t d _ l o g i c _ v e c t o r ( 3 d o wn t o 0 ) ;
st d_l ogi c;
s t d _ l o g i c _ v e c t o r ( 3 d o wn t o 0 ) ;
st d_l ogi c
e Ad d e r 4 ;
st r
Fu l
a,
s,
u c t u r e o f Ca r r y Ri p p l e Ad d e r 4
l Ad d e r
b, ci : i n st d_l ogi c;
c o : out s t d _ l o g i c
) ;
e n d c o mp o n e n t ;
s i gna l c o 1 , c o 2 , c o 3 :
be gi n
F u l l Ad d e r 1 : F u l l Ad d e r
p o r t ma p ( a ( 0 ) , b (
F u l l Ad d e r 2 : F u l l Ad d e r
p o r t ma p ( a ( 1 ) , b (
F u l l Ad d e r 3 : F u l l Ad d e r
p o r t ma p ( a ( 2 ) , b (
F u l l Ad d e r 4 : F u l l Ad d e r
p o r t ma p ( a ( 3 ) , b (
e nd s t r u c t u r e ;
i s
st d_l ogi c;
0) ,
ci ,
s( 0) ,
co1) ;
1) ,
co1,
s( 1) ,
co2) ;
2) ,
co2,
s( 2) ,
co3) ;
3) ,
co3,
s( 3) ,
co) ;
34
s
s0
Describing a Carry-Ripple Adder in Verilog
• Module
– Declares inputs/outputs
– Uses vectors for 4-bit
inputs/outputs
– Described structurally by
composing four fulladders (could have been
described behaviorally instead)
– Instantiates four fulladders, connects
• Note use of three internal
wires for connecting
carry-out of one stage to
carry-in of next stage
a3 b3
a2 b2
a1 b1
a0 b0 ci
a b ci
a b ci
a b ci
a b ci
FA
FA
FA
FA
co
s
co
s3
co
co3
s
s2
co
s
co2
s1
mo d u l e Ca r r y Ri p p l e Ad d e r 4 ( a ,
i nput [ 3 : 0 ] a ;
i nput [ 3 : 0 ] b ;
i nput c i ;
out put [ 3 : 0 ] s ;
out put c o ;
wi r e c o 1 ,
co2,
F u l l Ad d e r
F u l l Ad d e r 1 ( a [
s[
F u l l Ad d e r 2 ( a [
s[
F u l l Ad d e r 3 ( a [
s[
F u l l Ad d e r 4 ( a [
s[
F u l l Ad d e r
F u l l Ad d e r
F u l l Ad d e r
b,
co
s
co1
ci ,
s,
s0
co) ;
co3;
0]
0]
1]
1]
2]
2]
3]
3]
,
,
,
,
,
,
,
,
b[ 0]
co1)
b[ 1]
co2)
b[ 2]
co3)
b[ 3]
co) ;
,
;
,
;
,
;
,
ci ,
co1,
co2,
co3,
e n d mo d u l e
Digital Design
Copyright © 2006
Frank Vahid
35
Describing a Carry-Ripple Adder in SystemC
• Module
– Declares
inputs/outputs
– Uses vectors for 4-bit
inputs/outputs
– Described structurally
by composing four
full-adders (could have
# i nc l ude
# i nc l ude
SC_ MODUL E ( Ca r r y Ri p p l e Ad d e r 4 )
{
s c _ i n<s c _ l ogi c > a [ 4 ] ;
s c _ i n<s c _ l ogi c > b [ 4 ] ;
s c _ i n<s c _ l ogi c > c i ;
s c _ out <s c _ l ogi c > s [ 4 ] ;
s c _ o ut <s c _ l ogi c > c o ;
s c _ s i gna l <s c _ l ogi c > c o 1 ,
Fu l
Fu l
Fu l
Fu l
been described
behaviorally instead)
Ad d e r
Ad d e r
Ad d e r
Ad d e r
Fu l
Fu l
Fu l
Fu l
SC_ CT OR( Ca r
F u l l Ad d e r
F u l l Ad d e r
F u l l Ad d e r
F u l l Ad d e r
{
F u l l Ad d e r
F u l l Ad d e r
F u l l Ad d e r
– Instantiates four fulladders, connects
• Note use of three
internal wires for
connecting carryout of one stage to
carry-in of next
stage
Digital Design
Copyright © 2006
Frank Vahid
l
l
l
l
}
} ;
a3 b3
a2 b2
a1 b1
a0 b0 ci
a b ci
a b ci
a b ci
a b ci
FA
FA
FA
FA
" s y s t e mc . h "
" f ul l adder . h"
l
l
l
l
Ad d e r
Ad d e r
Ad d e r
Ad d e r
r y Ri
_1( "
_2( "
_3( "
_4( "
ppl
Fu l
Fu l
Fu l
Fu l
co2,
co
s
co
s3
co
co3
s
s2
co
co2
s
s1
co
co1
co3;
_1;
_2;
_3;
_4;
e4) :
l Ad d e r
l Ad d e r
l Ad d e r
l Ad d e r
_1"
_2"
_3"
_4"
) ,
) ,
) ,
)
_ 1 . a ( a [ 0 ] ) ; F u l l Ad d e r _ 1 . b ( b [ 0 ] ) ;
_ 1 . c i ( c i ) ; F u l l Ad d e r _ 1 . s ( s [ 0 ] ) ;
_1. co( co1) ;
F u l l Ad d e r _ 2 . a ( a [ 1 ] ) ;
F u l l Ad d e r _ 2 . c i ( c o 1 ) ;
F u l l Ad d e r _ 2 . c o ( c o 2 ) ;
F u l l Ad d e r _ 2 . b ( b [ 1 ] ) ;
F u l l Ad d e r _ 2 . s ( s [ 1 ] ) ;
F u l l Ad d e r _ 3 . a ( a [ 2 ] ) ;
F u l l Ad d e r _ 3 . c i ( c o 2 ) ;
F u l l Ad d e r _ 3 . c o ( c o 3 ) ;
F u l l Ad d e r _ 3 . b ( b [ 2 ] ) ;
F u l l Ad d e r _ 3 . s ( s [ 2 ] ) ;
F u l l Ad d e r _ 4 . a ( a [ 3 ] ) ;
F u l l Ad d e r _ 4 . c i ( c o 3 ) ;
F u l l Ad d e r _ 4 . c o ( c o ) ;
F u l l Ad d e r _ 4 . b ( b [ 3 ] ) ;
F u l l Ad d e r _ 4 . s ( s [ 3 ] ) ;
36
s
s0
Describing an Up-Counter in VHDL
l i br a r y i e e e ;
us e i e e e . s t d _ l o g i c _ 1 1 6 4 . a l l ;
4-bit up-counter
cnt
e n t i t y Up Co u n t e r i s
por t ( c l k : i n s t d _ l o g i c ;
c nt : i n st d_l ogi c;
C: o u t s t d _ l o g i c _ v e c t o r ( 3
t c : out s t d _ l o g i c
) ;
e n d Up Co u n t e r ;
ld
4-bit register
tempC
4
4
4
tc
+1
4
C
• Described structurally (could have
been described behaviorally)
• Includes process that updates
output port C whenever
internal signal tempC changes
– Need tempC signal because
can't read C due to C being
an output port
Digital Design
Copyright © 2006
Frank Vahid
a r c hi t e c t ur e
c o mp o n e n t
por t (
d o wn t o 0 ) ;
s t r u c t u r e o f Up Co u n t e r i s
Re g 4
I : i n s t d _ l o g i c _ v e c t o r ( 3 d o wn t o 0 ) ;
Q: o u t s t d _ l o g i c _ v e c t o r ( 3 d o wn t o 0 ) ;
cl k, l d: i n st d_l ogi c
) ;
e n d c o mp o n e n t ;
c o mp o n e n t I n c 4
p o r t ( a : i n s t d _ l o g i c _ v e c t o r ( 3 d o wn t o 0 ) ;
s : o u t s t d _ l o g i c _ v e c t o r ( 3 d o wn t o 0 )
) ;
e n d c o mp o n e n t ;
c o mp o n e n t AND4
p o r t ( w, x , y , z : i n s t d _ l o g i c ;
F: out s t d _ l o g i c
) ;
e n d c o mp o n e n t ;
s i g n a l t e mp C: s t d _ l o g i c _ v e c t o r ( 3 d o wn t o 0 ) ;
s i g n a l i n c C: s t d _ l o g i c _ v e c t o r ( 3 d o wn t o 0 ) ;
be gi n
Re g 4 _ 1 : Re g 4 p o r t ma p ( i n c C, t e mp C, c l k , c n t ) ;
I n c 4 _ 1 : I n c 4 p o r t ma p ( t e mp C, i n c C) ;
AND4 _ 1 : AND4 p o r t ma p ( t e mp C( 3 ) , t e mp C( 2 ) ,
t e mp C( 1 ) , t e mp C( 0 ) , t c ) ;
o u t p u t C: p r o c e s s ( t e mp C)
be gi n
C < = t e mp C;
e nd pr oc e s s ;
e nd s t r u c t u r e ;
37
Describing an Up-Counter in Verilog
mo d u l e Re g 4 ( I , Q, c l k ,
i nput [ 3 : 0 ] I ;
i nput c l k , l d ;
o u t p u t [ 3 : 0 ] Q;
/ / d e t a i l s n o t s h o wn
e n d mo d u l e
4-bit up-counter
cnt
ld
4-bit register
tempC
4
4
4
tc
+1
4
nc4( a, s) ;
[ 3: 0] a;
[ 3: 0] s;
a i l s n o t s h o wn
e
C
• Described structurally (could have
been described behaviorally)
• Includes always procedure
that updates output C
whenever internal wire tempC
changes
– Need tempC wire because
can't use C in the connection
statements
Digital Design
Copyright © 2006
Frank Vahid
mo d u l e I
i nput
out put
/ / det
e n d mo d u l
l d) ;
mo d u l e AND4 ( w, x , y , z , F ) ;
i n p u t w, x , y , z ;
out put F;
/ / d e t a i l s n o t s h o wn
e n d mo d u l e
mo d u l e Up Co u n t e r ( c l k ,
i nput c l k , c n t ;
o u t p u t [ 3 : 0 ] C;
r e g [ 3 : 0 ] C;
out put t c ;
wi r e [ 3 : 0 ]
wi r e [ 3 : 0 ]
cnt ,
C,
t c) ;
t e mp C;
i n c C;
Re g 4 Re g 4 _ 1 ( i n c C, t e mp C, c l k , c n t ) ;
I n c 4 I n c 4 _ 1 ( t e mp C, i n c C) ;
AND4 AND4 _ 1 ( t e mp C[ 3 ] , t e mp C[ 2 ] ,
t e mp C[ 1 ] , t e mp C[ 0 ] , t c ) ;
a l wa y s @( t e mp C)
be gi n
C < = t e mp C;
e nd
e n d mo d u l e
38
Describing an Up-Counter in SystemC
#i
#i
#i
#i
4-bit up-counter
cnt
nc l
nc l
nc l
nc l
ude
ude
ude
ude
"
"
"
"
s y s t e mc . h "
r eg4. h"
i nc4. h"
and4. h"
ld
4-bit register
tempC
4
4
4
tc
SC_ MODUL E ( Up Co u n t e r )
{
s c _ i n<s c _ l ogi c > c l k ,
s c _ o u t < s c _ l v < 4 > > C;
s c _ out <s c _ l ogi c > t c ;
+1
s c _ s i g n a l < s c _ l v < 4 > > t e mp C, i n c C;
s c _ s i g n a l < s c _ l o g i c > t e mp C_ b [ 4 ] ;
4
C
Re g 4 Re g 4 _ 1 ;
I nc4 I nc4_1;
AND4 AND4 _ 1 ;
• Described structurally (could have been
SC_ CT OR( Up Co u n t e r )
described behaviorally)
• Includes method that updates
output C whenever internal signal
tempC changes
Digital Design
Copyright © 2006
Frank Vahid
:
Re g 4 _ 1 ( " Re g 4 _ 1 " ) ,
I nc4_1( " I nc4_1" ) ,
AND4 _ 1 ( " AND4 _ 1 " )
{
Re g 4 _ 1 . I ( i n c C) ; Re g 4 _ 1 . Q( t e mp C) ;
Re g 4 _ 1 . c l k ( c l k ) ; Re g 4 _ 1 . l d ( c n t ) ;
I n c 4 _ 1 . a ( t e mp C) ;
I n c 4 _ 1 . s ( i n c C) ;
AND4 _ 1 . w( t e mp C_ b [ 0 ] ) ;
AND4 _ 1 . y ( t e mp C_ b [ 2 ] ) ;
AND4 _ 1 . F ( t c ) ;
– Need tempC signal because can't
use C in the connection statements
• Can't use logic vector bits
individually for connections, so
needed tempC_b array too
cnt ;
AND4 _ 1 . x ( t e mp C_ b [ 1 ] ) ;
AND4 _ 1 . z ( t e mp C_ b [ 3 ] ) ;
SC_ MET HOD( c o mb l o g i c ) ;
s e n s i t i v e < < t e mp C;
}
v o i d c o mb l
{
t e mp C_ b [
t e mp C_ b [
t e mp C_ b [
t e mp C_ b [
C. wr i t e (
}
} ;
ogi c( )
0] = t
1] = t
2] = t
3] = t
t e mp C)
e mp C.
e mp C.
e mp C.
e mp C.
;
r
r
r
r
ead(
ead(
ead(
ead(
)
)
)
)
[
[
[
[
0]
1]
2]
3]
;
;
;
;
39
RTL Design using Hardware Description
Languages
9.5
• Will consider two forms of RTL descriptions
– High-level state machine
– Controller and datapath
si
a
tap
a
rtn
o
co
t
g
Digital Design
Copyright © 2006
Frank Vahid
40
High-Level State Machine of the Laser-Based
Distance Measurer in VHDL
•
•
•
Architecture
similar to FSM,
but single
process
Asynch reset
forces to state
S0
For each rising
clock
– Perform
state's
computation
– Prepare to
go to next
state based
on state and
inputs
l i br a r y i e e e ;
us e i e e e . s t d _ l o g i c _ 1 1 6 4 . a l l ;
us e i e e e . s t d _ l o g i c _ a r i t h . a l l ;
(continued from Figure 9.34)
e n t i t y L a s e r Di s t Me a s u r e r i s
por t ( c l k , r s t : i n s t d _ l o g i c ;
B, S: i n s t d _ l o g i c ;
L : out s t d _ l o g i c ;
D: o u t u n s i g n e d ( 1 5 d o wn t o 0 )
) ;
e n d L a s e r Di s t Me a s u r e r ;
a r c hi t e c t ur e b e h a v i o r of
t y p e s t a t e t y p e i s ( S0 ,
s i gna l
s i gna l
L a s e r Di s t Me a s u r e r
S1 , S2 , S3 , S4 ) ;
st at e : st at et ype;
Dc t r : u n s i g n e d ( 1 5
d o wn t o
i s
0) ;
c o n s t a n t U_ Z ERO :
u n s i g n e d ( 1 5 d o wn t o 0 ) : = " 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 " ;
c o n s t a n t U_ ONE : u n s i g n e d ( 0 d o wn t o 0 ) : = " 1 " ;
be gi n
s t a t e ma c h i n e : p r o c e s s ( c l k , r s t )
be gi n
i f ( r s t =' 1 ' ) t he n
L <= ' 0' ;
D < = U_ Z ERO;
Dc t r < = U_ Z ERO;
s t a t e < = S0 ;
- - i ni t i al st at e
e l s i f ( c l k =' 1 ' a nd c l k ' e v e n t ) t he n
case st at e i s
wh e n S0 = >
L <= ' 0' ;
- - l aser of f
D < = U_ Z ERO;
- - cl ear D
s t a t e < = S1
(continued in Figure 9.35)
Digital Design
Copyright © 2006
Frank Vahid
S1
L=0
D=0
Dctr = 0
--
r eset
count
--
l aser
on
--
l aser
of f
--
cal cul at e D
S’
B’
S0
wh e n S1 = >
Dc t r < = U_ Z ERO;
i f ( B= ' 1 ' ) t h e n
s t a t e < = S2 ;
el se
s t a t e < = S1 ;
e nd i f ;
wh e n S2 = >
L <= ' 1' ;
s t a t e < = S3 ;
wh e n S3 = >
L <= ' 0' ;
Dc t r < = Dc t r + 1 ;
i f ( S= ' 1 ' ) t h e n
s t a t e < = S4 ;
el se
s t a t e < = S3 ;
e nd i f ;
wh e n S4 = >
D < = SHR( Dc t r , U_ ONE) ;
s t a t e < = S1 ;
e nd c a s e ;
e nd i f ;
e nd pr oc e s s ;
e nd b e h a v i o r ;
B
S2
L=1
S3
S
L=0
Dctr = Dctr + 1
S4
D = Dctr / 2
(calculate D)
41
mo d u l e L a s e r Di s t Me a s u r e r ( c l k ,
i n p u t c l k , r s t , B, S;
out put L ;
o u t p u t [ 1 5 : 0 ] D;
r eg L;
r e g [ 1 5 : 0 ] D;
p a r a me t e r
S0
S1
S2
S3
S4
=
=
=
=
=
3'
3'
3'
3'
3'
r st ,
B,
S,
b000,
b001,
b010,
b011,
b100;
L,
D) ;
High-Level State Machine of
the Laser-Based Distance
Measurer in Verilog
•
r eg [ 2: 0] st at e;
r e g [ 1 6 : 0 ] Dc t r ;
a l wa y s @( p o s e d g e r s t o r p o s e d g e c l k )
be gi n
i f ( r s t ==1 ) be gi n
L <= 0;
D <= 0;
Dc t r < = 0 ;
s t a t e < = S0 ; / / i n i t i a l s t a t e
e nd
e l s e be gi n
case ( st at e)
S0 : b e g i n
L <= 0;
/ / l aser of f
D <= 0;
/ / cl ear D
s t a t e < = S1 ;
e nd
S1 : b e g i n
Dc t r < = 0 ;
/ / r eset count
i f ( B= = 1 )
s t a t e < = S2 ;
el se
s t a t e < = S1 ;
e nd
S2 : b e g i n
L <= 1;
/ / l aser on
s t a t e < = S3 ;
e nd
(continued in Figure 9.37)
Digital Design
Copyright © 2006
Frank Vahid
(continued from Figure 9.36)
S3 : b e g i n
L <= 0;
/ / l aser of f
Dc t r < = Dc t r + 1 ;
i f ( S= = 1 )
s t a t e < = S4 ;
el se
s t a t e < = S3 ;
e nd
S4 : b e g i n
D < = Dc t r > > 1 ; / / c a l c u l a t e D
s t a t e < = S1 ;
e nd
e ndc a s e
e nd
e nd
e n d mo d u l e
S1
L=0
D=0
Dctr = 0
•
– Perform
state's
computation
– Prepare to go
to next state
based on
state and
inputs
S’
B’
S0
•
Module similar
to FSM, but
single "always"
procedure
Asynch reset
forces to state
S0
For each rising
clock
B
S2
L=1
S3
S
L=0
Dctr = Dctr + 1
S4
D = Dctr / 2
(calculate D)
42
High-Level State Machine of the Laser-Based
Distance Measurer in SystemC
# i nc l ude
•
•
•
Module similar
to FSM, but
single method
Asynch reset
forces to state
S0
For each rising
clock
– Perform
state's
computation
– Prepare to go
to next state
based on
state and
inputs
" s y s t e mc . h "
e num s t a t e t y p e {
S0 ,
S2 ,
S3 ,
S4 } ;
SC_ MODUL E ( L a s e r Di s t Me a s u r e r )
{
s c _ i n<s c _ l ogi c > c l k , r s t ;
s c _ i n < s c _ l o g i c > B, S;
s c _ out <s c _ l ogi c > L ;
s c _ o u t < s c _ l v < 1 6 > > D;
(continued from Figure 9.38)
s c _ s i gna l <s t a t e t y p e > s t a t e ;
s c _ s i g n a l < s c _ u i n t < 1 6 > > Dc t r ;
SC_ CT OR( L a s e r Di s t Me a s u r e r )
{
SC_ MET HOD( s t a t e ma c h i n e ) ;
s e ns i t i v e _ pos << r s t << c l k ;
}
v o i d s t a t e ma c h i n e ( )
{
i f ( r s t . r e a d ( ) = = SC_ L OGI C_ 1 ) {
}
L . wr i t e ( SC_ L OGI C_ 0 ) ;
}
D. wr i t e ( 0 ) ;
Dc t r = 0 ;
}
s t a t e = S0 ; / / i n i t i a l s t a t e
} ;
}
el se {
s wi t c h ( s t a t e ) {
c a s e S0 :
/ / l aser of f
L . wr i t e ( SC_ L OGI C_ 0 ) ;
/ / cl ear D
D. wr i t e ( 0 ) ;
s t a t e = S1 ;
br e a k ;
c a s e S1 :
/ / cl ear count
Dc t r = 0 ;
i f ( B. r e a d ( ) = = SC_ L OGI C_ 1 )
s t a t e = S2 ;
(continued in Figure 9.39)
Digital Design
Copyright © 2006
Frank Vahid
S1 ,
S’
B’
S0
S1
L=0
D=0
Dctr = 0
c a s e S2 :
L . wr i t e ( SC_ L OGI C_ 1 ) ;
/ / l aser on
s t a t e = S3 ;
br e a k ;
c a s e S3
L . wr i t e ( SC_ L OGI C_ 0 ) ;
/ / l aser of f
Dc t r = Dc t r . r e a d ( ) + 1 ;
i f ( S. r e a d ( ) = = SC_ L OGI C_ 1 )
s t a t e = S4 ;
el se
s t a t e = S3 ;
br e a k ;
c a s e S4 :
D. w r i t e ( Dc t r . r e a d ( ) > > 1 ) ; / / Ca l c u l a t e D
s t a t e = S1 ;
br e a k ;
B
S2
L=1
S3
S
L=0
Dctr = Dctr + 1
S4
D = Dctr / 2
(calculate D)
43
Controller and Datpath of the Laser-Based
Distance Measurer in VHDL
B
L
Dreg_clr
Dreg_ld
Dctr_clr
Dctr_cnt
to display
D
16
300 MHz Clock
Digital Design
Copyright © 2006
Frank Vahid
Datapath
from button
Controller
• At highest level, just
connection of controller
and datapath
components
to laser
from sensor
S
l i br a r y i e e e ;
us e i e e e . s t d _ l o g i c _ 1 1 6 4 . a l l ;
e n t i t y L a s e r Di s t Me a s u r e r i s
por t ( c l k , r s t : i n s t d _ l o g i c ;
B, S: i n s t d _ l o g i c ;
L : out s t d _ l o g i c ;
D: o u t s t d _ l o g i c _ v e c t o r ( 1 5
) ;
e n d L a s e r Di s t Me a s u r e r ;
a r c hi t e c t ur e
c o mp o n e n t
por t (
d o wn t o 0 )
s t r u c t u r e o f L a s e r Di s t Me a s u r e r i s
L DM_ Co n t r o l l e r
c l k , r s t : i n st d_l ogi c;
B, S: i n s t d _ l o g i c ;
L : out s t d _ l o g i c ;
Dr e g _ c l r , Dr e g _ l d : o u t s t d _ l o g i c ;
Dc t r _ c l r , Dc t r _ c n t : o u t s t d _ l o g i c
) ;
e n d c o mp o n e n t ;
c o mp o n e n t L DM_ Da t a p a t h
por t ( c l k : i n s t d _ l o g i c ;
Dr e g _ c l r , Dr e g _ l d : i n s t d _ l o g i c ;
Dc t r _ c l r , Dc t r _ c n t : i n s t d _ l o g i c ;
D: o u t s t d _ l o g i c _ v e c t o r ( 1 5 d o wn t o 0 )
) ;
e n d c o mp o n e n t ;
s i g n a l Dr e g _ c l r , Dr e g _ l d : s t d _ l o g i c ;
s i g n a l Dc t r _ c l r , Dc t r _ c n t : s t d _ l o g i c ;
be gi n
L DM_ Co n t r o l l e r _ 1 : L DM_ Co n t r o l l e r
p o r t ma p ( c l k , r s t , B, S, L ,
Dr e g _ c l r , Dr e g _ l d , Dc t r _ c l r ,
Dc t r _ c n t ) ;
L DM_ Da t a p a t h _ 1 : L DM_ Da t a p a t h
p o r t ma p ( c l k , Dr e g _ c l r , Dr e g _ l d ,
Dc t r _ c l r , Dc t r _ c n t , D) ;
e nd s t r u c t u r e ;
44
Datapath of the Laser-Based Distance Measurer
in VHDL
Datapath
l i br a r y i e e e ;
us e i e e e . s t d _ l o g i c _ 1 1 6 4 . a l l ;
>>1
16
Dreg_clr
Dreg_ld
Dctr_clr
Dctr_cnt
clear
count
clear
load
Dctr: 16-bit
up-counter
Q
16
I
Dreg: 16-bit
register
Q
16
L
Dreg_clr
Dreg_ld
Dctr_clr
Dctr_cnt
D
16
300 MHz Clock
Digital Design
Copyright © 2006
Frank Vahid
Datapath
B
Controller
D
S
• Datapath just
another connection
of components
– Assume upcounter, register,
and shift-right
components are
already designed
(similar to earlierdesigned items)
e n t i t y L DM_ Da t a p a t h i s
por t ( c l k : i n s t d _ l o g i c ;
Dr e g _ c l r , Dr e g _ l d :
i n st d_l ogi c;
Dc t r _ c l r , Dc t r _ c n t :
i n st d_l ogi c;
D: o u t s t d _ l o g i c _ v e c t o r ( 1 5 d o wn t o
) ;
e n d L DM_ Da t a p a t h ;
a r c hi t e c t ur e
c o mp o n e n t
por t (
0)
s t r u c t u r e o f L DM_ Da t a p a t h i s
Up Co u n t e r 1 6
cl k: i n st dl ogi c;
c l r , c nt : i n st d_l ogi c;
C: o u t s t d _ l o g i c _ v e c t o r ( 1 5 d o wn t o
0)
) ;
e n d c o mp o n e n t ;
c o mp o n e n t Re g 1 6
p o r t ( I : i n s t d _ l o g i c _ v e c t o r ( 1 5 d o wn t o 0 ) ;
Q: o u t s t d _ l o g i c _ v e c t o r ( 1 5 d o wn t o 0 ) ;
cl k, cl r , l d:
i n st d_l ogi c
) ;
e n d c o mp o n e n t ;
c o mp o n e n t Sh i f t Ri g h t On e 1 6
p o r t ( I : i n s t d _ l o g i c _ v e c t o r ( 1 5 d o wn t o 0 ) ;
S : o u t s t d _ l o g i c _ v e c t o r ( 1 5 d o wn t o 0 )
) ;
e n d c o mp o n e n t ;
s i g n a l t e mp C : s t d _ l o g i c _ v e c t o r ( 1 5 d o wn t o 0 ) ;
s i g n a l s h i f t C : s t d _ l o g i c _ v e c t o r ( 1 5 d o wn t o 0 ) ;
be gi n
Dc t r : Up Co u n t e r 1 6
p o r t ma p ( c l k , Dc t r _ c l r , Dc t r _ c n t , t e mp C) ;
S h i f t Ri g h t : S h i f t Ri g h t On e 1 6
p o r t ma p ( t e mp C, s h i f t C) ;
Dr e g : Re g 1 6
p o r t ma p ( s h i f t C, D, c l k , Dr e g _ c l r , Dr e g _ l d ) ;
e nd s t r u c t u r e ;
45
Controller of the Laser-Based
Distance Measurer in VHDL
Inputs: B, S
Outputs: L, Dreg_clr, Dreg_ld, Dctr_clr, Dctr_cnt
B’
S0
L=0
Dreg_clr = 1
(laser off)
(clear D reg)
•
S1
Dctr_clr = 1
(clear count)
S’
B
S2
L=1
(laser on)
S
S3
L=0
Dctr_cnt = 1
(laser off)
(count up)
S4
Dreg_ld = 1
Dctr_cnt = 0
(load D reg with Dctr/2)
(stop counting)
FSM similar to
high-level state
machine
– But high-level
operations
replaced by lowlevel datapath
signals
– Use twoprocess FSM
description
approach
Digital Design
Copyright © 2006
Frank Vahid
(continued from Figure 9.42)
wh e n S2 = >
L <= ' 1' ;
- n e x t s t a t e < = S3 ;
wh e n S3 = >
L <= ' 0' ;
- Dc t r _ c n t < = ' 1 ' ; - i f ( S= ' 1 ' ) t h e n
n e x t s t a t e < = S4 ;
el se
n e x t s t a t e < = S3 ;
e nd i f ;
wh e n S4 = >
Dr e g _ l d
<= ' 1' ; - Dc t r _ c n t < = ' 0 ' ; - n e x t s t a t e < = S1 ;
e nd c a s e ;
e nd pr oc e s s ;
e nd b e h a v i o r ;
l aser
on
l aser
count
of f
up
l o a d Dr e g
st op count i ng
l i br a r y i e e e ;
us e i e e e . s t d _ l o g i c _ 1 1 6 4 . a l l ;
e n t i t y L DM_ Co n t r o l l e r i s
por t ( c l k , r s t : i n s t d _ l o g i c ;
B, S: i n s t d _ l o g i c ;
L : out s t d _ l o g i c ;
Dr e g _ c l r , Dr e g _ l d : o u t s t d _ l o g i c ;
Dc t r _ c l r , Dc t r _ c n t : o u t s t d _ l o g i c
) ;
e n d L DM_ Co n t r o l l e r ;
a r c h i t e c t u r e b e h a v i o r o f L DM_ Co n t r o l l e r i s
t y p e s t a t e t y p e i s ( S0 , S1 , S2 , S3 , S4 ) ;
s i gna l c u r r e n t s t a t e , n e x t s t a t e : s t a t e t y p e ;
be gi n
s t a t e r e g : pr oc e s s ( c l k , r s t )
be gi n
i f ( r s t =' 1 ' ) t he n
c u r r e n t s t a t e < = S0 ; - - i n i t i a l s t a t e
e l s i f ( c l k =' 1 ' a nd c l k ' e v e n t ) t he n
c ur r ent s t at e <= nex t s t at e;
e nd i f ;
e nd pr oc e s s ;
c o mb l o g i c : p r o c e s s ( c u r r e n t s t
be gi n
L <= ' 0' ;
Dr e g _ c l r < = ' 0 ' ;
Dr e g _ l d < = ' 0 ' ;
Dc t r _ c l r < = ' 0 ' ;
Dc t r _ c n t < = ' 0 ' ;
case cur r ent st at e i s
wh e n S0 = >
L <= ' 0' ;
Dr e g _ c l r < = ' 1 ' ;
n e x t s t a t e < = S1 ;
wh e n S1 = >
Dc t r _ c l r < = ' 1 '
i f ( B= ' 1 ' ) t h e n
n e x t s t a t e < = S2 ;
el se
n e x t s t a t e < = S1 ;
e nd i f ;
at e,
B,
S)
-
l aser
cl ear
of f
Dr e g
-
cl ear
count
(continued in Figure 9.43)
46
Controller and Datpath of the Laser-Based
Distance Measurer in Verilog
• At highest level, just
connection of controller
and datapath
components
mo d u l e L a s e r Di s t Me a s u r e r ( c l k ,
i n p u t c l k , r s t , B, S;
out put L ;
o u t p u t [ 1 5 : 0 ] D;
B
L
Dreg_clr
Dreg_ld
Dctr_clr
Datapath
from button
Controller
wi r e
wi r e
to laser
from sensor
S
Dr e g _ c l r ,
Dc t r _ c l r ,
r st ,
B,
S,
L,
D) ;
Dr e g _ l d ;
Dc t r _ c n t ;
L DM_ Co n t r o l l e r
L DM_ Co n t r o l l e r _ 1 ( c l k , r s t , B, S, L ,
Dr e g _ c l r , Dr e g _ l d ,
Dc t r _ c l r , Dc t r _ c n t ) ;
L DM_ Da t a p a t h
L DM_ Da t a p a t h _ 1 ( c l k , Dr e g _ c l r , Dr e g _ l d ,
Dc t r _ c l r , Dc t r _ c n t , D) ;
e n d mo d u l e
Dctr_cnt
to display
D
16
300 MHz Clock
Digital Design
Copyright © 2006
Frank Vahid
47
Datapath of the Laser-Based Distance Measurer
in Verilog
Datapath
>>1
16
Dreg_clr
Dreg_ld
Dctr_clr
Dctr_cnt
clear
count
clear
load
Dctr: 16-bit
up-counter
Q
16
I
Dreg: 16-bit
register
Q
16
mo d u l e Up Co u n t e r 1 6 ( c l k ,
i nput c l k , c l r , c n t ;
o u t p u t [ 1 5 : 0 ] C;
/ / d e t a i l s n o t s h o wn
e n d mo d u l e
cl r ,
cnt ,
mo d u l e Re g 1 6 ( I ,
i nput [ 1 5 : 0 ] I
i nput c l k , c l r
out put [ 1 5 : 0 ]
/ / det ai l s not
e n d mo d u l e
cl r ,
l d) ;
Q, c l k ,
;
, l d;
Q;
s h o wn
C) ;
L
Dreg_clr
Dreg_ld
Dctr_clr
Dctr_cnt
D
16
300 MHz Clock
Digital Design
Copyright © 2006
Frank Vahid
Datapath
B
Controller
D
S
• Datapath just
another connection
of components
– Assume upcounter, register,
and shift-right
components are
already designed
(similar to earlierdesigned items)
mo d u l e Sh i f t Ri g h t On e 1 6 ( I ,
i nput [ 1 5 : 0 ] I ;
o u t p u t [ 1 5 : 0 ] S;
/ / d e t a i l s n o t s h o wn
e n d mo d u l e
S) ;
mo d u l e
L DM_ Da t a p a t h ( c l k , Dr e g _ c l r , Dr e g _ l d ,
Dc t r _ c l r , Dc t r _ c n t , D) ;
i nput c l k ;
i n p u t Dr e g _ c l r , Dr e g _ l d ;
i n p u t Dc t r _ c l r , Dc t r _ c n t ;
o u t p u t [ 1 5 : 0 ] D;
wi r e [ 1 5 : 0 ]
t e mp C,
s h i f t C;
Up Co u n t e r 1 6 Dc t r ( c l k , Dc t r _ c l r , Dc t r _ c n t ,
t e mp C) ;
Sh i f t Ri g h t On e 1 6 Sh i f t Ri g h t ( t e mp C, s h i f t C) ;
Re g 1 6 Dr e g ( s h i f t C, D, c l k , Dr e g _ c l r , Dr e g _ l d ) ;
e n d mo d u l e
48
Controller of the Laser-Based
Distance Measurer in Verilog
Inputs: B, S
Outputs: L, Dreg_clr, Dreg_ld, Dctr_clr, Dctr_cnt
B’
S0
L=0
Dreg_clr = 1
(laser off)
(clear D reg)
•
S1
Dctr_clr = 1
(clear count)
FSM similar to
high-level state
machine
– But high-level
operations
replaced by lowlevel datapath
signals
– Use twoprocedure FSM
description
approach
Digital Design
Copyright © 2006
Frank Vahid
S’
B
S2
L=1
(laser on)
S
S3
L=0
Dctr_cnt = 1
(laser off)
(count up)
L DM_ Co n t r o l l e r ( c l k , r s t , B, S, L ,
Dr e g _ l d , Dc t r _ c l r ,
Dc t r _ c n t ) ;
i n p u t c l k , r s t , B, S;
out put L ;
o u t p u t Dr e g _ c l k , Dr e g _ l d ;
o u t p u t Dc t r _ c l r , Dc t r _ c n t ;
r eg L;
r e g Dr e g _ c l r , Dr e g _ l d ;
r e g Dc t r _ c l r , Dc t r _ c n t ;
S4
Dreg_ld = 1
p a r a me t e r
Dctr_cnt = 0
(load D reg with Dctr/2)
(stop counting)
(continued from Figure 9.46)
S1 : b e g i n
Dc t r _ c l r < = 1 ;
i f ( B= = 1 )
n e x t s t a t e < = S2 ;
el se
n e x t s t a t e < = S1 ;
e nd
S2 : b e g i n
L <= 1;
n e x t s t a t e < = S3 ;
e nd
S3 : b e g i n
L <= 0;
Dc t r _ c n t < = 1 ;
i f ( S= = 1 )
n e x t s t a t e < = S4 ;
el se
n e x t s t a t e < = S3 ;
e nd
S4 : b e g i n
Dr e g _ l d < = 1 ;
Dc t r _ c n t < = 0 ;
n e x t s t a t e < = S1 ;
e nd
e ndc a s e
e nd
e n d mo d u l e
mo d u l e
/ /
/ /
cl ear
l aser
count
on
/ /
/ /
l aser
count
of f
up
/ /
/ /
l o a d Dr e g
st op count i ng
r eg [ 2: 0]
r eg [ 2: 0]
S0
S1
S2
S3
S4
=
=
=
=
=
3'
3'
3'
3'
3'
Dr e g _ c l k ,
b000,
b001,
b010,
b011,
b100;
cur r ent st at e;
next st at e;
a l wa y s @( p o s e d g e r s t o r p o s e d g e c l k )
be gi n
i f ( r s t ==1)
c u r r e n t s t a t e < = S0 ; / / i n i t i a l s t a t e
el se
c ur r ent s t at e <= nex t s t at e;
e nd
a l wa y s @( c u r r e n t s t a t e o r B o r S)
be gi n
L <= 0;
Dr e g _ c l r < = 0 ;
Dr e g _ l d < = 0 ;
Dc t r _ c l r < = 0 ;
Dc t r _ c n t < = 0 ;
case ( cur r ent st at e)
S0 : b e g i n
L <= 0;
/ / l aser of f
Dr e g _ c l r < = 1 ;
/ / c l e a r Dr e g
n e x t s t a t e < = S1 ;
e nd
(continued in Figure 9.47)
49
Controller and Datpath of the Laser-Based
Distance Measurer in SystemC
• At highest level, just
connection of controller
and datapath
components
# i nc l ude
# i nc l ude
# i nc l ude
" s y s t e mc . h "
" L DM_ Co n t r o l l e r . h "
" L DM_ Da t a p a t h . h "
SC_ MODUL E ( L a s e r Di s t Me a s u r e r )
{
s c _ i n<s c _ l ogi c > c l k , r s t ;
s c _ i n < s c _ l o g i c > B, S;
s c _ out <s c _ l ogi c > L ;
s c _ o u t < s c _ l v < 1 6 > > D;
s c _ s i g n a l < s c _ l o g i c > Dr e g _ c l r ,
s c _ s i g n a l < s c _ l o g i c > Dc t r _ c l r ,
Dr e g _ l d ;
Dc t r _ c n t ;
B
SC_ CT OR( L a s e r
L DM_ Co n t r o l
L DM_ Da t a p a t
{
L DM_ Co n t r o l
L DM_ Co n t r o l
L DM_ Co n t r o l
L DM_ Co n t r o l
L DM_ Co n t r o l
L DM_ Co n t r o l
L DM_ Co n t r o l
L DM_ Co n t r o l
L
Dreg_clr
Dreg_ld
Dctr_clr
Datapath
from button
Controller
L DM_ Co n t r o l l e r L DM_ Co n t r o l l e r _ 1 ;
L DM_ Da t a p a t h L DM_ Da t a p a t h _ 1 ;
to laser
from sensor
S
Dctr_cnt
to display
D
16
L DM_ Da t
L DM_ Da t
L DM_ Da t
L DM_ Da t
L DM_ Da t
L DM_ Da t
300 MHz Clock
Digital Design
Copyright © 2006
Frank Vahid
}
} ;
apat
apat
apat
apat
apat
apat
Di s t Me a s u r e r ) :
l e r _ 1 ( " L DM_ Co n t r o l l e r _ 1 " ) ,
h _ 1 ( " L DM_ Da t a p a t h _ 1 " )
l
l
l
l
l
l
l
l
er
er
er
er
er
er
er
er
_1.
_1.
_1.
_1.
_1.
_1.
_1.
_1.
h_1.
h_1.
h_1.
h_1.
h_1.
h_1.
cl k( cl k)
r st ( r st )
B( B) ;
S( S) ;
Dr e g _ c l r
Dr e g _ l d (
Dc t r _ c l r
Dc t r _ c n t
cl k( cl k)
Dr e g _ c l r
Dr e g _ l d (
Dc t r _ c l r
Dc t r _ c n t
D( D) ;
;
;
( Dr e g _ c l r ) ;
Dr e g _ l d ) ;
( Dc t r _ c l r ) ;
( Dc t r _ c n t ) ;
;
( Dr e g _ c l r ) ;
Dr e g _ l d ) ;
( Dc t r _ c l r ) ;
( Dc t r _ c n t ) ;
50
Datapath of the Laser-Based Distance Measurer
in SystemC
#i
#i
#i
#i
Datapath
>>1
16
Dreg_clr
Dreg_ld
Dctr_clr
Dctr_cnt
clear
count
clear
load
Dctr: 16-bit
up-counter
Q
16
I
Dreg: 16-bit
register
nc l
nc l
nc l
nc l
ude
ude
ude
ude
"
"
"
"
s y s t e mc . h "
upcount er 16. h"
r eg16. h"
shi f t r i ght one16. h"
SC_ MODUL E ( L DM_ Da t a p a t h )
{
s c _ i n<s c _ l ogi c > c l k ;
s c _ i n < s c _ l o g i c > Dr e g _ c l r ,
s c _ i n < s c _ l o g i c > Dc t r _ c l r ,
s c _ o u t < s c _ l v < 1 6 > > D;
Dr e g _ l d ;
Dc t r _ c n t ;
Q
s c _ s i g n a l < s c _ l v < 1 6 > > t e mp C;
s c _ s i g n a l < s c _ l v < 1 6 > > s h i f t C;
16
Up Co u n t e r 1 6 Dc t r ;
Re g 1 6 Dr e g ;
Sh i f t Ri g h t On e 1 6 Sh i f t Ri g h t ;
L
Dreg_clr
Dreg_ld
Dctr_clr
Dctr_cnt
D
16
300 MHz Clock
Digital Design
Copyright © 2006
Frank Vahid
Datapath
B
Controller
D
• Datapath just
S
another connection
of components
– Assume upcounter, register,
and shift-right
components are
already designed
(similar to earlierdesigned items)
SC_ CT OR( L DM_ Da t a p a t h ) :
Dc t r ( " Dc t r " ) , Dr e g ( " Dr e g " ) ,
Sh i f t Ri g h t ( " Sh i f t Ri g h t " )
{
Dc t r . c l k ( c l k ) ;
Dc t r . c l r ( Dc t r _ c l r ) ;
Dc t r . c n t ( Dc t r _ c n t ) ;
Dc t r . C( t e mp C) ;
Sh i f t Ri g h t . I ( t e mp C) ;
Sh i f t Ri g h t . S( s h i f t C) ;
Dr
Dr
Dr
Dr
Dr
eg.
eg.
eg.
eg.
eg.
I ( s h i f t C) ;
Q( D) ;
cl k( cl k) ;
c l r ( Dr e g _ c l r ) ;
l d ( Dr e g _ l d ) ;
}
} ;
51
Controller of the Laser-Based
Distance Measurer in SystemC
Inputs: B, S
Outputs: L, Dreg_clr, Dreg_ld, Dctr_clr, Dctr_cnt
B’
S0
L=0
Dreg_clr = 1
(laser off)
(clear D reg)
•
S’
B
S1
Dctr_clr = 1
(clear count)
FSM similar to
high-level state
machine
S
S3
L=0
Dctr_cnt = 1
(laser off)
(count up)
S4
Dreg_ld = 1
Dctr_cnt = 0
(load D reg with Dctr/2)
(stop counting)
(continued from Figure 9.50)
c a s e S1
Dc t r _ c l r . wr i t e ( SC_ L OGI C_ 1 ) ;
i f ( B. r e a d ( ) = = SC_ L OGI C_ 1 )
n e x t s t a t e = S2 ;
el se
n e x t s t a t e = S1 ;
br e a k ;
c a s e S2 :
L . wr i t e ( SC_ L OGI C_ 1 ) ;
n e x t s t a t e = S3 ;
br e a k ;
c a s e S3 :
L . wr i t e ( SC_ L OGI C_ 0 ) ;
Dc t r _ c n t . wr i t e ( SC_ L OGI C_ 1 ) ;
i f ( S. r e a d ( ) = = SC_ L OGI C_ 1 )
n e x t s t a t e = S4 ;
el se
n e x t s t a t e = S3 ;
br e a k ;
c a s e S4 :
Dr e g _ l d . wr i t e ( SC_ L OGI C_ 1 ) ;
Dc t r _ c n t . wr i t e ( SC_ L OGI C_ 0 ) ;
n e x t s t a t e = S1 ;
br e a k ; }
– But high-level
operations
replaced by lowlevel datapath
signals
– Use twoprocedure FSM
description
approach
Digital Design
Copyright © 2006
Frank Vahid
S2
L=1
(laser on)
/ /
cl ear
count
/ /
l aser
on
/ /
/ /
l aser
count
of f
up
/ /
/ /
l o a d Dr e g
st op count i ng
# i nc l ude
" s y s t e m. h "
e num s t a t e t y p e {
S0 ,
S1 ,
S2 ,
S3 ,
S4 } ;
SC_ MODUL E ( L DM_ Co n t r o l l e r )
{
s c _ i n < s c _ l o g i c > c l k , r s t , B, S;
s c _ out <s c _ l ogi c > L ;
s c _ o u t < s c _ l o g i c > Dr e g _ c l r , Dr e g _ l d ;
s c _ o u t < s c _ l o g i c > Dc t r _ c l r , Dc t r _ c n t ;
s c _ s i gna l <s t a t e t y pe > c u r r e n t s t a t e ,
next st at e;
SC_ CT OR( L DM_ Co n t r o l l e r )
{
SC_ MET HOD ( s t a t e r e g ) ;
s e ns i t i v e _ pos << r s t << c l k ;
SC_ MET HOD ( c o mb l o g i c ) ;
s e n s i t i v e < < c u r r e n t s t a t e < < B < < S;
}
v oi d s t
i f (
cur
el se
cur
}
at er eg( ) {
r s t . r e a d ( ) = = SC_ L OGI C_ 1 )
r e n t s t a t e = S0 ; / / i n i t i a l
st at e
r ent st at e = next st at e;
v o i d c o mb l
L . wr i t e (
Dr e g _ c l r
Dr e g _ l d .
Dc t r _ c l r
Dc t r _ c n t
ogi c( ) {
SC_ L OGI C_ 0 ) ;
. wr i t e ( SC_ L OGI C_ 0 ) ;
wr i t e ( SC_ L OGI C_ 0 ) ;
. wr i t e ( SC_ L OGI C_ 0 ) ;
. wr i t e ( SC_ L OGI C_ 0 ) ;
s wi t c h ( c u r r
c a s e S0 :
L . wr i t e (
Dr e g _ c l r
next st at
br e a k ;
ent st at e)
{
SC_ L OGI C_ 0 ) ;
. wr i t e ( SC_ L OGI C_ 0 ) ;
e = S1 ;
/ /
/ /
l aser
cl ear
(continued in Figure 9.51)
}
} ;
52
of f
Dr e g
Chapter Summary
• Hardware Description Languages (HDLs) are widely used
in modern digital design
– Textual rather than graphical language sufficient for many purposes
– HDLs are computer-readable
– Great for simulation
• VHDL, Verilog, and SystemC are popular
• Introduced languages mainly through examples
• Numerous HDL books exist to teach each language in
more detail
Digital Design
Copyright © 2006
Frank Vahid
53
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