Hardware Interrupts (HWI)
Chapter 5
C6000 Integration Workshop
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Technical Training
Organization
Copyright © 2005 Texas Instruments. All rights reserved.
Lab 5…
EDMA
gBuf1
2
CPU
gBuf0
1
Channel
3
Frame Transfer Complete
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Technical Training
Organization
1.
CPU writes buffer with sine values
2.
EDMA copies values from one buffer to another
3.
When the EDMA transfer is complete
 EDMA signals CPU to refill the buffer
 EDMA re-initializes itself
Outline

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Technical Training
Organization
Hardware Interrupts (HWI)

Generating Interrupt with the EDMA

Enabling & Responding to HWI’s

EDMA Auto-Initialization

Exercise

Lab

Optional Topics
Generate EDMA Interrupt
EDMA Channels
Channel #
0
1
..
.
15
What causes an EDMA channel to send an interrupt?
The channel’s “Transfer Count” going to zero
You can prevent (or enable) the channel from sending an interrupt…
Generate EDMA Interrupt (TCINT)
EDMA Channels
Channel #
0
Options
TCINT=0
1
..
.
15
Options TCINT
20

Channel’s Options register allows you to enable/disable
interrupt generation
Similar to the CPU's interrupt recognition, the EDMA has flag/enable bits ...
Generate EDMA Interrupt (TCINT)
EDMA Channels
Channel #
0
Options
EDMA Interrupt Generation
CIPR
0
TCINT=0
1
1
..
.
1
15
0
CIER
CIER0 = 0
CIER1 = 0
EDMAINT
CIER8 = 1
CIER15 = 0
Options TCINT
20

The Channel Interrupt Pending Register (CIPR) records
that an EDMA transfer complete has occurred
How do you pick which CIPR bit gets set?
Generate EDMA Interrupt (TCC)
EDMA Channels
Channel #
Options
EDMA Interrupt Generation
CIPR
TCINT=1
TCC=8
0
TCINT=0
TCC=0
1
..
.
TCINT=1
TCC=1
1
15
TCINT=0
TCC=15
0
Options TCINT
TCC
0
1
20
19
16



CIER
CIER0 = 0
CIER1 = 0
EDMAINT
CIER8 = 1
CIER15 = 0
Any channel can set any CIPR bit
Value in TCC bit field selects CIPR bit that will get set
Setting any CIPR bit is allows for EDMA channel chaining
(described later in Optional Topics)
To read/write CIPR or enable/disable CIER …
Generate EDMA Interrupt (TCC)
EDMA Channels
Channel #
EDMA Interrupt Generation
Options
CIPR
TCINT=1
TCC=8
0
TCINT=0
TCC=0
1
..
.
TCINT=1
TCC=1
1
15
TCINT=0
TCC=15
0
Options TCINT
TCC
0
1
20

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Organization
19
CIER
CIER0 = 0
CIER1 = 0
EDMAINT
CIER8 = 1
CIER15 = 0
16
Access CIPR bits using:
 EDMA_intTest(#)
 EDMA_intClear(#)
 EDMA_intAlloc(-1 or #)
 EDMA_intFree(#)

Enabling/disabling CIER bits using:
 EDMA_intEnable(#)
 EDMA_intDisable(#)
Where does EDMAINT go?
EDMA Interrupts the CPU
EDMA Channels
Channel #
EDMA
Interrupt
Generation
HWI4
0
1
2
CPU Interrupt
Logic
EDMAINT
HWI5
…
…
C6000
CPU
HWI15
1. First, we examined how the EDMA generates interrupts
to the CPU
2. Next, we explore how CPU interrupts (HWI’s) work
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Organization
How do Interrupts Work?
1. An interrupt
occurs
• EDMA
• HPI
• Timers
• Ext pins
• Etc.
2. Sets flag in
IFR register
...
Interrupting the CPU
IFR
IER
GIE
Interrupt
Flag
“Individual
Enable”
“Master
Enable”
0
EDMAINT
1
‘C6000
CPU
0
Interrupt Flag Reg (IFR)
bit set when int occurs
Interrupt Enable Reg (IER)
enables individual int's
Global Interrupt Enable (GIE) bit
in Control Status Reg
enables all IER-enabled interrupts
IRQ_enable(IRQ_EVT_XINT2)
IRQ_enable(IRQ_EVT_EDMAINT)
IRQ_globalEnable()
IRQ_globalDisable()
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How do Interrupts Work?
1. An interrupt
occurs

3. CPU acknowledges
interrupt and …
• DMA
• HPI
• Timers
• Ext pins
2. Sets flag in
IFR register
...
Technical Training
Organization
Stops what it is doing
Turn off interrupts globally
Clears flag in register
Saves return-to location
Determines which interrupt
•
Calls ISR
4. ISR (Interrupt Service Routine)
• Etc.
T TO
•
•
•
•
•
•
•
•
•
Saves context of system*
Runs your interrupt code (ISR)
Restores context of system*
Continues where left off*
* Must be done in user code, unless you choose to
use the DSP/BIOS HWI dispatcher
Outline

Generating an EDMA Interrupt (EDMAINT)

Hardware Interrupts (HWI)
How do interrupts work
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Technical Training
Organization

Interrupt service routines

Configuring HWI’s

Interrupt initialization (enabling int’s)

EDMA Auto-Initialization

Exercise

Lab

Optional Topics
Interrupt Service Routine

What do we want to happen when
the EDMA interrupts the CPU?
void edmaHWI()
{
}
Interrupt Service Routine

What do we want to happen when
the EDMA interrupts the CPU?
void edmaHWI()
{
SINE_blockFill();
EDMA_setChannel();
}
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Outline

Generating an EDMA Interrupt (EDMAINT)

Hardware Interrupts (HWI)
How do interrupts work
Interrupt service routines
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Organization

Configuring HWI’s

Interrupt initialization (enabling int’s)

EDMA Auto-Initialization

Exercise

Lab

Optional Topics
HWI Objects
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Organization

C6000 has 16 hardware interrupts (HWI)

When multiple interrupts are pending,
they are serviced in the order shown

Each interrupt object is associated with
an:
 Interrupt source
 Interrupt service routine
Configure HWI Object
void edmaHwi()
{
...
}
Notes:  HWI_INT8 happens to be default for EDMA interrupt
Configure HWI Object
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Notes:  HWI_INT8 happens to be default for EDMA interrupt
 Dispatcher saves/restores context for the ISR
How does the dispatcher work?
HWI Interrupt Dispatcher
HWI Dispatcher
0 Reset
_c_int00
…
…
HWI_nothing
Context
Save
4 EXTINT4
HWI_nothing
Context
Restore
…
EDMA
Channel
Count = 0
EDMAINT
C6000
CPU
5 EDMAINT _edmaHWI
…
15 XINT2
void edmaHWI()
{
…
}
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HWI_nothing
HWI_nothing
Outline

Generating an EDMA Interrupt (EDMAINT)

Hardware Interrupts (HWI)
How do interrupts work
Interrupt service routines
Configuring HWI’s (source, ISR)

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Technical Training
Organization
Interrupt initialization (enabling int’s)

EDMA Auto-Initialization

Exercise

Lab

Optional Topics
Enable CPU Interrupts

Exercise: Fill in the lines of code required
to enable the EDMAINT hardware interrupt:
void initHWI(void)
{
}
Enable CPU Interrupts

Exercise 1: Fill in the lines of code required
to enable the EDMAINT hardware interrupt:
void initHWI(void)
{
IRQ_enable(IRQ_EVT_EDMAINT);
IRQ_globalEnable();
}
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Outline
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
Generating an EDMA Interrupt (EDMAINT)

Hardware Interrupts (HWI)

EDMA Dispatcher

EDMA Auto-Initialization

Exercise

Lab

Optional Topics
EDMA ISR Problem

How many EDMA channels?
16 (or 64)

How many EDMA interrupt
service routines could exist?
16 (or 64)

How many EDMA interrupts?
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Organization
1
Therefore ...
Which Channel?
EDMA Channels
Channel #
Options
EDMA Interrupt Generation
CIPR
CIER
TCINT=1
TCC=8
0
CIER0 = 0
TCINT=0
TCC=0
1
CIER1 = 0
..
.
TCINT=1
TCC=1
1
15
TCINT=0
TCC=15
0
0
1

EDMAINT
CIER8 = 1
CIER15 = 0
Since there is only one EDMA interrupt to the CPU, how
does the CPU know which channel caused it?
Which Channel?
EDMA Channels
Channel #
Options
CIER
TCC=8
0
CIER0 = 0
TCINT=0
TCC=0
1
CIER1 = 0
..
.
TCINT=1
TCC=1
1
15
TCINT=0
TCC=15
0
1

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CIPR
TCINT=1
0
Technical Training
Organization
EDMA Interrupt Generation
EDMAINT
CIER8 = 1
CIER15 = 0
Since there is only one EDMA interrupt to the CPU, how
does the CPU know which channel caused it?
Two methods:
1.
Test each CIPR bit using: EDMA_intTest(bit #)
2.
Automate testing each CIPR bit using
EDMA Interrupt Dispatcher
EDMA Interrupt Problem?
EDMA
Channel
HWI Dispatcher
0 Reset
Count = 0
EDMAINT
C6000
CPU
Context
Save
Context
Restore
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EDMA_intDispatcher
5 EDMAINT _edmaHWI
15 XINT2
HWI_nothing

Previously, our EDMAINT vectored directly to
our Interrupt Service Routine

Can you think of a problem this might create?

Technical Training
Organization
_c_int00

What if two different EDMA channels cause an interrupt?

Do you want all channels to use the same ISR?
(Not very convenient)
To solve this problem, CSL provides a simple
EDMA Interrupt Dispatcher
EDMA
Channel
EDMA Interrupt Dispatcher
HWI Dispatcher
0 Reset
Count = 0
EDMAINT
C6000
CPU
Context
Save
Context
Restore
_c_int00
5 EDMAINT _EDMA_intDispatcher
15 XINT2
HWI_nothing
EDMA Int Dispatcher
1.
2.
Read CIPR & CIER
For each enabled CIPR bit,
(starting with CIPR0), call the
associated (“hooked”) function
CIPR Function to Call
bit (“hooked” function)
0 ….
8
…
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_edmaHWI
void edmaHWI(CIPR bit)
{
…
}
How do you "hook" a function to a CIPR bit?
EDMA_intHook
void initEDMA()
{
...
EDMA_intHook(8, edmaHWI);
...
}
CIPR Function to Call
bit (“hooked” function)
0 ….
8
…
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Organization
_edmaHWI
Plugs entry in
EDMA Interrupt Dispatch table
Outline
 Chapter Objective
 HWI – Hardware Interrupts
 EDMA – Interrupt Generation

EDMA – Auto-Initialization



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What is it?
How many are there?
6 Step Procedure

Summary & Exercise

Lab

Optional Topics
When the Transfer is Complete …
EDMA
EDMA Channel
Channel 0
Options
Channel 1
Source
Channel 2
Transfer Count = 5
Destination
...
Channel 63 (15)
= 0x0
= 0x10
Index
Count Reload
31
16 15
When TC (transfer count) reaches 0 …
Link Addr
0
When the Transfer is Complete …
EDMA
EDMA Channel
Channel 0
Options
Channel 1
Source
Channel 2
Transfer Count = 4
Destination
...
Channel 63 (15)
= 0x1
= 0x11
Index
Count Reload
31
16 15
When TC (transfer count) reaches 0 …
Link Addr
0
When the Transfer is Complete …
EDMA
EDMA Channel
Channel 0
Options
Channel 1
Source
Channel 2
Transfer Count = 3
Destination
...
Channel 63 (15)
= 0x2
= 0x12
Index
Count Reload
31
16 15
When TC (transfer count) reaches 0 …
Link Addr
0
When the Transfer is Complete …
EDMA
EDMA Channel
Channel 0
Options
Channel 1
Source
Channel 2
Transfer Count = 2
Destination
...
Channel 63 (15)
= 0x3
= 0x13
Index
Count Reload
31
16 15
When TC (transfer count) reaches 0 …
Link Addr
0
When the Transfer is Complete …
EDMA
EDMA Channel
Channel 0
Options
Channel 1
Source
Channel 2
Transfer Count = 1
Destination
...
Channel 63 (15)
= 0x4
= 0x14
Index
Count Reload
31
16 15
When TC (transfer count) reaches 0 …
Link Addr
0
When the Transfer is Complete …
EDMA
EDMA Channel
Channel 0
Options
Channel 1
Source
Channel 2
Transfer Count = 0
Destination
...
Channel 63 (15)
= 0x5
= 0x15
Index
Count Reload
31
16 15
Link Addr
0
When TC (transfer count) reaches 0:
 Channel stops moving data
 EDMA can send interrupt to CPU
(just discussed)

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Technical Training
Organization
Which registers have changed since
EDMA was started?
Source, Destination, Count
How can the EDMA parameters get reloaded?
When the Transfer is Completes …
EDMA
EDMA Channel
Channel 0
Options
Channel 1
Source
Channel 2
Transfer Count = 0
Destination
...
Channel 63 (15)
Reload 0
= 0x5
= 0x15
Index
Count Reload
31
16 15
Link Addr
0
Reload 1
Reload 2
...
Reload 21 (69)
When TC (transfer count) reaches 0:
 EDMA can reload the channel’s parameters
from one of the many Reload sets
 Each Reload set consists of six 32-bit values
Essentially, the EDMA has its
own 2KB parameter RAM split
between channels & reloads
How can you choose a specific reload set?
When the Transfer is Completes …
EDMA
Channel 0
EDMA Channel
LINK=1
Options
Channel 1
Source
Channel 2
Transfer Count = 0
Destination
...
Channel 63 (15)
Reload 0
= 0x5
= 0x15
Index
Count Reload
31
16 15
Link Addr
0
Reload 1
Reload 2
...
Reload 21 (69)
Essentially, the EDMA has its
own 2KB parameter RAM split
between channels & reloads
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Organization
When TC (transfer count) reaches 0:
 EDMA can reload the channel’s parameters
from one of the many Reload sets
 Each Reload set consists of six 32-bit values
 Link Address points to the next Reload setup
 Auto-Init, Reload, and Linking all refer to the
same EDMA feature
Creating a “Linked-List” of Transfers
Reload 1
Options (Link=1)
Source
Transfer Count
Destination
Index
Count Reload Link Addr
Channel 0
Options (Link=1)
Source
Transfer Count
Reload 2
Destination
Index
Count Reload
31
16 15



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Link Addr

0
Options (Link=1)
Source
Transfer Count
Destination
Index
Count Reload Link Addr
Offloads CPU ... can reinitialize all six registers of an EDMA channel
Next transfer specified by Link Address
Perform simple re-initialization or create linked-list of events
Useful for ping-pong buffers, data sorting, circular buffers, etc.
EDMA Auto-Initialization
 Why auto-initialization?
 What resources does EDMA have?

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Organization
What are the steps?
Reloading an EDMA channel in 6 Steps
1
hMyHandle
Channel 0
…
Channel 15
Reload 1
…
Reload 21 (69)
Options (Link = 1)
Source
Transfer Count
Destination
Index
Cnt Reload Link Addr
Procedure
1. Choose LINK option
Reloading an EDMA channel in 6 Steps
1
hMyHandle
Channel 0
…
Channel 15
2
hMyReload
Reload 1
…
Reload 21 (69)
Options (Link = 1)
Source
Transfer Count
Destination
Index
Cnt Reload Link Addr
Procedure
1. Choose LINK option
2. Allocate handle for
reload values
Reloading an EDMA channel in 6 Steps
1
hMyHandle
Channel 0
…
Channel 15
2
hMyReload
3
Reload 1
…
Reload 21 (69)
Options (Link = 1)
Source
Transfer Count
Destination
Index
Cnt Reload Link Addr
Procedure
1. Choose LINK option
2. Allocate handle for
reload values
3. Allocate a reload set
Reloading an EDMA channel in 6 Steps
1
hMyHandle
Options (Link = 1)
Source
Transfer Count
Destination
Index
Cnt Reload Link Addr
Channel 0
…
Channel 15
2
hMyReload
3
4
Reload 1
…
Reload 21 (69)
Procedure
1.
Choose LINK option
2.
Allocate handle for
reload values
3.
Allocate a reload set
4.
Configure reload set
(with same values as
original channel)
Options
Source
Transfer Count
Destination
Index
Cnt Reload Link Addr
And the 5th step is ...
Steps 5 & 6: Set the Link Address fields
EDMA_link(hMyHandle, hMyReload)
hMyHandle
Channel 0
…
Channel 15
hMyReload
Reload 1
…
Reload 21 (69)
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Organization
Options
Source
Transfer Count
Destination
Index
Cnt Reload Link Addr
Options
Source
Transfer Count
Destination
Index
Cnt Reload Link Addr
5

EDMA_link() pokes
hMyReload address
into Link Address field
6
EDMA_link(hMyReload, hMyReload)
Reloading an EDMA channel in 6 Steps
1 Modify your config to enable linking:
EDMA_OPT_RMK(
…
EDMA_OPT_LINK_YES, … ),
2 Create a handle to reference a Reload location:
EDMA_Handle hMyReload;
3 Allocate a Reload location (reserve a reload set; -1 for “any”)
hMyReload = EDMA_allocTable(-1);
4 Configure reload set (writes config structure to reload set)
EDMA_config(hMyReload, &myConfig);
Update Link Address fields (modifies field in chan, not myConfig struct)
5
EDMA_link(hMyHandle, hMyReload);
6
EDMA_link(hMyReload, hMyReload);
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Outline
 Chapter Objective
 HWI – Hardware Interrupts
 EDMA – Interrupt Generation
 EDMA – Auto-Initialization

Summary
Generate Interrupt (EDMA, HWI)
 EDMA ISR
 Summary of CSL’s EDMA functions

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Technical Training
Organization

Exercise

Lab
Generate EDMA Interrupt Summary
EDMA Channels
Channel #
0
1
..
.
15
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Organization
Options
TCINT=1
TCC=8
TCINT=0
TCC=0
TCINT=1
TCC=1
TCINT=0
TCC=15
CPU Interrupts
EDMA Int Generation
CIPR
0
1
1
0
IFR
CIER
0
CIER0 = 0
CIER1 = 0
CIER8 = 1
CIER15 = 0
EDMAINT
1
1
0
IER
IER4 = 0
IER5 = 0
IERx = 1
IER15 = 0

Set EDMA to generate an interrupt to the CPU:
1. (CIPR)
Reserve CIPR bit using EDMA_intAlloc()
2. (Options)
TCINT = 1
TCC = set # to match reserved CIPR bit
3. (CIER)
Set CIER bit to match TCC value

Set CPU to respond to interrupt from EDMA
1. (IER)
Enable individual EDMA interrupt
2. (CSRGIE)
Enable interrupts globally
CPU
GIE
EDMA Interrupts (6 steps)
1
Modify EDMA Config structure for TCINT & TCC
EDMA_OPT_TCINT_YES, //set channel to interrupt CPU
EDMA_OPT_TCC_OF(0), //set TCC in code
Part 1:
Allow EDMA to
Generate Ints
gTcc = EDMA_intAlloc(-1);
//reserve TCC (0-15)
myConfig.opt |= EDMA_FMK(OPT,TCC, gTcc); //set TCC in myConfig
What does the _FMK macro do?
Part 2:
Enabling CPU Ints
CSL’s _FMK macro (field make)
EDMA Options Register
TCC
19 16
<< 16
0011
gTCC=3
EDMA_FMK(OPT, TCC, gTCC) = 0x00030000
Peripheral
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Organization
Register
Field
Value
EDMA Interrupts (Part 1)
Modify EDMA Config structure for TCINT & TCC
1
EDMA_OPT_TCINT_YES, //set channel to interrupt CPU
EDMA_OPT_TCC_OF(0), //set TCC in code
Part 1:
Allow EDMA to
Generate Ints
gTcc = EDMA_intAlloc(-1);
//reserve TCC (0-15)
myConfig.opt |= EDMA_FMK(OPT,TCC, gTcc); //set TCC in myConfig
2
Hook the ISR to the appropriate TCC value:
EDMA_intHook(gTcc, myISR);
3
Set the appropriate bit in the CIER register
EDMA_intEnable(gTcc);
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// must match chosen TCC value
What about setting up hardware interrupts?
EDMA Interrupts (Part 2)
Part 2:
Enabling CPU Ints
4
Include the header file
#include <csl_irq.h>
5
Set the appropriate bit in the IER register
IRQ_enable(IRQ_EVT_EDMAINT);
6
Turn on global interrupts
IRQ_globalEnable( ); // turn on interrupts globally
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When the transfer completes…what happens?
Summary
 Generate Interrupt (EDMA, HWI)


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EDMA ISR
Summary of CSL’s EDMA functions
EDMA ISR
Count = 0

EDMAINT
C6000
CPU
HWI
Dispatcher
When the transfer count reaches zero:


EDMA interrupt is sent to the CPU
Channel reg’s are re-initialized (autoinit)
EDMA
Dispatcher
void edmaHwi(CIPR bit) {
SINE_blockFill(…);
EDMA_setChannel(hMyChannel);

EDMA Dispatcher will:
}
 Read CIPR and CIER
 Clear CIPR bits
 Call ISR functions for set (and enabled) CIPR bits

Your ISR needs to:
 Perform whatever your system requires
 Initiate the next block transfer with EDMA_setChannel
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(unless your system uses EDMA synchronization – discussed in Ch 6)
Summary
 Generate Interrupt (EDMA, HWI)
 EDMA ISR

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Organization
Summary of CSL’s EDMA functions
EDMA Functions (Which Registers they Affect)
EDMA_setChannel
ESR
EDMA_clearChannel
ECR
EDMA_getChannel
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Organization
ER
EDMA_enableChannel
EDMA_disableChannel
EER
EDMA_enableChaining
EDMA_disableChaining
CCER
EDMA_intAlloc
EDMA_intFree
EDMA_intTest
EDMA_intClear
CIPR
EDMA_intEnable
EDMA_intDisable
CIER
Outline
 Chapter Objective
 HWI – Hardware Interrupts
 EDMA – Interrupt Generation
 EDMA – Auto-Initialization
 Summary
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Organization

Exercise

Lab

Optional Topics
Exercise 1 (Review)
•
Complete the following Interrupt Service Routine.
Here’s a few hints:

Follow the code outlined on the “EDMA ISR” slide.

Don’t forget, though, that our exercise (and the upcoming lab) uses
different variable names than those used in the slide’s example code.

To “fill the buffer”, what function did we use in Labs 2 and 4 to create
a buffer of sine wave data?
void edmaHwi(void)
{
};
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SINE_blockFill(gBuf0, BUFFSIZE);
// Fill buffer with sine data
EDMA_setChannel(hEdma);
// start EDMA running
Exercise 2: Step 1
1. Change gEdmaConfig so that it will:
(Just cross-out the old and jot in the new value)

Interrupt the CPU when transfer count reaches 0

Auto-initialize and keep running
EDMA_Config gEdmaConfig = {
EDMA_OPT_RMK(
EDMA_OPT_PRI_LOW,
EDMA_OPT_ESIZE_16BIT,
EDMA_OPT_2DS_NO,
EDMA_OPT_SUM_INC,
EDMA_OPT_2DD_NO,
EDMA_OPT_DUM_INC,
EDMA_OPT_TCINT_NO,
EDMA_OPT_TCC_OF(0),
EDMA_OPT_LINK_NO,
EDMA_OPT_FS_YES ),
... };
//
//
//
//
//
//
//
//
//
//
Priority?
Element size?
2 dimensional source?
Src update mode?
2 dimensional dest?
Dest update mode?
Cause EDMA interrupt?
Transfer complete code?
Enable link parameters?
Use frame sync?
Exercise 2: Step 1
1. Change gEdmaConfig so that it will:
(Just cross-out the old and jot in the new value)

Interrupt the CPU when transfer count reaches 0

Auto-initialize and keep running
EDMA_Config gEdmaConfig = {
EDMA_OPT_RMK(
EDMA_OPT_PRI_LOW,
EDMA_OPT_ESIZE_16BIT,
EDMA_OPT_2DS_NO,
EDMA_OPT_SUM_INC,
EDMA_OPT_2DD_NO,
EDMA_OPT_DUM_INC,
EDMA_OPT_TCINT_NO,
EDMA_OPT_TCC_OF(0),
EDMA_OPT_LINK_NO,
EDMA_OPT_FS_YES ),
... };
T TO
Technical Training
Organization
//
//
//
//
//
//
//
//
//
//
Priority?
Element size?
2 dimensional source?
Src update mode?
2 dimensional dest?
Dest update mode?
Cause EDMA interrupt?
Transfer complete code?
Enable link parameters?
Use frame sync?
Exercise 2: Steps 2-4
2. Reserve “any” CIPR bit (save it to gXmtTCC). Then set this value in the
gEdmaConfig structure.
3. Allow the EDMA’s interrupt to pass through to the CPU.
That is, set the appropriate CIER bit.
(Hint: the TCC value indicates which bit in CIPR and CIER are used)
4. Hook the ISR function so it is called whenever the appropriate CIPR bit
is set and the CPU is interrupted.
Exercise 2: Steps 2-4
2. Reserve “any” CIPR bit (save it to gXmtTCC). Then set this value in the
gEdmaConfig structure.
gXmtTCC = EDMA_intAlloc(-1);
gEdmaConfig.opt |= EDMA_FMK (OPT, TCC, gXmtTCC);
3. Allow the EDMA’s interrupt to pass through to the CPU.
That is, set the appropriate CIER bit.
(Hint: the TCC value indicates which bit in CIPR and CIER are used)
EDMA_intEnable(gXmtTCC);
4. Hook the ISR function so it is called whenever the appropriate CIPR bit
is set and the CPU is interrupted.
EDMA_intHook(gXmtTCC, edmaHWI);
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Technical Training
Organization
Exercise 2: Steps 5
5. Enable the CPU to accept the EDMA interrupt. (Hint: Add 3 lines of code.)
void initHwi(void)
{
};
Exercise 2: Steps 5
5. Enable the CPU to accept the EDMA interrupt. (Hint: Add 3 lines of code.)
#include <csl_irq.h>
void initHwi(void)
{
IRQ_enable(IRQ_EVT_EDMAINT);
IRQ_globalEnable(void);
};
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Technical Training
Organization
Exercise 2: Steps 6-9 (EDMA Reload)
6. Declare a handle for an EDMA reload location and name it
hEdmaReload:
7. Allocate one of the Reload sets:
(Hint: hEdmaReload gets this value)
8. Configure the EDMA reload set:
9. Modify both the EDMA channel and the reload set to link to the
reload set of parameters:
Exercise 2: Steps 6-9 (EDMA Reload)
6. Declare a handle for an EDMA reload location and name it
hEdmaReload:
EDMA_Handle hEdmaReload;
7. Allocate one of the Reload sets:
hEdmaReload
(Hint: hEdmaReload gets this value)
= EDMA_allocTable( -1 );
8. Configure the EDMA reload set:
EDMA_config (hEdmaReload,&gEdmaConfig);
9. Modify both the EDMA channel and the reload set to link to the
reload set of parameters:
EDMA_link(hEdma, hEdmaReload);
EDMA_link(hEdmaReload, hEdmaReload);
T TO
Technical Training
Organization
Outline
 Chapter Objective
 HWI – Hardware Interrupts
 EDMA – Interrupt Generation
 EDMA – Auto-Initialization
 Summary
 Exercise
T TO
Technical Training
Organization

Lab

Optional Topics
Lab 5 – Programming the EDMA
CPU
EDMA
gBuf0
gBuf1
EDMA
Frame Transfer Complete
Pseudo Code
1. CPU generates 32 sine values into buf0
2. EDMA transfers 32 elements from buf0 to buf1
3. EDMA sends “transfer complete” interrupt to CPU
4. Go to step 1
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Technical Training
Organization
Lab 5 Debrief
1.
2.
3.
4.
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Technical Training
Organization
Why did we use HWI_INT8?
Why not HWI_INT7?
What should we check if we never get to
the EDMA’s Interrupt Service Routine?
In an EDMA ISR, what needs to be
checked and cleared? How did we do
this in the lab?
Why do we need to allocate both a set of
reload registers AND an EDMA channel?
Click Here for Chapter 6
Using the McBSP Serial Port
Chapter 5: Optional Topics
T TO
Technical Training
Organization

Saving Context in HWI’s (3 methods)

Interrupts and the DMA (vs. EDMA)

Chaining EDMA channels

Additional HWI topics
Click Here for Chapter 6
Using the McBSP Serial Port
Chapter 5: Optional Topics
T TO
Technical Training
Organization

Saving Context in HWI’s (3 methods)

Interrupts and the DMA (vs. EDMA)

Chaining EDMA channels

Additional HWI topics
Click Here for Chapter 6
Using the McBSP Serial Port
Chapter 5: Optional Topics
T TO
Technical Training
Organization

Saving Context in HWI’s (3 methods)

Interrupts and the DMA (vs. EDMA)

Chaining EDMA channels

Additional HWI topics
Click Here for Chapter 6
Using the McBSP Serial Port
Chapter 5: Optional Topics
T TO
Technical Training
Organization

Saving Context in HWI’s (3 methods)

Interrupts and the DMA (vs. EDMA)

Chaining EDMA channels

Additional HWI topics
Technical Training
Organization
ti