ECE 551: Digital System Design & Synthesis Spring 2003 Lecture Materials Prepared by: Charles Kime, Kewal Saluja and Michael Schulte 1 ECE 551: Digital System Design & Synthesis Lecture Set 1: oIntroduction oOverview of Contemporary Digital Design oPragmatics 1 1/16/2003 ECE 551 Spring 2003 2 ECE 551 - Digital System Design & Synthesis Lecture 1.1 - Introduction Overview o Course o Course o Course o Course 1/16/2003 Purpose Topics Tools Info ECE 551 Spring 2003 3 Course Purpose To provide knowledge and experience in performing contemporary logic design based on o Hardware description languages (HDLs) o HDL simulation o Automated logic synthesis o Timing analysis With consideration for o Practical design and test issues o Chip layout issues o Design reuse for system-on-a-chip (SoC) 1/16/2003 ECE 551 Spring 2003 4 Course Topics Pragmatics of Digital Design Hardware Modeling with the Verilog HDL Event-Driven Simulation and Testbenches Verilog Language Constructs and Delay Behavioral Descriptions in Verilog An Overview of VHDL Logic Synthesis and Timing Physical Design and Design Reuse 1/16/2003 ECE 551 Spring 2003 5 Course Tools Modelsim HDL Simulation Tools (Mentor) Design Analyzer Synthesis Tools (Synopsys) G11 Technology Library (LSI Logic) 1/16/2003 ECE 551 Spring 2003 6 Course Information Course Conduct Standard Reference The above plus all other course material can be found at http://courses.engr.wisc.edu/ecow/ge t/ece/551/kime/ Be familiar with all! 1/16/2003 ECE 551 Spring 2003 7 Lecture 1.2 – Contemporary Digital Design Overview o Layout Lite o Application Specific Integrated Circuit (ASIC) Technologies o IC Costs o ASIC Design Flows The Role of HDLs and Synthesis The Role of IP Cores and Reuse The Role of Physical Design o Summary 1/16/2003 ECE 551 Spring 2003 8 Layout Lite - 1 IC are produced from masks that correspond to geometric layouts produced by the designer or by EDA tools. In CMOS, a typical IC cross-section: Metal 3 Oxide Metal 2 Metal 1 Transistor Polysilicon Diffusion Substrate 1/16/2003 Channel ECE 551 Spring 2003 9 Layout Lite - 2 The layout corresponding to the cross-section: Transistor Channel o The transistor is outlined in broad yellow lines. o Everything else is interconnect. 1/16/2003 ECE 551 Spring 2003 10 IC Implementation Technologies STANDARD IC ASIC FULL CUSTOM STANDARD CELL 1/16/2003 SEMICUSTOM GATE ARRAY, SEA OF GATES FIELD PROGRAMMABLE FPGA ECE 551 Spring 2003 PLD 11 Distinguishing Features of IC Technologies - 1 Implementation technologies are distinguished by: o The levels of the layout 1) transistors and 2) interconnect that are: Common to distinct IC designs (L1) Different for distinct IC designs (L2) o The use of predesigned layout cells Predesigned cells are used (P1) Predesigned cells are not used (P2) 1/16/2003 ECE 551 Spring 2003 12 Distinguishing Features of IC Technologies - 2 Implementation technologies are distinguished by: o Mechanism used for instantiating distinct IC designs: Metallization (M) Fuses or Antifuses (F) Stored Charge (C) Static Storage (R) 1/16/2003 ECE 551 Spring 2003 13 Technologies in Terms of Distinguishing Features - 1 Full Custom – P2, M o Transistors – L2, Interconnects – L2 Standard Cell – P1, M o Transistors – L2, Interconnects – L2 Gate Array, Sea of Gates – P1, M o Transistors – L1, Interconnects – L2 1/16/2003 ECE 551 Spring 2003 14 Technologies in Terms of Distinguishing Features - 2 FPGA – P1, F or R o Transistors – L1, Interconnects – L1 PLD – P1, F or C o Transistors – L1, Interconnects – L1 1/16/2003 ECE 551 Spring 2003 15 Technologies in Terms of Shared Fabrication Steps Custom Fabricated Layers o Full Custom and Standard Cells – all layers are custom fabricated o Gate Arrays and Sea of Gates – only interconnect (metallization) layers custom fabricated o FPGAs and PLDs – nothing is custom fabricated Consequences due to economy-of-scale: o Fab costs reduced for Gate Arrays and Sea of Gates o Fab costs further reduced for FPGAs and PLDs 1/16/2003 ECE 551 Spring 2003 16 Layout Styles - 1 Technologies in terms of layout styles: Standard Cell Adjustable Spacing … Megacells Gate Array - Channeled Fixed Spacing … Base Cell 1/16/2003 ECE 551 Spring 2003 17 Layout Styles - 2 Technologies in terms of layout styles: Gate Array - Channel-less … (Sea of Gates) Base Cell Gate Array - Structured Fixed Embedded Block 1/16/2003 ECE 551 Spring 2003 … … 18 IC Costs - 1 An example: 10,000 gate circuit [1] o Fixed costs Standard Cell - $146,000 Gate Array - $86,000 FPGA - $21,800 o Variable costs Standard Cell - $8 per IC Gate Array - $10 per IC FPGA - $39 per IC 1/16/2003 ECE 551 Spring 2003 19 IC Costs - 2 An example: 10,000 gate circuit 4,000,000 3,500,000 Standard Cell Gate Array FPGA 3,000,000 2,500,000 2,000,000 1,500,000 1,000,000 500,000 0 1/16/2003 100 1000 10000 ECE 551 Spring 2003 100000 20 IC Costs – 3 Why isn’t FPGA cheaper per unit due to economy-of-scale? o The chip area required by each of the successive technologies from Full Custom to FPGAs increases for a fixed-sized design. o The larger the chip area, the poorer the yield of working chips during fabrication o Also, due to increased sales, FPGA prices have declined since the mid-90’s much faster than the other technologies. 1/16/2003 ECE 551 Spring 2003 21 ASIC Design Flow - Traditional Write Specifications Draw Datapath Schematics * Define System Architecture Define State Diag/Tables Partition - Datapath &Control Draw Control Schematics * Do Physical Design* *Steps followed by validation Implement* 1/16/2003 and refinement ECE 551 Spring 2003 Integrate Design* 22 Traditional Flow Problems Schematic Diagrams o Limited descriptive power o Limited portability o Limited complexity State Diagrams and Algorithmic State Machines o Limited complexity o Difficult to describe parallelism Time-Intensive and Hard to Update 1/16/2003 ECE 551 Spring 2003 23 How about HDLs Instead of Diagrams? - 1 Hardware description languages (HDLs) o Computer-based programming languages o Model and simulate the functional behavior and timing of digital hardware o Synthesizable into a technology-specific netlist Two main HDLs used by industry o Verilog HDL (C-based, industry-driven) o VHSIC HDL or VHDL (Ada-based, defense/industry/university-driven). 1/16/2003 ECE 551 Spring 2003 24 How about HDLs Instead of Diagrams? - 2 Advantages of HDLs o Highly portable (text) o Describes multiple levels of abstraction o Represents parallelism o Provides many descriptive styles Structural Register Transfer Level (RTL) Behavioral o Serve as input ECE for551synthesis Spring 2003 1/16/2003 25 How about Synthesis instead of Manual Design? Increased Potential Ability space 1/16/2003 for better optimization to explore more of overall design Reduces Are design efficiency verification/validation problem there disadvantages? ECE 551 Spring 2003 26 HDL/Synthesis Design Flow - 1 Design Specification Design Partition Design Entry: HDL Behavioral 1/16/2003 Verification: Functional Pre-Synthesis Sign-Off Integration Synthesis and Technology Map Verification: Functional ECE 551 Spring 2003 To next page 27 HDL/Synthesis Design Flow - 2 From prior page Verification: Post-Synthesis Timing Verification: Post-Synthesis 1/16/2003 Test Generation & Fault Simulation Extract Parasitics Physical Design Verification: Physical & Electrical ECE 551 Spring 2003 Design Sign-Off 28 An Example from Industry A G3 wireless processor was designed using the following methodology: o Entire processor modeled and tested using VHDL and C-based test programs o Processor functionality verified by synthesizing to an FPGA and running 3G wireless applications at 25 MHz o Processor timing and design feasibility verified by synthesizing to a standard cell library and running applications at 500 MHz. o Final version of processor implemented using a mix of standard cell and custom logic to achieve lowpower and 800 MHz clock speed. 1/16/2003 ECE 551 Spring 2003 29 Newer Technologies and Design Flows - SOC System-on-a-Chip (SoC) o Designers use (Intellectual Property – IP) cores RISC Core, DSP, Microcontroller, Memory The main function is to glue many cores and generate/design only those components for which cores and designs may not be available Used in ASIC as well as custom design environment The issues relevant to this will be discussed near the end of the course 1/16/2003 30 ECE 551 Spring 2003 Contemporary Design Flow - 1 Design Specification Design Partition Select IP Cores Preliminary Phys. Design Design Entry: HDL Behavioral Verification: Functional Integration & Verification: Functional Pre-Synthesis Sign-Off Synthesis and Technology Map To HDL/Synth Design Flow -2 1/16/2003 ECE 551 Spring 2003 31 Lecture 1.2 Summary Application Specific Integrated Circuit (ASIC) Technologies o Provides a basis for what we will design IC Costs o Gives a basis for technology selection ASIC Design Flows o Shows the role of HDLs and synthesis o Provides a structure for what we will learn What we will do 1/16/2003 ECE 551 Spring 2003 32 References 1) Smith, Michael J. S., Application-Specific Integrated Circuits, Addison-Wesley, 1997. 1/16/2003 ECE 551 Spring 2003 33 Lecture 1.3 Pragmatics 1 Pragmatics refers to practical design choices and techniques Topics o Cell Libraries o Asynchronous Circuits o Three-State Logic and Hi-Z State 1/16/2003 ECE 551 Spring 2003 34 Cells and Cell Libraries What is a cell? What is a cell library? What appears in the cell library for each ASIC cell? 1/16/2003 ECE 551 Spring 2003 35 What is a Cell? Cells are the building blocks for digital designs Come in different sizes, shapes and functions varying from transistors to large memory arrays or even a processor Typically cells: o Small Scale: AND, OR, NAND, NOR, NOT, AOI, OAI, Flip-Flops, Latches o Medium Scale: Multiplexers, Decoders, Adders o Large Scale: Memories, Processors Provided by ASIC vendors 1/16/2003 ECE 551 Spring 2003 36 What is a Cell Library? A database specifying and describing the target technology in the form of predesigned objects called cells. Synthesis target technology. In-Class Discussion: What are typical components in the database for each cell? 1/16/2003 ECE 551 Spring 2003 37 Asynchronous Techniques Delay-dependent design Combinational hazards Combinational hazard prevention Asynchronous design 1/16/2003 ECE 551 Spring 2003 38 Delay-Dependent Design 1 LA PA A LA A PA Example: Level-to-Pulse Converter(Delay-Based) 1/16/2003 ECE 551 Spring 2003 39 Delay-Dependent Design 2 Sometimes useful But should be avoided Time delays vary and so may: o Fail o Produce variable results, e. g. pulse length 1/16/2003 ECE 551 Spring 2003 40 Delay-Dependent Design 3 Level to Pulse Converter (Synchronous) LA PA D Clock C Q Level on LA must be longer than a clock period and must not rise close to the positive clock edge. Ideally, synchronous with Clock. 1/16/2003 ECE 551 Spring 2003 41 Combinational Hazards 1 Example - Hazard in a Multiplexer A 1 B F 1 C B F 1/16/2003 ECE 551 Spring 2003 42 Combinational Hazards - 2 A circuit has a hazard if there exists an assignment of delays such that an unwanted signal transition (glitch), can occur. Types of changes on combinational circuit inputs : o Single-input change (SIC) o Multiple-input change (MIC) A SIC static hazard exists on a circuit output if in response to a SIC, the output momentarily changes to the opposite value. o Static 1-hazard – output value to remain at 1 o Static 0-hazard – output value to remain at 0 1/16/2003 ECE 551 Spring 2003 43 Combinational Hazards - 3 Classification of Combinational Hazards o Static – SIC/MIC – output changes when it should remain fixed - output value within the “transition region of input changes is fixed. o Dynamic – SIC/MIC – output changes three or more times when it should change only once. o Essential – MIC – output changes when it should remain fixed – output value within the “transition region” of input changes not fixed. 1/16/2003 ECE 551 Spring 2003 44 Combination Hazards - 4 In-class Example: Illustration of static, dynamic and essential hazards 1/16/2003 ECE 551 Spring 2003 45 Combinational Hazards - 5 Consequences of Hazards o Signals with hazards within or entering asynchronous circuits (note that a flip-flop is an asynchronous circuit with respect to its clock signal!) o Cause incorrect state behavior Extra state changes Incorrect state changes In-Class Example: Prevention of Hazards o Redundant Logic o Delay Dependence 1/16/2003 ECE 551 Spring 2003 46 Asynchronous Design - 1 Which of the following sequential circuits involve asynchronous design? o A circuit that has no global clock signal involved in its operation – state changes occur in response to input changes only. o A D flip-flop circuit o A circuit using clock gating on flip-flop clock inputs o A circuit with a clock which uses the clear and preset inputs on the flip-flops for other than initialization. 1/16/2003 ECE 551 Spring 2003 47 Asynchronous Design - 2 Because of the difficulty of eliminating hazards, it is very difficult to insure correct operation under all timing possibilities Design must be done manually or by use of very specialized synthesis tools. Therefore, avoid it if you can! If you truly need it, investigate some of the more contemporary approaches[1] which avoid some of the many difficulties. 1/16/2003 ECE 551 Spring 2003 48 Three-State and Other Hi-Z States Three-state conflicts Floating three-state nets and inputs Pull-ups and Pull-downs Bus keepers 1/16/2003 ECE 551 Spring 2003 49 Three-State Conflicts - 1 What are they and what are their effects? o Static – Chip damage or static power consumption o Dynamic – Dynamic or static power consumption 1/16/2003 1 D0 1 E0 0 D1 1 E1 E0 1 E1 1 1 E0 0 E1 01 OUT ECE 551 Spring 2003 50 Three-State Conflicts - 2 How can conflicts be avoided? o Static – Decoded enable signals o Dynamic – Delay control 1 0 1/16/2003 1 E0 0 E1 01 D0 E0 1 E0 0 E1 1 OUT D1 E1 ECE 551 Spring 2003 51 Floating Inputs and ThreeState Nets - 1 Floating input values on gates can cause: o static power dissipation o high-frequency switching that induces power supply noise Floating input values arise from: o Gate inputs, e. g., for example on exterior of IC, that are not connected o Lines driven by 3-state buffer or gate outputs, all of which are in the Hi-Z state. 1/16/2003 ECE 551 Spring 2003 52 Floating Inputs and ThreeState Nets – 2 How can floating inputs and nets be avoided? o Use a pull-up or pull-down resistor or transistor with a fixed gate voltage value. Advantage – simple Disadvantages – static power dissipation and loading of node o On internal lines, particularly buses, use a bus keeper (weak buffer) 1/16/2003 ECE 551 Spring 2003 53 Non-D flip-flops D Flip-Flops o Unique characteristic – the typical master-slave DFF is also functionally an edge-triggered DFF. Non- D Flip-Flops (JK, T, etc.) o In the cell libraries, these flip-flop may be full-custom designs or may simply consist of a DFF with added logic. o If it is just a DFF with added logic, you might as well design for a DFF to give the logic optimization software more flexibility. 1/16/2003 ECE 551 Spring 2003 54 References [1] Chris J. Myers, Asynchronous Circuit Design, John Wiley & Sons, Inc., New York, 2001. 1/16/2003 ECE 551 Spring 2003 55