ARM
Introduction &
Instruction Set Architecture
Aleksandar Milenkovic
E-mail:
Web:
milenka@ece.uah.edu
http://www.ece.uah.edu/~milenka
Outline
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ARM Architecture
ARM Organization and Implementation
ARM Instruction Set
Architectural Support for High-level Languages
Thumb Instruction Set
Architectural Support for System Development
ARM Processor Cores
Memory Hierarchy
Architectural Support for Operating Systems
ARM CPU Cores
Embedded ARM Applications
2
ARM History
 ARM – Acorn RISC Machine (1983 – 1985)
 Acorn Computers Limited, Cambridge, England
 ARM – Advanced RISC Machine 1990
 ARM Limited, 1990
 ARM has been licensed to many semiconductor
manufacturers
3
ARM’s visible registers
 User level
 15 GPRs, PC,
CPSR (current
program status
register)
 Remaining registers
are used for
system-level
programming and
for handling
exceptions
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13
r14
r15 (PC)
CPSR
user mode
usable in user mode
system modes only
r8_fiq
r9_fiq
r10_fiq
r11_fiq
r12_fiq
r13_fiq
r14_fiq
r13_svc
r14_svc
r13_abt
r14_abt
r13_irq
r14_irq
r13_und
r14_und
SPSR_irq SPSR_und
SPSR_abt
SPSR_fiq SPSR_svc
fiq
mode
svc
mode
abort
mode
irq
mode
undefined
mode
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ARM CPSR format
 N (Negative), Z (Zero), C (Carry), V (oVerflow)
 mode – control processor mode
 T – control instruction set
 T = 1 – instruction stream is 16-bit Thumb instructions
 T = 0 – instruction stream is 32-bit ARM instructions
 I F – interrupt enables
31
28 27
N ZC V
8 7 6 5 4
unused
IF T
0
mode
5
ARM memory organization
 Linear array of bytes numbered from 0
to 232 – 1
 Data items
 bytes (8 bits)
 half-words (16 bits) – always
aligned to 2-byte boundaries (start
at an even byte address)
 words (32 bits) – always aligned to
4-byte boundaries (start at a byte
address which is multiple of 4)
bit 31
bit 0
23
22
21
20
19
18
17
16
word16
15
14
13
12
half-word14 half-word12
11
10
9
8
5
4
word8
7
6
byte6 half-word4
3
2
1
0
byte3 byte2 byte1 byte0
byte
address
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ARM instruction set
 Load-store architecture
 operands are in GPRs
 load/store – only instructions that operate with memory
 Instructions
 Data Processing – use and change only register values
 Data Transfer – copy memory values into registers (load) or
copy register values into memory (store)
 Control Flow
o branch
o branch-and-link –
save return address to resume the original sequence
o trapping into system code – supervisor calls
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ARM instruction set (cont’d)
Three-address data processing instructions
Conditional execution of every instruction
Powerful load/store multiple register instructions
Ability to perform a general shift operation and a general
ALU operation in a single instruction that executes in a
single clock cycle
 Open instruction set extension through coprocessor
instruction set, including adding new registers and data
types to the programmer’s model
 Very dense 16-bit compressed representation of the
instruction set in the Thumb architecture
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I/O system
 I/O is memory mapped
 internal registers of peripherals (disk controllers, network
interfaces, etc) are addressable locations within the ARM’s
memory map and may be read and written using the loadstore instructions
 Peripherals may use either the normal interrupt (IRQ) or
fast interrupt (FIQ) input
 normally most interrupt sources share the IRQ input, while
just one or two time-critical sources are connected to the
FIQ input
 Some systems may include external DMA hardware to
handle high-bandwidth I/O traffic
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ARM exceptions
 ARM supports a range of interrupts, traps, and supervisor calls – all
are grouped under the general heading of exceptions
 Handling exceptions
 current state is saved by copying the PC into r14_exc and CPSR
into SPSR_exc (exc stands for exception type)
 processor operating mode is changed to the appropriate exception
mode
 PC is forced to a value between 0016 and 1C16, the particular value
depending on the type of exception
 instruction at the location PC is forced to (the vector address)
usually contains a branch to the exception handler; the exception
handler will use r13_exc, which is normally initialized to point to a
dedicated stack in memory, to save some user registers
 return: restore the user registers and then restore PC and CPSR
atomically
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ARM cross-development toolkit
 Software development
 tools developed by ARM
Limited
 public domain tools
(ARM back end for gcc C
compiler)
C source
C libraries
C compiler
assembler
.aof
object
libraries
linker
 Cross-development
 tools run on different
architecture from one
for which they produce
code
asm source
.axf
system model
ARMulator
debug
ARMsd
development
board
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Outline
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ARM Architecture
ARM Assembly Language Programming
ARM Organization and Implementation
ARM Instruction Set
Architectural Support for High-level Languages
Thumb Instruction Set
Architectural Support for System Development
ARM Processor Cores
Memory Hierarchy
Architectural Support for Operating Systems
ARM CPU Cores
Embedded ARM Applications
12
ARM Instruction Set
 Data Processing Instructions
 Data Transfer Instructions
 Control flow Instructions
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Data Processing Instructions
 Classes of data processing instructions
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Arithmetic operations
Bit-wise logical operations
Register-movement operations
Comparison operations
 Operands: 32-bits wide;
there are 3 ways to specify operands
 come from registers
 the second operand may be a constant (immediate)
 shifted register operand
 Result: 32-bits wide, placed in a register
 long multiply produces a 64-bit result
14
Data Processing Instructions (cont’d)
Arithmetic Operations
Bit-wise Logical Operations
ADD r0, r1, r2
r0 := r1 + r2
AND r0, r1, r2 r0 := r1 and r2
ADC r0, r1, r2
r0 := r1 + r2 + C
ORR r0, r1, r2
r0 := r1 or r2
SUB r0, r1, r2
r0 := r1 - r2
EOR r0, r1, r2
r0 := r1 xor r2
SBC r0, r1, r2
r0 := r1 - r2 + C - 1
BIC r0, r1, r2
r0 := r1 and (not) r2
RSB r0, r1, r2
r0 := r2 – r1
RSC r0, r1, r2
r0 := r2 – r1 + C - 1
Register Movement
Comparison Operations
MOV r0, r2
r0 := r2
CMP r1, r2
set cc on r1 - r2
MVN r0, r2
r0 := not r2
CMN r1, r2
set cc on r1 + r2
TST r1, r2
set cc on r1 and r2
TEQ r1, r2
set cc on r1 xor r2
15
Data Processing Instructions (cont’d)
 Immediate operands:
immediate = (0->255) x 22n, 0 <= n <= 12
ADD r3, r3, #3
r3 := r3 + 3
AND r8, r7, #&ff
r8 := r7[7:0], & for hex
 Shifted register operands
 the second operand is subject to a shift operation before it is
combined with the first operand
ADD r3, r2, r1, LSL #3 r3 := r2 + 8 x r1
ADD r5, r5, r3, LSL r2
r5 := r5 + 2r2 x r3
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ARM shift operations
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LSL – Logical Shift Left
LSR – Logical Shift Right
ASR – Arithmetic Shift Right
ROR – Rotate Right
RRX – Rotate Right
Extended by 1 place
31
0
31
00000
00000
LSL #5
31
LSR #5
0
31
0
1
00000 0
11111 1
ASR #5 , pos itiv e operand
31
0
0
ASR #5 , negativ e operand
0
31
0
C
C
ROR #5
C
RRX
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Setting the condition codes
 Any DPI can set the condition codes (N, Z, V, and C)
 for all DPIs except the comparison operations
a specific request must be made
 at the assembly language level this request is indicated by
adding an `S` to the opcode
 Example (r3-r2 := r1-r0 + r3-r2)
ADDS r2, r2, r0 ; carry out to C
ADC r3, r3, r1
; ... add into high word
 Arithmetic operations set all the flags (N, Z, C, and V)
 Logical and move operations set N and Z
 preserve V and either preserve C when there is no shift
operation, or set C according to shift operation (fall off bit)
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Multiplies
 Example (Multiply, Multiply-Accumulate)
MUL r4, r3, r2
r4 := [r3 x r2]<31:0>
MLA r4, r3, r2, r1
r4 := [r3 x r2 + r1]
<31:0>
 Note
 least significant 32-bits are placed in the result register,
the rest are ignored
 immediate second operand is not supported
 result register must not be the same
as the first source register
 if `S` bit is set the V is preserved and
the C is rendered meaningless
 Example (r0 = r0 x 35)
 ADD r0, r0, r0, LSL #2 ; r0’ = r0 x 5
RSB r3, r3, r1
; r0’’ = 7 x r0’
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Data transfer instructions
 Single register load and store instructions
 transfer of a data item (byte, half-word, word)
between ARM registers and memory
 Multiple register load and store instructions
 enable transfer of large quantities of data
 used for procedure entry and exit, to save/restore workspace
registers, to copy blocks of data around memory
 Single register swap instructions
 allow exchange between a register and memory
in one instruction
 used to implement semaphores to ensure mutual exclusion
on accesses to shared data in multis
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Data Transfer Instructions (cont’d)
Register-indirect addressing
Single register load and store
LDR r0, [r1]
r0 := mem32[r1]
STR r0, [r1]
mem32[r1] := r0
Note: r1 keeps a word address (2 LSBs are 0)
Base+offset addressing
(offset of up to 4Kbytes)
LDR r0, [r1, #4] r0 := mem32[r1 +4]
LDRB r0, [r1]
r0 := mem8[r1]
Note: no restrictions for r1
Auto-indexing addressing
LDR r0, [r1, #4]! r0 := mem32[r1 + 4]
r1 := r1 + 4
Post-indexed addressing
LDR r0, [r1], #4
r0 := mem32[r1]
r1 := r1 + 4
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Data Transfer Instructions (cont’d)
COPY:
ADR r1, TABLE1
ADR r2, TABLE2
LOOP:
LDR r0, [r1]
STR r0, [r2]
ADD r1, r1, #4
ADD r2, r2, #4
...
TABLE1: ...
TABLE2:...
; r1 points to TABLE1
; r2 points to TABLE2
COPY:
ADR r1, TABLE1
ADR r2, TABLE2
LOOP:
LDR r0, [r1], #4
STR r0, [r2], #4
...
TABLE1: ...
TABLE2:...
; r1 points to TABLE1
; r2 points to TABLE2
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Data Transfer Instructions
Multiple register data transfers
LDMIA r1, {r0, r2, r5}
r0 := mem32[r1]
r2 := mem32[r1 + 4]
r5 := mem32[r1 + 8]
Note: any subset (or all) of the registers may be
transferred with a single instruction
Note: the order of registers within the list is
insignificant
Note: including r15 in the list will cause a change
in the control flow
 Stack organizations
 FA – full ascending
 EA – empty ascending
 FD – full descending
 ED – empty descending
 Block copy view
 data is to be stored above
or below the the address
held in the base register
 address incrementing or
decrementing begins before
or after storing the first
value
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Multiple register transfer addressing
modes
r9’
r9
1018
r5
r1
r0
16
100c 16
1000
r9
r9’
r5
r1
r0
16
STMDA r9!, {r0,r1,r5}
1018
16
100c 16
r9
1000
16
STMIB r9!, {r0,r1,r5}
1018
16
100c 16
1000
r5
r1
r0
16
STMIA r9!, {r0,r1,r5}
1018
r9’
100c 16
r9
r9’
16
r5
r1
r0
1000
16
STMDB r9!, {r0,r1,r5}
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The mapping between the stack and
block copy views
B e f o re
In c re me n t
Af t e r
B e f o re
De c re me n t
Af t e r
As c e n di n g
Ful l
Emp t y
STMIB
STMFA
STMIA
STMEA
LDMDB
LDMEA
LDMDA
LDMFA
De s c e n di n g
Ful l
Emp t y
LDMIB
LDMED
LDMIA
LDMFD
STMDB
STMFD
STMDA
STMED
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Control flow instructions
Branch
B
BAL
BEQ
BNE
BPL
BMI
BCC
BLO
BCS
BHS
BVC
BVS
BGT
BGE
Interpretation
Unconditional
Always
Equal
Not equal
Plus
Minus
Carry clear
Lower
Carry set
Higher or same
Overflow clear
Overflow set
Greater than
Greater or equal
BLT
BLE
Less than
Less or equal
BHI
BLS
Higher
Lower or same
Normal uses
Always take this branch
Always take this branch
Comparison equal or zero result
Comparison not equal or non-zero result
Result positive or zero
Result minus or negative
Arithmetic operation did not give carry-out
Unsigned comparison gave lower
Arithmetic operation gave carry-out
Unsigned comparison gave higher or same
Signed integer operation; no overflow occurred
Signed integer operation; overflow occurred
Signed integer comparison gave greater than
Signed integer comparison gave greater or
equal
Signed integer comparison gave less than
Signed integer comparison gave less than or
equal
Unsigned comparison gave higher
Unsigned comparison gave lower or same
26
Conditional execution
 Conditional execution to avoid branch instructions used to
skip a small number of non-branch instructions
 Example
CMP r0, #5
BEQ BYPASS
ADD r1, r1, r0
SUB r1, r1, r2
BYPASS: ...
;
; if (r0!=5) {
; r1:=r1+r0-r2
;}
With conditional execution
CMP r0, #5
ADDNE r1, r1, r0
SUBNE r1, r1, r2
...
;
;
;
Note: add 2 –letter condition after the 3-letter opcode
; if ((a==b) && (c==d)) e++;
CMP r0, r1
CMPEQ r2, r3
ADDEQ r4, r4, #1
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Branch and link instructions
 Branch to subroutine (r14 serves as a link register)
BL SUBR ; branch to SUBR
..
; return here
SUBR:
..
; SUBR entry point
MOV pc, r14 ; return
 Nested subroutines
SUB1:
SUB2:
BL SUB1
..
; save work and link register
STMFD r13!, {r0-r2,r14}
BL SUB2
..
LDMFD r13!, {r0-r2,pc}
..
MOV pc, r14 ; copy r14 into r15
28
Supervisor calls
 Supervisor is a program which operates at a privileged
level – it can do things that a user-level program cannot do
directly
 Example: send text to the display
 ARM ISA includes SWI (SoftWare Interrupt)
; output r0[7:0]
SWI SWI_WriteC
; return from a user program back to monitor
SWI SWI_Exit
29
Jump tables
 Call one of a set of subroutines depending on a value
computed by the program
JTAB:
BL JTAB
...
CMP r0, #0
BEQ SUB0
CMP r0, #1
BEQ SUB1
CMP r0, #2
BEQ SUB2
Note: slow when the list is long,
and all subroutines are equally
frequent
BL JTAB
...
JTAB:
ADR r1, SUBTAB
CMP r0, #SUBMAX ; overrun?
LDRLS pc, [r1, r0, LSL #2]
B ERROR
SUBTAB: DCD SUB0
DCD SUB1
DCD SUB2
...
30
Hello ARM World!
AREA HelloW, CODE, READONLY ; declare code area
SWI_WriteC
EQU
&0
; output character in r0
SWI_Exit
EQU
&11
; finish program
ENTRY
; code entry point
START: ADR r1, TEXT
; r1 <- Hello ARM World!
LOOP:
LDRB r0, [r1], #1
; get the next byte
CMP r0, #0
; check for text end
SWINE SWI_WriteC
; if not end of string, print
BNE LOOP
SWI SWI_Exit
; end of execution
TEXT
= “Hello ARM World!”, &0a, &0d, 0
END
31