Design of the Front-end
Electronics for the GOSSIPO
chip.
Vladimir Gromov
Electronics Technology
NIKHEF, Amsterdam,
the Netherlands
CERN, July the 22th, 2005
Highlights.
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Main functionalities of the GOSSIPO.
Main objectives and principal block diagram of the prototype
of the chip .
Evaluation of the parasitic capacitances at the input of the
charge-sensitive preamplifier.
Injection of the input test signal.
Design and performance of the charge-sensitive
preamplifier.
Design and performance of the current comparator and
output LVDS driver.
Design and performance of the bias circuit.
Conclusion and plans.
The GOSSIPO chip.
(Gas On Slimmed Silicon Pixel)
Cathode (drift) plane
Cluster1
Cluster2
Cluster3
Micromegas
Input pixel
1mm,
400Volts
Silicon wafer with read-out electronics on it
50um,
400Volts
20um
The Input signal.
Shape of the current signal coming on the pixel pad
0
0
Time-walk vs pulse height distribution
34
30
ion component, Qi =90%
0.05
s( t )
Input
current,0.1
P ( n  2000 ) 32
Gain=8000
P ( n  4000 ) 32
P ( n  8000 ) 32 20
0.13 0.15
nA
10
10
electron component, Qe=10%
0
0
10
10
20
t
20
30
30
Gain=4000
n
Gain=2000
40
40
time,ns
Twalk
jt  1
10
Tw( n )
Time-walk curve
0
0
0
0
THR=350e
5000
1 10
4
4
1.5 10
n  n  n  448  Twalk
jt  0
Signal, electrons
448  n
2 10
4
4
2.5 10
4
3 10
30000
Main features of the GOSSIPO chip.
1.
2.
There will no silicon sensor on the chip due to a novel concept of the particle detection that allows
to circumvent major constrains related to that.
Low input parasitic capacitance and no need for the detector leakage current compensation at the
input are the reasons to expect an outstanding performance of the design.
Objectives for the prototype.
Testing of the performance and the functionality of the Front-end electronics on the bare chip
(without InGrid and with InGrid on it).
The design is expected to demonstrate:
a) low-threshold operation (THR=350e).
b) fast pulse response (δ-response peaking time ≈ 36ns , real signal response peaking time ≈ 52ns ).
c) low analog power dissipation (≈ 1.7uW/channel for 1.2V supply).
d) low channel-to-channel threshold dispersion (σTHR ≈140e).
e) low parasitic feedback cross-talk.
Charge sensitive
preamplifier
Cfb ≈ 1fF
Bias generator
Voltage-to-current
converter
Current Comparator
with DC hysteresis
LVDS driver
Vref
Rfb ≈ 80MΩ
Idet(t)
Bias control
Principal block diagram of the GOSSIPO front-end circuit.
Ron ≈ 2GΩ
Cc ≈ 200fF
Cpar ≈ 30fF
Ithr=42nA
Rl ≈ 1kΩ
Rl ≈ 1kΩ
Channel#1
Outputs
Channel#2
Channel#3
Channel#4
Cfb ≈ 1fF
Rfb ≈ 80MΩ
Idet(t)
Charge sensitive
preamplifier
Cpar ≈ 30fF
Channel#5
Voltage follower
Parasitic capacitances associated with the input pad.
noise
peaking time
charge collection
Micromegas
Cp-grid
Cp-grid
Cp-grid
Cp-p
Cp-p
Input pad
Substrate of the wafer
Cpar = Cp-grid + Cp-p + Cp-sub
,
Cp-sub
where
Cp-sub
Cp-sub is pad-to-substrate capacitance coupling
Cp-grid is pad-to-Micromegas capacitance coupling
Cp-p is pad-to-pad capacitance coupling .
Evaluation of the pad-to-Micromegas parasitic capacitances Cp-grid.
Model for analytical calculations of the pad-to-Micromegas parasitic capacitance.
R - is a radius of the pad. The pad is a circle.
d - is pad-to-Micromegas distance.
0 - is vacuum dielectric constant.
Ideal uniformly charged disk
R
2  3.14   0
C( R d )
d
D
1
z
r
d rd z
Ideal boundless plane
3
2
z
0
2 2 2
r R
0
2.5
2
C R  25 10
6
C R  50 10
6
C R  75 10
6
C=1.8fF when
R=25um, d=50um
1.5
1
0.5
0
0
5 10
6
1 10
5
1.5 10
R
5
2 10
5
2.5 10
5
Evaluation of the pad-to-substrate parasitic capacitances Cp-sub in
0.13um CMOS technology.
Layout of the input pad coupling in
0.13um CMOS technology
(CMOS8SF, flavour LM 6_2).
Input pad
(LM, copper 0.55um)
R
MQ, copper 0.55um
Via 2x2,
0.8um x 0.8um
M6, copper 0.32um
M5, copper 0.32um
M4, copper 0.32um
M3, copper 0.32um
≈ 6um
M2, copper 0.32um
M1, copper 0.29um
PC
Capacitive parasitics based on the physical design of the layout
have been extracted within DIVA Extract rules supplied in the
Design Kit. Both available methodologies (CDS_coeffgen_Cap
and Raphael_Cap) have been used.
Suggested Diva Deck Extraction Methodology
(from the PDK User’s guide)
- generate a trial test structure which mimic possible design
geometries as much as possible.
- run extraction tool for both methodologies.
- review the capacitance numbers and use the tool that gives the
more pessimistic results. Compare the numbers to hand
calculations or a 3D field solver.
3030
30
Substrate
Cp-sub=27fF
R=25um,
2525
C R  6 10
Cp-sub
C1bare
k
6
2020
Extraction done by DIVA
with CDS_coeffgen_Cap
option
1515
Analytical
calculation
fF
C2bare
k
1010
55
0.86
Extraction done by DIVA with
Raphael_Cap option
00 0
0
5 10
5 10
6
5
6
1 10
10 5
5
1.5 10
Rr
k
15
2 10
205
R , um
2.5 10
25
5
3 10
5
Evaluation of the pad-to-pad parasitic capacitances Cp-p in 0.13um
CMOS technology.
Model for analytical calculations of the
pad-to-pad parasitic capacitance.
4  3.14   0   r
Cp_p ( a  b )
2.9
3
Extraction done by DIVA
with Raphael_Cap option
2.5
2.5
a
0.5
2
z
2
2  10
10
z
2 2 2
x b
Extraction done by DIVA with
CDS_coeffgen_Cap option
22
d xd z
3
C1 a  30 10
k
Cp-p
Crap30x30
6
k1
1.5
1.5
Analytical
calculation on the
basis of the model.
fFk1
0.5
Ccoeff30x30
11
where
b is dimension of the pad,
c is thickness of the pad,
a is pad-to-pad distance,
ε0 is vacuum dielectric constant,
εr is relative permittivity of the medium
b
b
a
Input pad
Input pad
c=0.55um
Cp-p
Pad-to-pad layout
0.5
0.5
0
00 0
0
0 10
5 10
6
5
6
5
1 10
a  a1  a1
k k1 k1
10
1.5 10
5
15
2 10
5
20
a ,um
6
22 10
Evaluation of the input pad-to-pad
capacitances in 0.13um CMOS technology
(CMOS8SF, flavour LM 6_2). Large pads
(b=30um)
Injection of the input test signal.
Cpar* = Cpar + Cin
Cin<< Cpar= 30fF
, therefore
Cfb ≈ 1fF
Charge sensitive
preamplifier
Uin ≈ 20mV
Upulse(t)
Rfb ≈ 80MΩ
Qin=Cin Uin≈ 0.06fC (350e)
Rt=50Ω
Cpar ≈ 30fF
Cin ≈ 3fF
Vertical Parallel Plate (VPP) capacitor in LM layer.
40um
Passive pad
Test input
a=1800nm
Passive pad
Active pad
Cfringe=3.2fF
d=550um
!!! Accuracy of the fringe capacitors.
Δa=50nm, Δa/a=3% (lithography accuracy)
± 25%
Δd=±140nm, Δd/d=± 25% (LM layer thickness accuracy)
The charge-sensitive preamplifier. The feedback capacitance.
Cfb ≈ 1fF
1. Charge sensitivity: Uamplitude ≈ Qdet / Cfb
2. Charge collection (input impedance)
Cin *= A Cfb ≈ 140fF
Cin *>> Cpar ≈ 30fF
Rfb ≈ 80MΩ
Qdet
U(t)
Idet(t)
Cpar ≈ 30fF
A≈140
**≈ 0.5fF
C
Coaxial-like layout of the input interconnection. Extraction with the parasitics.
40um
40um
Input pad
0.18um
0.2um
Cfb = 1fF
!!! Accuracy of the fringe
capacitor is ± 25%
(metal layers accuracy)
C** = 0.5fF
Substrate
Cp-sub = 23fF
The charge-sensitive preamplifier. The feedback resistor.
Cfb ≈ 1fF
1.
det(t)
Δtdet ≈ 30ns
Classic F.Krummenacher charge sensitive preamplifier realizes
large Rfb and compensates for the detector leakage current.
!!! Cint → ∞ in order to avoid differentiation of the input signal.
A≈140
Ib=1nA
Ib=1nA
M2
Cfb
Ileak
Output
Cint
Cpar ≈ 30fF
M1
Cfb
Ileak + Ip
U(t)
There is no need to compensate for the detector
leakage in GOSSIPO chip.
!!! Cint is not needed in this preamplifier and Ip=Ib.
Rfb ≈ 1/gmM1+1/gmM2 ≈ 80MΩ ,where gm is
common-source transconductance of transistor.
2Ip
Silicon
sensor
Rfb ≈ 80MΩ
Qdet
To avoid ballistic deficit: Rfb Cfb > Δtdet=30ns
Rfb > 30MΩ
I
Ip
Input
Output
Ip=Ib=1nA
The charge-sensitive preamplifier. Channel-to-channel variation of
the DC offset at the output.
Vdd=1.2V
M8
Vbias3
Ibias2=2nA
M2
M1
UoutDC varies from channel to channel.
Three source of mismatch are in the design:
M10
M9
Vbias2
Ibias3=1nA
1.
Cfb =1fF
Mismatch in the diffrential pair M1 vs M2
σ(δVg)=√2•[(σTM1 )2 +(σβM1•IdM1/gmM1)2] ≈ √2•σTM1
OPAMP
M3
Input
Ib=1nA
A
(jw)
K=127
Vbias1
Output
Ibias3=0.2uA
2.
Mismatch in the current mirrors M10 vs M8,M9
σ{[IdM8+ IdM9- IdM10]- /[IdM8+ IdM9]}=[(σβM10 )2 +(σ
M10•gmM10/IdM10)2] ≈ σ M10 • gmM10/IdM10
T
T
Ibias4=1uA
M7
M6
M5
M4
3. Mismatch in the current mirrors M5 vs M4
σ(δIdM5/IdM5)=√ 2•[(σβM5 )2 +(σ TM5•gmM5/IdM5)2] ≈ √ 2•gmM5/IdM5•σ TM5
Standard deviation of the statistical variations of Uout DC
σ(δUoutDC)=√ {(√2•σTM1)2 + (2•√2• σ TM5•gmM5/gmM1)2 + (σ TM10•gmM10/gmM1)2 }
Monte-Carlo simulations in Cadence give
σ(δUoutDC) =
20mV (170e) .
The charge-sensitive preamplifier. The OPAMP.
Cfb ≈ 1fF
Rfb ≈ 80MΩ
Qdet
U(t)
Idet(t)
Cpar ≈ 30fF
OPAMP
The OPAMP.
A(jw)=gmT75/[gdsT75•(gdsT73/gmT73)+gdsT77+jwC*]
=140/(1+jw•14ns)
gm is common-source transconductance of transistor.
gds is common-source output conductance of transistor
C* is total parasitic capacitance at the output.
The charge-sensitive preamplifier. Real signal response and stability.
Cfb ≈ 1fF
Rfb ≈ 80MΩ
Qdet
U(t)
Idet(t)
Cpar ≈ 30fF
OPAMP
Peaking time
44ns
Phase-to-frequency
response
Amplitude 52mV
Output signal
Decay of the
signal is
proportional to
exp(-t/80ns)
Phase margin
62º
Magnitude-to-frequency
response
Input signal
438e = 70aC
30ns
Unity gain line
Phase margin of the preamplifier.
Real signal response of the preamplifier.
The charge-sensitive preamplifier. Main specifications.
Cfb ≈ 1fF
Rfb ≈ 80MΩ
Qdet
U(t)
Idet(t)
Cpar ≈ 30fF
OPAMP
R
0um
15um
20um
25um
Parasitic capacitance at the input of the preamplifier
Cpar
0fF
10fF
20fF
30fF
Charge sensitivity
Gain
140mV/ke
130mV/ke
125 mV/ke
120 mV/ke
Input referred noise (Affirma SPECTRE simulation)
Nsim
34e RMS
43e RMS
57e RMS
71e RMS
Input referred noise (hand calculation of serial thermal
noise )
Peaking time of the output signal when it is a δ-response.
Ncal
4.5e RMS
21e RMS
35e RMS
46e RMS
Tpint
20ns
27ns
32ns
36ns
Peaking time of the output signal when it is the response
to the real signal
Tpreal
41ns
46ns
50ns
52ns
Channel-to-channel variation of the DC offset at the
output.
Power dissipation
δUDC
σ ≈ 170e
P
1.2uW/channel for 1.2V supply
Radius of the input pad
Conversion to digital signal. Current comparator.(H.Traff 1992).
Low
Ithr
T1
-A
Uout+
Uout-
High
Iin
T2
Uout+ - Uout-
VtT2=200mV
Low
High
Iin - Ithr
VtT1=200mV
Ambiguity zone ± 30nA !!!
Design of the Current comparator as a current-to-voltage
converter.
T1
Vt=200mV
gm=1.6u
Iin
T4
Vt=200mV
33
Vbias
T3
Vt=400mV
Gainopen loop = gmT3 / gdsT3 = 53 (High state)
= 18 (Low state)
Uout+
130nA
T2
Vt=200mV
gm=1.6u
Degradation of the output impedance of T3 in Low state causes drop of the
open loop gain.
UDC=300mV
Uout-
Zin
Zin=1/ [gmT1,T2 • Gainopen loop]
500kΩ
40kΩ
14kΩ
Ambiguity state.
Iin = 0nA.
Low state. Iin = - 60nA
High state. Iin = 60nA
10MHz
Freg,
Interface to the Current comparator. Design of the accoupled voltage-to-current converter.
Charge sensitive
Preamplifier is a
Current-to-voltage
converter
voltage
Voltage-to-current
converter
Vbias2
current
Current Comparator
is
a current-to-voltage
converter
LVDS
Driver
Ibias1=200nA
Cc=200fF
M1
Uin
M2
M4 Ron=1GΩ
Vbias3
Ithr=42nA
1. Differentiation time constant of the AC-coupling:
Cc • Ron = 200usec >> signal duration time.
2. Gain = Iout/Uin = 0.5• gmT1 = 90nA/52mV (438e).
3. Channel-to-channel Gain variation:
σ(δGain/Gain) = 10% (44e).
Vbias1
M3
Iout
4. Output impedance = 1/ gdsT3 = 100 MΩ.
5. Channel-to-channel variation of the output DC current:
σ(δIoutDC) = 24nA (120e).
Design of the complete comparator with DC hysteresis.
Charge sensitive
Preamplifier is a
Current-to-voltage
converter
voltage
Voltage-to-current
converter
current
THRup
≈ σnoise
THRdown
Vbias2
Uin
Current Comparator
voltage
is
a current-to-voltage
converter
LVDS
Driver
Hysteresis or positive feedback allows to
avoid too short pulses and double
pulses at the output of the
comparator.
U(THRup )-U(THRdown) = 15nA(73e)
σnoise= 0.2 • U(THRup) = 75e
Vbias3
Ithr=42nA
Vbias
33
Vbias1
Iout
Ithr=15nA
Uout+
130nA
UDC=300mV
Uout-
Design of the LVDS output driver.
Charge sensitive
Preamplifier is a
Current-to-voltage
converter
voltage
Voltage-to-current
converter
current
Current Comparator
voltage
is
a current-to-voltage
converter
The Low Voltage Differential Driver (LVDS)
delivers the digital signals to the external low
impedance load.
Ibias=21uA
Ibias=85uA
ΔU= 100mV
ΔU= 55mV
Uin+
Uout-
Uin-
Uout+
Rl=7kΩ
R3=1kΩ
R4=1kΩ
R2=7kΩ
Cpar ≈ 8pF
Cpar ≈ 8pF
LVDS
Driver
voltage
The signals in the design .
Time-walk at the output of the LVDS driver as a function of the signal
amplitude (Amp).
Threshold = 350e.
Input current signal
coming from pixel pad
Amp=9000e
Amp=1800e
Amp=900e
Output of the
preamplifier
Threshold
Amp=438e
Amp=350e
Output of the
current comparator.
ΔT=45ns
Output of the LVDS
driver.
Design of the bias circuit.
A filter is needed to suppress common bus noise.
A 1th order low-pass filter with cut-off frequency
fcut-off= 1/[2π • Ron • Cncap] = 16kHz
T1
Ron=1GΩ
W/L=0.16u/24u
Vgs=38mW
Vthr=250mV
Cncap = 10fF
(11fF/um2 )
T2
R1
Vgs=38mW
T3
Control
determines current
(voltage drop over R1).
T4
Channel-to-channel spread of the output impedances T1…T4 is given as follows:
σ(δ(gds)/gds)= σ(δVt) /[n•Φt ] ≈ 15%
Conclusion and plans.
. There will be no silicon sensor on the GOSSIPO chip due to a novel concept of the particle
detection that allows to circumvent major constrains related to that.
. Low input parasitic capacitance and no need for the detector leakage current compensation at the
input are the reasons to expect an outstanding performance of the design.
. Design of the GOSSIPO chip is in progress on the basis of the potentialities of the 0.13um CMOS .
The following specification have been found feasible so far:
a) parasitic input capacitance 10fF….30fF.
b) input referred electronic noise σnoise = 70e (corresponds to THR=350e).
c) δ-response peaking time ≈ 36ns , real signal response peaking time ≈ 52ns .
d) analog power dissipation ≈ 1.7uW/channel for 1.2V supply (without LVDS driver).
e) channel-to-channel threshold dispersion σTHR ≈140e.
. There will be 4 individual channels on the chip. Each channel will be equipped with a chargesensitive preamplifier ac-coupled to a current comparator with DC hysteresis and a LVDS
driver.
. Vertical Parallel Plate (VPP) or fringe capacitor seems to be suitable for injection of the test signal.
The VPP-based capacitance is taken to implement the feedback capacitance in the preamplifier.
. A dedicated circuit on the chip will provide all the channels with bias voltages (currents).
. Low-pass filters have been added to each channel to avoid common bus noise.
. We look to submit this prototype within CERN organized MPW run in December 2005.