Clocking – Lecture 2 and 3
Purpose – Clocking Design Topics
Read Chapter 12
12/4/2002
2
Optional Additional Reading
 http://www.uoguelph.ca/~antoon/gadge
ts/pll/pll.html © by Tony van Roon
 http://www.cwc.nus.edu.sg/news/semi
nar/arch/PLL_seminar.pdf
Introduction
12/4/2002
3
Agenda
 Clock Signal Requirements
 Intro to Phase Lock Loop – Baby Steps
 Clock Circuit Examples
Introduction
12/4/2002
4
In a system design, clocks may be
generated by external chips
CPUs
RAM Memory &
I/O control
clock
 The idea assumption is that the clock edge are


synchronized at each device
A digital clock signal is ideally a 50% duty cycle
square wave
A “clock domain” is comprised of the a set of signals
that are referenced to the same idea clock signal.
Introduction
12/4/2002
5
Clock Signal Requirements
 Monotonic edges
Avoid double clocking and meta-stable behavior.
Controlled with distribution topology
 Fast edges
Reduce uncertainty from slew rate
Controlled by length
 Low Skew
Controlled by topology, loading, and receiver
sensitivity.
 Low Jitter
Mostly a clock generation issue.
 High fan-out - Topology
Includes cpu’s, i/o chips, expansion connectors,
memory chips, control chips
Introduction
12/4/2002
6
Non-monotonic series terminated effects
Wave is reflected at
the load and turns
around here
Wave is re-reflected at
the source due to
imperfect termination
and transmitted back
to load.
Threshold limits
This “bump” move up and down depending
on relation to Zl, Zs, rterm, and Zo.
So we can see how more than just time
delay effects the clock skew
Introduction
12/4/2002
7
Fast Edge Reduce Skew – but…
 Fast edges can reduce the time
uncertainty through the thresholds
 However stub and packages can make
fast edges more susceptible to ringing
which can cause double clocking of the
data
Introduction
12/4/2002
Issues with single ended threshold sensitivity
Vref
Vss Tx
Vref
Vss Rx1
Vref
 The wave is referenced to either Vcc or Vss.

8
Vss Rx2
Consequently the effective DC value of the wave will
be tied to one of these rails.
The wave is attenuated around the effective DC
component of the waveform, but the reference does
not change accordingly. Hence the clock trigger point
between various clock load points is very sensitive to
distortion and attenuation.
Introduction
12/4/2002
Differential Clocking vs Single Ended Clocking
9
 Greater detail will be covered in in the next course.
 For a Single ended (SE) clock, the buffer drives the


clock signal on one trace.
For a Differential (Diff) clock, the buffer drives
two traces in equal but in opposite directions. The
signal are received at the load end with a differential
amplifier. This means that the qualifying “clock”
waveform is the difference of the signals on the two
traces.
Single ended signaling requires a threshold reference
voltage.
This voltage is generated either on or off of the die.
The problem with single ended clocking is that is sensitive to
more to attenuation and edge distortion.
 Differential signaling reference threshold is normally
at 0 volts. We will explore differential clocking later.
Introduction
12/4/2002
10
Low Skew
Data Bus
D
SET
CLR
Q
Q
SET
Q
D
Q
D
CLR
SET
CLR
Q
Q
SET
CLR
Q
D
Q
D
SET
CLR
Q
Q
SET
Q
D
Q
SET
CLR
D
Q
Q
CLR
SET
Q
Q
D
CLR
Skew Factors
 Clock path arrival
Clock
Clock Buffer
Tree
Phase
Locked
Loop
Introduction
mis-match
 Clock buffer Tco
pin to pin skew
 Receiver loading
12/4/2002
11
Review of Clock Skew
Transmit
clock at
device a
Receive
clock at
device b
 Clock Skew: pin-to-pin variation in the timing of

input clock at each agent (source & destination, in
our example) on a bus.
The net effect of clock skew is that it can
reduce the total delay that signals are allowed to have for
a given frequency target.
require larger minimum signal delays in order to avoid logic
errors. (We’ll cover this in more detail shortly.)
Introduction
12/4/2002
12
Clock path arrival mismatch
considerations (Skew)
 Clock distribution design decisions
include:
Choice of Topology
Enumeration is in following slides
Routed trace length rules
 If all bus devices are identical,
matching is just making equal length
routes from the clock buffer.
This is usually not the case
Introduction
12/4/2002
Serpentine Routing is used to adjust for lengths
L1
L2
Buffer
L1=L2
 Space between serpentine traces should be
minimum of 3x the dielectric height for
stripline and 5x the dielectric height for
microstrip.
 We can estimate the effect using the
coupling coefficient from a 2 D field solvers.
Introduction
12/4/2002
13
Changing layers in a clock tree
14
 Maintain the same length on the same
layer similar segments.
 Dielectric constant and impedance can
vary up to 10% between layers.
 Changing layers is subject to return
path effects
 Changing layers is normally not
desirable but may be unavoidable.
Simulation of parametric variation is use
to determine skew impact.
Introduction
12/4/2002
Jitter
15
Data Bus
D
SET
CLR
Q
Q
SET
CLR
Q
D
Q
D
SET
CLR
Q
Q
SET
CLR
Q
D
Q
D
SET
CLR
Q
Q
SET
Q
D
Q
SET
CLR
D
Q
Q
CLR
SET
Q
Q
D
CLR
 Reference oscillator
 PLL jitter – many types
 Buffer jitter
Clock Buffer
Mostly caused power
disturbance and SSO
 On Chip clock
distribution
Phase
Locked
Loop
Normally part of timing
spec
However, subject to
cascaded loop jitter.
Introduction
12/4/2002
16
Clock Source
 The traceable reference for most clocks
sources is a crystal oscillator.
 A phase locked loop (PLL) regenerates clocks
for distribution.
The primary purpose of a phase lock loop is to
synchronize signal edges.
PLLs may be the main clock domain source
PLLs may be used within each chip to
synchronizes internal nodes and external clock
references.
 PLLs are feedback amplifiers and subject to
stability criteria. This especially true when
PLLs cascaded.
Introduction
12/4/2002
17
Phase Locked Loop – Simple Circuit
Feedback Clock
Route
VCO
0
0
0
Phase detector
Clock in
Distribution Route
“Same electrical
length as feedback
clock”
When this point is 0 V
the distribution clocks
are in phase with the
“clock in”
Introduction
12/4/2002
18
Review Clock Jitter
Idea
clock
Clock with
Cycle to
Cycle
Jitter
Bar graph
of each
cycle time
Pulse Width
(Ideal)
Pulse Width
(Actual)
 Cycle to cycle variation of clock
 Reduces the time it take for data to get from


transmitter to receiver
Jitter + Skew is clock budget for setup
Skew is clock budget for hold
Hold uses same cycle of clock
In many cases we can ignore certain types of jitter
 There are other types of jitter – more advanced
topic
Introduction
12/4/2002
19
PLL
 Refer to the racing game





analogy in the text
The angle of travel is analogous
to frequency control.
The transfer function is
tracking gain vs. frequency of
phase error.
Low frequencies are tracked
well i.e. the gain is 1.
High frequencies are filtered.
PLL’s are cascaded the
response is product.
Tracking
Gain Tracking
4
Range
Filter
Range
3
Severe
Resonance
2
1
Well Damped
Freq.
Results response > 1 can cause
loop stability issues.
Introduction
12/4/2002
20
Other Types of Synchronizers
 Delay Locked Loop (DLL) – Adjust to sub-
clock phases. Synchronizing to quadrate is an
example.
Input
90 degree phase shift
 Phase Interpolator
The difference function only increments a count.
The phase stabilizes to the median of edge
crossings.
Adjustment is not proportional to amount of
phase error
Is use to pull a clock out of data signals
Introduction
12/4/2002
21
Phase Interpolator is a Voting Circuit
Interpolator
Lead/Lag Detect
Data Bit
D
Counter
Count
up
SET
Count
down
CLR
Ref
clock
DLL (edge position)
Introduction
Q
Q
Clock out
12/4/2002
22
Jitter Response measurement
 In all but simplest of
cases jitter
measurement can be
difficult.
 Power ripple can
introduce jitter
 This suggest that
PLL power should be
filtered
 Some data
generations can
introduce edge to
edge jitter.
Power Rail
AC
Introduction
PLL
12/4/2002
23
Clock Topologies – 2nd half of lecture
 We will go over additions to what is in
the text
 We will go over the clock simulation
project.
 You will need sweep parameters and
may need use Monte Carlo analysis that
was presented last semester.
 This is similar to an actual signal
integrity design task.
Introduction
12/4/2002
Source Series Termination
 Little or no re-reflection at
Rterm
D
L2a
L1a
CLR
Rterm
L1b
D
L2b
Rterm
L2a
SET
CLR
D
L2b
SET
CLR
D
Rterm
SET
SET
CLR
Q
Q
Q
Q
Q
Q
Q
Q
24
source.
 No additional components
required at loads.
Loads may be 1000+ pin BGAs
with limited component placement
room
Easier to get termination close to
source.
Clock buffers are relatively small
compared to computer and chip
set chips
Can support multiple loads on one
line with some restrictions
 Low DC power.
 Low impedance buffers can be
used.
 L1a and L1b need to be short
lengths
Introduction
12/4/2002
25
Ganged Source Termination
L1a L2a Rterm
L1b L2b
Rterm
L1c
L2c
L1d
Rterm
L2d
L3a
D
SET
CLR
L3b
D
SET
CLR
L3c
D
SET
CLR
Rterm
L3d
D
SET



Q
Q
Q
Q
Q
Via
Q
Q
Layout Example
L1a,b,c,d and L2a,b,c,d and L3a,b,c,d are matched.
L1’s and L2’s are short.
Many drivers have issues ganging outputs.
Buffer delays between legs is eliminated.
As the number of ganging goes up the via node tends
toward 0 ohms
CLR

Buffer Chip
Q
Introduction
12/4/2002
26
Double (multiple) loaded lines
 Electrically this appears
L1 Rterm
L2
SET
D
CLR
L3
D
Q
Q
SET
CLR
D
L1 Rterm
L2
SET
L3
CLR
L3
D
SET
CLR
Q
Q
Q
Q
Q
Q
unattractive at first
glance
 May be required if clock
buffers are scarce.
 Simulation can determine
if the edges are
monotonic and if skew is
acceptable.
 In general: This is OK for
clock with slow edges
There is a design task to
determine L3.
L3 is usually short.
Introduction
12/4/2002
27
Case Study and Project – testckt_clk.sp
L1
Ln1 Rterm
Ln2
L2
C1
D
C2
SET
CLR
Q
Q
L4
L3
Ln1 Rterm
Ln3
Ln4
C3
Ln5
D
C4
L5
•
•
•
•
•
CLR
D
C5
SET
SET
CLR
Q
Q
Q
Q
Buffer: 100 MHz, Rn=10 ohm, Rp=70 ohm, Tr=700ps
Rterm=40 ohm, all inductors 1nH, All caps=1pf,
Ln1=.5”, Ln2=10”, Ln3=9”, Ln5=LN4=1”
Transmission line: er=4.1 Z0=68ohms
Receiver threshold = 1.5V +/- 0.1V
Introduction
12/4/2002
28
Main program
 Use level 1 behavioral model for MYBUF
 Create new board, package, and receiver
subcircuits
Introduction
12/4/2002
Level 1 Behavioral Model
29
 Pass capacitor load in as parameter
 10 ohms up and 70 ohms down (Rp and Rn)
 Slew is controlled by input pulse
Introduction
12/4/2002
Packages are just series inductors
30
 Receiver package has the inductance value
passed in.
 No coupling in buffer package and the
inductance is set to 1 nH
Introduction
12/4/2002
The topology is captured in the brd subcircuit
31
 The length and terminators are not
parameterized here.
 For our project you will need to parameterize
them.
Introduction
12/4/2002
32
Transmission line model
 We will parameterize L0 and C0 in terms of Z0 and er.
 This means we can change Z0 and er and get a realistic

transmission line. Notice the equations above in the
first line.
This is quick way to parameterize a lossy transmission
line. For 100MHz, the loss parameter are less
significant that for 1GHz+. It will suffice for our
example
Introduction
12/4/2002
33
Simple receiver model
 In our test case, rload is 10K and cload is 1 pF
Introduction
12/4/2002
34
Results
Potential oxide
wear out
problem
 Blue is the single line
 Red is the end of the forked line
Introduction
Potential for
glitch on
negative edge
12/4/2002
35
Effect of impedance sweep from 40 to 90 W
 Skew measurements are done for the steady state
solution for clocks
i.e. take measurements on the 3rd edge
.MEAS TRAN skew1 TRIG V(clk1_pad) VAL=vil
+RISE=3 TD=0ns TARG V(clk2a_pad) VAL=vih RISE=3 TD=0ns
Introduction
12/4/2002
36
Example of dependencies
skew
1800
1600
1400
ps
1200
1000
skew
800
600
400
200
0
0
20
40
60
80
100
impedance
 When the impedance Z0 is below 50 ohms the skew
increases rapidly
 This is only one case of other simulation parameters
 Your project need to evaluate all cases
Introduction
12/4/2002
37
Clock Design Project
 You are to define board design parameters target Z0,
Ln1, Ln3, Ln4, Ln5
Each segment can have a separate Z0 but may not be
necessary and is will add cost to the design.
 The skew goal is 900 ps (not +/-)
 The undershoot safe limit is -600 mV
You can exceed -600 mV to -1V but only for 1 ns
 It may not be possible to meet all requirements.
If so, determine the best design and the weak corners.
 Hand in 10-15 minutes of Power Point proving your


design
Use HSPICE with a combination of Monte Carlo and
sweeping to acquire supporting data.
You will need to further parameterize testckt_clk.sp
Introduction
12/4/2002
Transmission Lines
 All lines are on the same layer
 They can be different impedances but if one
38
varies by 10 %, they all will see the same
variation.
 L2 is given to be exactly 10 inches
 L1 at least 1 inch
 Er is constant at 4.1
 You need to choose the impedance target for
each of the segments
 The chosen target impedance will vary +/- 10%
across all products
 Use Model on slide 27
“Case Study and Project – testckt_clk.sp”
Introduction
12/4/2002
39
Buffer
 Clock frequency is 100 MHz
 Rise fall time varies between 4Volts/ns and 0.75 V/ns
when driving a 1K ohms load to ground and measured
between 1.3 and 1.7 volts.





You will have to adjust pulse “tr” time to compensate.
Both buffers Rn and Rp move together.
Rn and Rp vary by 20% and move together.
Rp target is 10 ohms
Rn target is 70 ohms
Vcc target is 3.3 volts +/- 10 %
You may determine this regulation may need to improve. If
so, you will need to report the acceptable percentage.
 The capacitance buffer load (bload) is 1pF
Introduction
12/4/2002
40
Packages
 Inductance of buffer ranges between
1nH and 2nH.
 Inductance of load (receiver) packages
ranges between 1nH and 2nH and vary
independently.
Introduction
12/4/2002
41
Load (Receiver)
 Receiver threshold is between 1.4 and
1.6 volts.
 Capacitance load of single load circuit is
between 1pF and 2pF.
 Capacitance loads of dual load circuit
(fork) is between 1pF and 3pF and varies
independently.
 DC load of all receivers is 10K to ground.
Introduction
12/4/2002
Suggestion on how to start
42
 List all parameters
 List ranges
 Determine sensitivity
Introduction
12/4/2002