BACHELOR’S DEGREE IN TELECOMMUNICATIONS
Second chance exam 3GM – 3GT
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12 June 2015
Digital Circuits and Systems (CSD)
J. Jordana, F. J. Robert
Grades will be available on 16 June 2015.
Questions about the exam: Lecturer’s office hours.
VERY IMPORTANT: Follow general instructions1 to solve the problem.
Individual Test 2
1- Draw the hierarchical block diagram of a frequency divider. Take into account that its input clock frequency is 16 MHz
and it is required to obtain the following square output frequencies: 100 Hz, 500 Hz and 10 kHz. How many VHDL files
are required?
Write the main VHDL sentences of the top level circuit.
Write the main sentences of the test bench file in order to simulate its behaviour.
Indicate the files involved in a functional simulation and the files involved in a gate level simulation.
[4 p]
2- Draw the entity of a 5-bit universal shift register. Identify clearly its inputs and outputs. Draw the ASM chart
corresponding to its CC1.
Explain by means of a timing diagram its function. Suppose that you initially load the value Din = “00111”. Justify clearly
the values of the input ports and output ports. Write the main sentences of the test bench file.
[2 p]
3- Design a binary counter that satisfies the following sequence: 0, 2, 4, 6, 8, 1, 3, 5, 7, 9, 0, 2, …
Draw the entity of the circuit and write the main sentences of the VHDL code file.
[2 p]
4- How many synchronous D-type flip-flops are required to implement a sequential circuit with 129 states? And a
sequential circuit with N states? Justify your response.
[2 p]
1
http://digsys.upc.es/ed/CSD/terms/1213Q1/cntl.html. A student interview about the submitted work may also be requested.
Individual Test 3
The 8-bit dedicated datapath represented in Fig. 1 is able to generate and add the numbers from n down to 1, where n is an 8bit user-input number. The datapath outputs the sum of the numbers when done and notify external devices that the
calculation is completed by asserting a Done signal. The operations are performed accordingly to the algorithm:
Fig. 1. The datapath for solving the proposed summation. Circuit reference: Hwang, E. O., “Digital logic and
microprocessor design with VHDL”, Brooks-Cole, 2005.
1.
2.
Run an example, for instance, considering that input = 5, to analyse and figure out how the operation is performed.
Annotate the values for all the signals and ports.
Draw the general block diagram consisting of the datapath and the control unit. Suppose that the operation is triggered
when clicking a start button (ST) signal. Which are the control signals from the control unit to the datapath? Which are
the status signals from the datapath to the control unit? Which is the data input and data output? Which are the user
control signals?
Fig. 2. General structure of a dedicated processor.
3.
4.
5.
Determine how many states are required to control the processing of the operation by means of this proposed
datapath and name them all. Draw the state diagram.
How long does it take to solve the algorithm if Input = 25? Consider that the CLK is 1 MHz.
How many VHDL files will this system require? Justify your answer.
Individual Test 4
(Model 1)
1.
Explain how you would program pins 1, 3, and 5 of PORTC of Atmega8535 as inputs, and the other pins as outputs.
Indicate the values that you load on the registers associated to this port.
[2p]
2. a) Draw the entity and schematic of the 1 digit BCD adder, considering both, the schematic and the function
(read_inputs() represented in Fig. 3. Indicate the port pins of the Atmega8535 where the summands (Value_A, Value_B)
and carry input (C_in) are connected.
b) Plan the flow chart of the truth table and translate it into C code for obtaining the BCD result (Value_BCD_Units,
Value_Cout).
c) Explain in C code, how you would program the sum (S3,S2,S1,S0) and the carry output (C_out) in order to represent
the result in the following pins: PB1 (S3), PB2 (S2), PB3(S1), PB4 (S0) and PB7 (C_out).
[2p]
static
static
static
static
static
static
char
char
char
char
char
char
Value_A;
Value_B;
Value_Cin;
Bin_Sum;
Value_BCD_Units;
Value_C_out;
void read_inputs (void){
char Read_Value, Read_Value2;
Read_Value = PINC & 0b00001100;
Value_A = Read_Value | (PINC & 0x03);
Read_Value = (PIND & 0b000011000) >>3;
Read_Value2 = (PINC & 0b11000000)>>4;
Value_B = Read_Value | Read_Value2;
Value_Cin = (PINA & 0x04 )>>2;
}
Fig. 3. The 1-digit BCD adder.
3.
Assuming fosc = 8 MHz and a prescaler of 8. What Timer0 configuration will generate a periodic interrupt every 500 s
with Atmega8535? How would you generate a delay of 4 s, using this interrupt? Indicate approximately the C code for
the interrupt service routine.
[1p]
4.
Indicate the interrupt vector address of the external interrupt INT0. How would you program this interrupt to be active
on the rising edge of the pulse applied to it?
[1p]
5.
Indicate which of the following interrupts of Atmega8535 has the lower priority? Justify your response.
[1p]
- ADC conversion complete.
- External interrupt INT2.
- Timer 0 overflow.
6.
Analyse the following code fragment corresponding to the microcontroller Atmega8535.
[3p]
ISR(TIMER0_OVF_vect) {
TCNT0 = 0bx00011111;
++time_count;
If (time_count == N){
Time_flag =0;
}
}
a) If TCCR0 = 0x02 and Fosc = 6 MHz, Indicate which is the interrupt period of Timer0.
b) Which decimal value would you charge to TCNT0 to create an interrupt period of 88 s?
c) If initially time_count = 0 and Time_flag = 1, which value would be charged on variable N to produce a delay of 0.7 s
when Time_flag reaches the value ’0’? (Suppose TCNT0 = 0xB5).
Individual Test 4
(Model 2)
We’ve been examining the documentation of the PICDEM Lab Development Kit from Microchip (Part Number: DM163045), and
we want to adapt an example to our AVR mega 16/32 starter development board. Let’s adapt the LAB #4: Rotate LEDs exercise
to our CSD programming style and conventions and to the ATmega8535 microcontroller. Therefore, our aim is to implement an
8-bit shift register which works as an LED rotator as explained in the Fig. 5. The system restarts automatically after clicking
RESET.
a)
b)
Fig. 4 a) The AVR mega 16/32 starter development board is designed to provide a comprehensive development and
learning platform for Atmel AVR microcontrollers; b) The circuit of our project.
Fig. 5 Modes of operation of our LED rotator.
1.
Specify the hardware: general I/O and external interrupt pin configuration.
2.
Specify the software: table to define how the system works, state diagram, timing diagram, etc.
3.
Plan: FSM style. General C program organisation, functions to be used and software variables, flow chart of each
function. To run the system at the CLK frequency of 2.5 Hz, use interrupts from one of these sources:
Option a) Use the external 2.5 Hz square wave.
Option b) Use the Timer0 peripheral (FOSC = 8 MHz).
4.
Develop: Write the C language modifying an existing sample design, Atmel Studio and the C compiler, etc.
5.
(Optional) Test: Simulate the hardware circuit from Fig. 4b in the Proteus virtual laboratory, and then, download the
configuration file (*.hex) onto the development and learning Board ATMEL Kit.
6.
How to connect an LCD to this system? How many source “*.c” files will include the project?