Technion - Israel institute of technology
department of Electrical Engineering
High speed digital systems laboratory
‫ מכון טכנולוגי לישראל‬- ‫הטכניון‬
‫הפקולטה להנדסת חשמל‬
‫המעבדה למערכות ספרתיות מהירות‬
)’‫דו”ח סיכום פרויקט (חלק א‬
Subject:
Generic Daughter Board
For 5510 EVM
Performed by:
Instructor:
Roi Sherman
Eyal Wilamowski
Mr. Michael Itzkovich
‫סמסטר חורף תשס"ב‬
‫המעבדה למערכות ספרתיות מהירות‬
High speed digital systems laboratory
Abstract
The project aim is to implement a general purpose daughter
board for the TI 5510 EVM prototype board. The card could be
used for connecting of up to 4 DSP’s through the McBSP for
Parallel Computation and system resources sharing.
The card would have the ability to operate as master in a
standalone mode, or even connect to an expansion board of it’s
own.
The implemented card is generic as possible yielding maximum
use of pins, connectors etc. High percent of all resources are not
purpose and controlled by the main control unit.
‫המעבדה למערכות ספרתיות מהירות‬
High speed digital systems laboratory
System description
• 3.3v operation for all components
2MB
SRAM
1MB
Flash
• 5v power supply
EMIF
MB Interface
• 32 Bit Data Bus
RS232
Control Unit
(Altera)
GPIO
• FPGA Control Unit
McBSP
• JTAG programming interface
Peripheral Interface
• 8MBytes Address Space
‫המעבדה למערכות ספרתיות מהירות‬
High speed digital systems laboratory
System description (cont.)
• General Purpose discrete interface
2MB
SRAM
1MB
Flash
• 1MB Flash Memory
EMIF
MB Interface
• 2 x RS232 serial channels
RS232
Control Unit
(Altera)
GPIO
• 3 x McBSP channels
McBSP
• Led Indicators
Peripheral Interface
• 2MB Asynchronous SRAM
High speed digital systems laboratory
‫המעבדה למערכות ספרתיות מהירות‬
Hardware Specification
• Altera’s EPF10K100ARC-1 FPGA
• Altera’s EPC2TC32
• 2 x AMD 4Mb Flash Memory AM29LV400BT-70
• 4 x Alliance 4Mb Async SRAM AS7C34098-10TC
• 16-Bit Bus Transceivers SN74LVTH16245
• National’s LM1085 Voltage Regulator
• 2 x RS-232 MAX3238 Transceivers
High speed digital systems laboratory
‫המעבדה למערכות ספרתיות מהירות‬
Hardware Specification (cont.)
• 2 x TL16C550CPT Single UART with FIFO
• SN74LVC08A AND gates
• MAX821TUS-T Voltage Monitor
• 40MHz Oscillator
• 1.8432MHz Oscillator
‫המעבדה למערכות ספרתיות מהירות‬
High speed digital systems laboratory
Flash Memory
MAIN PROPERTIES
4Mb
4Mb
Flash
Flash
Address
MB Control
 IC Arrangement 16*256M .
DB Control
EVM 5510
Data
 2 X 4Mb AMD Flash memory.
 PN: AM29LV400-70. Package TSOP
48 pin .
 Could be replaced by larger sized ICs
with same pinout. Up to total of
4MBytes.
 Conclusion:
Control Unit
(Altera)
Fast , Reliable Manufacturer,
Upgradeable.
‫המעבדה למערכות ספרתיות מהירות‬
High speed digital systems laboratory
X_D[0:31]
X_A [2..21]
X_A [2..21]
U4
X_A 2
X_A 3
X_A 4
X_A 5
X_A 6
X_A 7
X_A 8
X_A 9
X_A 10
X_A 11
X_A 12
X_A 13
X_A 14
X_A 15
X_A 16
X_A 17
X_A 18
X_A 19
X_A 20
X_A 21
FLA SH_BYTE_NOT
X_OE_NOT
X_RESET_NOT
X_WE_ NOT
FLA SH0_CE
25
24
23
22
21
20
19
18
8
7
6
5
4
3
2
1
48
17
16
9
47
28
12
11
26
37
3.3V
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A 10
A 11
A 12
A 13
A 14
A 15
A 16
A 17
NC
NC
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15/A -1
RY /BY
U5
X_D0
X_D1
X_D2
X_D3
X_D4
X_D5
X_D6
X_D7
X_D8
X_D9
X_D10
X_D11
X_D12
X_D13
X_D14
X_D15
29
31
33
35
38
40
42
44
30
32
34
36
39
41
43
45
15
X_A 2
X_A 3
X_A 4
X_A 5
X_A 6
X_A 7
X_A 8
X_A 9
X_A 10
X_A 11
X_A 12
X_A 13
X_A 14
X_A 15
X_A 16
X_A 17
X_A 18
X_A 19
X_A 20
X_A 21
FLA SH0_RDY
BY TE
OE
RST
WE
CE
FLASH
V CC
FLA SH_BYTE_NOT
X_OE_NOT
X_RESET_NOT
X_WE_ NOT
FLA SH1_CE
25
24
23
22
21
20
19
18
8
7
6
5
4
3
2
1
48
17
16
9
47
28
12
11
26
37
3.3V
A M2 9LV40 0/SO48
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A 10
A 11
A 12
A 13
A 14
A 15
A 16
A 17
NC
NC
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15/A -1
RY /BY
BY TE
OE
RST
WE
CE
V CC
A M2 9LV40 0/SO48
3.3V
3.3V
C13
C14
FLASH CE
PULL UP
100nF
R28
10K
R29
10K
FLA SH0_CE
FLA SH1_CE
100nF
29
31
33
35
38
40
42
44
30
32
34
36
39
41
43
45
15
X_D16
X_D17
X_D18
X_D19
X_D20
X_D21
X_D22
X_D23
X_D24
X_D25
X_D26
X_D27
X_D28
X_D29
X_D30
X_D31
FLA SH1_RDY
‫המעבדה למערכות ספרתיות מהירות‬
High speed digital systems laboratory
SRAM
4Mb
4Mb
Flash
4Mb
SRAM
4Mb
SRAM
SRAM
MAIN PROPERTIES
 4 X 4Mb Alliance
Semiconductor Async SRAM.
 IC Arrangement 16*256M .
Address
MB Control
DB Control
EVM 5510
Data
 10nSec Access Time.
 CS for each IC controlled by
FPGA only.
 Why asynchronous ?
TI’s daughter board specification.
Control Unit
(Altera)
 Conclusion:
Large, Fast, available.
‫המעבדה למערכות ספרתיות מהירות‬
X_OE_NOT
X_WE_ NOT
SRA M0_CS
C62
C63
C64
10uF
100nF
100nF
7
8
9
10
13
14
15
16
29
30
31
32
35
36
37
38
OE
WE
CS
X_OE_NOT
X_WE_ NOT
SRA M1_CS
11
33
C68
C69
100nF
100nF
R67
10K
3.3V
R68
10K
R69
10K
39
40
X_BE0_NOT
X_BE1_NOT
41
17
6
X_OE_NOT
X_WE_ NOT
SRA M2_CS
SRAM
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A 10
A 11
A 12
A 13
A 14
A 15
A 16
A 17
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
7
8
9
10
13
14
15
16
29
30
31
32
35
36
37
38
C65
C66
C67
10uF
100nF
100nF
OE
WE
CS
V CC
V CC
3.3V
1
2
3
4
5
18
19
20
21
22
23
24
25
26
27
42
43
44
39
40
X_BE2_NOT
X_BE3_NOT
V CC
V CC
7
8
9
10
13
14
15
16
29
30
31
32
35
36
37
38
A S7C34098-10TC
U18
X_A 2
X_A 3
X_A 4
X_A 5
X_A 6
X_A 7
X_A 8
X_A 9
X_A 10
X_A 11
X_A 12
X_A 13
X_A 14
X_A 15
X_A 16
X_A 17
X_A 18
X_A 19
LB
UB
OE
WE
CS
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
X_D0
X_D1
X_D2
X_D3
X_D4
X_D5
X_D6
X_D7
X_D8
X_D9
X_D10
X_D11
X_D12
X_D13
X_D14
X_D15
LB
UB
X_A [2:19]
X_D16
X_D17
X_D18
X_D19
X_D20
X_D21
X_D22
X_D23
X_D24
X_D25
X_D26
X_D27
X_D28
X_D29
X_D30
X_D31
41
17
6
X_OE_NOT
X_WE_ NOT
SRA M3_CS
11
33
GND
GND
41
17
6
R66
10K
3.3V
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A 10
A 11
A 12
A 13
A 14
A 15
A 16
A 17
A S7C34098-10TC
12
34
39
40
X_BE2_NOT
X_BE3_NOT
3.3V
1
2
3
4
5
18
19
20
21
22
23
24
25
26
27
42
43
44
3.3V
1
2
3
4
5
18
19
20
21
22
23
24
25
26
27
42
43
44
11
33
U17
X_A 2
X_A 3
X_A 4
X_A 5
X_A 6
X_A 7
X_A 8
X_A 9
X_A 10
X_A 11
X_A 12
X_A 13
X_A 14
X_A 15
X_A 16
X_A 17
X_A 18
X_A 19
3.3V
3.3V
V CC
V CC
X_A [2:19]
SRAM CS PULL UP
SRA M0_CS
SRA M1_CS
SRA M2_CS
SRA M3_CS
LB
UB
12
34
11
33
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
X_D[0:31]
U16
X_A 2
X_A 3
X_A 4
X_A 5
X_A 6
X_A 7
X_A 8
X_A 9
X_A 10
X_A 11
X_A 12
X_A 13
X_A 14
X_A 15
X_A 16
X_A 17
X_A 18
X_A 19
12
34
41
17
6
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A 10
A 11
A 12
A 13
A 14
A 15
A 16
A 17
X_A [2:19]
GND
GND
39
40
X_BE0_NOT
X_BE1_NOT
3.3V
1
2
3
4
5
18
19
20
21
22
23
24
25
26
27
42
43
44
X_D0
X_D1
X_D2
X_D3
X_D4
X_D5
X_D6
X_D7
X_D8
X_D9
X_D10
X_D11
X_D12
X_D13
X_D14
X_D15
GND
GND
X_D[0:31]
U15
X_A 2
X_A 3
X_A 4
X_A 5
X_A 6
X_A 7
X_A 8
X_A 9
X_A 10
X_A 11
X_A 12
X_A 13
X_A 14
X_A 15
X_A 16
X_A 17
X_A 18
X_A 19
A S7C34098-10TC
C70
C71
100nF
100nF
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A 10
A 11
A 12
A 13
A 14
A 15
A 16
A 17
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
7
8
9
10
13
14
15
16
29
30
31
32
35
36
37
38
LB
UB
OE
WE
CS
V CC
V CC
GND
GND
X_A [2:19]
12
34
High speed digital systems laboratory
A S7C34098-10TC
X_D16
X_D17
X_D18
X_D19
X_D20
X_D21
X_D22
X_D23
X_D24
X_D25
X_D26
X_D27
X_D28
X_D29
X_D30
X_D31
‫המעבדה למערכות ספרתיות מהירות‬
High speed digital systems laboratory
RS232 Channels
MAIN PROPERTIES
Control Unit (Altera)
Ctrl
data
addr
Ctrl
data
addr
UART
UART
 2 configurable standard RS232
serial channels.
 TI TL16C550CPT single
UART’s with 16 Byte FIFO.
 MAX3238 RS232 Transceivers.
RS232
Transceiver
RS232
Transceiver
 Standard DB9 connectors.
 1.8432Mhz Oscillator.
 Memory Mapped.
DB9
DB9
 Asynchronous operation, using
interrupts.
‫המעבדה למערכות ספרתיות מהירות‬
High speed digital systems laboratory
RS232 Channels (cont.)
Control Unit (Altera)
Ctrl
data
addr
Ctrl
data
addr
 Conclusion:
 Industry standard UART.
UART
UART
 Reliable & Available
Transceiver.
 Standard RS232 Connectors.
RS232
Transceiver
RS232
Transceiver
 UART: IC or ALTERA CORE ?
 Reduce FPGA resources.
DB9
DB9
 Academic - more HW
substance.
‫המעבדה למערכות ספרתיות מהירות‬
High speed digital systems laboratory
UART CS
PUPs
U_D[0..7]
U11
U_A [0..2]
3.3V
UART CS PULL UP
3.3V
3.3V
R53
10K
R55
10K
R54
10K
U_D0
U_D1
U_D2
U_D3
U_D4
U_D5
U_D6
U_D7
43
44
45
46
47
2
3
4
U_A 0
U_A 1
U_A 2
28
27
26
R56
10K
9
10
30
35
29
23
U1_INT
U_RST
U1_CS
U2_CS
11
16
19
U1_CS
U_WR
U_RD
24
20
17
R58
1K
R59
1K
R60
1K
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
CS0
CS1
INTRPT
MR
RXRDY
TXRDY
CS2
WR1
RD1
A DS
RD2
WR2
U12
OUT1
DTR
SDO
RTS
OUT2
CTS
SDI
DSR
DCD
RI
DDIS
BA UDOUT
RCLK
XIN
34
33
8
32
31
24
23
22
19
17
38
7
39
21
20
18
40
41
22
C49
0.22uF
C50
0.22uF
12
5
14
3.3V
3.3V
28
25
1
3
27
4
15
C52
100nF
R57
1K
R1OUT
R2OUT
R3OUT
C1+
C1C2+
C2V+
V-
C51
0.22uF
T1OUT
T2OUT
T3OUT
T4OUT
T5OUT
R1IN
R2IN
R3IN
R1OUTB
INVA LID
FORCEON
FORCEOFF
26
XOUT
T1IN
T2IN
T3IN
T4IN
T5IN
5
6
7
10
12
8
9
11
P_DCD1
P_DSR1
P_RXD1
P_CTS1
P_RI1
P_RTS1
P_TXD1
P_DTR1
16
15
13
14
RS1_INV
RS1_FRC_ON
RS1_FRC_OFF
V CC
C53 MAX32 38/SO
0.22uF
3.3V
V CC
Y2
42
3
TL16C550C/FP
C54
100nF
OUT
EN
V CC
1
4
OSC-1.8432MHz/SM
UART
RS232
TRANSCEIVER
C55
100nF
U_CLK
U_D[0..7]
U13
U_A [0..2]
3.3V
R61
10K
R62
10K
U_D0
U_D1
U_D2
U_D3
U_D4
U_D5
U_D6
U_D7
43
44
45
46
47
2
3
4
U_A 0
U_A 1
U_A 2
28
27
26
9
10
U2_INT
U_RST
U2_CS
U_WR
U_RD
30
35
29
23
11
16
19
24
20
17
R63
1K
R64
1K
R65
1K
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
CS0
CS1
INTRPT
MR
RXRDY
TXRDY
CS2
WR1
RD1
A DS
RD2
WR2
U14
OUT1
DTR
SDO
RTS
OUT2
CTS
SDI
DSR
DCD
RI
DDIS
BA UDOUT
RCLK
XIN
XOUT
34
33
8
32
31
24
23
22
19
17
38
7
39
21
20
18
40
41
22
C56
0.22uF
C57
0.22uF
12
5
CLK
1.8432MHz
14
15
3.3V
V CC
TL16C550C/FP
42
C61
100nF
3.3V
28
25
1
3
27
4
C58
0.22uF
R1OUT
R2OUT
R3OUT
C1+
C1C2+
C2V+
V-
T1OUT
T2OUT
T3OUT
T4OUT
T5OUT
R1IN
R2IN
R3IN
R1OUTB
INVA LID
FORCEON
FORCEOFF
26
C59
100nF
T1IN
T2IN
T3IN
T4IN
T5IN
V CC
C60 MAX32 38/SO
0.22uF
5
6
7
10
12
8
9
11
P_DCD2
P_DSR2
P_RXD2
P_CTS2
P_RI2
P_RTS2
P_TXD2
P_DTR2
16
15
13
14
RS2_INV
RS2_FRC_ON
RS2_FRC_OFF
‫המעבדה למערכות ספרתיות מהירות‬
High speed digital systems laboratory
GPIO
MAIN PROPERTIES
Control Unit
(Altera)
 3 X 16 bit wide buses.
 10 X 2 connectors. Suitable for logic analyzer
100KΩ Termination Adapter.
 Busses are buffered for FPGA protection & for
Current driving.
 Bi-directional TI’s SN74LVTH16245 bus
transceivers (Standard & Availability).
Header
10 X 2Header
10 X 2Header
10 X 2
 Transceivers direction controlled by FPGA.
 40MHz/1.8432MHz clock signals.
 UART data bus connected to a gpio bus.
 1 bus could be realized as open/gnd or open/vcc.
‫המעבדה למערכות ספרתיות מהירות‬
High speed digital systems laboratory
3.3V
3.3V
C1
100nF
C2
100nF
C3
100nF
3.3V
C4
100nF
3.3V
C5
100nF
C6
100nF
C7
100nF
U1
18
7
GPA [0..15]
3.3V
R1
10K
R2
10K
GPA 0
GPA 1
GPA 2
GPA 3
GPA 4
GPA 5
GPA 6
GPA 7
47
46
44
43
41
40
38
37
GPA 8
GPA 9
GPA 10
GPA 11
GPA 12
GPA 13
GPA 14
GPA 15
36
35
33
32
30
29
27
26
1
24
GPA _1DIR
GPA _2DIR
48
25
GPA _1OE
GPA _2OE
3.3V
V CC
V CC
V CC
V CC
1A 1
1A 2
1A 3
1A 4
1A 5
1A 6
1A 7
1A 8
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2A 1
2A 2
2A 3
2A 4
2A 5
2A 6
2A 7
2A 8
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
31
42
P_GPA [0..15]
2
3
5
6
8
9
11
12
P_GPA 0
P_GPA 1
P_GPA 2
P_GPA 3
P_GPA 4
P_GPA 5
P_GPA 6
P_GPA 7
13
14
16
17
19
20
22
23
P_GPA 8
P_GPA 9
P_GPA 10
P_GPA 11
P_GPA 12
P_GPA 13
P_GPA 14
P_GPA 15
18
7
GPB[0..15 ]
3.3V
R3
10K
1DIR
2DIR
GPB_1DIR
GPB_2DIR
1OE
2OE
GPB_1OE
GPB_2OE
74LV TH16245/SO
C9
100nF
C8
100nF
U2
R4
10K
GPB0
GPB1
GPB2
GPB3
GPB4
GPB5
GPB6
GPB7
47
46
44
43
41
40
38
37
GPB8
GPB9
GPB10
GPB11
GPB12
GPB13
GPB14
GPB15
36
35
33
32
30
29
27
26
1
24
C10
100nF
C11
100nF
V CC
V CC
1A 1
1A 2
1A 3
1A 4
1A 5
1A 6
1A 7
1A 8
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2A 1
2A 2
2A 3
2A 4
2A 5
2A 6
2A 7
2A 8
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
31
42
P_GPB[0..15]
2
3
5
6
8
9
11
12
P_GPB0
P_GPB1
P_GPB2
P_GPB3
P_GPB4
P_GPB5
P_GPB6
P_GPB7
13
14
16
17
19
20
22
23
P_GPB8
P_GPB9
P_GPB10
P_GPB11
P_GPB12
P_GPB13
P_GPB14
P_GPB15
1DIR
2DIR
48
25
3.3V
V CC
V CC
1OE
2OE
74LV TH16245/SO
C12
100nF
BUFFERS
P_GPB[0..15]
U3
3.3V
NA
18
7
GPC[0..7]
GPC0
GPC1
GPC2
GPC3
GPC4
GPC5
GPC6
GPC7
U_D[0..7]
3.3V
R22
10K
GPC_1DIR
GPC_2DIR
GPC_1OE
GPC_2OE
R23
10K
U_D0
U_D1
U_D2
U_D3
U_D4
U_D5
U_D6
U_D7
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1
24
48
25
V CC
V CC
V CC
V CC
1A 1
1A 2
1A 3
1A 4
1A 5
1A 6
1A 7
1A 8
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2A 1
2A 2
2A 3
2A 4
2A 5
2A 6
2A 7
2A 8
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
31
42
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
P_GPC0
P_GPC1
P_GPC2
P_GPC3
P_GPC4
P_GPC5
P_GPC6
P_GPC7
74LV TH16245/SO
0
P_UD0
P_UD1
P_UD2
P_UD3
P_UD4
P_UD5
P_UD6
P_UD7
NA
P_UD[0 ..7]
NA
P_GPB1
R6
10K
R7
10K
P_GPB0
P_GPB3
R8
10K
R9
10K
P_GPB2
P_GPB5
R10 10K
R11 10K
P_GPB4
P_GPB7
R12 10K
R13 10K
P_GPB6
P_GPB9
R14 10K
R15 10K
P_GPB8
P_GPB11
R16 10K
R17 10K
P_GPB10
P_GPB13
R18 10K
R19 10K
P_GPB12
P_GPB15
R20 10K
R21 10K
P_GPB14
1DIR
2DIR
1OE
2OE
R5
P_GPC[0..7]
NA
R24
0
‫המעבדה למערכות ספרתיות מהירות‬
High speed digital systems laboratory
McBSP
MAIN PROPERTIES
Control Unit
(Altera)
 3 McBSP channels
 Full duplex serial communication.
EVM 5510
 Double buffered.
 Channel 2 is connected to the FPGA
through spare pines in the McBSP
connector.
Header
4 X 2 Header
4 X 2 Header
4X2
 Use of Channel 2 requires alteration of
the MB.
 Main purpose – connecting DSP’s for
parallel operation.
‫המעבדה למערכות ספרתיות מהירות‬
High speed digital systems laboratory
FPGA
 Altera’s EPF10K100ARC-1 FPGA.
 RQFP 240 pin package.
 189 IO pins, all used.
 Size 1,200,000 bits.
 Programmed by EPC2 E2PROM.
 EPC2TC32 size : 1,695,680 bits.
JTAG interface for EPC2 programming.
C25
C28
10uF
C31
10uF
C34
for
McBSP2
use
R36
0
X_CLKOUT_R
3.3V
PIN 5
3.3V
C18
100nF
3.3V
PIN 16
C20
100nF
3.3V
PIN 27
PIN 112
C22
10uF
PIN 37
C24
100nF
PIN 47
C27
100nF
10uF
PIN 57
C30
100nF
PIN 77
C33
100nF
PIN 89
C36
100nF
PIN 96
C38
100nF
C40
100nF
LEDS
PIN 122
C19
100nF
PIN 130
C21
100nF
PIN 140
C23
100nF
PIN 150
C26
100nF
PIN 160
C29
100nF
PIN 170
C32
100nF
EPC2
PIN 189
C35
100nF
PIN 205
C37
100nF
PIN 224
C39
100nF
A _LED1
A _LED2
A _LED3
A _LED4
3.3V
3.3V
3.3V
R41
1K
R37
150
R38
150
R39
150
R40
150
D1
LED
D2
LED
D3
LED
D4
LED
R42
1K
R43
1K
R44
1K
TMS
TDI
TCK
R47
1K
U7
100nF
17
3
A _STA TUS 7
A _CONF_ DONE 10
25
13
32
TMS
TDI
TCK
VCC
RS1_INV
RS2_INV
27
X_CNTL0
X_CNTL1
23
X_CLKOUT
C16
100nF
V PPSEL
V CCSEL
DCLK
DA TA
OE
CS
CA SC
INIT_CONF
TDO
2
31
16
28
GPC[0..7]
C17
100nF
R34
A_LED1
A_LED2
A_LED3
A_LED4
I/O/INIT_DONE
I/O/CLKUSR
I/O/CS
I/O/RDY/BSY
U_D[0..7]
3
ALTERAEPF10K100ARC
EPF10K100ARC
ALTERA
GPB[0..15 ]
OUT
R45
1K
EPF10K100ARC/PFP240
MSEL 1
MSEL 0
DCLK
CONFIG
STATUS
CONF_DONE
DATA0
123
124
179
121
60
2
180
177
4
58
59
1
D_CLK
A_CONFIG
A_STATUS
A_CONF_DONE
A_DATA0
A_TMS
A_TRST
A_TCK
A_TDI
GPA0
GPA1
GPA2
GPA3
GPA4
GPA5
GPA6
GPA7
GPA8
GPA9
GPA10
GPA11
GPA12
GPA13
GPA14
GPA15
GPA_1OE
GPA_1DIR
GPA_2OE
GPA_2DIR
FLASH0_CE
FLASH0_RDY
FLASH_BYTE_NOT
FLASH1_CE
FLASH1_RDY
X_A2
X_A3
X_A4
X_A5
X_A6
X_A7
X_A8
X_A9
X_A10
X_A11
X_A12
X_A13
X_A14
X_A15
X_A16
X_A17
X_A18
X_A19
X_A20
X_A21
X_BE0_NOT
X_BE1_NOT
X_BE2_NOT
X_BE3_NOT
R31
1K
26
11
240
23
CE
CEO
TDI
TDO
TMS
TRST
TCK
201
202
203
204
206
207
208
209
213
214
215
217
218
219
220
221
222
223
225
226
198
210
199
200
212
149
148
147
146
144
143
142
141
139
138
137
136
134
133
132
131
129
128
127
126
154
153
152
151
X_D0
X_D1
X_D2
X_D3
X_D4
X_D5
X_D6
X_D7
X_D8
X_D9
X_D10
X_D11
X_D12
X_D13
X_D14
X_D15
X_D16
X_D17
X_D18
X_D19
X_D20
X_D21
X_D22
X_D23
X_D24
X_D25
X_D26
X_D27
X_D28
X_D29
X_D30
X_D31
R30
1K
178
3
XCLK
CLK
FRCON2
FRCOFF2
FRCON1
FRCOFF1
RS2INV
RS1INV
GPA0
GPA1
GPA2
GPA3
GPA4
GPA5
GPA6
GPA7
GPA8
GPA9
GPA10
GPA11
GPA12
GPA13
GPA14
GPA15
GPA1OE
GPA1DIR
GPA2OE
GPA2DIR
F0CE
F0RDY
FBYTE
F1CE
F1RDY
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
BE0
BE1
BE2
BE3
196
195
194
193
192
191
190
188
187
186
185
184
183
182
181
175
174
173
172
171
169
168
167
166
164
163
162
161
159
158
157
156
SRAM0_CS
SRAM1_CS
SRAM2_CS
SRAM3_CS
X_D[0..31]
91
211
106
107
108
109
90
92
RS2_FRC_OFF
RS2_FRC_ON
RS1_FRC_OFF
RS1_FRC_ON
RS2_INV
RS1_INV
U2CS
U1CS
UWR
URD
U2INT
U1INT
URST
UA2
UA1
UA0
UD7
UD6
UD5
UD4
UD3
UD2
UD1
UD0
GPC0
GPC1
GPC2
GPC3
GPC4
GPC5
GPC6
GPC7
GPC1 OE
GPC1 DIR
GPC2 OE
GPC2 DIR
GPB0
GPB1
GPB2
GPB3
GPB4
GPB5
GPB6
GPB7
GPB8
GPB9
GPB10
GPB11
GPB12
GPB13
GPB14
GPB15
GPB1OE
GPB1DIR
GPB2OE
GPB2DIR
XTOUT0
XTIN0
XTOUT1
XTIN1
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
110
111
113
114
A_RST_NOT
X_CE2_NOT
X_CE1_NOT
X_OE_NOT
X_ARDY
X_RE_NOT
X_WE_NOT
X_A [2..21 ]
X_CLKOUT_R
A_CLK
80
81
82
83
102
103
105
99
100
101
84
86
87
88
94
95
97
98
227
228
229
230
231
233
234
235
236
237
238
239
54
55
56
61
62
63
64
65
66
67
68
70
71
72
73
74
75
76
78
79
19
20
25
28
U2_CS
U1_CS
U_WR
U_RD
U2_INT
U1_INT
U_RST
U_A2
U_A1
U_A0
U_D7
U_D6
U_D5
U_D4
U_D3
U_D2
U_D1
U_D0
GPC0
GPC1
GPC2
GPC3
GPC4
GPC5
GPC6
GPC7
GPC_ 1OE
GPC_ 1DIR
GPC_ 2OE
GPC_ 2DIR
GPB0
GPB1
GPB2
GPB3
GPB4
GPB5
GPB6
GPB7
GPB8
GPB9
GPB10
GPB11
GPB12
GPB13
GPB14
GPB15
GPB_1OE
GPB_1DIR
GPB_2OE
GPB_2DIR
X_TOUT0
X_TIN0
X_TOUT1
X_TIN1
XCNTL0
XCNTL1
XSTAT0
XSTAT1
V CC
V CC
V CC
V CC
V CC
V CC
V CC
V CC
V CC
V CC
V CC
V CC
V CC
V CC
V CC
V CC
V CC
V CC
V CC
39
40
41
43
224
205
189
170
160
150
140
130
122
112
96
89
77
57
47
37
27
16
5
X_CNTL 0
X_CNTL 1
X_STAT0
X_STAT1
3.3V
S0CS
S1CS
S2CS
S3CS
36
116
46
117
118
119
120
X_WE_ NOT
X_RE_NOT
XINT0
XINT1
XINT2
XINT3
XIACK
XDBINT
X_OE_NOT
X_CE2_NOT
X_CE1_NOT
A _RST_NOT
XRST
XCE1
XCE2
XOE
XRDY
XRE
XWE
X_BE3_NOT
X_BE2_NOT
X_BE1_NOT
X_BE0_NOT
21
29
24
44
30
35
X_SP0
X_SP1
X_SP2
X_SP3
X_SP4
X_SP5
X_SP6
X_SP7
X_SP8
X_SP9
X_SP10
X_SP11
X_SP12
X_SP13
X_SP14
X_SP15
X_SP16
X_SP17
X_SP18
X_SP19
X_SP20
XSP0
XSP1
XSP2
XSP3
XSP4
XSP5
XSP6
XSP7
XSP8
XSP9
XSP10
XSP11
XSP12
XSP13
XSP14
XSP15
XSP16
XSP17
XSP18
XSP19
XSP20
X_A [2..21 ]
X_INT0_NOT
X_INT1_NOT
X_INT2_NOT
X_INT3_NOT
X_IACK_NOT
X_DBINT_NOT
X_IACK_NOT
X_DBINT_ NOT
115
53
51
50
49
48
45
38
34
33
31
18
17
15
14
13
12
9
8
7
6
FLA SH1_RDY
FLA SH0_RDY
VPP
X_TOUT0
X_TOUT1
X_SP0
X_SP1
X_SP2
X_SP3
X_SP4
X_SP5
X_SP6
X_SP7
X_SP8
X_SP9
X_SP10
X_SP11
X_SP12
X_SP13
X_SP14
X_SP15
X_SP16
X_SP17
X_SP18
X_SP19
X_SP20
High speed digital systems laboratory
‫המעבדה למערכות ספרתיות מהירות‬
3.3V
R32
1K
GPA [0..15]
X_A RDY
SRA M0_CS
SRA M1_CS
SRA M2_CS
SRA M3_CS
R33
1K
EN
V CC
3.3V
X_D[0..31]
FLA SH0_CE
FLA SH_BYTE_NOT
FLA SH1_CE
GPA [0..15]
U6
0
U_A [0..2]
3.3V
3.3V
D_CLK
A _DATA0
15
R46
1K
A _CONFIG
TDO
EPC2
GPA _1OE
GPA _1DIR
GPA _2OE
GPA _2DIR
OSC-40MHz/SM
X_INT0_NOT
X_INT1_NOT
X_INT2_NOT
X_INT3_NOT
X_STA T0
X_STA T1
X_TIN0
X_TIN1
GPB[0..15 ]
GPB_1OE
GPB_1DIR
GPB_2OE
GPB_2DIR
GPC[0..7]
GPC_1OE
GPC_1DIR
GPC_2OE
GPC_2DIR
U_D[0..7]
U_A [0..2]
3.3V
U1_INT
U2_INT
U1_CS
U2_CS
U_WR
U_RD
U_RST
R35
1K
RS1_FRC_OFF
RS1_FRC_ON
RS2_FRC_OFF
RS2_FRC_ON
Y1
3.3V
1
4
C15
100nF
A _CLK
CLK
1.8432MHz
‫המעבדה למערכות ספרתיות מהירות‬
High speed digital systems laboratory
FPGA Block Diagram
addr
addr
data
Memory
Interface
UART
Interface
ctrl
data
ctrl
Main
Control
Spare
MB Signals
Interface
GPIO
Interface
ctrl
Indicators
Interface
‫המעבדה למערכות ספרתיות מהירות‬
High speed digital systems laboratory
Power Supply
5v External
Power Supply
Reverse Power
protect
Power
Regulator
3.3v Layer
6A Trace
J10
5V _SUPPLY
3
OUT
3.3V
2
C42
D6
CONN PWR 4-H
IN
R49
150
DIODE
C43
C44
10nF
100nF
+ C41
22uF
1
4
3
2
1
GND
U8 LM1085
D5
C45
C46
ZENER
10nF
100nF
D7
LED
4 pin standard
PS connector
place 10nF cap
& zenner close
Power
Indicator
OVP
+
22uF
‫המעבדה למערכות ספרתיות מהירות‬
High speed digital systems laboratory
System Reset
Active Low Reset
Set
Delay
3.3V
3.3V
3.3V
reset delay:
res connected
- 20ms
res not connected - 100ms
C47
100nF
R50
0
14
R51
10K
X_RESET_NOT
U9A
1
U10
3
2
3
4
3.3V
SW1
SRT
RST
A _RST_NOT
2
V CC
SN74LV C08A /PW
MAX82 1/SOT143
R52
10K
C48
100nF
SW PUSHBUTTON- SPDT
normally closed
Manual
Reset
MB
Reset
MAX821
Voltage Monitor
To
FPGA
High speed digital systems laboratory
‫המעבדה למערכות ספרתיות מהירות‬
Design Issues
 Timing:
 DB System Clock 40MHz.
 MB Supplies configurable Clock 20MHz ÷ 160MHz.
 DSP  DB CS Delay ~23nSec (before simulation).
 DSP  DB Memory Addr/Data ~9nSec
 Fanout :
 Borderline (capacity) for most memory signals. Single Buffer
drives 7 outputs.
High speed digital systems laboratory
‫המעבדה למערכות ספרתיות מהירות‬
Layout Guidelines
 Place Memory IC close to Memory connector
 Information Flow
 Altera’s Pins same as connected IC’s pins as possible
 Lines as simple as possible
 Critical lines : Clocks
 Easy Access to Connectors/Switch/Leds
By The
Numbers:
Size: 191mm X 76.2mm
6 Layers
430 Nets
~1200 Pads
‫המעבדה למערכות ספרתיות מהירות‬
High speed digital systems laboratory
Layout
Power
Connector
Flas
h
Reverse
REGULATOR
EMIF Connector
S
R
A
M
OVP
McBSP
Headers
FPGA
BUFFER
EPC2
BUFFERS
UARTS
RS232
JTAG
Header
Peripheral Connector
High speed digital systems laboratory
‫המעבדה למערכות ספרתיות מהירות‬
On The Agenda
 Final Preparation for production.
 Finish FPGA Code & Simulation.
 Learning the Code Composer environment.
 Writing test programs.
 Electrical wiring test of the board after production.
 Components assembly & Functional Debug.
 Parallel Operation of 3 DSP’s.
High speed digital systems laboratory
‫המעבדה למערכות ספרתיות מהירות‬
The End